WO2023130548A1 - 并串转换电路、并串转换电路版图及存储器 - Google Patents

并串转换电路、并串转换电路版图及存储器 Download PDF

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Publication number
WO2023130548A1
WO2023130548A1 PCT/CN2022/078110 CN2022078110W WO2023130548A1 WO 2023130548 A1 WO2023130548 A1 WO 2023130548A1 CN 2022078110 W CN2022078110 W CN 2022078110W WO 2023130548 A1 WO2023130548 A1 WO 2023130548A1
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Prior art keywords
parallel
layout
conversion circuit
selection
signal
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PCT/CN2022/078110
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English (en)
French (fr)
Inventor
黄克琴
冀康灵
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/849,033 priority Critical patent/US12047069B2/en
Publication of WO2023130548A1 publication Critical patent/WO2023130548A1/zh
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the field of semiconductor circuit design, in particular to a parallel-serial conversion circuit, a layout of the parallel-serial conversion circuit and a memory.
  • the delay between each parallel input and the serial output needs to be consistent, so additional winding is required in the circuit design to make the connection distances from each parallel input to the serial output consistent.
  • the delay between the serial input and each parallel output is consistent, so additional winding is required in the circuit design to make the connection distance from the serial input to each parallel output consistent.
  • An embodiment of the present disclosure provides a parallel-to-serial conversion circuit, including: a plurality of parallel branches, each of which includes: a first input terminal, a second input terminal, a control terminal, and an output terminal; wherein, the first input The terminal is used to receive a high-level signal, the second input terminal is used to receive a low-level signal, the control terminal is connected to the selection unit, and the output terminal is connected to a serial wire; the selection unit is used to receive the selection signal and at least two branch signals, and is It is configured to, based on the selection signal, select a branch signal and transmit it to the parallel branch; the serial wire is used to organize the signals output by multiple parallel branches into a serial signal; the drive unit is connected to the serial wire for enhancing The driving capability of the serial wire, the output terminal of the driving unit is used to output the serial signal.
  • the selection unit includes: a multiplexer and a selection subunit; the multiplexer is used to receive at least two branch signals and is connected to the selection subunit; the selection subunit is used to receive a selection command and generate a selection signal based on the selection command ; The multiplexer is configured to, based on the selection signal, select a branch signal and transmit it to the parallel branch through the control terminal.
  • the multiplexer only receives two branch signals, and the selection command is an internal clock signal.
  • the period of the selection signal is n times the period of the internal clock signal, and n is the number of parallel branches.
  • At most one is a continuous signal.
  • at most one of the selection signals and branch signals connected to the same selection unit for a continuous signal is a continuous signal.
  • the high-level data has overlapping parts.
  • the parallel branch includes: a switch PMOS tube and a switch NMOS tube; the gate of the switch PMOS tube and the gate of the switch NMOS tube are used as the control terminal of the parallel branch for connecting the selection unit; the source of the switch PMOS tube and the switch The drain of the NMOS transistor is connected to the serial wire; the drain of the switch PMOS transistor is used as the first input terminal of the parallel branch for receiving a high level signal; the source of the switch NMOS transistor is used as the second input terminal of the parallel branch, Used to receive low-level signals.
  • the drive unit includes: two inverters, wherein the input end of one inverter is connected to the serial wire, the output end is connected to the input end of the other inverter, and the output end of the other inverter is used to output the serial wire. line signal.
  • the inverter includes: driving the PMOS transistor and driving the NMOS transistor; driving the gate of the PMOS transistor and driving the gate of the NMOS transistor, connecting the source of the driving PMOS transistor and driving the drain of the NMOS transistor; driving the drain of the PMOS transistor The pole is used to receive high-level signals, and the source of the drive NMOS transistor is used to receive low-level signals.
  • An embodiment of the present disclosure provides a parallel-to-serial conversion circuit layout for forming the above-mentioned parallel-serial conversion circuit, including: a parallel branch circuit layout, used to form a parallel branch, and a selection unit connected to the parallel branch; a drive unit The layout is used to form the drive unit; wherein, each parallel branch layout and the drive unit layout are set in different layout layers, and the layout layers where the multiple parallel branch layouts are located are set symmetrically based on the layout layer where the drive unit layout is located; the connection The serial wires of the parallel branch layout and the driver unit layout are arranged symmetrically based on the layout layer where the driver unit layout is located.
  • the layout of the parallel branch circuit and the layout of the driving unit overlap in the projection part perpendicular to the direction of the layout layer.
  • An embodiment of the present disclosure provides a memory in which the above-mentioned parallel-to-serial conversion circuit is applied.
  • An embodiment of the present disclosure provides a memory, and the layout structure of the memory adopts the above-mentioned parallel-to-serial conversion circuit layout.
  • FIG. 1 is a schematic structural diagram of a parallel-to-serial conversion circuit provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of each parallel branch provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a selection unit provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a drive unit provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a parallel-to-serial conversion circuit based on the structural components shown in FIGS. 1 to 4 provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic waveform diagram of a selection signal in the circuit shown in FIG. 5 provided by an embodiment of the present disclosure
  • FIG. 7 is a specific waveform diagram of a selection signal in the circuit shown in FIG. 6 provided by an embodiment of the present disclosure
  • FIGS. 8 and 9 are structural schematic diagrams of a parallel-to-serial conversion circuit layout with two parallel branches provided by another embodiment of the present disclosure.
  • 10 and 11 are structural schematic diagrams of a parallel-to-serial conversion circuit layout with four parallel branches provided by another embodiment of the present disclosure.
  • the embodiment of the present disclosure provides a parallel-to-serial conversion circuit, which greatly reduces the load on the internal nodes of the conversion circuit, effectively improves the performance of the internal nodes of the conversion circuit, and makes the signal in the conversion circuit have a large swing, and the duty cycle The loss is small.
  • Fig. 1 is a schematic structural diagram of the parallel-to-serial conversion circuit provided by this embodiment
  • Fig. 2 is a schematic structural diagram of each parallel branch provided by this embodiment
  • Fig. 3 is a schematic structural diagram of a selection unit provided by this embodiment
  • Fig. 4 is a schematic diagram of this embodiment
  • Fig. 5 is a schematic structural diagram of the parallel-serial conversion circuit based on the structural components shown in Fig. 1 to Fig. 4 provided in this embodiment
  • Fig. 6 is the circuit shown in Fig. 5 provided in this embodiment
  • FIG. 7 is a specific waveform diagram of the selection signal in the circuit shown in FIG. 6 provided by this embodiment.
  • the parallel-to-serial conversion circuit provided by this embodiment is further described in detail below in conjunction with the accompanying drawings, as follows:
  • the parallel-to-serial conversion circuit includes: a plurality of parallel branches 101 , serial wires 102 and a driving unit 103 .
  • each parallel branch 101 includes: a first input terminal K1, a second input terminal K2, a control terminal C, and an output terminal D; wherein, the first input terminal K1 is used to receive a high-level signal V DD , the second input terminal K2 is used to receive the low-level signal GND, the control terminal C is connected to the selection unit 104 , and the output terminal D is connected to the serial wire 102 .
  • the selection unit 104 is configured to receive a selection signal and at least two branch signals, and the selection unit 104 is configured to select a branch signal and transmit it to the parallel branch 101 based on the selection signal.
  • the serial wire 102 is used to organize the signals output by the multiple parallel branches 101 into a serial signal.
  • the driving unit 103 is connected to the serial wire 102 for enhancing the driving capability of the serial wire 102 , and the output terminal of the driving unit 103 is used for outputting a serial signal.
  • Each parallel branch 101 receives multiple channels of parallel signals through the selection unit 104, and the received multiple channels of parallel signals are selected for data through the selection signal, thereby realizing the transmission of multiple channels of parallel signals through a single parallel branch 101, thus saving the required setup time
  • the number of parallel branches 101 further saves the length of the serial wire 102 that needs to be set, thereby reducing the load of the serial wire 102; in addition, by saving the number of parallel branches 101, it saves part of the parallel branch layout.
  • the parallel branch 101 includes: a switch PMOS transistor and a switch NMOS transistor; wherein, the gate of the switch PMOS transistor and the gate of the switch NMOS transistor are used as the control terminal C of the parallel branch 101 for connecting the selection unit 104 , the source of the switch PMOS transistor and the drain of the switch NMOS transistor are connected to the serial wire 102, and the drain of the switch PMOS transistor is used as the first input terminal K1 of the parallel branch 101 for receiving the high-level signal V DD , the switch NMOS The drain of the tube serves as the second input terminal K2 of the parallel branch 101 for receiving the low-level signal GND.
  • Both the gate of the switch PMOS transistor and the gate of the switch NMOS transistor are used as the control terminal C, so that only one of the switch PMOS transistor and the switch NMOS can be turned on based on the parallel signal output by the selection unit 104.
  • the switch PMOS transistor is turned on, the serial The row wire 102 is connected to the high-level signal V DD to output a high-level signal.
  • the switch NMOS transistor is turned on, the serial wire 102 is connected to the low-level signal GND to output a low-level signal.
  • grounding is used as the received low-level signal GND, and the internal power supply voltage is used as the high-level signal V DD , which does not constitute a limitation to this embodiment; in other embodiments, any A power signal that can be recognized as a high level by the memory provides a high level signal, and similarly, any power signal that can be recognized as a low level by the memory can be selected to provide a low level signal.
  • the specific connection mode of "source” and “drain” does not constitute a limitation to this embodiment.
  • “drain” can be used instead of “source”.
  • “, “source” replaces the “drain” connection.
  • the drain of the switch PMOS transistor as defined above is used as the first input terminal K1
  • the drain of the switch NMOS transistor is used as the second input terminal K2, which does not constitute a limitation to this embodiment; in other embodiments, a switch can be used
  • the drain of the PMOS transistor is used as the second input terminal K2
  • the drain of the switch NMOS transistor is used as the first input terminal K1; at this time, when the switch PMOS transistor is turned on, the serial wire 102 is connected to the low-level signal GND to output A low-level signal, when the switch NMSO transistor is turned on, the serial wire 102 is connected with the high-level signal V DD to output a high-level signal.
  • the selection unit 104 includes: a multiplexer 301 and a selection subunit 302 .
  • the multiplexer 301 is used to receive at least two branch signals, and is connected to the selection subunit 302 .
  • the selection subunit 302 is configured to receive a selection command and generate a selection signal based on the selection command.
  • the multiplexer 301 is configured to select a branch signal and transmit it to the parallel branch 101 through the control terminal C based on the selection signal.
  • the driving unit 103 includes: two inverters, wherein the input end of one inverter is connected to the serial wire 102, the output end is connected to the input end of the other inverter, and the other inverter The output terminal of the inverter is used to output the serial signal.
  • the inverter includes: driving the PMOS transistor and driving the NMOS transistor, the gate of the driving PMOS transistor is connected to the gate of the driving NMOS transistor, the source of the driving PMOS transistor is connected to the drain of the driving NMOS transistor, and the driving The drain of the PMOS transistor is used to receive the high-level signal V DD , and the source of the driving NMOS transistor is used to receive the low-level signal GND.
  • the gate of the driving PMOS transistor is connected to the gate of the driving NMOS transistor as the input terminal of the inverter.
  • the driving NMOS transistor When the input is high, the driving NMOS transistor is turned on, and the output terminal of the inverter is connected to the low-level signal GND to Output low level data, when input low level, drive PMOS tube conduction, the output terminal of the inverter is connected with high level signal V DD to output high level data, so as to realize data inversion; in addition, output
  • the high-level data is the high-level signal V DD
  • the output low-level data is the low-level signal GND, thereby increasing the signal swing and reducing the duty cycle loss of the signal.
  • the selection unit 104 receives two branch signals, that is, the multiplexer 301 only receives two branch signals, and combines the circuits shown in FIG. 1 to FIG. 4 to form the circuit shown in FIG. 5 .
  • the selection command may use the internal clock signal CK, and in other examples, the selection command may be controlled by using an external signal as an instruction.
  • the example in Figure 5 takes the parallel-to-serial conversion circuit with two parallel branches as an example to make a specific introduction, which does not constitute a limitation on the number of parallel branches in the parallel-to-serial conversion circuit, as follows:
  • the period of the selection signal corresponding to each selection unit 104 generated according to the selection command is n times the period of the internal clock signal, and n is the number of branches of the parallel branch 101 in the parallel-to-serial conversion circuit; therefore, in this example , the period of the selection signal is twice the period of the internal clock signal; in other embodiments, if the number of parallel branches in the parallel-to-serial conversion circuit is n, the selection signal corresponding to each selection unit generated according to the selection command The period is n times the period of the internal clock signal.
  • the period of the first selection signal CK1 for controlling the first parallel branch and the period of the second selection signal CK2 for controlling the second parallel branch are twice the period of the internal clock signal CK.
  • the oblique lines shown in the signal diagram can be at high level or at low level, so four groups of first selection signals as shown in FIG. 7 can be formed.
  • the high-level data are alternately distributed; From the flat distribution, it can be seen that among the selection signals received by the selection units 104 connected to the multiple parallel branches 101 , the high-level data has overlapping parts.
  • the first selection signal CK1 is used to control the output of the first branch signal IN1 and the third branch signal IN3, and the second selection signal CK2 is used to control the output of the second branch signal IN2 and the fourth branch signal IN4. output.
  • the first branch signal IN1 controls the parallel branch 101 through the selection unit 104 to input a high-level signal V DD or a low-level signal GND to the serial conductor 102;
  • the second branch signal IN2 controls the parallel branch 101 through the selection unit 104 to input the high-level signal V DD or the low-level signal GND into the serial wire 102;
  • the first branch signal IN1 passes through the selection
  • the unit 104 controls the parallel branch 101 to input the high-level signal V DD or the low-level signal GND to the serial wire 102;
  • the second branch signal IN2 controls the parallel branch 101 to be high through the selection unit 104
  • a level signal V DD or a low level signal GND is input to the serial wire 102 .
  • the first selection signal CK1 and the second selection signal CK2 are intermittent signals, that is, the slash level shown in FIG. 6 is empty; in one example, the branch signals IN1, IN2, IN3 and IN4 are intermittent signals. At this time, when the first selection signal CK1 and the second selection signal CK2 are valid signals, the branch signals IN1, IN2, IN3 and IN4 have valid levels; in one example, the selection signals and The branch signals are all discontinuous signals, and the effective levels of the selection signal and the branch signals have an intersection.
  • each parallel branch is used to receive more than 2 branch signals.
  • the selection unit nested connection shown in FIG. 5 is used to realize the parallel branch receiving more than 2 branch signals.
  • the selection unit receives more than 2 branch signals so that each parallel branch receives more than 2 branch signals.
  • each parallel branch receives multiple parallel signals through the selection unit, and the received multi-channel parallel signals select data through the selection signal, thereby realizing the transmission of multiple parallel signals through a single parallel branch, thus saving the required
  • the number of parallel branches set further saves the length of the serial wires that need to be set, thereby reducing the load of the serial wires; in addition, by saving the number of parallel branches, it saves part of the parallel branch layout. layout area, thereby reducing the layout area of the parallel-serial conversion circuit and achieving a greater degree of integration; in addition, by saving the number of parallel branches, the layout layer for setting parallel branches is saved, thereby reducing the layout of the parallel-serial conversion circuit Storey height.
  • Another embodiment of the present disclosure provides a parallel-to-serial conversion circuit layout, which is used to form the parallel-to-serial conversion circuit provided in the above-mentioned embodiments.
  • the layout area occupied by part of the parallel branch layout is saved, thereby Reduce the layout area of the parallel-serial conversion circuit to achieve a greater degree of integration; in addition, by saving the number of parallel branch layouts, the layout layers for setting the parallel branch layout are saved, thereby reducing the layout layers of the parallel-serial conversion circuit layout High; by setting the layout layer where the parallel branch layout is located symmetrically based on the layout layer where the drive unit layout is located, the delay between the parallel input and the serial output is consistent.
  • FIG 8 and Figure 9 are structural schematic diagrams of the parallel-serial conversion circuit layout with two parallel branches provided in this embodiment
  • Figure 10 and Figure 11 are the parallel-serial conversion circuit layout with four parallel branches provided in this embodiment
  • Schematic diagram of the structure of the parallel-to-serial conversion circuit layout provided by this embodiment is further described in detail below in conjunction with the accompanying drawings, as follows:
  • the layout of the parallel-to-serial conversion circuit includes:
  • the parallel branch layout 401 is used to form parallel branches and select units connected to the parallel branches.
  • the driving unit layout 402 is used to form the driving unit.
  • each parallel branch layout 401 and the driving unit layout 402 are arranged in different layout layers, and the layout layers where the multiple parallel branch layouts 401 are located are arranged symmetrically based on the layout layer where the driving unit layout 402 is located, and the parallel branch layouts are connected. 401 and the serial wires of the driving unit layout 402 are arranged symmetrically based on the layout layer where the driving unit layout is located.
  • the layout area occupied by part of the parallel branch layout 401 is saved, thereby reducing the layout area of the parallel-to-serial conversion circuit and achieving a greater degree of integration; in addition, by saving the layout area of the parallel branch layout 401 The quantity saves the layout layer for setting the parallel branch circuit layout 401, thereby reducing the layout layer height of the parallel-to-serial conversion circuit layout.
  • the projections of the parallel branch layout 401 and the driving unit layout 402 in the direction perpendicular to the layout layer do not coincide, that is, the parallel branch layout 401 and the driving unit layout 402 are arranged along different directions of the layout layer.
  • the parallel branch layout 401 and the driving unit layout 402 overlap in the projection portion perpendicular to the direction of the layout layer, that is, the parallel branch layout 401 and the driving unit layout 402 are arranged along the same direction of the layout layer, so that The layout area of the parallel-to-serial conversion circuit is further saved.
  • the drive unit layout 402 is set at the middle layout layer position of the parallel-to-serial conversion circuit. Since the delays of each parallel input and serial output need to be consistent, that is, it is set on both sides of the drive unit layout 402 and connected to the drive unit.
  • the parallel branch layout 401 where the layout 402 is located is arranged symmetrically at the same distance from the layout layer, and in the direction perpendicular to the extending direction of the layout layer, the projections of the symmetrically arranged two parallel branch layouts 401 on the layout layer coincide to realize the parallel branch
  • the lengths of the serial wires connecting the layout 401 and the driving unit layout 402 are equal.
  • the drive unit layout 402 is set at the middle layout layer position of the parallel-to-serial conversion circuit. Since the delay of each parallel input and serial output needs to be consistent, the parallel branch layout set on the same side of the drive unit layout 402 401 in the layout layer, the length of the serial wire gradually decreases with the increase of the distance between the layout layer where the parallel branch layout 401 is located and the layout layer where the drive unit layout 402 is located, so as to meet the requirements of parallel wires arranged on the same side of the drive unit layout 401.
  • the conversion circuit 401 and the serial wires connected to the drive unit layout 402 have the same length, and the parallel branch layout 401 arranged on both sides of the drive unit layout 402 and at the same distance from the layout layer where the drive unit layout 402 is located is symmetrically arranged, and is perpendicular to the layout. In the direction of layer extension, the projections of the two symmetrically arranged parallel branch layouts 401 on the layout layer coincide, so that the lengths of the serial wires connected between the symmetrically arranged parallel branch layouts 401 and the drive unit layout 402 are equal.
  • Another embodiment of the present disclosure provides a memory.
  • the memory adopts the parallel-serial conversion circuit of the above-mentioned embodiment, or the layout structure of the memory is constructed by using the above-mentioned parallel-serial conversion circuit layout.
  • the memory is a DRAM chip, wherein the memory of the DRAM chip conforms to the DDR2 memory specification.
  • the memory is a DRAM chip, wherein the memory of the DRAM chip conforms to the DDR3 memory specification.
  • the memory is a dynamic random access memory DRAM chip, wherein the memory of the dynamic random access memory DRAM chip conforms to the DDR4 memory specification.
  • the memory is a dynamic random access memory DRAM chip, wherein the memory of the dynamic random access memory DRAM chip conforms to the DDR5 memory specification.

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Abstract

一种并串转换电路、并串转换电路版图及存储器，涉及半导体电路设计领域，包括：多个并行支路(101)，每一并行支路(101)都包括：第一输入端、第二输入端、控制端和输出端；其中，第一输入端用于接收高电平信号、第二输入端用于接收低电平信号、控制端连接选择单元，输出端连接串行导线(102)；选择单元(104)用于接收选择信号和至少两路支路信号，被配置为，基于选择信号，选择一路支路信号传输至并行支路(101)中；串行导线(102)用于将多个并行支路(101)输出的信号组织成串行信号；驱动单元(103)，连接串行导线(102)，用于增强串行导线(102)的驱动能力，驱动单元(103)的输出端用于输出串行信号。

Description

并串转换电路、并串转换电路版图及存储器
交叉引用
本公开要求于2022年01月10日递交的名称为“并串转换电路、并串转换电路版图及存储器”、申请号为202210023003.1的中国专利申请的优先权，其通过引用被全部并入本公开。
技术领域
本公开涉及半导体电路设计领域，特别涉及一种并串转换电路、并串转换电路版图及存储器。
背景技术
对于存储器中的并串转换电路，需要各个并行输入与串行输出的延迟保持一致，因此在电路设计中需要额外绕线，以使各个并行输入到串行输出的连线距离一致。
同理，对于存储器中的串并转换电路，串行输入与各个并行输出的延迟保持一致，因此在电路设计中需要额外绕线，以使串行输入到各个并行输出的连线距离一致。
由于转换电路的额外绕线，增大了转换电路的负载，从而减低了转换电路的性能，负载过大的线路中传输的信号摆幅小且波形占空比偏差较大，容易造成存储器的写入/读出错误。
发明内容
本公开实施例提供了一种并串转换电路，包括：多个并行支路，每一并行支路都包括：第一输入端、第二输入端、控制端和输出端；其中，第一输入端用于接收高电平信号、第二输入端用于接收低电平信号、控制端连接选择单元，输出端连接串行导线；选择单元用于接收选择信号和至少两路支路信号，被配置为，基于选择信号，选择一路支路信号传输至并行支路中；串行导线用于将多个并行支路输出的信号组织成串行信号；驱动单元，连接串行导线，用于增强串行导线的驱动能力，驱动单元的输出端用于输出串行信号。
另外，选择单元包括：多路选择器和选择子单元；多路选择器用于接收至少两路支路信号，并连接选择子单元；选择子单元用于接收选择命令，并基于选择命令生成选择信号；多路选择器被配置为，基于选择信号，选择一路支路信号通过控制端传输至并行支路中。
另外，多路选择器仅接收两路支路信号，选择命令为内部时钟信号。
另外，选择信号的周期为内部时钟信号周期的n倍，且n为多个并行支路的支路数。
另外，同一选择单元所接收的选择信号和支路信号中，至多一者为连续信号，为了防止其他并行支路的信号影响，同一选择单元所连接的选择信号和支路信号中，至多一者为连续信号。
另外，多个并行支路所连接的选择单元所接收的选择信号中，高电平数据交替分布。
另外，多个并行支路所连接的选择单元所接收的选择信号中，高电平数据具有重叠部分。
另外，并行支路包括：开关PMOS管和开关NMOS管；开关PMOS管的栅极和开关NMOS管的栅极作为并行支路的控制端，用于连接选择单元；开关PMOS管的源极和开关NMOS管的漏极连接串行导线；开关PMOS管的漏极作为并行支路的第一输入端，用于接收高电平信号；开关NMOS管的源极作为并行支路的第二输入端，用于接收低电平信号。
另外，驱动单元包括：两个反相器，其中，一反相器的输入端连接串行导线，输出端连接另一反相器的输入端，另一反相器的输出端用于输出串行信号。
另外，反相器包括：驱动PMOS管和驱动NMOS管；驱动PMOS管的栅极和驱动NMOS管的栅极连接，驱动PMOS管的源极和驱动NMOS管的漏极连接；驱动PMOS管的漏极用于接收高电平信号，驱动NMOS管的源极用于接收低电平信号。
本公开实施例提供了一种并串转换电路版图，用于形成上述并串转换电路，包括：并行支路版图，用于形成并行支路，以及形成与并行支路连接的选 择单元；驱动单元版图，用于形成驱动单元；其中，每一并行支路版图和驱动单元版图设置在不同版图层中，且多个并行支路版图所在的版图层基于驱动单元版图所在的版图层对称设置；连接并行支路版图和驱动单元版图的串行导线基于驱动单元版图所在的版图层对称设置。
另外，并行支路版图和驱动单元版图在垂直于版图层方向的投影部分重合。
另外，并行支路版图和驱动单元版图在垂直于版图层方向的投影不重合。
本公开实施例提供了一种存储器，存储器中应用上述并串转换电路。
本公开实施例提供了一种存储器，存储器的版图架构采用上述并串转换电路版图。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领缺普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的并串转换电路的结构示意图；
图2为本公开一实施例提供的各并行支路的结构示意图；
图3为本公开一实施例提供的选择单元的结构示意图；
图4为本公开一实施例提供的驱动单元的结构示意图；
图5为本公开一实施例提供的基于图1～图4所示结构构件的并串转换电路的结构示意图；
图6为本公开一实施例提供的图5所示电路中选择信号的波形示意图；
图7为本公开一实施例提供的图6所示电路中选择信号的具体波形图；
图8和图9为本公开另一实施例提供的具有两个并行支路的并串转换电路版图的结构示意图；
图10和图11为本公开另一实施例提供的具有四个并行支路的并串转换电路版图的结构示意图。
具体实施方式
由于转换电路的额外绕线，增大了转换电路的负载，从而减低了转换电路的性能，负载过大的线路中传输的信号摆幅小且波形占空比偏差较大，容易造成存储器的写入/读出错误。
本公开实施例提供了一种并串转换电路，极大的降低转换电路内部节点的负载，有效提高转换电路内部节点的性能，使得转换电路内的信号具有较大的摆幅，且占空比损失较小。
本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本公开的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1为本实施例提供的并串转换电路的结构示意图，图2为本实施例提供的各并行支路的结构示意图，图3为本实施例提供的选择单元的结构示意图，图4为本实施例提供的驱动单元的结构示意图，图5为本实施例提供的基于图1～图4所示结构构件的并串转换电路的结构示意图，图6为本实施例提供的图5所示电路中选择信号的波形示意图，图7为本实施例提供的图6所示电路中选择信号的具体波形图，以下结合附图对本实施例提供的并串转换电路作进一步详细说明，具体如下：
参考图1，并串转换电路，包括：多个并行支路101、串行导线102和驱动单元103。
具体参考图2，每一并行支路101都包括：第一输入端K1、第二输入端K2、控制端C和输出端D；其中，第一输入端K1用于接收高电平信号V DD，第二输入端K2用于接收低电平信号GND，控制端C连接选择单元104，输出端D连接串行导线102。
选择单元104用于接收选择信号和至少两路支路信号，选择单元104被 配置为，基于选择信号，选择一路支路信号传输至并行支路101中。
串行导线102用于将多个并行支路101输出的信号组织成串行信号。
驱动单元103，连接串行导线102，用于增强串行导线102的驱动能力，驱动单元103的输出端用于输出串行信号。
每一并行支路101通过选择单元104接收多路并行信号，接收的多路并行信号通过选择信号进行选择数据，实现了通过单一并行支路101传输多路并行信号，从而节省了所需设置的并行支路101的数量，进一步节省了所需设置的串行导线102的长度，从而降低了串行导线102的负载；另外，通过节省并行支路101的数量，节省了部分并行支路版图所占用的版图面积，从而减小并串转换电路的版图面积，实现更大程度的集成；另外，通过节省并行支路101的数量，节省了设置并行支路101的版图层，从而减少了并串转换电路的版图层高。
继续参考图2，并行支路101包括：开关PMOS管和开关NMOS管；其中，开关PMOS管的栅极和开关NMOS管的栅极作为并行支路101的控制端C，用于连接选择单元104，开关PMOS管的源极和开关NMOS管的漏极连接串行导线102，开关PMOS管的漏极作为并行支路101的第一输入端K1，用于接收高电平信号V DD，开关NMOS管的漏极作为并行支路101的第二输入端K2，用于接收低电平信号GND。
开关PMOS管的栅极和开关NMOS管的栅极都作为控制端C，使得开关PMOS管和开关NMOS只能基于选择单元104输出的并行信号导通其中一个，当开关PMOS管导通时，串行导线102与高电平信号V DD相连，以输出一个高电平信号，当开关NMOS管导通时，串行导线102与低电平信号GND相连，以输出一个低电平信号。
需要说明的是，本公开实施例通过接地作为接收的低电平信号GND，通过内部电源电压作高电平信号V DD，并不构成对本实施例的限定；在其他实施例中，可以选择任意可被存储器识别为高电平的电源信号提供高电平信号，同理可以选择任意可被存储器识别为低电平的电源信号提供低电平信号。
另外，对于开关PMOS管和开关NMOS管，具体“源极”和“漏极”的连接方式，并不构成对本实施例的限定，在其他实施例中，可以采用“漏极” 替换“源极”，“源极”替换“漏极”的连接方式。
另外，对于上述限定的开关PMOS管的漏极作为第一输入端K1，开关NMOS管的漏极作为第二输入端K2，并不构成对本实施例的限定；在其他实施例中，可以采用开关PMOS管的漏极作为第二输入端K2，开关NMOS管的漏极作为第一输入端K1；此时，当开关PMOS管导通时，串行导线102与低电平信号GND相连，以输出一个低电平信号，当开关NMSO管导通时，串行导线102与高电平信号V DD相连，以输出一个高电平信号。
在一些实施例中，参考图3，选择单元104包括：多路选择器301和选择子单元302。
多路选择器301用于接收至少两路支路信号，并连接选择子单元302。
选择子单元302用于接收选择命令，并基于选择命令生成选择信号，多路选择器301被配置为基于选择信号，选择一路支路信号通过控制端C传输至并行支路101中。
在一些实施例中，参考图4，驱动单元103包括：两个反相器，其中，一反相器的输入端连接串行导线102，输出端连接另一反相器的输入端，另一反相器的输出端用于输出串行信号。
继续参考图4，反相器包括：驱动PMOS管和驱动NMOS管，驱动PMOS管的栅极和驱动NMOS管的栅极相连接，驱动PMOS管的源极和驱动NMOS管的漏极连接，驱动PMOS管的漏极用于接收高电平信号V DD，驱动NMOS管的源极用于接收低电平信号GND。
驱动PMOS管的栅极和驱动NMOS管的栅极相连接作为反相器的输入端，当输入高电平时，驱动NMOS管导通，反相器的输出端与低电平信号GND相连，以输出低电平数据，当输入低电平时，驱动PMOS管导通，反相器的输出端与高电平信号V DD相连，以输出高电平数据，从而实现数据的反相；另外，输出的高电平数据为高电平信号V DD，输出的低电平数据为低电平信号GND，从而增加了信号的摆幅，且减小了信号的占空比损失。
在一个例子中，若选择单元104接收的支路信号为两路，即多路选择器301仅接收两路支路信号，并结合图1～图4电路，形成图5所示电路。
在本公开示例中，选择命令可以选用内部时钟信号CK，在其他示例中，选择命令可以采用外部信号作为指令进行控制。
图5的示例以并串转换电路具有2个并行支路为例进行具体介绍，并不构成对并串转换电路中并行支路的数量限定，具体如下：
具体地，根据选择命令生成的对应于各选择单元104的选择信号的周期为内部时钟信号周期的n倍，n为并串转换电路中并行支路101的支路数；因此，在本示例中，选择信号的周期为内部时钟信号周期的2倍；在其他实施例中，若并串转换电路中并行支路的支路数为n，则根据选择命令生成的对应于各选择单元的选择信号的周期为内部时钟信号周期的n倍。
具体参考图6，用于第一并行支路控制的第一选择信号CK1的周期和用于第二并行支路控制的第二选择信号CK2的周期为内部时钟信号CK周期的2倍。
需要说明的是，对于第一选择信号CK1和第二选择信号CK2信号图中所示的斜线可以为高电平，也可以为低电平，因此可以形成如图7所示的4组第一选择信号CK1和第二选择信号CK2。
参考图7中第三组电平分布可知，多个并行支路101所连接的选择单元104所接收的选择信号中，高电平数据交替分布；参考图7中第一、二和四组电平分布可知，多个并行支路101所连接的选择单元104所接收的选择信号中，高电平数据具有重叠部分。
参考图6，第一选择信号CK1用于控制第一支路信号IN1和第三支路信号IN3的输出，第二选择信号CK2用于控制第二支路信号IN2和第四支路信号IN4的输出。
具体地，当CK1为高电平时，第一支路信号IN1通过选择单元104控制并行支路101将高电平信号V DD或低电平信号GND输入串行导线102；当CK2为高电平时，第二支路信号IN2通过选择单元104控制并行支路101将高电平信号V DD或低电平信号GND输入串行导线102；当CK1为低电平时，第一支路信号IN1通过选择单元104控制并行支路101将高电平信号V DD或低电平信号GND输入串行导线102；当CK2为低电平时，第二支路信号IN2通过选择单元104控制并行支路101将高电平信号V DD或低电平信号GND输入串行导线102。
需要说明的是，为了防止其他并行支路的信号影响，同一选择单元所连接的选择信号和支路信号中，至多一者为连续信号，使得其他并行支路在工作时，其他并行支路中的开关PMOS管或开关NMOS管并不导通，其他并行支路不会对串行导线102中信号造成影响。
在一个例子中，第一选择信号CK1和第二选择信号CK2为间断信号，即图6所示的斜线电平为空；在一个例子中，传输至选择单元的支路信号IN1、IN2、IN3和IN4为间断信号，此时，当第一选择信号CK1和第二选择信号CK2为有效信号时，支路信号IN1、IN2、IN3和IN4具有有效电平；在一个例子中，选择信号和支路信号都为间断信号，且选择信号和支路信号的有效电平具有交集。
在其他示例中，每个并行支路用于接收大于2路支路信号，例如采用图5所示选择单元嵌套连接的方式实现并行支路接收大于2路支路信号，也可以用每个选择单元接收大于2路支路信号实现每个并行支路接收大于2路支路信号。
本公开实施例通过每一并行支路通过选择单元接收多路并行信号，接收的多路并行信号通过选择信号进行选择数据，实现了通过单一并行支路传输多路并行信号，从而节省了所需设置的并行支路的数量，进一步节省了所需设置的串行导线的长度，从而降低了串行导线的负载；另外，通过节省并行支路的数量，节省了部分并行支路版图所占用的版图面积，从而减小并串转换电路的版图面积，实现更大程度的集成；另外，通过节省并行支路的数量，节省了设置并行支路的版图层，从而减少了并串转换电路的版图层高。
需要说明的是，上述实施例所提供的并串转换电路中所揭露的特征，在不冲突的情况下可以任意组合，可以得到新的并串转换电路实施例。
本公开另一实施例提供一种并串转换电路版图，用于形成上述实施例提供的并串转换电路，通过节省并行支路的数量，节省了部分并行支路版图所占用的版图面积，从而减小并串转换电路的版图面积，实现更大程度的集成；另外，通过节省并行支路版图的数量，节省了设置并行支路版图的版图层，从而减少了并串转换电路版图的版图层高；通过将并行支路版图所在版图层基于驱动单元版图所在的版图层对称设置，实现并行输入与串行输出的延迟保持一致。
图8和图9为本实施例提供的具有两个并行支路的并串转换电路版图的结构示意图，图10和图11为本实施例提供的具有四个并行支路的并串转换电 路版图的结构示意图，以下结合附图对本实施例提供的并串转换电路版图作进一步详细说明，具体如下：
参考图8和图9，并串转换电路版图，包括：
并行支路版图401，用于形成并行支路，以及形成与并行支路连接的选择单元。
驱动单元版图402，用于形成驱动单元。
其中，每一并行支路版图401和驱动单元版图402设置在不同版图层中，且多个并行支路版图401所在的版图层基于驱动单元版图402所在的版图层对称设置，连接并行支路版图401和驱动单元版图402的串行导线基于驱动单元版图所在的版图层对称设置。通过将并行支路版图401所在版图层基于驱动单元版图402所在的版图层对称设置，实现并行输入与串行输出的延迟保持一致。
通过节省并行支路的数量，节省了部分并行支路版图401所占用的版图面积，从而减小并串转换电路的版图面积，实现更大程度的集成；另外，通过节省并行支路版图401的数量，节省了设置并行支路版图401的版图层，从而减少了并串转换电路版图的版图层高。
在一个例子中，参考图8，并行支路版图401和驱动单元版图402在垂直于版图层方向的投影不重合，即并行支路版图401和驱动单元版图402沿版图层的不同方向设置。
在一个例子中，参考图9，并行支路版图401和驱动单元版图402在垂直于版图层方向的投影部分重合，即并行支路版图401和驱动单元版图402沿版图层的同一方向设置，以进一步节省并串转换电路的版图面积。
本实施例以并串转换电路中包括两个并行支路401或四个并行支路401为例，进行具体并串转换电路版图的说明，具体如下：
参考图8和图9，驱动单元版图402设置在并串转换电路的中间版图层位置，由于需要各个并行输入与串行输出的延迟保持一致，即设置在驱动单元版图402两侧且与驱动单元版图402所在版图层距离相等的并行支路版图401对称设置，且在垂直于版图层延伸方向上，对称设置的两个并行支路版图401在版图层上的投影相重合，以实现并行支路版图401与驱动单元版图402连接的 串行导线的长度相等。
参考图10和图11，驱动单元版图402设置在并串转换电路的中间版图层位置，由于需要各个并行输入与串行输出的延迟保持一致，设置在驱动单元版图402同侧的并行支路版图401在版图层中串行导线的长度随着并行支路版图401所在版图层与驱动单元版图402所在版图层的距离增大而逐渐减小，以满足设置在驱动单元版图401同侧的并串转换电路401与驱动单元版图402连接的串行导线的长度相等，设置在驱动单元版图402两侧且与驱动单元版图402所在版图层距离相等的并行支路版图401对称设置，且在垂直于版图层延伸方向上，对称设置的两个并行支路版图401在版图层上的投影相重合，以实现对称设置的并行支路版图401与驱动单元版图402连接的串行导线的长度相等。
需要说明的是，当并串转换电路中并行支路401的数量大于4，其版图基于图10和图11所示版图进行构建，以满足所有并串转换电路401与驱动单元版图402连接的串行导线的长度相等。
需要说明的是，以上并串转换电路版图的描述，与上述并串转换电路实施例的描述是类似的，具有同并串转换电路实施例相似的有益效果，因此不做赘述。对于本公开实施例并串转换电路版图中未披露的技术细节，请参照本公开实施例中并串转换电路的描述而理解。
本公开又一实施例提供一种存储器，存储器采用上述实施例的并串转换电路，或存储器的版图架构采用上述并串转换电路版图构建。
在一些实施例中，存储器为动态随机存取存储器DRAM芯片，其中，动态随机存取存储器DRAM芯片的内存符合DDR2内存规格。
在一些实施例中，存储器为动态随机存取存储器DRAM芯片，其中，动态随机存取存储器DRAM芯片的内存符合DDR3内存规格。
在一些实施例中，存储器为动态随机存取存储器DRAM芯片，其中，动态随机存取存储器DRAM芯片的内存符合DDR4内存规格。
在一些实施例中，存储器为动态随机存取存储器DRAM芯片，其中，动态随机存取存储器DRAM芯片的内存符合DDR5内存规格。
本领域的普通技术人员可以理解，上述各实施例是实现本公开的具体实 施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。

Claims (15)

  1. 一种并串转换电路，包括：
    多个并行支路，每一所述并行支路都包括：第一输入端、第二输入端、控制端和输出端；
    其中，所述第一输入端用于接收高电平信号、所述第二输入端用于接收低电平信号、所述控制端连接选择单元，所述输出端连接串行导线；
    所述选择单元用于接收选择信号和至少两路支路信号，被配置为，基于所述选择信号，选择一路所述支路信号传输至所述并行支路中；
    所述串行导线用于将多个所述并行支路输出的信号组织成串行信号；
    驱动单元，连接所述串行导线，用于增强所述串行导线的驱动能力，所述驱动单元的输出端用于输出所述串行信号。
  2. 根据权利要求1所述的并串转换电路，其中，所述选择单元包括：多路选择器和选择子单元；
    所述多路选择器用于接收至少两路所述支路信号，并连接所述选择子单元；
    所述选择子单元用于接收选择命令，并基于所述选择命令生成所述选择信号；
    所述多路选择器被配置为，基于所述选择信号，选择一路所述支路信号通过所述控制端传输至所述并行支路中。
  3. 根据权利要求2所述的并串转换电路，其中，所述多路选择器仅接收两路所述支路信号，所述选择命令为内部时钟信号。
  4. 根据权利要求3所述的并串转换电路，其中，所述选择信号的周期为所述内部时钟信号周期的n倍，且所述n为多个所述并行支路的支路数。
  5. 根据权利要求3所述的并串转换电路，其中，同一所述选择单元所接收的所述选择信号和所述支路信号中，至多一者为连续信号。
  6. 根据权利要求3所述的并串转换电路，其中，多个所述并行支路所连接的选择单元所接收的所述选择信号中，高电平数据交替分布。
  7. 根据权利要求3所述的并串转换电路，其中，多个所述并行支路所连接的选 择单元所接收的所述选择信号中，高电平数据具有重叠部分。
  8. 根据权利要求1所述的并串转换电路，其中，所述并行支路包括：开关PMOS管和开关NMOS管；
    所述开关PMOS管的栅极和所述开关NMOS管的栅极作为所述并行支路的控制端，用于连接所述选择单元；
    所述开关PMOS管的源极和所述开关NMOS管的漏极连接所述串行导线；
    所述开关PMOS管的漏极作为所述并行支路的第一输入端，用于接收所述高电平信号；
    所述开关NMOS管的源极作为所述并行支路的第二输入端，用于接收所述低电平信号。
  9. 根据权利要求1所述的并串转换电路，其中，所述驱动单元包括：两个反相器，其中，一所述反相器的输入端连接所述串行导线，输出端连接另一所述反相器的输入端，另一所述反相器的输出端用于输出所述串行信号。
  10. 根据权利要求9所述的并串转换电路，其中，所述反相器包括：驱动PMOS管和驱动NMOS管；
    所述驱动PMOS管的栅极和所述驱动NMOS管的栅极连接，所述驱动PMOS管的源极和所述驱动NMOS管的漏极连接；
    所述驱动PMOS管的漏极用于接收所述高电平信号，所述驱动NMOS管的源极用于接收所述低电平信号。
  11. 一种并串转换电路版图，用于形成权利要求1～10中任一项所述并串转换电路，包括：
    并行支路版图，用于形成并行支路，以及形成与所述并行支路连接的所述选择单元；
    驱动单元版图，用于形成驱动单元；
    其中，每一所述并行支路版图和所述驱动单元版图设置在不同版图层中，且多个所述并行支路版图所在的版图层基于所述驱动单元版图所在的版图层对称设置；
    连接所述并行支路版图和所述驱动单元版图的串行导线基于所述驱动单元版图所在的版图层对称设置。
  12. 根据权利要求11所述的并串转换电路版图，其中，所述并行支路版图和所述驱动单元版图在垂直于所述版图层方向的投影部分重合。
  13. 根据权利要求11所述的并串转换电路版图，其中，所述并行支路版图和所述驱动单元版图在垂直于所述版图层方向的投影不重合。
  14. 一种存储器，所述存储器中应用权利要求1～10中任一项所述并串转换电路。
  15. 一种存储器，所述存储器的版图架构采用权利要求11～13中任一项所述的并串转换电路版图。
PCT/CN2022/078110 2022-01-10 2022-02-25 并串转换电路、并串转换电路版图及存储器 Ceased WO2023130548A1 (zh)

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