WO2023130502A1

WO2023130502A1 - Semiconductor structure and fabrication method therefor

Info

Publication number: WO2023130502A1
Application number: PCT/CN2022/072493
Authority: WO
Inventors: 沈宇桐
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-01-06
Filing date: 2022-01-18
Publication date: 2023-07-13
Also published as: CN116454132A

Abstract

Embodiments of the present application disclose a semiconductor structure and a fabrication method therefor. The semiconductor structure comprises: providing a substrate; forming a gate oxide layer on the substrate; and forming a gate stack structure on the gate oxide layer, wherein the gate stack structure at least comprises a barrier layer and a metal gate located on the barrier layer, the metal element contained in the metal gate is the same as the metal element contained in the barrier layer, and the barrier layer is used for absorbing metal atoms diffused from the metal gate to the gate oxide layer.

Description

Semiconductor structure and manufacturing method thereof

Cross References to Related Applications

This disclosure is based on the Chinese patent application with the application number 202210011441.6, the filing date is January 06, 2022, and the title of the invention is "semiconductor structure and its manufacturing method", and claims the priority of the Chinese patent application. The Chinese patent application This disclosure is hereby incorporated by reference in its entirety.

technical field

The present disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.

Background technique

Metal-Oxide-Semiconductor (MOS, Metal-Oxide-Semiconductor) devices become the basis of Complementary Metal-Oxide-Semiconductor (CMOS, Complementary Metal Oxide-Semiconductor) logic used in modern integrated circuits. One or more layers of dielectric material are formed on a semiconductor (typically silicon) substrate, and then a gate is formed on the dielectric. Early devices used silicon oxide (SiO ₂ ) as the gate dielectric and polysilicon (Poly) as the gate. However, as the feature size decreases, the thickness of the gate dielectric layer becomes smaller and smaller. The reduction in oxide thickness directly leads to significant gate oxide leakage due to tunneling. In order to alleviate this problem, a material with a higher dielectric constant than silicon oxide, ie a high-k (High-k) material, has been used in the related art to replace silicon oxide as the gate dielectric layer. Here, a high-K material generally refers to a material with a dielectric constant higher than 3.9, and usually significantly higher than this value. For example, K=5 is considered moderately high and K=20 is considered extremely high. With the introduction of research, the use of metal gates to replace traditional polysilicon gates has become inevitable for the further development of devices.

However, in the related art, the metal contained in the metal gate, such as aluminum (Al), tends to diffuse in a high-temperature process, thereby affecting the performance of the MOS device.

Contents of the invention

In order to solve related technical problems, embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof.

An embodiment of the present disclosure provides a semiconductor structure, including:

Substrate;

a gate oxide layer on the substrate;

A gate stack structure located on the gate oxide layer; the gate stack structure at least includes: a barrier layer and a metal gate located on the barrier layer; the metal element contained in the metal gate and the metal gate The metal elements contained in the barrier layer are the same;

Wherein, the barrier layer is used to absorb metal atoms diffused from the metal gate toward the gate oxide layer.

In the above solution, the metal elements contained in the metal gate and the barrier layer are both aluminum.

In the above solution, the material of the barrier layer includes aluminum oxide or aluminum nitride.

In the above solution, the thickness of the barrier layer is smaller than the thickness of the metal gate, and the thickness of the barrier layer is greater than 0.2 nm.

In the above solution, the gate stack structure further includes a work function adjustment layer, and the work function adjustment layer includes at least one of the following:

first work function layer;

second work function layer;

polysilicon layer;

Wherein, the first work function layer is located between the gate oxide layer and the barrier layer; the second work function layer is located on the metal gate; the polysilicon layer is located on the second work function layer. layer; the materials of the first work function layer and the second work function layer both include titanium nitride.

In the above solution, the gate oxide layer includes an insulating layer and a dielectric layer; the dielectric constant of the material of the dielectric layer is greater than 3.9.

An embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, including:

provide the substrate;

forming a gate oxide layer on the substrate;

A gate stack structure is formed on the gate oxide layer; the gate stack structure at least includes: a barrier layer and a metal gate located on the barrier layer; the metal element contained in the metal gate and the metal gate The metal elements contained in the barrier layer are the same;

In the above solution, the formation of the gate stack structure on the gate oxide layer includes:

forming a metal layer on the gate oxide layer;

performing doping treatment on the metal layer to form the barrier layer;

A metal gate is formed on the barrier layer.

In the above solution, the metal elements contained in the metal gate and the barrier layer are both aluminum; the doping treatment of the metal layer includes:

performing oxygen ion doping treatment on the metal layer to obtain the barrier layer whose material includes aluminum oxide;

or,

Nitrogen ion doping treatment is performed on the metal layer to obtain the barrier layer covered with aluminum nitride.

In the above solution, when nitrogen ion doping is performed on the metal layer, the implanted source gas includes nitrogen or nitrogen oxide.

In the above scheme, when nitrogen ion doping treatment is performed on the metal layer, the energy range of the nitrogen ion implantation is 1keV-100keV; the dose range of the nitrogen ion implantation is 1E11 atoms/cm ² -1E15 atoms/cm ² .

In the above scheme, the method also includes:

Before forming the barrier layer, a first work function layer is formed on the gate oxide layer; the material of the first work function layer includes titanium nitride;

The forming a metal layer on the gate oxide layer includes;

The metal layer is formed on the first work function layer.

In the above scheme, the method also includes:

forming the metal gate overlying the barrier layer;

forming a second work function layer on the metal gate; the material of the second work function layer includes titanium nitride;

A polysilicon layer is formed on the second work function layer.

In the above solution, the formation of the gate oxide layer on the substrate includes:

forming an insulating layer on the substrate;

A dielectric layer is formed on the insulating layer; the dielectric constant of the material of the dielectric layer is greater than 3.9.

Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, by providing a substrate; forming a gate oxide layer on the substrate; forming a gate stack structure on the gate oxide layer; The stacked structure at least includes: a barrier layer and a metal gate located on the barrier layer; the metal element contained in the metal gate is the same as the metal element contained in the barrier layer; wherein the barrier layer is used for absorbing metal atoms diffused from the metal gate toward the gate oxide layer. In the embodiment of the present disclosure, in the process of forming the gate stack structure, a barrier layer containing the same metal element as that contained in the metal gate is firstly formed; and then the metal gate is formed on the barrier layer. The previously formed barrier layer can fully absorb the metal elements diffused from the metal gate, that is, prevent the metal atoms in the metal gate from diffusing to the direction of the gate oxide layer, thereby ensuring the formation of the semiconductor structure. The stability of the electrical properties of semiconductor devices.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure;

FIG. 2 is a schematic flow diagram of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

Figure 3a-Figure 3e is a schematic diagram of the structural relationship between several metal oxide layers and silicate layers provided by embodiments of the present disclosure;

FIG. 4 is a schematic cross-sectional view of another semiconductor structure provided by an embodiment of the present disclosure.

Detailed ways

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiment are not described here, and well-known functions and structures are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It should be understood that spatially relative terms such as "below", "under", "under", "under", "on", "above", etc. are used herein Descriptive convenience may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not to be taken as a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "consists of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude one or more other Presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

The term "layer" as used in this disclosure refers to a portion of material comprising a region having a thickness. A layer may extend across the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes there. Layers may extend horizontally, vertically and/or along the tapered surface. A substrate may be a layer, may include one or more layers, and/or may have one or more layers thereon, above, and/or below. Layers may include multiple layers. For example, interconnect layers may include one or more conductor and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

It should be noted that: "first", "second", etc. are used to distinguish similar objects, and not necessarily used to describe a specific order or sequence.

In order to understand the characteristics and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. The attached drawings are only for reference and description, and are not intended to limit the embodiments of the present disclosure.

In the field of manufacturing semiconductor devices, as the dimensions continue to shrink, the thickness of the dielectric layer continues to decrease. Using silicon oxide as the dielectric layer brings non-negligible gate leakage, so a high dielectric constant (high K) material is introduced during the preparation of the device dielectric layer. With the introduction of research, the use of metal gates to replace traditional polysilicon gates has become inevitable for the further development of devices.

In the related art, as shown in FIG. 1 , in the manufacturing process of MOS devices, various doped regions such as source, drain, pocket doping (Halo, implant), and lightly doped drain regions are first formed in the substrate. (LDD, Lightly Doped Drain); Next, an interfacial layer (silicon oxide layer in Fig. 1) and a high-K dielectric layer (High-k layer in Fig. 1) are formed on the substrate; Form the first work function layer (the first titanium nitride layer in Figure 1) and the metal gate (the aluminum layer in Figure 1) on the dielectric layer; The second titanium nitride layer in 1) and the polysilicon gate (the polysilicon layer in Figure 1); finally form side walls to protect each functional layer.

In practical applications, regardless of the gate-first process or the gate-last process, the material of the metal gate is usually aluminum, and aluminum atoms are prone to diffusion under high-temperature processes, and aluminum atoms diffuse to the first A work function layer or even a high-K dielectric layer reduces the effective work function (eWF) of the MOS device, thereby affecting the performance and reliability of the MOS device. Therefore, preventing the diffusion of metal atoms in the metal gate is the key to improving the performance of the MOS device. The essential.

One solution to the above problem is to improve the crystal structure of the first work function layer so that the aluminum atoms diffused in the metal gate will not pass through the first work function layer and continue to diffuse downward into the high-K dielectric layer . However, ion implantation into the first work function layer may affect the adjustment of the grid work function, and the blocking effect on the diffusion of aluminum atoms is not good enough.

In order to prevent the diffusion of metal atoms in the metal grid without affecting the adjustment function of the work function layer, in each embodiment of the present disclosure, before forming the metal grid, a layer of metal nitrogen that is the same as the metal element in the metal grid is pre-formed. layer or oxide layer, and then form the metal gate. It can be understood that the pre-formed metal nitride layer or oxide layer can fully absorb the metal atoms diffused from the metal gate; and, the metal nitride layer or oxide layer does not change the structure of the work function layer and will not affect the work function layer regulation. That is to say, the pre-formed metal nitride layer or oxide layer prevents further diffusion of metal atoms diffused from the metal gate to the high-k dielectric layer on the premise that the work function layer can normally adjust the work function of the device. The stability and reliability of the device are guaranteed.

In order to solve the problem of the diffusion of metal atoms in the metal gate stack structure, embodiments of the present disclosure provide a new growth solution of the metal gate stack structure. The new metal gate stack structure growth process provided by the embodiments of the present disclosure is applicable to but not limited to the important process steps of CMOS based on the High-k structure.

An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, and FIG. 2 is a schematic flowchart of an implementation of the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. As shown in Figure 2, the manufacturing method of the semiconductor structure includes:

Step 201: providing a substrate;

Step 202: forming a gate oxide layer on the substrate;

Step 203: forming a gate stack structure on the gate oxide layer; the gate stack structure at least includes: a barrier layer and a metal gate on the barrier layer; the metal contained in the metal gate The element is the same as the metal element contained in the barrier layer;

3a-3e are examples of cross-sectional views of a manufacturing process of a semiconductor structure provided by an embodiment of the present disclosure. It should be understood that the operations shown in FIG. 2 are not necessarily performed in an exact order. Instead, various steps may be processed in reverse order or concurrently. At the same time, other operations are either added to these procedures, or a certain step or steps are removed from these procedures. The method for forming the semiconductor structure according to the embodiment of the present disclosure will be described below with reference to FIG. 2 , and FIG. 3 a - FIG. 3 e .

It should be noted that the semiconductor structure is at least a part that will be used in subsequent processes to form a final device structure. The final devices here include but are not limited to MOS transistors, various electronic devices including MOS transistors such as memory devices, and the like.

Wherein, in step 201, as shown in FIG. 3a, a substrate 301 is provided.

In practical applications, the substrate 301 may include a single semiconductor material substrate (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (such as a silicon germanium (SiGe) substrate etc.), silicon-on-insulator (SOI) substrates, germanium-on-insulator (GeOI) substrates, etc. In some specific embodiments, the substrate 301 is a silicon substrate.

In practical applications, an isolation structure may also be formed in the substrate 301, the isolation structure is a shallow trench isolation (STI) structure or a local oxide of silicon (LOCOS) isolation structure, and the isolation structure divides the substrate 301 into different Active region, various semiconductor devices can be formed in the active region, such as N-type metal oxide semiconductor (NMOS, N Metal Oxide Semiconductor) and P-type metal oxide semiconductor (PMOS, P Metal Oxide Semiconductor). Various well structures are also formed in the semiconductor substrate 100 , which are omitted in FIG. 3 a for simplicity.

Next, in step 202, as shown in FIG. 3b, a gate oxide layer 302 is mainly formed.

In some embodiments, forming the gate oxide layer 302 on the substrate 301 includes:

forming an insulating layer 3021 on the substrate 301;

A dielectric layer 3022 is formed on the insulating layer 3021; the dielectric constant of the material of the dielectric layer 3022 is greater than 3.9.

Here, the material of the insulating layer 3021 (equivalent to the aforementioned interface layer) may include but not limited to silicon oxide; the material of the dielectric layer 3022 (equivalent to the aforementioned high-K dielectric layer) includes a high-K material, that is, dielectric A material with an electric constant higher than 3.9. In practical applications, the material of the dielectric layer 3022 may include but not limited to zirconia (ZrO ₂ ), hafnium oxide (HfO ₂ ), yttrium oxide (Y ₂ O ₃ ), aluminum oxide (Al ₂ O ₃ ).

In practical application, the insulating layer 3021 and the dielectric layer 3022 may adopt processes such as chemical vapor deposition (CVD, Chemical Vapor Deposition), physical vapor deposition (PVD, Physical Vapor Deposition), or atomic layer deposition (ALD, Atomic Layer Deposition). form.

It should be noted that the insulating layer 3021 here can be actively formed or passively formed when the dielectric layer 3022 is formed. It is desirable that the thickness of the insulating layer 3021 be as thin as possible, because the lower the K value of the insulating layer , the smaller the influence on the K value of the entire gate oxide layer.

Next, in step 203 , as shown in FIG. 3 c - FIG. 3 e , a gate stack structure 303 is mainly formed.

As mentioned above, in the implementation of the present disclosure, in the process of forming the gate stack structure, the barrier layer containing the same metal elements as the metal elements contained in the metal gate is first formed; and then the metal gate is formed on the barrier layer .

In some embodiments, forming the gate stack structure 303 on the gate oxide layer 302 includes:

Forming a metal layer 3032' on the gate oxide layer 302;

Doping the metal layer 3032' to form the barrier layer 3032;

A metal gate 3033 is formed on the barrier layer 3032 .

In practical application, the material of the metal gate 3033 includes but not limited to aluminum, tungsten (W) and the like. Wherein, in some embodiments, the metal elements contained in the metal gate 3033 and the metal layer 3032' are both aluminum.

It should be noted that the barrier layer 3032 is used to absorb metal atoms diffused from the metal gate 3033 to the direction of the gate oxide layer 302; and the metal gate 3033 is used as a gate, that is, the barrier layer 3032 and The metal gate 3033 has different functions, and based on the different functions of the two, the thickness of the metal layer 3032 ′ is different from that of the metal gate 3033 . In some embodiments, the thickness of the metal layer is smaller than the thickness of the metal gate.

Here, the process of forming the metal layer 3032' can refer to FIG. 3c. In practical application, the process of forming the metal layer 3032' can adopt CVD process or the like.

Here, the process of doping the metal layer 3032' can refer to Fig. 3d. In practical application, the doping treatment can be realized by ion implantation process. In some embodiments, the ion implantation process may be plasma implantation.

In some embodiments, the doping treatment of the metal layer 3032' includes:

Doping the metal layer 3032' with oxygen ions to obtain the barrier layer 3032 made of aluminum oxide (Al _x O _y );

or,

The metal layer 3032' is doped with nitrogen ions to obtain the barrier layer 3032 made of aluminum nitride (Al _x N _y ).

In practical applications, ions for ion implantation may include oxygen ions or nitrogen ions.

Exemplarily, the ion implanted is nitrogen ion. At this time, the implanted source gas can be nitrogen (N ₂ ), nitrogen oxide (N ₂ O or NO), etc., the energy of the nitrogen ion implantation can be 1keV-100keV, and the dose can be 1Ell atoms/cm ² -1E15 atoms /cm ² . Here, eV refers to electron volts, which can be expressed as electron Volt in English; atoms/cm ² is the number of atoms per square centimeter.

It should be noted that during the ion implantation process, the energy of the ion implantation needs to be controlled so that all the metals in the metal layer 3032' are oxidized or nitrided, so as to avoid introducing more possible downward diffusion. Metal.

Here, the process of forming the metal gate 3033 can refer to FIG. 3e. In practical application, the process of forming the metal gate 3033 may adopt CVD, ALD process and the like.

In practical applications, the gate stack structure 303 may include at least one work function layer and/or polysilicon layer in addition to the barrier layer 3032 and the metal gate 3033 .

In some embodiments, as shown in Figure 3c, the method further includes:

Before forming the barrier layer 3032, a first work function layer 3031 is formed on the gate oxide layer 302; the material of the first work function layer 3031 includes titanium nitride;

The formation of the metal layer 3032' on the gate oxide layer 302 includes;

The metal layer 3032' is formed on the first work function layer 3031.

In some embodiments, as shown in Figure 3d, the method further includes:

forming the metal gate 3033 covering the barrier layer 3032;

Forming a second work function layer 3034 on the metal gate 3033; the material of the second work function layer 3034 includes titanium nitride;

A polysilicon layer 3035 is formed on the second work function layer 3034 .

Here, the materials of the first work function layer 3031 and the second work function layer 3034 include but are not limited to titanium nitride (TiN), tantalum carbide (TaC), molybdenum nitride (MoN), tantalum nitride (TaN), etc. . In the embodiment of the present disclosure, the material of the first work function layer 3031 and the second work function layer 3034 is titanium nitride.

In practical applications, the first work function layer 3031 and the second work function layer 3034 may be formed by CVD, PVD, or ALD processes.

Here, a polysilicon layer may also be formed on the second work function layer 3034 . The first work function layer 3031/second work function layer 3034/polysilicon layer 3035 can be used to adjust the effective work function of the gate structure. It is understandable that in order to reduce the potential barrier between the metal and the semiconductor and lower the threshold voltage to turn on the transistor, the work function of the gate metal of the transistor is usually adjusted. In practical applications, the work function of the NMOS gate stack structure At around 4.2eV, the work function of the PMOS gate stack structure is around 5.1eV.

An example of a semiconductor structure manufacturing method is given below. Refer to FIG. 4 for the semiconductor structure formed in this example. In this example, the material of the metal gate is aluminum, and the material of the work function layer is titanium nitride.

Step 1: providing a substrate;

Step 2: Form various doped regions in the substrate, such as source and drain; Halo and LDD of the source; Halo and LDD of the drain; it should be noted that in practical applications, the gate structure can also be formed first, performing doping again to form doped regions;

Step 3: forming a gate oxide layer on the substrate, including a silicon oxide layer and/or a High-k layer (such as ZrO ₂ , HfO ₂ , Y ₂ O ₃ , Al ₂ O ₃ , etc.);

Step 4: depositing a first titanium nitride layer on the gate oxide layer;

Step five: pre-grow a thin Al layer on the first titanium nitride layer;

Step 6: doping the pre-grown Al layer with N or O ions, and forming an Al _x N _y layer or an Al _x O _y layer on the surface of the first work function layer by controlling the energy of ion implantation;

Step 7: continue to deposit an Al layer on the surface of the Al _x N _y layer or the Al _x O _y layer;

Step 8: forming a second titanium nitride layer on the Al layer;

Step 9: forming a polysilicon layer on the surface of the second titanium nitride layer;

Step Ten: Form the Side Walls.

In this example, a layer of Al is pre-grown, and ion implantation is performed on the pre-grown Al. On this basis, metal Al is deposited to optimize the metal gate stack and prevent the diffusion of Al atoms, thereby improving the stability of the semiconductor device.

Based on the above method for manufacturing a semiconductor structure, an embodiment of the present disclosure further provides a semiconductor structure, the semiconductor structure comprising:

Substrate;

a gate oxide layer on the substrate;

Wherein, in some embodiments, the metal elements contained in the metal gate and the barrier layer are both aluminum.

In some embodiments, the material of the barrier layer includes aluminum oxide or aluminum nitride.

In some embodiments, the barrier layer has a thickness smaller than that of the metal gate, and the barrier layer has a thickness greater than 0.2 nm.

In some embodiments, the gate stack structure further includes a work function adjustment layer, and the work function adjustment layer includes at least one of the following:

first work function layer;

second work function layer;

polysilicon layer;

In some embodiments, the gate oxide layer includes an insulating layer and a dielectric layer; the dielectric constant of the material of the dielectric layer is greater than 3.9.

It should be noted that each layer included in the above-mentioned semiconductor structure has been described in the foregoing manufacturing embodiments of the present disclosure, and will not be repeated here.

It should be understood that reference throughout the specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic related to the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of "in one embodiment" or "in an embodiment" in various places throughout the specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that in various embodiments of the present disclosure, the sequence numbers of the above-mentioned processes do not mean the order of execution, and the execution order of the processes should be determined by their functions and internal logic, rather than by the embodiments of the present disclosure. The implementation process constitutes any limitation. The serial numbers of the above-mentioned embodiments of the present disclosure are for description only, and do not represent the advantages and disadvantages of the embodiments.

The methods disclosed in several method embodiments provided in the present disclosure can be combined arbitrarily without conflict to obtain new method embodiments.

The above is only a specific implementation of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope of the present disclosure. should fall within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be determined by the protection scope of the claims.

Industrial Applicability

In the embodiment of the present disclosure, in the process of forming the gate stack structure, a barrier layer containing the same metal element as that contained in the metal gate is firstly formed; and then a metal gate is formed on the barrier layer. The previously formed barrier layer can fully absorb the metal elements diffused from the metal gate, that is, prevent the metal atoms in the metal gate from diffusing to the direction of the gate oxide layer, thereby ensuring the formation of the semiconductor structure. The stability of the electrical properties of semiconductor devices.

Claims

A semiconductor structure comprising:

Substrate;

a gate oxide layer on the substrate;

A gate stack structure located on the gate oxide layer; the gate stack structure at least includes: a barrier layer and a metal gate located on the barrier layer; the metal element contained in the metal gate and the metal gate The metal elements contained in the barrier layer are the same;

Wherein, the barrier layer is used to absorb metal atoms diffused from the metal gate toward the gate oxide layer.
The semiconductor structure according to claim 1, wherein the metal elements contained in the metal gate and the barrier layer are aluminum.
The semiconductor structure according to claim 2, wherein the material of the barrier layer comprises aluminum oxide or aluminum nitride.
The semiconductor structure according to claim 1, wherein the thickness of the barrier layer is smaller than the thickness of the metal gate, and the thickness of the barrier layer is greater than 0.2 nm.
The semiconductor structure according to claim 1, wherein the gate stack structure further comprises a work function adjustment layer, and the work function adjustment layer comprises at least one of the following:

first work function layer;

second work function layer;

polysilicon layer;

Wherein, the first work function layer is located between the gate oxide layer and the barrier layer; the second work function layer is located on the metal gate; the polysilicon layer is located on the second work function layer. layer; the materials of the first work function layer and the second work function layer both include titanium nitride.
The semiconductor structure according to claim 1, wherein the gate oxide layer comprises an insulating layer and a dielectric layer; the dielectric constant of the material of the dielectric layer is greater than 3.9.
A method of fabricating a semiconductor structure, comprising:

provide the substrate;

forming a gate oxide layer on the substrate;

A gate stack structure is formed on the gate oxide layer, and the gate stack structure at least includes: a barrier layer and a metal gate formed on the barrier layer, the metal element contained in the metal gate and the metal gate The metal elements contained in the barrier layer are the same;

Wherein, the barrier layer is used to absorb metal atoms diffused from the metal gate toward the gate oxide layer.
The manufacturing method according to claim 7, wherein the forming a gate stack structure on the gate oxide layer comprises:

forming a metal layer on the gate oxide layer;

performing doping treatment on the metal layer to form the barrier layer;

A metal gate is formed on the barrier layer.
The manufacturing method according to claim 8, wherein the metal elements contained in the metal gate and the barrier layer are both aluminum; the doping treatment of the metal layer includes:

performing oxygen ion doping treatment on the metal layer to obtain the barrier layer whose material includes aluminum oxide;

or,

Nitrogen ion doping treatment is performed on the metal layer to obtain the barrier layer covered with aluminum nitride.
The manufacturing method according to claim 9, wherein, when nitrogen ion doping is performed on the metal layer, the implanted source gas includes nitrogen or nitrogen oxide.
The manufacturing method according to claim 10, wherein, when nitrogen ion doping is performed on the metal layer, the energy range of the nitrogen ion implantation is 1keV-100keV; the dose range of the nitrogen ion implantation is 1E11 atoms /cm 2 -1E15 atoms/cm 2 .
The manufacturing method according to claim 8, wherein the method further comprises:

Before forming the blocking layer, a first work function layer is formed on the gate oxide layer; the material of the first work function layer includes titanium nitride;

The forming a metal layer on the gate oxide layer includes;

The metal layer is formed on the first work function layer.
The manufacturing method according to claim 8, wherein the method further comprises:

forming the metal gate overlying the barrier layer;

forming a second work function layer on the metal gate; the material of the second work function layer includes titanium nitride;

A polysilicon layer is formed on the second work function layer.
The manufacturing method according to claim 7, wherein said forming a gate oxide layer on said substrate comprises:

forming an insulating layer on the substrate;

A dielectric layer is formed on the insulating layer; the dielectric constant of the material of the dielectric layer is greater than 3.9.