WO2023123823A1 - 一种基于 rs485 的单线半双工转换电路 - Google Patents

一种基于 rs485 的单线半双工转换电路 Download PDF

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Publication number
WO2023123823A1
WO2023123823A1 PCT/CN2022/092883 CN2022092883W WO2023123823A1 WO 2023123823 A1 WO2023123823 A1 WO 2023123823A1 CN 2022092883 W CN2022092883 W CN 2022092883W WO 2023123823 A1 WO2023123823 A1 WO 2023123823A1
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Prior art keywords
analog comparator
pin
resistor
diode
serial port
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PCT/CN2022/092883
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English (en)
French (fr)
Inventor
周荣
吴金炳
樊晓臻
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苏州路之遥科技股份有限公司
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Publication of WO2023123823A1 publication Critical patent/WO2023123823A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/14—Two-way operation using the same type of signal, i.e. duplex
    • H04L5/16—Half-duplex systems; Simplex/duplex switching; Transmission of break signals non-automatically inverting the direction of transmission

Definitions

  • the invention relates to the technical field of communication, in particular to an RS485-based single-wire half-duplex conversion circuit.
  • the circuit using RS485 communication requires more data lines and the circuit is more complicated.
  • the existing single-wire two-way communication needs to be established on the premise that the peripheral device and the host power supply level are consistent. If the two levels are inconsistent, the device is easy to be damaged and the reliability is low.
  • RS485 uses two lines for signal transmission, and a half-duplex mode transceiver is selected to connect the RS485 signal terminal and the UART signal terminal, that is, through a one-way signal
  • a half-duplex mode transceiver is selected to connect the RS485 signal terminal and the UART signal terminal, that is, through a one-way signal
  • the embodiment of the present invention provides an RS485-based single-wire half-duplex conversion circuit to solve the problems in the prior art that circuits using RS485 communication have low reliability and conflicts in data transmission and reception.
  • the embodiment of the present invention provides a RS485-based single-wire half-duplex conversion circuit, including:
  • RS485 differential driver chip its first serial port pin and second serial port pin are respectively connected with RS485 signal input end and RS485 signal output end;
  • the first analog comparator its IN+ pin is connected to the UART serial bus, and the output end of the first analog comparator is connected to the third serial port pin of the RS485 differential drive chip;
  • the second analog comparator its IN-pin is connected to the fourth serial port pin of the RS485 differential drive chip; the output terminal of the second analog comparator is connected to the UART serial bus;
  • RC time-lock circuit its first input end is connected with the output end of the first analog comparator, the second input end of RC time-lock circuit is connected with the IN- pin of the first analog comparator; The second input end of RC time-lock circuit The terminal is also connected with the output terminal of the second analog comparator U3A; the output terminal of the RC time-lock circuit is connected with the signal direction control pin of the RS485 differential driver chip.
  • the first diode one end of which is connected between the first serial port pin and the RS485 signal input end, and the other end of the first diode is grounded;
  • the second diode one end of which is connected between the second serial port pin and the RS485 signal output end, and the other end of the second diode is grounded;
  • One end of the third diode is connected between the RS485 signal input end and the first serial port pin, and the other end of the third diode is connected between the RS485 signal output end and the second serial port pin.
  • the UART serial bus and the RS485 differential driver chip also includes: a fourth diode; the cathode of the fourth diode is connected to the UART serial bus; the anode of the fourth diode is connected to the first The IN+ pin of the analog comparator is connected; the output terminal of the first analog comparator is connected with the third serial port pin.
  • the RC time-lock circuit includes:
  • the third analog comparator whose output terminal is connected to the RE pin and DE pin of the RS485 differential drive chip at the same time; the IN- pin of the third analog comparator is connected to the output terminal of the first analog comparator through the fifth diode ;
  • the IN-pin of the third analog comparator is connected to the anode of the fifth diode; the output terminal of the first analog comparator is connected to the cathode of the fifth diode; the IN+ pin of the third analog comparator is compared with the first The IN-pin connection of the simulator;
  • the first resistor one end of which is connected to the IN+ pin of the third analog comparator, and the other end of the first resistor is connected to a high level;
  • a second resistor one end of which is connected to the IN+ pin of the third analog comparator, and the other end of the second resistor is grounded;
  • the first capacitor one end of which is connected to the IN+ pin of the third analog comparator, and the other end of the first capacitor is grounded;
  • a third resistor one end of which is connected to the IN- pin of the third analog comparator, and the other end of the third resistor is connected to a high level;
  • a fourth resistor one end of which is connected to the IN-pin of the third analog comparator, and the other end of the fourth resistor is grounded;
  • a second capacitor one end of which is connected to the IN-pin of the third analog comparator, and the other end of the second capacitor is grounded;
  • the resistance value of the first resistor is greater than the resistance value of the second resistor; the resistance value of the third resistor is the same as that of the fourth resistor; the capacitance of the first capacitor is smaller than that of the second capacitor.
  • the IN-pin of the second analog comparator is connected to the fourth serial port pin of the RSS485 differential driver chip through the sixth diode; the anode of the sixth diode is connected to the IN-pin of the second analog comparator ; The cathode of the sixth diode is connected to the fourth serial port pin of the RSS485 differential drive chip.
  • the IN+ pin of the second analog comparator is connected to the output terminal of the first analog comparator through the fifth resistor; the seventh diode is connected in parallel with both ends of the fifth resistor, and the anode of the seventh diode is connected to the The IN+ pin of the second analog comparator is connected, and the cathode of the seventh diode is connected with the output terminal of the first analog comparator; the output terminal of the second analog comparator is connected with the IN- pin of the first analog comparator; the second The IN+ pin of the analog comparator is also connected to the third capacitor.
  • it also includes: a fourth analog comparator; wherein, the IN-pin of the fourth analog comparator is connected to the output terminal of the second analog comparator; the output terminal of the fourth analog comparator is connected to the output terminal of the first analog comparator
  • the IN- pin is connected; the IN+ pin of the fourth analog comparator is respectively connected to one end of the sixth resistor and one end of the seventh resistor; the other end of the sixth resistor is connected to a high level; the other end of the seventh resistor is grounded.
  • it also includes: a first field effect transistor, the drain of which is connected to the UART serial bus; the gate of the first field effect transistor is connected to the output terminal of the second analog comparator through an eighth resistor; the first field effect transistor The source of the tube is grounded; wherein, the IN-pin of the fourth analog comparator is connected between the output terminal of the second analog comparator and the eighth resistor.
  • a second field effect transistor the drain of which is connected to the IN-pin of the first analog comparator; the gate of the second field effect transistor is connected to the output end of the second analog comparator through a ninth resistor ;
  • the source of the second FET is grounded; one end of the ninth resistor is connected to the gate of the second FET; the other end of the ninth resistor is connected to the output terminal of the second analog comparator; the other end of the ninth resistor It is also connected with one end of the tenth resistor; the other end of the tenth resistor is grounded.
  • the circuit By setting the first analog comparator, the second analog comparator and the RC time lock circuit, the signals of the UART terminal and the RS485 terminal are obtained respectively, and the signals of the UART terminal and the RS485 terminal are used as two input signals of the RC time lock circuit to make the RC time lock
  • the circuit outputs high level or low level to control the working mode of the RS485 differential driver chip, thereby realizing single-line half-duplex data conversion based on RS485.
  • Fig. 1 shows a kind of UART partial circuit connection diagram in the RS485-based single-wire half-duplex conversion circuit in the embodiment of the present invention
  • Fig. 2 shows a RS485 partial circuit connection diagram in a RS485-based single-wire half-duplex conversion circuit in an embodiment of the present invention
  • FIG. 3 shows a circuit connection diagram of part of the UART in another RS485-based single-wire half-duplex conversion circuit in an embodiment of the present invention.
  • the embodiment of the present invention provides a RS485-based single-wire half-duplex conversion circuit, as shown in Figure 1 and Figure 2, including RS485 differential drive chip U2, first analog comparator U3B, second analog comparator U3A and RC time lock circuit, where:
  • the first serial port pin and the second serial port pin of the RS485 differential driver chip U2 are connected to the RS485 signal input terminal and the RS485 signal output terminal respectively;
  • the IN+ pin of the first analog comparator U3B is connected to the UART serial bus, and the output end of the first analog comparator U3B is connected to the third serial port pin of the RS485 differential drive chip;
  • the IN-pin of the second analog comparator U3A is connected to the fourth serial port pin of the RS485 differential drive chip; the output terminal of the second analog comparator U3A is connected to the UART serial bus;
  • the first input end of the RC time-lock circuit is connected with the output end of the first analog comparator U3B, and the second input end of the RC time-lock circuit is connected with the IN- pin of the first analog comparator U3B;
  • the input terminal is also connected with the output terminal of the second analog comparator U3A;
  • the output terminal of the RC time-lock circuit is connected with the signal direction control pin of the RS485 differential drive chip.
  • the RS485 differential drive chip adopts SN65LBC184DR, pins 1, 4, 6, and 7 are serial port pins, pins 6 and 7 are respectively connected to the input and output ends of the RS485 signal, and pin 1 is the output of the RS485 signal Terminal, pin 4 is the input terminal of the UART serial port signal.
  • the function of the first analog comparator is to filter the UART serial signal, and only output high level or low level.
  • the function of the second analog comparator is to filter the RS485 signal processed by the RS485 differential driver chip.
  • the two input signals of the RC time-locked circuit are the output signal of the first analog comparator and the output signal of the second analog comparator respectively.
  • the RC time-lock circuit compares the output signal of the first analog comparator with the output signal of the second analog comparator through the third analog comparator, for example, the output of the first analog comparator
  • the signal is high level, and at the same time the output signal of the second analog comparator is low level, then the third analog comparator outputs high level, which is sent to the RE/DE pin of the RS485 differential driver chip to make the RS485 differential driver chip work
  • the state is switched to receive enable, and the signal transmission direction is: UART terminal to RS485 terminal.
  • the RS485 differential driver chip working state is switched to transmit enable, realizing data transmission from the RS485 end to the UART end.
  • the circuit By setting the first analog comparator, the second analog comparator and the RC time lock circuit, the signals of the UART terminal and the RS485 terminal are obtained respectively, and the signals of the UART terminal and the RS485 terminal are used as two input signals of the RC time lock circuit to make the RC time lock
  • the circuit outputs high level or low level to control the working mode of the RS485 differential driver chip, thereby realizing single-line half-duplex data conversion based on RS485.
  • it also includes: a first diode D8, one end of which is connected between the first serial port pin and the RS485 signal input end, and the other end of the first diode D8 is grounded; the second diode D10, one end of which is connected between the second serial port pin and the RS485 signal output end, the other end of the second diode D10 is grounded; the third diode D7, one end of which is connected between the RS485 signal input end and the first serial port Between the pins, the other end of the third diode D7 is connected between the RS485 signal output end and the second serial port pin.
  • the ESD protection of the circuit is realized by setting three diodes, so as to prevent the circuit from being damaged when the RS485 input/output signal has a momentary high current.
  • the UART serial bus and the RS485 differential drive chip also includes: a fourth diode D3; the cathode of the fourth diode D3 is connected to the UART serial bus; the fourth diode D3 The anode of the first analog comparator U3B is connected to the IN+ pin; the output terminal of the first analog comparator U3B is connected to the third serial port pin.
  • pull-up resistors are respectively connected to both ends of the fourth diode D3 to suppress reflected wave interference.
  • the anode of the fourth diode D3 is connected to the IN+ pin of the first analog comparator, and the cathode of the fourth diode D3 is connected to the UART serial bus. Assuming that the UART serial bus outputs a low level, the fourth diode The cathode of D3 is affected by the right circuit, the voltage drops, and at the same time, the anode voltage of the fourth diode D3 is pulled down.
  • the IN+ pin voltage of the first analog comparator U3B is lower than the IN- pin voltage, and the first analog comparator The device U3B outputs low level to make the RE pin of RS485 differential driver chip U2 work and trigger the receiving enable.
  • the signal transmission mode of RS485 differential driver chip U2 is data transmission from pin 4 to pin 6 and pin 7; otherwise, the first analog The comparator U3B outputs a high level, enabling the transmission of the DE pin of the RS485 differential driver chip U2, and triggering the working mode of signal transmission from pin 6 and pin 7 to pin 1.
  • the RC time lock circuit includes:
  • the third analog comparator U3C its output terminal is connected with the RE pin and the DE pin of the RS485 differential drive chip U2 at the same time; the IN- pin of the third analog comparator U3C is connected with the first analog comparator through the fifth diode D5 The output end of U3B is connected; the IN- pin of the third analog comparator U3C is connected with the anode of the fifth diode D5; the output end of the first analog comparator U3B is connected with the cathode of the fifth diode D5; the third analog The IN+ pin of the comparator U3C is connected with the IN- pin of the first comparison simulator U3B;
  • One end of the first resistor R28 is connected to the IN+ pin of the third analog comparator U3C, and the other end of the first resistor R28 is connected to a high level;
  • the second resistor R32 one end of which is connected to the IN+ pin of the third analog comparator U3C, and the other end of the second resistor R32 is grounded;
  • the first capacitor C11 one end of which is connected to the IN+ pin of the third analog comparator U3C, and the other end of the first capacitor C11 is grounded;
  • the third resistor R30 one end of which is connected to the IN- pin of the third analog comparator U3C, and the other end of the third resistor R30 is connected to a high level;
  • the fourth resistor R31 one end of which is connected to the IN- pin of the third analog comparator U3C, and the other end of the fourth resistor R31 is grounded;
  • the second capacitor C12 one end of which is connected to the IN- pin of the third analog comparator U3C, and the other end of the second capacitor C12 is grounded;
  • the resistance value of the first resistor R28 is greater than the resistance value of the second resistor R32; the resistance value of the third resistor R30 is the same as the resistance value of the fourth resistor R31; the capacitance of the first capacitor C11 is smaller than the capacitance of the second capacitor C12 .
  • the RC time-lock circuit adopts the third analog comparator U3C, and a group of RC circuits are respectively arranged at the two input terminals of the third analog comparator U3C, and the RC circuit includes a pull-up resistor, a pull-down resistor and a capacitor.
  • the resistance value of the pull-up resistor connected to the IN+ pin of the third analog comparator U3C is greater than the resistance value of the pull-down resistor. Its working principle is: when the input signal changes, the RC capacitor is charged and discharged.
  • the initial state is set to V IN- > V IN+
  • the third analog comparator outputs low level by default
  • the input signal changes that is, V IN- ⁇ V IN+
  • the first capacitor C11 is charged, when the input signal returns to V IN- >V IN+ , the first capacitor C11 discharges, and because the resistance of the first resistor is greater than the resistance of the second resistor, the first The capacitance of the capacitor C11 is smaller than the capacitance of the second capacitor C12, and the discharge duration of the two capacitors is different.
  • the voltages at the two input terminals of the third analog comparator keep V IN- ⁇ V IN+ , realizing
  • the IN+ pin of the third analog comparator U3C always maintains a high level state, and the third analog comparator U3C always outputs a high level. Level, so as to control the RE/DE state of the RS485 differential driver chip to keep sending enabled.
  • the IN- pin of the second analog comparator U3A is connected to the fourth serial port pin of the RSS485 differential driver chip U2 through the sixth diode D4; the anode of the sixth diode D4 is connected to the second analog The IN-pin of the comparator U3A is connected; the cathode of the sixth diode D4 is connected to the fourth serial port pin of the RSS485 differential driver chip U2.
  • the signal interference of the circuit between the IN+ pin of the second analog comparator and the RS485 differential driver chip is eliminated through the sixth diode D4. Both ends of the sixth diode D4 are respectively connected with a pull-up resistor.
  • the signal received by the IN- pin of the second analog comparator U3A changes, the output of the second analog comparator U3A also changes accordingly, and the output of the second analog comparator U3A is the input of the third analog comparator U3C
  • One of the signals, that is, through the circuit in this embodiment, the precise control of the RC time-locked circuit can be realized based on the RS485 signal.
  • the IN+ pin of the second analog comparator U3A is connected to the output terminal of the first analog comparator U3B through the fifth resistor R23; the seventh diode D6 is connected in parallel to both ends of the fifth resistor R23, and The anode of the seventh diode D6 is connected with the IN+ pin of the second analog comparator U3A, and the cathode of the seventh diode D6 is connected with the output end of the first analog comparator U3B; the output end of the second analog comparator U3A is connected with The IN-pin of the first analog comparator U3B is connected.
  • the IN+ pin of the second analog comparator U3A is also respectively connected to the pull-down resistor R26 and the third capacitor C13, and the other end of the third capacitor C13 is grounded.
  • the fifth resistor R23 and the pull-down resistor R26 provide voltage division.
  • the seventh diode D6 quickly transfers the third capacitor C13 The voltage of is pulled low, so that the output of the second analog comparator U3A is low.
  • the drain of the first field effect transistor Q1 is connected to the UART serial bus; the gate of the first field effect transistor Q1 is connected to the output terminal of the second analog comparator U3A through the eighth resistor R13; the first The source of the field effect transistor Q1 is grounded; wherein, the IN- pin of the fourth analog comparator U3D is connected between the output terminal of the second analog comparator U3A and the eighth resistor R13.
  • a field effect transistor Q1 is also connected between the UART serial bus and the second analog comparator U3A. Turns on at very high voltage. When the output of the second analog comparator U3A is low, the FET is quickly turned off.
  • the premise that the output of the first analog comparator U3B is low is that the output of the UART serial bus is low, that is to say, if there is data sent from the UART serial bus first, then the FET Q1 must be disconnected to avoid affecting the subsequent UART data output.
  • the output of the first analog comparator U3B is at a high level, the voltage of the third capacitor C13 rises through the fifth resistor R23.
  • it also includes: a fourth analog comparator U3D; wherein, the IN-pin of the fourth analog comparator U3D is connected to the output terminal of the second analog comparator U3A; the output terminal of the fourth analog comparator U3D Connect with the IN-pin of the first analog comparator U3B; connect the IN+ pin of the fourth analog comparator U3D with one end of the sixth resistor R11 and one end of the seventh resistor R17 respectively; connect the other end of the sixth resistor R11 with high level ; The other end of the seventh resistor R17 is grounded.
  • a fourth analog comparator U3D wherein, the IN-pin of the fourth analog comparator U3D is connected to the output terminal of the second analog comparator U3A; the output terminal of the fourth analog comparator U3D Connect with the IN-pin of the first analog comparator U3B; connect the IN+ pin of the fourth analog comparator U3D with one end of the sixth resistor R11 and one end of the seventh resistor R17 respectively; connect the other end of the sixth resist
  • the fourth analog comparator U3D when the second analog comparator U3A outputs a low level, the fourth analog comparator U3D outputs a low level, and the output terminal of the fourth analog comparator U3D is connected to the first capacitor C11, so the first capacitor C11 When the fourth analog comparator U3D outputs a low voltage, it discharges quickly, so that the third analog comparator U3C outputs a low level, triggering the reception enable of the RS485 differential driver chip.
  • the function of the fourth analog comparator U3D in this embodiment can also be realized by a MOSFET:
  • the drain of the second field effect transistor Q2 is connected to the IN-pin of the first analog comparator U3B; the gate of the second field effect transistor Q2 is connected to the second analog comparator U3A through the ninth resistor R20
  • the output end is connected; the source of the second field effect transistor Q2 is grounded; one end of the ninth resistor R20 is connected to the gate of the second field effect transistor Q2; the other end of the ninth resistor R20 is connected to the output end of the second analog comparator U3A
  • the other end of the ninth resistor R20 is also connected to one end of the tenth resistor R22; the other end of the tenth resistor R22 is grounded.
  • the second field effect transistor Q2 is a depletion MOSFET.
  • the field effect transistor When the gate voltage is at a low level, the field effect transistor is turned off, and when the gate voltage is at a high level, the field effect transistor is turned on.
  • the second analog comparator When the second analog comparator outputs a high level, V IN- >V IN+ of the fourth analog comparator, the fourth analog comparator outputs a low level, and both the first FET Q1 and the second FET Q2 are turned on , the UART serial bus is grounded, the IN- pin of the first analog comparator U3B is grounded, the IN+ pin of the third analog comparator U3C is grounded, and the first capacitor C11 is quickly discharged through the second field effect transistor Q2.
  • the first capacitor C11 is slowly charged through the first resistor R28 and the second resistor R32 until the voltage of the first capacitor C11 rises to the point where the voltage at the IN+ pin of the third analog comparator U3C is higher than the voltage at the CIN- pin of the third analog comparator U3C .
  • the RC time lock circuit outputs a low level when it is idle, that is, the default signal transmission direction is RS485 to send data to the UART serial bus.
  • the UART When the UART sends data, its start bit is a low level, then the IN+ pin of the first analog comparator U3B is pulled low by the output of the UART serial bus, and the first analog comparator U3B outputs a low level. At this time, the second capacitor C12 pulls down the voltage through the low level at the cathode of the fifth diode, and quickly discharges it.
  • the first analog comparator U3B When the first analog comparator U3B outputs a low level, the third capacitor C13 at the input terminal of the second analog comparator U3A is rapidly discharged through the seventh diode, and the third capacitor C13 is slowly charged through the fifth resistor R23 and the pull-down resistor R26, The second analog comparator U3A outputs a low level.
  • the IN- pin input of the fourth analog comparator U3D is the low level output by the second analog comparator U3A, and the fourth analog comparator U3D outputs a high level, which pulls up the voltage of the first capacitor C11, so that the third analog comparator U3C outputs a high level to switch the RS485 differential driver chip to enable transmission.
  • the second capacitor C12 is voltage-divided by the third resistor R30 and the fourth resistor R31, and charged slowly. Before the voltage of the second capacitor C12 is higher than the voltage of the first capacitor C11, the third analog comparator always outputs a high level. Specifically, the parameter condition of the capacitor resistance is: the charging time of the first capacitor is longer than the time interval between two adjacent low levels sent by the UART.

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Abstract

本发明公开了一种基于RS485的单线半双工转换电路，包括：RS485差分驱动芯片，其第一串口引脚和第二串口引脚分别与RS485信号输入/输出端连接；第一模拟比较器，其IN+脚与UART串行总线连接，第一模拟比较器的输出端与第三串口引脚连接；第二模拟比较器，其IN-脚与RS485差分驱动芯片的第四串口引脚连接；第二模拟比较器的输出端与UART串行总线连接；RC时间锁定电路，其第一输入端与第一模拟比较器的输出端连接，RC时间锁定电路的第二输入端与第一模拟比较器的IN-脚连接；RC时间锁定电路的第二输入端还与第二模拟比较器的输出端连接；RC时间锁定电路的输出端与RS485差分驱动芯片的信号方向控制引脚连接。

Description

一种基于RS485的单线半双工转换电路 技术领域
本发明涉及通信技术领域，具体涉及一种基于RS485的单线半双工转换电路。
 背景技术
如今市场上的通讯配件越来越多，同时其规格参数种类繁多，主机与各个外围器件进行通信的需求也越来越多。
目前使用RS485通信的电路，需要的数据线较多，电路较为复杂。现有的单线双向通信需要建立在外围器件与主机电源电平一致的前提下，若两者电平不一致，则容易损坏器件，可靠性较低。为实现RS485与UART信号互发功能，由于UART端采用单线进行信号传输，RS485采用双线进行信号传输，选择半双工模式的收发器以连接RS485信号端和UART信号端，即通过单向信号传输的存在数据收发冲突的问题。
 技术问题
有鉴于此，本发明实施例提供了一种基于RS485的单线半双工转换电路，以解决现有技术中使用RS485通信的电路可靠性较低、数据收发存在冲突的问题。
 技术解决方案
本发明实施例提供了一种基于RS485的单线半双工转换电路，包括：
RS485差分驱动芯片，其第一串口引脚和第二串口引脚分别与RS485信号输入端和RS485信号输出端连接；
第一模拟比较器，其IN+脚与UART串行总线连接，第一模拟比较器的输出端与RS485差分驱动芯片的第三串口引脚连接；
第二模拟比较器，其IN-脚与RS485差分驱动芯片的第四串口引脚连接；第二模拟比较器的输出端与UART串行总线连接；
RC时间锁定电路，其第一输入端与第一模拟比较器的输出端连接，RC时间锁定电路的第二输入端与第一模拟比较器的IN-脚连接；RC时间锁定电路的第二输入端还与第二模拟比较器U3A的输出端连接；RC时间锁定电路的输出端与RS485差分驱动芯片的信号方向控制引脚连接。
可选地，还包括：
第一二极管，其一端接在第一串口引脚和RS485信号输入端之间，第一二极管的另一端接地；
第二二极管，其一端接在第二串口引脚和RS485信号输出端之间，第二二极管的另一端接地；
第三二极管，其一端接在在RS485信号输入端和第一串口引脚之间，第三二极管的另一端接在RS485信号输出端和第二串口引脚之间。
可选地，在UART串行总线和RS485差分驱动芯片之间还包括：第四二极管；第四二极管的阴极与UART串行总线连接；第四二极管的阳极连接与第一模拟比较器的IN+脚连接；第一模拟比较器的输出端与第三串口引脚连接。
可选地，RC时间锁定电路包括：
第三模拟比较器，其输出端同时与RS485差分驱动芯片的RE引脚和DE引脚连接；第三模拟比较器的IN-脚通过第五二极管与第一模拟比较器的输出端连接；第三模拟比较器的IN-脚与第五二极管的阳极连接；第一模拟比较器的输出端与第五二极管的阴极连接；第三模拟比较器的IN+脚与第一比较模拟器的IN-脚连接；
第一电阻，其一端与第三模拟比较器的IN+脚连接，第一电阻的另一端接高电平；
第二电阻，其一端与第三模拟比较器的IN+脚连接，第二电阻的另一端接地；
第一电容，其一端与第三模拟比较器的IN+脚连接，第一电容的另一端接地；
第三电阻，其一端与第三模拟比较器的IN-脚连接，第三电阻的另一端接高电平；
第四电阻，其一端与第三模拟比较器的IN-脚连接，第四电阻的另一端接地；
第二电容，其一端与第三模拟比较器的IN-脚连接，第二电容的另一端接地；
其中，第一电阻的阻值大于第二电阻的阻值；第三电阻的阻值与第四电阻的阻值相同；第一电容的电容量小于第二电容的电容量。
可选地，第二模拟比较器的IN-脚通过第六二极管与RSS485差分驱动芯片的第四串口引脚连接；第六二极管的阳极与第二模拟比较器的IN-脚连接；第六二极管的阴极与RSS485差分驱动芯片的第四串口引脚连接。
可选地，第二模拟比较器的IN+脚通过第五电阻与第一模拟比较器的输出端连接；第七二极管并联在第五电阻的两端，且第七二极管的阳极与第二模拟比较器的IN+脚连接，第七二极管的阴极与第一模拟比较器的输出端连接；第二模拟比较器的输出端与第一模拟比较器的IN-脚连接；第二模拟比较器的IN+脚还与第三电容连接。
可选地，还包括：第四模拟比较器；其中，第四模拟比较器的IN-脚与第二模拟比较器的输出端连接；第四模拟比较器的输出端与第一模拟比较器的IN-脚连接；第四模拟比较器的IN+脚分别与第六电阻的一端和第七电阻的一端连接；第六电阻的另一端接高电平；第七电阻的另一端接地。
可选地，还包括：第一场效应管，其漏极与UART串行总线连接；第一场效应管的栅极通过第八电阻与第二模拟比较器的输出端连接；第一场效应管的源极接地；其中，第四模拟比较器的IN-脚接在第二模拟比较器的输出端和第八电阻之间。
可选地，还包括：第二场效应管，其漏极与第一模拟比较器的IN-脚连接；第二场效应管的栅极通过第九电阻与第二模拟比较器的输出端连接；第二场效应管的源极接地；第九电阻的一端与第二场效应管的栅极连接；第九电阻的另一端与第二模拟比较器的输出端连接；第九电阻的另一端还与第十电阻的一端连接；第十电阻的另一端接地。
 有益效果
通过设置第一模拟比较器、第二模拟比较器和RC时间锁定电路，分别获取UART端和RS485端的信号，将UART端和RS485端的信号作为RC时间锁定电路的两个输入信号，使RC时间锁定电路输出高电平或低电平，控制RS485差分驱动芯片的工作模式，从而实现基于RS485的单线半双工数据转换。
 附图说明
通过参考附图会更加清楚的理解本发明的特征和优点，附图是示意性的而不应理解为对本发明进行任何限制，在附图中：
图1示出了本发明实施例中一种基于RS485的单线半双工转换电路中UART部分电路连接图；
图2示出了本发明实施例中一种基于RS485的单线半双工转换电路中RS485部分电路连接图
图3示出了本发明实施例中另一种基于RS485的单线半双工转换电路中UART部分电路连接图。
 本发明的实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供了一种基于RS485的单线半双工转换电路，如图1和图2所示，包括RS485差分驱动芯片U2、第一模拟比较器U3B、第二模拟比较器U3A和RC时间锁定电路，其中：
RS485差分驱动芯片U2的第一串口引脚和第二串口引脚分别与RS485信号输入端和RS485信号输出端连接；
第一模拟比较器U3B的IN+脚与UART串行总线连接，第一模拟比较器U3B的输出端与RS485差分驱动芯片的第三串口引脚连接；
第二模拟比较器U3A的IN-脚与RS485差分驱动芯片的第四串口引脚连接；第二模拟比较器U3A的输出端与UART串行总线连接；
RC时间锁定电路的第一输入端与第一模拟比较器U3B的输出端连接，RC时间锁定电路的第二输入端与第一模拟比较器U3B的IN-脚连接；RC时间锁定电路的第二输入端还与第二模拟比较器U3A的输出端连接；RC时间锁定电路的输出端与RS485差分驱动芯片的信号方向控制引脚连接。
在本实施例中，RS485差分驱动芯片采用SN65LBC184DR，1、4、6、7脚为串口引脚，6脚和7脚分别与RS485信号的输入端和输出端连接，1脚为RS485信号的输出端，4脚为UART串口信号的输入端。
第一模拟比较器的作用是对UART串行信号进行滤波，只输出高电平或者低电平。第二模拟比较器的作用是对经过RS485差分驱动芯片处理的RS485信号进行滤波。
RC时间锁定电路的两个输入信号分别是第一模拟比较器的输出信号和第二模拟比较器的输出信号。在具体实施例中，RC时间锁定电路通过第三模拟比较器对第一模拟比较器的输出信号和第二模拟比较器的输出信号进行电平高低的比较，例如，第一模拟比较器的输出信号为高电平，同时第二模拟比较器的输出信号是低电平，则第三模拟比较器输出高电平，发送到RS485差分驱动芯片的RE/DE引脚，使RS485差分驱动芯片工作状态切换为接收使能，信号传输方向为：UART端至RS485端。反之，RS485差分驱动芯片工作状态切换为发送使能，实现数据从RS485端向UART端的传输。
通过设置第一模拟比较器、第二模拟比较器和RC时间锁定电路，分别获取UART端和RS485端的信号，将UART端和RS485端的信号作为RC时间锁定电路的两个输入信号，使RC时间锁定电路输出高电平或低电平，控制RS485差分驱动芯片的工作模式，从而实现基于RS485的单线半双工数据转换。
作为可选的实施方式，还包括：第一二极管D8，其一端接在第一串口引脚和RS485信号输入端之间，第一二极管D8的另一端接地；第二二极管D10，其一端接在第二串口引脚和RS485信号输出端之间，第二二极管D10的另一端接地；第三二极管D7，其一端接在在RS485信号输入端和第一串口引脚之间，第三二极管D7的另一端接在RS485信号输出端和第二串口引脚之间。
在本实施例中，如图2所示，通过设置三个二极管实现对电路的ESD保护，避免RS485输入/输出信号出现瞬间大电流时，损坏电路。
作为可选的实施方式，在UART串行总线和RS485差分驱动芯片之间还包括：第四二极管D3；第四二极管D3的阴极与UART串行总线连接；第四二极管D3的阳极连接与第一模拟比较器U3B的IN+脚连接；第一模拟比较器U3B的输出端与第三串口引脚连接。
在本实施例中，如图1所示，第四二极管D3两端还分别连接了上拉电阻，作用是抑制反射波干扰。第四二极管D3的阳极与第一模拟比较器的IN+脚连接，第四二极管D3的阴极与UART串行总线连接，假设UART串行总线输出低电平，则第四二极管D3的阴极受到右侧电路的影响，电压降低，同时拉低第四二极管D3的阳极电压降低，此时第一模拟比较器U3B的IN+脚电压低于IN-脚电压，第一模拟比较器U3B输出低电平，使RS485差分驱动芯片U2的RE脚工作，触发接收使能，RS485差分驱动芯片U2的信号传输模式为数据从4脚传输至6脚、7脚；反之，第一模拟比较器U3B输出高电平，使RS485差分驱动芯片U2的DE脚发送使能，触发由6脚和7脚向1脚信号传输的工作模式。
作为可选的实施方式，RC时间锁定电路包括：
第三模拟比较器U3C，其输出端同时与RS485差分驱动芯片U2的RE引脚和DE引脚连接；第三模拟比较器U3C的IN-脚通过第五二极管D5与第一模拟比较器U3B的输出端连接；第三模拟比较器U3C的IN-脚与第五二极管D5的阳极连接；第一模拟比较器U3B的输出端与第五二极管D5的阴极连接；第三模拟比较器U3C的IN+脚与第一比较模拟器U3B的IN-脚连接；
第一电阻R28，其一端与第三模拟比较器U3C的IN+脚连接，第一电阻R28的另一端接高电平；
第二电阻R32，其一端与第三模拟比较器U3C的IN+脚连接，第二电阻R32的另一端接地；
第一电容C11，其一端与第三模拟比较器U3C的IN+脚连接，第一电容C11的另一端接地；
第三电阻R30，其一端与第三模拟比较器U3C的IN-脚连接，第三电阻R30的另一端接高电平；
第四电阻R31，其一端与第三模拟比较器U3C的IN-脚连接，第四电阻R31的另一端接地；
第二电容C12，其一端与第三模拟比较器U3C的IN-脚连接，第二电容C12的另一端接地；
其中，第一电阻R28的阻值大于第二电阻R32的阻值；第三电阻R30的阻值与第四电阻R31的阻值相同；第一电容C11的电容量小于第二电容C12的电容量。
如图1所示，RC时间锁定电路采用第三模拟比较器U3C，并在第三模拟比较器U3C的两个输入端分别设置一组RC电路，RC电路包括一上拉电阻、一下拉电阻和一电容。与第三模拟比较器U3C的IN+脚连接的上拉电阻的阻值大于下拉电阻的阻值。其工作原理为：当输入信号发生变化时，RC电容发生充放电现象，例如，初始状态设置为V IN-＞V IN+，第三模拟比较器默认输出低电平，输入信号发生变化，即V IN-＜V IN+，第一电容C11充电，当输入信号又变回V IN-＞V IN+时，第一电容C11放电，又由于第一电阻的阻值大于第二电阻的阻值，第一电容C11的电容量小于第二电容C12的电容量，两个电容放电持续时间不同，在第一电容C11放电完成之前，第三模拟比较器两个输入端的电压保持V IN-＜V IN+，实现了在数据传输过程中，出现高低电平变化时，由于RC电路的缓慢放电过程，使得第三模拟比较器U3C的IN+脚始终保持高电平的状态，第三模拟比较器U3C始终输出高电平，从而控制RS485差分驱动芯片的RE/DE状态保持为发送使能。
作为可选的实施方式，第二模拟比较器U3A的IN-脚通过第六二极管D4与RSS485差分驱动芯片U2的第四串口引脚连接；第六二极管D4的阳极与第二模拟比较器U3A的IN-脚连接；第六二极管D4的阴极与RSS485差分驱动芯片U2的第四串口引脚连接。
在本实施例中，通过第六二极管D4消除第二模拟比较器IN+引脚至RS485差分驱动芯片之间电路的信号干扰。第六二极管D4两端各接一个上拉电阻。当第二模拟比较器U3A的IN-脚接收到的信号发生变化时，第二模拟比较器U3A的输出也随之变化，且第二模拟比较器U3A的输出为第三模拟比较器U3C的输入信号之一，即，通过本实施例中的电路，能够实现依据RS485信号对RC时间锁定电路进行精准控制。
作为可选的实施方式，第二模拟比较器U3A的IN+脚通过第五电阻R23与第一模拟比较器U3B的输出端连接；第七二极管D6并联在第五电阻R23的两端，且第七二极管D6的阳极与第二模拟比较器U3A的IN+脚连接，第七二极管D6的阴极与第一模拟比较器U3B的输出端连接；第二模拟比较器U3A的输出端与第一模拟比较器U3B的IN-脚连接。第二模拟比较器U3A的IN+脚还分别与下拉电阻R26和第三电容C13连接，第三电容C13另一端接地。
在本实施例中，如图1所示，第五电阻R23与下拉电阻R26提供分压，当第一模拟比较器U3B的输出为低时，第七二极管D6快速地将第三电容C13的电压拉低，从而使第二模拟比较器U3A的输出为低。
在具体实施例中，第一场效应管Q1的漏极与UART串行总线连接；第一场效应管Q1的栅极通过第八电阻R13与第二模拟比较器U3A的输出端连接；第一场效应管Q1的源极接地；其中，第四模拟比较器U3D的IN-脚接在第二模拟比较器U3A的输出端和第八电阻R13之间。
如图1所示，在UART串行总线和第二模拟比较器U3A之间还连接了一个场效应管Q1，场效应管Q1场效应管采用耗尽型MOSFET，栅极低压时关断、栅极高压时导通。在第二模拟比较器U3A的输出为低时，场效应管被快速关闭。而第一模拟比较器U3B的输出为低的前提是UART串行总线输出为低，也就是说，有数据先从UART串行总线发出，那么就要把场效应管Q1断开，免得影响后续的UART数据输出。当第一模拟比较器U3B输出为高电平时，第三电容C13的电压通过第五电阻R23上升。
作为可选的实施方式，还包括：第四模拟比较器U3D；其中，第四模拟比较器U3D的IN-脚与第二模拟比较器U3A的输出端连接；第四模拟比较器U3D的输出端与第一模拟比较器U3B的IN-脚连接；第四模拟比较器U3D的IN+脚分别与第六电阻R11的一端和第七电阻R17的一端连接；第六电阻R11的另一端接高电平；第七电阻R17的另一端接地。
在本实施中，当第二模拟比较器U3A输出低电平时，第四模拟比较器U3D输出低电平，第四模拟比较器U3D的输出端又与第一电容C11连接，因此第一电容C11在第四模拟比较器U3D输出低电压时快速放电，使得第三模拟比较器U3C输出低电平，触发RS485差分驱动芯片的接收使能。
本实施例中的第四模拟比较器U3D的功能也可以通过一个MOSFET管实现：
如图3所示，第二场效应管Q2的漏极与第一模拟比较器U3B的IN-脚连接；第二场效应管Q2的栅极通过第九电阻R20与第二模拟比较器U3A的输出端连接；第二场效应管Q2的源极接地；第九电阻R20的一端与第二场效应管Q2的栅极连接；第九电阻R20的另一端与第二模拟比较器U3A的输出端连接；第九电阻R20的另一端还与第十电阻R22的一端连接；第十电阻R22的另一端接地。
如图3所示，第二场效应管Q2采用耗尽型MOSFET，栅极电压为低电平时，场效应管关闭，栅极电压为高电平时，场效应管导通。当第二模拟比较器输出高电平，第四模拟比较器的V IN->V IN+，第四模拟比较器输出低电平，第一场效应管Q1和第二场效应管Q2均导通，UART串行总线接地，第一模拟比较器U3B的IN-脚接地，第三模拟比较器U3C的IN+脚接地，第一电容C11通过第二场效应管Q2接地快速放电。第一电容C11再通过第一电阻R28和第二电阻R32缓慢充电，直至第一电容C11的电压上升至第三模拟比较器U3C的IN+脚的电压高于第三模拟比较器U3CIN-脚的电压。
在具体实施例中，由于第一电阻R28的阻值大于第二电阻R32的阻值，而第三电阻R30的阻值与第四电阻的阻值相同，因此电路空闲时第一电容C11的电压低于第二电容C12的电压，RC时间锁定电路空闲时输出低电平，即默认信号传输方向为RS485向UART串行总线发送数据。
本发明实施例的工作原理为：
UART发送数据时，其start位是一个低电平，则第一模拟比较器U3B的IN+脚被UART串行总线的输出的拉低电平，第一模拟比较器U3B输出低电平。此时，第二电容C12通过第五二极管阴极处的低电平拉低电压，快速放电。当第一模拟比较器U3B输出低电平时，第二模拟比较器U3A的输入端的第三电容C13通过第七二极管迅速放电，第三电容C13通过第五电阻R23和下拉电阻R26缓慢充电，第二模拟比较器U3A输出低电平。第四模拟比较器U3D的IN-脚输入为第二模拟比较器U3A输出的低电平，第四模拟比较器U3D输出高电平，拉高第一电容C11的电压，使第三模拟比较器U3C输出高电平，使RS485差分驱动芯片切换为发送使能。
第二电容C12通过第三电阻R30和第四电阻R31分压，缓慢充电，在第二电容C12的电压高于第一电容C11的电压之前，第三模拟比较器始终输出高电平。具体地，电容电阻的参数的条件为：第一电容的充电时间大于UART发送相邻的两个低电平的时间间隔。
而当RS485端发送数据时，第二模拟比较器U3A输出低电平时，第一场效应管Q1导通，UART串行接口接地，排除UART串行接口对RC时间锁定电路的影响。
虽然结合附图描述了本发明的实施例，但是本领域技术人员可以在不脱离本发明的精神和范围的情况下作出各种修改和变型，这样的修改和变型均落入由所附权利要求所限定的范围之内。

Claims (9)

  1. 一种基于RS485的单线半双工转换电路，其特征在于，包括：
    RS485差分驱动芯片，其第一串口引脚和第二串口引脚分别与RS485信号输入端和RS485信号输出端连接；
    第一模拟比较器，其IN+脚与UART串行总线连接，所述第一模拟比较器的输出端与所述RS485差分驱动芯片的第三串口引脚连接；
    第二模拟比较器，其IN-脚与所述RS485差分驱动芯片的第四串口引脚连接；所述第二模拟比较器的输出端与所述UART串行总线连接；
    RC时间锁定电路，其第一输入端与所述第一模拟比较器的输出端连接，所述RC时间锁定电路的第二输入端与所述第一模拟比较器的IN-脚连接；所述RC时间锁定电路的第二输入端还与所述第二模拟比较器U3A的输出端连接；所述RC时间锁定电路的输出端与所述RS485差分驱动芯片的信号方向控制引脚连接。
  2. 根据权利要求1所述的基于RS485的单线半双工转换电路，其特征在于，还包括：
    第一二极管，其一端接在所述第一串口引脚和所述RS485信号输入端之间，所述第一二极管的另一端接地；
    第二二极管，其一端接在所述第二串口引脚和所述RS485信号输出端之间，所述第二二极管的另一端接地；
    第三二极管，其一端接在在所述RS485信号输入端和所述第一串口引脚之间，所述第三二极管的另一端接在所述RS485信号输出端和所述第二串口引脚之间。
  3. 根据权利要求1所述的基于RS485的单线半双工转换电路，其特征在于，在所述UART串行总线和所述RS485差分驱动芯片之间还包括：第四二极管；所述第四二极管的阴极与所述UART串行总线连接；所述第四二极管的阳极连接与所述第一模拟比较器的IN+脚连接；所述第一模拟比较器的输出端与所述第三串口引脚连接。
  4. 根据权利要求1所述的基于RS485的单线半双工转换电路，其特征在于，所述RC时间锁定电路包括：
    第三模拟比较器，其输出端同时与所述RS485差分驱动芯片的RE引脚和DE引脚连接；所述第三模拟比较器的IN-脚通过第五二极管与所述第一模拟比较器的输出端连接；所述第三模拟比较器的IN-脚与所述第五二极管的阳极连接；所述第一模拟比较器的输出端与所述第五二极管的阴极连接；所述第三模拟比较器的IN+脚与所述第一比较模拟器的IN-脚连接；
    第一电阻，其一端与所述第三模拟比较器的IN+脚连接，所述第一电阻的另一端接高电平；
    第二电阻，其一端与所述第三模拟比较器的IN+脚连接，所述第二电阻的另一端接地；
    第一电容，其一端与所述第三模拟比较器的IN+脚连接，所述第一电容的另一端接地；
    第三电阻，其一端与所述第三模拟比较器的IN-脚连接，所述第三电阻的另一端接高电平；
    第四电阻，其一端与所述第三模拟比较器的IN-脚连接，所述第四电阻的另一端接地；
    第二电容，其一端与所述第三模拟比较器的IN-脚连接，所述第二电容的另一端接地；
    其中，所述第一电阻的阻值大于所述第二电阻的阻值；所述第三电阻的阻值与所述第四电阻的阻值相同；所述第一电容的电容量小于所述第二电容的电容量。
  5. 根据权利要求1所述的基于RS485的单线半双工转换电路，其特征在于，所述第二模拟比较器的IN-脚通过第六二极管与所述RSS485差分驱动芯片的第四串口引脚连接；所述第六二极管的阳极与所述第二模拟比较器的IN-脚连接；所述第六二极管的阴极与所述RSS485差分驱动芯片的第四串口引脚连接。
  6. 根据权利要求4所述的基于RS485的单线半双工转换电路，其特征在于，所述第二模拟比较器的IN+脚通过第五电阻与所述第一模拟比较器的输出端连接；第七二极管并联在所述第五电阻的两端，且所述第七二极管的阳极与所述第二模拟比较器的IN+脚连接，所述第七二极管的阴极与所述第一模拟比较器的输出端连接；所述第二模拟比较器的输出端与所述第一模拟比较器的IN-脚连接；所述第二模拟比较器的IN+脚还与第三电容连接。
  7. 根据权利要求6所述的基于RS485的单线半双工转换电路，其特征在于，还包括：第四模拟比较器；其中，所述第四模拟比较器的IN-脚与所述第二模拟比较器的输出端连接；所述第四模拟比较器的输出端与所述第一模拟比较器的IN-脚连接；所述第四模拟比较器的IN+脚分别与第六电阻的一端和第七电阻的一端连接；所述第六电阻的另一端接高电平；所述第七电阻的另一端接地。
  8. 根据权利要求7所述的基于RS485的单线半双工转换电路，其特征在于，还包括：第一场效应管，其漏极与所述UART串行总线连接；所述第一场效应管的栅极通过第八电阻与所述第二模拟比较器的输出端连接；所述第一场效应管的源极接地；其中，所述第四模拟比较器的IN-脚接在所述第二模拟比较器的输出端和所述第八电阻之间。
  9. 根据权利要求1所述的基于RS485的单线半双工转换电路，其特征在于，还包括：第二场效应管，其漏极与所述第一模拟比较器的IN-脚连接；所述第二场效应管的栅极通过第九电阻与所述第二模拟比较器的输出端连接；所述第二场效应管的源极接地；所述第九电阻的一端与所述第二场效应管的栅极连接；所述第九电阻的另一端与所述第二模拟比较器的输出端连接；所述第九电阻的另一端还与第十电阻的一端连接；所述第十电阻的另一端接地。
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