WO2023116291A1

WO2023116291A1 - Vector synthesis structure for phase shifter

Info

Publication number: WO2023116291A1
Application number: PCT/CN2022/132750
Authority: WO
Inventors: 黄光锐; 宣凯; 郭嘉帅
Original assignee: 深圳飞骧科技股份有限公司
Priority date: 2021-12-20
Filing date: 2022-11-18
Publication date: 2023-06-29
Also published as: CN114244315A

Abstract

Provided in the present invention is a vector synthesis structure for a phase shifter. The vector synthesis structure comprises a first vector synthesis branch and a second vector synthesis branch. The first vector synthesis branch comprises: a first tail current source, a first DAC bias circuit and a first gate width control circuit, wherein the first tail current source comprises a plurality of first tail current units, the width-to-length ratios of which gradually increase; and the first DAC bias circuit is correspondingly provided with a plurality of first current mirror bias units. The second vector synthesis branch comprises: a second tail current source, a second DAC bias circuit and a second gate width control circuit, wherein the second tail current source comprises a plurality of second tail current units, the width-to-length ratios of which gradually increase; and the second DAC bias circuit is correspondingly provided with a plurality of second current mirror bias units. By means of the present invention, the linearity of an active phase shifter can be improved while the precision of phase shifting is ensured.

Description

A vector synthesis structure of phase shifter

【Technical field】

The invention relates to the field of electronic technology, in particular to a vector synthesis structure of a phase shifter.

【Background technique】

Since the signals of the phased array system can be superimposed in a certain direction, it can improve the signal-to-noise ratio, and it has the functions of beam forming and beam scanning. As the key module of the phased array system, the phase shifter is self-evident. According to the position of the phase shifter in the system, it can be divided into local oscillator phase shifter, intermediate frequency phase shifter and radio frequency phase shifter. The existing active phase shifter architecture is shown in Figure 1, including quadrature generator, VGA, vector synthesis unit and DAC. Among them, as shown in Figure 2 is the existing vector synthesis architecture, which mainly includes a Gilbert unit, which is a DAC circuit biased by a tail current source, and phase shifting can be performed by changing the current ratio of the I and Q circuits.

Due to the use of the Gilbert structure in the prior art vector synthesis, the MOS tubes M9-M14 all work in the saturation region, and there will be a certain Vdsat (saturated drain-source voltage), and the voltage margin of the RF differential pair tube will be reduced , the swing is reduced, so that the linearity will be poor.

【Content of invention】

The purpose of the present invention is to overcome at least one technical problem above, and provide a vector synthesis structure of a phase shifter.

In order to achieve the above object, the present invention provides a vector synthesis structure of a phase shifter, including: a first vector synthesis branch and a second vector synthesis branch; wherein,

The first vector synthesis branch includes: a first tail current source, a first DAC bias circuit, and a first grid width control circuit, and the first tail current source includes a plurality of first tails with gradually increasing width-to-length ratios. A current unit, the first DAC bias circuit is correspondingly provided with a plurality of first current mirror bias units;

The second vector synthesis branch includes: a second tail current source, a second DAC bias circuit, and a second grid width control circuit, and the second tail current source includes a plurality of second tails with gradually increasing width-to-length ratios. For the current unit, the second DAC bias circuit is correspondingly provided with a plurality of second current mirror bias units.

Preferably, the first gate width control circuit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor, the gates of the first MOS transistor and the fourth MOS transistor are connected and connected to The first input signal is connected, the gates of the second MOS transistor and the third MOS transistor are connected and connected with the second input signal.

Preferably, the second gate width control circuit includes a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, and an eighth MOS transistor; the gates of the first and fourth MOS transistors are connected to The first input signal is connected, the gates of the second MOS transistor and the third MOS transistor are connected and connected with the second input signal.

Preferably, each of the first tail current units includes: a first one MOS transistor, a first two MOS transistor, and a first three MOS transistor, wherein the gates of the first one MOS transistor and the first two MOS transistors are respectively The first switch and the second switch are connected to the first port of the first DAC bias circuit, the sources of the first one MOS transistor and the first two MOS transistors are connected and connected to the drains of the first three MOS transistors pole, the gate of the first three MOS transistors is connected to the second port of the first DAC bias circuit, and the source of the first three MOS transistors is grounded.

Preferably, each of the second tail current units includes: a second 1 MOS transistor, a second 2 MOS transistor, and a second 3 MOS transistor, wherein the gates of the second 1 MOS transistor and the second 2 MOS transistor are respectively The third switch and the fourth switch are connected to the third port of the second DAC bias circuit, the sources of the second one MOS transistor and the second two MOS transistors are connected and connected to the drain of the second three MOS transistors pole, the gate of the second three MOS transistors is connected to the fourth port of the second DAC bias circuit, and the source of the second three MOS transistors is grounded.

Preferably, the width-to-length ratios of the plurality of first tail current units in the first tail current source increase in binary form from to , and the width-to-length ratios of the plurality of second tail current units in the second tail current source range from to increment in binary form.

Preferably, each of the first current mirror bias units includes: a plurality of first current steering units and a corresponding number of first current mirror units;

Each of the second current mirror bias units includes: a plurality of second current steering units and a corresponding number of second current mirror units.

Preferably, the first current steering unit includes: a fourth-first MOS transistor, a fifth-first MOS transistor, and a fifth-first switch, the gate of the fourth-first MOS transistor is connected to a bias current, and the fourth-first MOS transistor is connected to a bias current. The source of the MOS transistor is connected to the power supply, the drain of the fourth MOS transistor is connected to the source of the fifth MOS transistor, and the gate of the fifth MOS transistor is connected to the fifth switch, The drain of the fifth first switch is connected to the port of the first current mirror unit.

Preferably, the second current steering unit includes: a fourth-first MOS transistor, a sixth-first MOS transistor, and a seventh-first switch, the gate of the fourth-first MOS transistor is connected to a bias current, and the fourth-first MOS transistor is connected to a bias current. The source of the MOS transistor is connected to the power supply, the drain of the fourth MOS transistor is connected to the source of the sixth MOS transistor, the gate of the seventh MOS transistor is connected to the seventh first switch, A drain of the seventh first switch is connected to a port of the second current mirror unit.

Preferably, the first current mirror unit includes: an eighth-fifth MOS transistor, an eighth-sixth MOS transistor, an eighth-seventh MOS transistor, and an eighth-eighth MOS transistor, the eighth-fifth MOS transistor, the eighth-sixth MOS transistor The drains of the eighty-seven MOS transistors and the eighth-eighth MOS transistors are respectively connected to the gates of the eighth-fifth MOS transistors and the eighth-sixth MOS transistors. The sources of the eighth-fifth MOS transistors, the eighth-sixth MOS transistors, the gates of the eighth-seven MOS transistors, and the eighth-eighth MOS transistors are connected, and are respectively connected to the port Ibias through a control switch; the second current The structure of the mirror unit is the same as that of the first current mirror unit.

Compared with the related technology, the invention can improve the linearity of the active phase shifter while ensuring the phase shifting precision.

【Description of drawings】

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative work, wherein:

Fig. 1 is a structure diagram of an existing phase shifter;

Fig. 2 is the schematic diagram of existing vector synthesis structure;

FIG. 3 is a schematic diagram of orthogonal synthesis in an embodiment of the present invention;

Fig. 4 is the schematic diagram of the vector synthesis structure of the embodiment of the present invention;

Fig. 5 is the schematic diagram of the tail current source I of the embodiment of the present invention;

6 is a schematic diagram of a tail current source Q according to an embodiment of the present invention;

7 is a schematic diagram of a DAC bias circuit according to an embodiment of the present invention;

FIG. 8 is a structural diagram of a current mirror used in an embodiment of the present invention;

FIG. 9 is a structure diagram of a conventional current mirror.

【Detailed ways】

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The synthesis principle of this embodiment is shown in Figure 3, the phase shifter synthesis mode is quadrature synthesis, and the gain and phase after synthesis are respectively:

Among them, g _mI and g _mQ are the transconductances of the tail current source I and the tail current source Q respectively, I _ssI and I _ssQ are the currents of the tail current source I and the tail current source Q respectively, and R _out is equivalent load impedance.

It can be seen from the equation that if the ratio of the two currents of the tail current source I and the tail current source Q is changed, the phase will change, while keeping the sum of the two currents unchanged, the gain will not change.

Please refer to FIG. 4 , based on the above principles, an embodiment of the present invention provides a vector synthesis structure of a phase shifter, including: a first vector synthesis branch 100 and a second vector synthesis branch 200 .

Wherein, the first vector synthesis branch 100 includes: a first tail current source 110 (tail current source I), a first DAC bias circuit 120 , and a first gate width control circuit 130 . As shown in FIG. 5, the first tail current source includes a plurality of first tail current units 111 with gradually increasing aspect ratios. As shown in FIG. 7, the first DAC bias circuit 120 is correspondingly provided with a plurality of first tail current units 111. A current mirror bias unit 121 .

The second vector synthesis branch 200 includes: a second tail current source 210 (micro current source Q), a second DAC bias circuit 220 , and a second gate width control circuit 230 . As shown in FIG. 5 , the second tail current source 210 includes a plurality of second tail current units 211 with gradually increasing aspect ratios. As shown in FIG. 7 , the second DAC bias circuit 220 is correspondingly provided with a plurality of The second current mirror bias unit 221 .

In this embodiment, the first gate width control circuit 130 includes a first MOS transistor M1, a second MOS transistor M1, a third MOS transistor M1, and a fourth MOS transistor M1. The first MOS transistor M1, the second MOS transistor M1 The gates of the four MOS transistors M4 are connected and connected to the first input signal Ip, and the gates of the second MOS transistor M2 and the third MOS transistor M3 are connected and connected to the second input signal Qn.

In this embodiment, the second gate width control circuit 230 includes a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, and an eighth MOS transistor M8; The gates of the four MOS transistors M4 are connected and connected to the first input signal Ip, and the gates of the second MOS transistor M2 and the third MOS transistor M3 are connected and connected to the second input signal Qn.

In this embodiment, as shown in FIG. 5 , each of the first tail current units 111 includes: a first MOS transistor MIn1, a first MOS transistor MIn2, and a first MOS transistor MIn3, wherein the first The gates of the first MOS transistor MIn1 and the first and second MOS transistors MIn2 are respectively connected to the first port Ibias1 of the first DAC bias circuit through the first switch SIn1 and the second switch SIn2, the first MOS transistor MIn1, the first The sources of the two MOS transistors MIn2 are connected to the drain of the first three MOS transistors MIn3, and the gates of the first three MOS transistors MIn3 are connected to the second port Ibias2 of the first DAC bias circuit, The source of the first three MOS transistors MIn3 is set to be grounded. In this embodiment, n in the reference symbol MIn1 represents the first MOS in the nth first tail current unit, for example, the first MOS transistor MIn1 belongs to For the first first tail current unit, it is denoted as MI11, and the expressions of the other marks above and below are similar, and the description will not be repeated.

In this embodiment, as shown in FIG. 6, each of the second tail current units includes: a second one MOS transistor MQn1, a second two MOS transistor MQn2, and a second three MOS transistor MQn3, wherein the second one The gates of the MOS transistor MQn1 and the second and second MOS transistors MQn2 are respectively connected to the third port Qbias1 of the second DAC bias circuit through the third switch SQn1 and the fourth switch SQn2. The source of the MOS transistor MQn2 is connected to the drain of the second three MOS transistor MQn3, and the gate of the second three MOS transistor MQn3 is connected to the fourth port Qbias2 of the second DAC bias circuit, so Describe the source grounding setting of the second and third MOS transistors MQn3.

In this embodiment, the aspect ratio of the plurality of first tail current units in the first tail current source is from

arrive

Incremented in binary form, the width-to-length ratio of the plurality of second tail current units in the second tail current source is from

arrive

Increment in binary form.

In this embodiment, as shown in FIG. 7, each of the first current mirror bias units 120 includes: a plurality of first current steering units 121 and a corresponding number of first current mirror units 122; The second current mirror bias unit 220 includes: a plurality of second current steering units 221 and a corresponding number of second current mirror units 222 .

In this embodiment, as shown in FIG. 7 , the first current steering unit 121 includes: a fourth-first MOS transistor Mnb, a fifth-first MOS transistor MIn, and a fifth-first switch SIn, and the fourth-first MOS transistor Mnb The gate of the first MOS transistor Mnb is connected to the bias current bias, the source of the fourth first MOS transistor Mnb is connected to the power supply, the drain of the fourth first MOS transistor Mnb is connected to the source of the fifth first MOS transistor MIn, and The gate of the fifth first MOS transistor is connected to the fifth first switch SIn, and the drain of the fifth first switch SIn is connected to the second port Ibias2 of the first current mirror unit.

In this embodiment, as shown in FIG. 7 , the second current steering unit 221 includes: a fourth-first MOS transistor Mnb (shared with the first current steering unit 121 ), a sixth-first MOS transistor MQn, and a seventh-first MOS transistor MQn. switch SQn, the gate of the fourth MOS transistor Mnb is connected to the bias current bias, the source of the fourth MOS transistor Mnb is connected to the power supply, and the drain of the fourth MOS transistor Mnb is connected to the The source of the sixth MOS transistor MQn, the gate of the seventh MOS transistor is connected to the seventh first switch SQn, and the drain of the seventh first switch SIn is connected to the first current mirror unit of the second current mirror unit. Four-port Qbias2.

In this embodiment, the structure of the second current mirror unit 222 is the same as that of the first current mirror unit 122 , and will not be repeated here.

In this embodiment, as shown in FIG. 8, the first current mirror unit 122 is used for illustration, which specifically includes: the eighth-first MOS transistor MIN1, the eighth-second MOS transistor MIN2, the eighth-fourth MOS transistor MIN4, and the eighth-fourth MOS transistor MIN4, and the eighth-fourth MOS transistor MIN4. Five MOS transistors MIN5, the drains of the eighth-first MOS transistor MIN1 and the eighth-second MOS transistor MIN2 are respectively connected to the second port Ibias2, the gates of the eighth-first MOS transistor MIN1 and the eighth-second MOS transistor MIN2 are connected , the drains of the eighth-fourth MOS transistor MIN4 and the eighth-fifth MOS transistor MIN5 are respectively connected to the sources of the eighth-first MOS transistor MIN1 and the eighth-second MIN2 MOS transistor; the eighth-fourth MOS transistor MIN4 and the eighth-fourth MOS transistor MIN4 The gates of eighty-five MOS transistors MIN5 are connected, and are respectively connected to the second port Ibias2 through a control switch; the structure of the second current mirror unit is the same as that of the first current mirror unit, and will not be repeated here describe.

Referring to FIG. 9, it is a schematic diagram of another current mirror unit structure. The minimum drain voltage of M2 in FIG. 9 is:

V _D2min ＝V _N -V _TH ＝V _GS1 +V _GS3 -V _TH ＝(V _GS1 -V _TH )+(V _GS3 -V _TH )+V _TH ＝2V _ov +V _TH

Among them, V _ov is the overdrive voltage, and V _TH is the threshold voltage.

As shown in Figure 7, the minimum drain voltage of M6 is:

V _D6min = 2V _ov

It can be seen from the above formula that the output drain potential of M6 in Figure 8 is lower than the output drain potential of M2 in Figure 9 by a threshold voltage, and the current mirror unit shown in Figure 8 can obtain a larger swing. In this embodiment, the vector synthesis tail current source adopts the current mirror shown in FIG. 8 , and the differential pair can obtain a larger voltage swing, thereby obtaining better linearity.

During the phase shifting process of the phase shifter from 0° to 360°, the currents of the tail current source I and the tail current source Q are always changing. If the tail current source I and the tail current source Q adopt a fixed width-to-length ratio, then for the Q circuit, as the current gradually increases, the MOS tube will enter the linear region, which will cause errors in the current mirror and affect the shift. phase accuracy. In order to solve this problem, the embodiment of the present invention adopts multiple pairs of tail current sources, and the current mirror bias of the DAC should correspond to them, as shown in FIG. 7 . aspect ratio from

arrive

Increment in binary form. If the nth bit of the DAC current steering PMOS is turned on, the nth bit of the NMOS current mirror bias will also be turned on. Because the width-to-length ratio is increasing, the Ibias potential remains unchanged, corresponding to The RF differential pair is also the nth tail current source is turned on, and the source potential of the differential pair remains unchanged. The tail current source MOS is always in the saturation region, which ensures the accuracy of the mirror image and the accuracy of the phase shift.

What has been described above is only the embodiment of the present invention. It should be pointed out that for those of ordinary skill in the art, improvements can be made without departing from the creative concept of the present invention, but these all belong to the present invention. scope of protection.

Claims

A vector synthesis structure of a phase shifter, characterized in that it comprises: a first vector synthesis branch and a second vector synthesis branch; wherein,

The first vector synthesis branch includes: a first tail current source, a first DAC bias circuit, and a first grid width control circuit, and the first tail current source includes a plurality of first tails with gradually increasing width-to-length ratios. A current unit, the first DAC bias circuit is correspondingly provided with a plurality of first current mirror bias units;

The second vector synthesis branch includes: a second tail current source, a second DAC bias circuit, and a second grid width control circuit, and the second tail current source includes a plurality of second tails with gradually increasing width-to-length ratios. For the current unit, the second DAC bias circuit is correspondingly provided with a plurality of second current mirror bias units.
The vector synthesis structure of the phase shifter according to claim 1, wherein the first gate width control circuit comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor, so The gates of the first MOS transistor and the fourth MOS transistor are connected to the first input signal, and the gates of the second MOS transistor and the third MOS transistor are connected to the second input signal.
The vector synthesis structure of the phase shifter according to claim 3, wherein the second gate width control circuit comprises a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, and an eighth MOS transistor; The gates of the first MOS transistor and the fourth MOS transistor are connected to the first input signal, and the gates of the second MOS transistor and the third MOS transistor are connected to the second input signal.
The vector synthesis structure of the phase shifter according to claim 1, wherein each of the first tail current units comprises: a first one MOS transistor, a first two MOS transistors, and a first three MOS transistors, wherein , the gates of the first one MOS tube and the first two MOS tubes are respectively connected to the first port of the first DAC bias circuit through the first switch and the second switch, the first one MOS tube, the first two MOS tubes The source of the first three MOS transistors is connected to the drain of the first three MOS transistors, the gate of the first three MOS transistors is connected to the second port of the first DAC bias circuit, and the first three MOS transistors The source ground setting.
The vector synthesis structure of the phase shifter according to claim 4, wherein each of the second tail current units comprises: a second 1 MOS transistor, a second 2 MOS transistor, and a second 3 MOS transistor, wherein , the gates of the second one MOS tube and the second two MOS tubes are respectively connected to the third port of the second DAC bias circuit through the third switch and the fourth switch, the second one MOS tube, the second two MOS tubes The source is connected to the drain of the second three MOS transistors, the gate of the second three MOS transistors is connected to the fourth port of the second DAC bias circuit, and the second three MOS transistors The source ground setting.
The vector synthesis structure of the phase shifter as claimed in claim 5, wherein the width-to-length ratio of a plurality of first tail current units in the first tail current source is from
arrive
Incremented in binary form, the width-to-length ratio of the plurality of second tail current units in the second tail current source is from
arrive
Increment in binary form.
The vector synthesis structure of the phase shifter according to claim 1, wherein each of the first current mirror bias units comprises: a plurality of first current steering units and a corresponding number of first current mirror units ;

Each of the second current mirror bias units includes: a plurality of second current steering units and a corresponding number of second current mirror units.
The vector synthesis structure of the phase shifter according to claim 7, wherein the first current steering unit comprises: a fourth MOS transistor, a fifth MOS transistor, and a fifth switch, and the fourth The gate of a MOS transistor is connected to the bias current, the source of the fourth MOS transistor is connected to the power supply, the drain of the fourth MOS transistor is connected to the source of the fifth MOS transistor, and the source of the fourth MOS transistor is connected to the source of the fifth MOS transistor. The gate of the fifth MOS transistor is connected to the fifth first switch, and the drain of the fifth first switch is connected to the second port of the first current mirror unit.
The vector synthesis structure of the phase shifter according to claim 7, wherein the second current steering unit comprises: a fourth MOS transistor, a sixth MOS transistor, and a seventh first switch, and the fourth The gate of a MOS transistor is connected to the bias current, the source of the fourth MOS transistor is connected to the power supply, the drain of the fourth MOS transistor is connected to the source of the sixth MOS transistor, and the source of the fourth MOS transistor is connected to the source of the sixth MOS transistor. The gate of the seventh MOS transistor is connected to the seventh first switch, and the drain of the seventh first switch is connected to the fourth port of the second current mirror unit.
The vector synthesizing structure of the phase shifter according to claim 7, wherein the first current mirror unit comprises: an eighth-fifth MOS transistor, an eighth-sixth MOS transistor, an eighth-seventh MOS transistor, and an eighth-eighth MOS transistor. MOS transistors, the drains of the eighth-fifth MOS transistors and the eighth-sixth MOS transistors are respectively connected to the second port, the gates of the eighth-fifth MOS transistors and the eighth-sixth MOS transistors are connected, and the eighth-seven MOS transistors , and the drains of the eighth and eighth MOS transistors are respectively connected to the sources of the eighth-fifth MOS transistors and the eighth-sixth MOS transistors, and the gates of the eighth-seven MOS transistors and the eighth-eighth MOS transistors are connected, and are respectively connected to the second ports through control switches; the structure of the second current mirror unit is the same as that of the first current mirror unit.