WO2023114552A3 - Dynamic adjustment of word line timing in static random access memory - Google Patents

Dynamic adjustment of word line timing in static random access memory Download PDF

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Publication number
WO2023114552A3
WO2023114552A3 PCT/US2022/053414 US2022053414W WO2023114552A3 WO 2023114552 A3 WO2023114552 A3 WO 2023114552A3 US 2022053414 W US2022053414 W US 2022053414W WO 2023114552 A3 WO2023114552 A3 WO 2023114552A3
Authority
WO
WIPO (PCT)
Prior art keywords
wordline
error rate
pulse width
random access
memory cells
Prior art date
Application number
PCT/US2022/053414
Other languages
French (fr)
Other versions
WO2023114552A2 (en
Inventor
Robert Wiser
Neelam SURANA
Jay Chesavage
Original Assignee
Ceremorphic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US17/555,501 external-priority patent/US11935587B2/en
Priority claimed from US17/734,045 external-priority patent/US20230352082A1/en
Application filed by Ceremorphic Inc filed Critical Ceremorphic Inc
Publication of WO2023114552A2 publication Critical patent/WO2023114552A2/en
Publication of WO2023114552A3 publication Critical patent/WO2023114552A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

A static random access memory (SRAM) has one or more arrays of memory cells, each array of memory cells activated in columns by a wordline. The activated column of memory cells asserts output data onto a plurality of bitlines coupled to output drivers. The SRAM includes a wordline controller generating a variable pulse width wordline which may be reduced sufficient to introduce memory read errors. SRAM power consumption of a high error rate, medium error rate, low error rate, and error-free rate is associated with a pulse width value generated by the wordline controller. The wordline controller is thereby able to associate a wordline pulse width to an associated error rate for performing tasks which are insensitive to a high error rate or a medium error rate, which are specific to certain neural network training and inference using various NN data types.
PCT/US2022/053414 2021-12-19 2022-12-19 Dynamic adjustment of word line timing in static random access memory WO2023114552A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US17/555,501 US11935587B2 (en) 2021-12-19 2021-12-19 Dynamic adjustment of wordline timing in static random access memory
US17/555,501 2021-12-19
US17/734,045 2022-04-30
US17/734,045 US20230352082A1 (en) 2022-04-30 2022-04-30 Dynamic Adjustment of Word Line Timing in Static Random Access Memory

Publications (2)

Publication Number Publication Date
WO2023114552A2 WO2023114552A2 (en) 2023-06-22
WO2023114552A3 true WO2023114552A3 (en) 2023-08-03

Family

ID=86773473

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2022/053414 WO2023114552A2 (en) 2021-12-19 2022-12-19 Dynamic adjustment of word line timing in static random access memory

Country Status (1)

Country Link
WO (1) WO2023114552A2 (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020159285A1 (en) * 2000-03-01 2002-10-31 Stephen Morley Data balancing scheme in solid state storage devices
US20060176743A1 (en) * 2005-02-09 2006-08-10 International Business Machines Corporation Write driver circuit for memory array
US7516280B1 (en) * 2004-03-30 2009-04-07 Cypress Semiconductor Corporation Pulsed arbitration system and method
US20130176784A1 (en) * 2011-03-30 2013-07-11 Stec, Inc. Adjusting operating parameters for memory cells based on wordline address and cycle information
US20130301335A1 (en) * 2012-05-08 2013-11-14 Adrian E. Ong Architecture, system and method for testing resistive type memory
US20160099059A1 (en) * 2014-10-07 2016-04-07 SanDisk Technologies, Inc. Non-volatile memory and method with adjusted timing for individual programming pulses
US20160148680A1 (en) * 2014-11-21 2016-05-26 Panasonic intellectual property Management co., Ltd Tamper-resistant non-volatile memory device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020159285A1 (en) * 2000-03-01 2002-10-31 Stephen Morley Data balancing scheme in solid state storage devices
US7516280B1 (en) * 2004-03-30 2009-04-07 Cypress Semiconductor Corporation Pulsed arbitration system and method
US20060176743A1 (en) * 2005-02-09 2006-08-10 International Business Machines Corporation Write driver circuit for memory array
US20130176784A1 (en) * 2011-03-30 2013-07-11 Stec, Inc. Adjusting operating parameters for memory cells based on wordline address and cycle information
US20130301335A1 (en) * 2012-05-08 2013-11-14 Adrian E. Ong Architecture, system and method for testing resistive type memory
US20160099059A1 (en) * 2014-10-07 2016-04-07 SanDisk Technologies, Inc. Non-volatile memory and method with adjusted timing for individual programming pulses
US20160148680A1 (en) * 2014-11-21 2016-05-26 Panasonic intellectual property Management co., Ltd Tamper-resistant non-volatile memory device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
YANG JUN, JI HAO, GUO YICHEN, ZHU JIZHE, ZHUANG YUAN, LI ZHI, LIU XINNING, SHI LONGXING: "A Double Sensing Scheme With Selective Bitline Voltage Regulation for Ultralow-Voltage Timing Speculative SRAM", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE, USA, vol. 53, no. 8, 1 August 2018 (2018-08-01), USA, pages 2415 - 2426, XP093083294, ISSN: 0018-9200, DOI: 10.1109/JSSC.2018.2837862 *

Also Published As

Publication number Publication date
WO2023114552A2 (en) 2023-06-22

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