WO2023108415A1

WO2023108415A1 - Light-emitting transistor and manufacturing method therefor, and display substrate

Info

Publication number: WO2023108415A1
Application number: PCT/CN2021/137896
Authority: WO
Inventors: 闫华杰; 焦志强; 王路; 王鹏
Original assignee: 京东方科技集团股份有限公司
Priority date: 2021-12-14
Filing date: 2021-12-14
Publication date: 2023-06-22
Also published as: CN116649007A

Abstract

Disclosed are a light-emitting transistor and a manufacturing method therefor, and a display substrate. The light-emitting transistor comprises: a gate, provided on a base substrate; an insulating layer, provided on the side of the gate away from the base substrate; a first electrode, provided on the side of the insulating layer away from the base substrate, the first electrode having a plurality of through holes, the plurality of through holes of the first electrode being divided into a plurality of through hole groups provided side by side in a first direction, each of the through hole groups comprising a plurality of through holes arranged in a second direction, and the first direction intersecting the second direction; a light-emitting functional layer, provided on the side of the first electrode away from the base substrate; and a second electrode, provided on the side of the light-emitting functional layer away from the base substrate.

Description

Light-emitting transistor, manufacturing method thereof, and display substrate

technical field

The present disclosure relates to the field of display technology, in particular to a light-emitting transistor, a manufacturing method thereof, and a display substrate.

Background technique

Organic electronic devices such as organic light-emitting diodes and organic field-effect transistors have attracted great attention due to their light weight, flexibility, and low-cost mass production. Research on organic light emitting diodes is mainly used in flat panel displays, while organic field effect transistors can be applied to active drive units of flat panel displays. Organic light-emitting transistors that integrate light emission and current-regulating functions of traditional transistors can lay the foundation for the realization of truly all-organic highly integrated electronic devices.

Contents of the invention

The disclosure proposes a light-emitting transistor, a manufacturing method thereof, and a display substrate.

The present disclosure provides a light-emitting transistor, including:

The gate is arranged on the base substrate;

an insulating layer disposed on a side of the gate away from the base substrate;

The first electrode is arranged on the side of the insulating layer away from the base substrate, the first electrode has a plurality of through holes, and the plurality of through holes of the first electrode are divided to be arranged side by side in the first direction a plurality of via groups, each via group comprising a plurality of vias arranged in a second direction, the first direction intersecting the second direction;

A light-emitting functional layer disposed on a side of the first electrode away from the base substrate;

The second electrode is disposed on a side of the light-emitting functional layer away from the base substrate.

In some embodiments, the light-emitting transistor further includes: a topological insulating pattern layer disposed on the insulating layer, the topological insulating pattern layer includes a plurality of topological insulating pattern parts arranged at intervals, and the topological insulating pattern parts are connected with the topological insulating pattern parts. The through holes are arranged in one-to-one correspondence, the material of the topological insulation pattern part includes a metal-organic topological insulator material, the material of the first electrode includes a metal material, and the metal element in the metal material is in the same state as the metal-organic insulator material. The metal elements in organic topological insulator materials are the same.

In some embodiments, the metal-organic topological insulating material includes MgAg-DCA, and the material of the first electrode includes magnesium-silver alloy.

In some embodiments, a plurality of insulating protrusions spaced apart from each other are provided on the surface of the insulating layer away from the base substrate, and the insulating protrusions correspond to the through holes one by one;

The light-emitting transistor includes a first metal layer, and the first metal layer includes the first electrode and a plurality of redundant electrodes; each of the redundant electrodes is arranged on one of the insulating protrusions away from the base substrate On the surface of , the redundant electrode is disconnected from the first electrode.

In some embodiments, the cross-sectional area of the end of the insulating protrusion close to the base substrate is smaller than the cross-sectional area of the end of the insulating protrusion away from the base substrate.

In some embodiments, the first electrode has a grid structure, and the grid structure includes a plurality of metal parts arranged side by side in the first direction, and every two adjacent metal parts are mirror-image symmetrical, The metal part includes: a plurality of first bent parts and a plurality of second bent parts, the first bent parts and the second bent parts are arranged alternately in the second direction, the first bent parts and the second bent parts The second bent portion is bent in opposite directions; wherein, the plurality of first bent portions and the plurality of second bent portions of every two adjacent metal portions define a plurality of meshes of the grid structure.

In some embodiments, the orthographic projection of the through hole on the base substrate is polygonal or substantially circular.

In some embodiments, the thickness of the first electrode is between 1 nm˜1000 nm.

In some embodiments, the insulating layer at least includes: a first insulating sublayer and a second insulating sublayer, the first insulating sublayer is located on a side of the second insulating sublayer close to the base substrate, the first insulating sublayer is The dielectric constant of the insulating sublayer is greater than that of the second insulating sublayer, and the breakdown field strength of the first insulating sublayer is smaller than the breakdown field strength of the second insulating sublayer.

In some embodiments, the light-emitting functional layer includes: an electron transport layer, a light-emitting layer, and a hole transport layer arranged in sequence along a direction away from the base substrate; or,

The light-emitting functional layer includes: a hole transport layer, a light-emitting layer and an electron transport layer arranged in sequence along a direction away from the base substrate.

An embodiment of the present disclosure also provides a method for manufacturing a light-emitting transistor, including:

forming a gate on the base substrate;

forming an insulating layer on a side of the gate away from the substrate;

A first electrode is formed on the side of the insulating layer away from the base substrate, the first electrode has a plurality of through holes, and the plurality of through holes of the first electrode are divided into a plurality of through holes arranged side by side in the first direction. a plurality of via groups, each via group comprising a plurality of vias arranged in a second direction, the first direction intersecting the second direction;

forming a light-emitting functional layer on the side of the first electrode away from the base substrate;

A second electrode is formed on a side of the light emitting functional layer away from the base substrate.

In some embodiments, forming a first electrode on a side of the insulating layer away from the base substrate specifically includes:

A topological insulating pattern layer is formed on the side of the insulating layer away from the base substrate, the topological insulating pattern layer includes a plurality of topological insulating pattern parts arranged at intervals, and the material of the topological insulating pattern parts includes metal-organic topology Insulator material;

Depositing a metal material on the insulating layer, the metal element in the metal material is the same as the metal element in the metal-organic topological insulator material, so as to form a first electrode with a plurality of through holes, and the The through holes are in one-to-one correspondence with the topological insulation pattern parts.

In some embodiments, the topological insulating material includes MgAg-DCA; the material of the first electrode includes magnesium-silver alloy.

forming a plurality of first metal parts spaced apart from each other on the insulating layer;

forming a plurality of second metal parts spaced apart from each other on the insulating layer;

Wherein, the plurality of first metal parts and the plurality of second metal parts form a first electrode of a grid structure, and the plurality of first metal parts and the plurality of second metal parts are arranged side by side in the first direction , each of the first metal parts is mirror-symmetrical to its adjacent second metal part, and each of the first metal part and the second metal part includes: a plurality of first metal parts alternately arranged in the second direction A curved part and a plurality of second curved parts, the first curved part and the second curved part are bent in opposite directions; wherein, each of the first metal parts and the number of adjacent second metal parts A first bend and a plurality of second bends define a plurality of cells of the lattice structure.

In some embodiments, the manufacturing method further includes: forming a plurality of insulating protrusions spaced apart from each other on a side of the insulating layer away from the base substrate;

Forming a first electrode on a side of the insulating layer away from the base substrate, specifically includes:

Depositing a first metal layer on the insulating layer and the plurality of insulating protrusions, the first metal layer includes the first electrode and a plurality of redundant electrodes, the insulating protrusion and the first electrodes Each of the redundant electrodes is arranged on the surface of one of the insulating protrusions away from the base substrate, and the redundant electrodes are disconnected from the first electrodes.

In some embodiments, the first electrode is formed by a physical vapor deposition process.

In some embodiments, the physical vapor deposition process is an evaporation process.

In some embodiments, an insulating layer is formed on a side of the gate away from the base substrate, which specifically includes:

forming a first insulating sublayer on a side of the gate away from the substrate;

forming a second insulating sublayer on a side of the first insulating sublayer away from the base substrate;

Wherein, the dielectric constant of the first insulating sublayer is greater than that of the second insulating sublayer, and the breakdown strength of the first insulating sublayer is smaller than that of the second insulating sublayer.

In some embodiments, a light-emitting functional layer is formed on the side of the first electrode away from the base substrate, which specifically includes:

Forming sequentially along a direction away from the base substrate: an electron transport layer, a light emitting layer and a hole transport layer; or,

Formed sequentially along the direction away from the base substrate: a hole transport layer, a light emitting layer and an electron transport layer.

An embodiment of the present disclosure also provides a display substrate, including a plurality of the above-mentioned light-emitting transistors.

Description of drawings

The accompanying drawings are used to provide a further understanding of the present disclosure, and constitute a part of the description, together with the following specific embodiments, are used to explain the present disclosure, but do not constitute a limitation to the present disclosure. In the attached picture:

FIG. 1A is a schematic diagram of a light emitting transistor provided in some embodiments of the present disclosure.

FIG. 1B is a schematic diagram of a light-emitting transistor provided in other embodiments of the present disclosure.

2A to 2C are schematic diagrams of the light emitting process of the light emitting transistor provided in some embodiments of the present disclosure.

3 is a plan view of a first electrode of a light emitting transistor provided in some embodiments of the present disclosure.

FIG. 4A is a schematic diagram of a light emitting transistor provided in some other embodiments of the present disclosure.

FIG. 4B is a scanning electron micrograph of a light-emitting transistor provided in some other embodiments of the present disclosure.

Fig. 4C is a schematic diagram of the structure of the DCA molecule and the structure of the MgAg-DCA metal-organic lattice.

FIG. 5 is a schematic diagram of a light emitting transistor provided in still other embodiments of the present disclosure.

FIG. 6 is a flow chart of a manufacturing method of a light-emitting transistor provided in some embodiments of the present disclosure.

FIG. 7 is a schematic structural diagram corresponding to the manufacturing method of the light-emitting transistor provided in some embodiments of the present disclosure.

FIG. 8 is a plan view of a first mask plate and a second mask plate provided in an embodiment of the present disclosure.

FIG. 9 is a schematic structural diagram corresponding to the manufacturing method of the light-emitting transistor provided in other embodiments of the present disclosure.

FIG. 10 is a schematic structural diagram corresponding to the manufacturing method of the light-emitting transistor provided in some further embodiments of the present disclosure.

Detailed ways

Specific embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It should be understood that the specific embodiments described here are only used to illustrate and explain the present disclosure, and are not intended to limit the present disclosure.

Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure shall have the usual meanings understood by those skilled in the art to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Likewise, "comprising" or "comprises" and similar words mean that the elements or items appearing before the word include the elements or items listed after the word and their equivalents, and do not exclude other elements or items. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right" and so on are only used to indicate the relative positional relationship. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

The organic light-emitting transistor (VOLET) with a vertically stacked structure can output high current at a low operating voltage, thus providing the possibility to better solve the active matrix driving of organic light-emitting diodes. The good working performance of VOFET devices is mainly due to the vertical structure, which can reduce the conduction channel of carriers and greatly increase the area of carrier channels, and finally can output high current at low operating voltage.

FIG. 1A is a schematic diagram of a light-emitting transistor provided in some embodiments of the present disclosure, and FIG. 1B is a schematic diagram of a light-emitting transistor provided in other embodiments of the present disclosure. As shown in FIGS. 1A and 1B , the light-emitting transistor includes: a gate 20 , an insulating layer 30 , a first electrode 40 , a light-emitting functional layer 50 and a second electrode 60 . The gate 20 is disposed on the base substrate 10, and the gate 20 may be made of metal materials such as magnesium, aluminum, silver, and the like. The insulating layer 30 is disposed on the side of the gate 20 away from the substrate 10 , and the insulating layer 30 may be a single layer or a multi-layer. The first electrode 40 is disposed on a side of the insulating layer 30 away from the base substrate 10 , and the first electrode 40 has a plurality of through holes H1 . The light-emitting functional layer 50 is disposed on the side of the first electrode 40 away from the base substrate 10 , and the light-emitting functional layer 50 is made of organic materials. The second electrode 60 is disposed on a side of the light emitting functional layer 50 away from the base substrate 10 . Wherein, the first electrode 40 may be a source, and the second electrode 60 may be a drain.

In some embodiments, the light-emitting transistor may adopt an upright structure or an inverted structure. When the light-emitting transistor adopts a positive structure, the light-emitting functional layer 50 may include a hole transport layer 53, a light-emitting layer 52, and an electron transport layer 51 arranged in sequence along the direction away from the base substrate 10; of course, the light-emitting functional layer 50 may also include : the hole injection layer located between the hole transport layer 53 and the first electrode 40 , the electron injection layer located between the electron transport layer 51 and the second electrode 60 . When the light-emitting transistor adopts an inverted structure, the light-emitting functional layer 50 may include an electron transport layer 51 , a light-emitting layer 52 and a hole transport layer 53 arranged in sequence along a direction away from the base substrate 10 . Of course, the light-emitting transistor may also include: an electron injection layer and a hole injection layer, the electron injection layer is located between the first electrode 40 and the electron transport layer 51, and the hole injection layer is located between the second electrode 60 and the hole transport layer 53 . Wherein, the above-mentioned light emitting layer 52 may be an organic light emitting layer, or may be a quantum dot light emitting layer.

2A to FIG. 2C are schematic diagrams of the light emitting process of the light emitting transistor provided in some embodiments of the present disclosure. FIG. 2A to FIG. 2C illustrate the light emitting process by taking an inverted structure of the light emitting transistor as an example. As shown in FIG. 2A, since the gate 20, the first electrode 40 and the insulating layer 30 between the two can be equivalent to a capacitor, when different voltages are applied to the gate 20 and the first electrode 40 (for example, the gate pole 20 is connected to the anode of the first power supply V1, and the first electrode 40 is connected to the cathode of the first power supply V1), under the action of an electric field, a large amount of electrons will be induced at the interface between the first electrode 40 and the insulating layer 30, and these electrons It will be accumulated on the upper surface of the first electrode 40 through the through hole H1 on the first electrode 40 (as shown in FIG. 2B ). When different voltages are applied to the first electrode 40 and the second electrode 60 (for example, the first electrode 40 is connected to the cathode of the second power supply V2, and the second electrode 60 is connected to the anode of the second power supply V2), the second electrode 60 and the hole A large number of holes will be induced at the interface of the transport layer 53, and the holes will tunnel to the light-emitting layer 52 with a certain probability under the attraction of the first electrode 40 voltage; the electrons will tunnel with a certain probability under the attraction of the second electrode 60 voltage. It passes through the light-emitting layer 52 and recombines with the holes therein to emit light. Wherein, the voltage on the gate 20 can realize regulation and control of the luminous brightness.

3 is a plan view of a first electrode of a light emitting transistor provided in some embodiments of the present disclosure. In order to improve the uniformity and stability of the film layer of the first electrode 40, as shown in FIG. The multiple through holes H1 of 40 are divided into multiple through hole groups H0 arranged side by side along the first direction, and each through hole group H0 includes a plurality of through holes H1 arranged along the second direction, wherein the first direction and the second The directions intersect, for example, the first direction is perpendicular to the second direction. In some examples, the through holes H1 in two adjacent through hole groups H0 may be arranged alternately.

By adopting this regular arrangement method, the through holes H1 on the first electrode 40 can be distributed more uniformly, so that the film formation uniformity and stability of the first electrode 40 are better, which is beneficial to improve the electrical properties of the light-emitting transistor. switch characteristics.

In the embodiment of the present disclosure, the thickness of the first electrode 40 can be between 1 nm and 1000 nm, so that electrons at the interface between the first electrode 40 and the insulating layer 30 can move to the interface between the first electrode 40 and the light-emitting functional layer 50 place. For example, the thickness of the first electrode 40 is between 1-500 nm; or between 1-200 nm; or between 1-100 nm; or between 1-50 nm; or between 1-30 nm. Preferably, the thickness of the first electrode 40 is between 1-20 nm, so that electrons can move to the interface between the first electrode 40 and the light-emitting functional layer 50 as much as possible. For example, the thickness of the first electrode 40 is 1 nm or 5 nm or 10 nm or 15 nm or 20 nm.

In some embodiments, the orthographic projection of the through hole H1 on the first electrode 40 on the substrate 10 is a polygon, such as a hexagon, an octagon, a decagon, and the like. Preferably, the orthographic projection of the through hole H1 on the first electrode 40 on the base substrate 10 is circular or approximately circular. In this case, when the phototransistor is used in a display product, the diffraction phenomenon of light can be reduced, thereby improving the display effect of the display product.

Wherein, the diameter of the through hole H1 may be between 50nm and 700nm, for example, the diameter of the through hole H1 is 50nm or 100nm or 200nm or 300nm or 400nm or 500nm or 600nm or 700nm. The total opening area s1 of the plurality of through holes H1 on the first electrode 40 may be 10% to 99% of the orthographic projection area s2 of the gate 20 on the base substrate 10, for example, s1 is 10% to 30% of s2 , or 30% to 50%, or 50% to 70%, or 70% to 90%, or 80% to 99%. The first electrode 40 can leak out of the insulating layer 30 as much as possible, so that electrons are more conducive to entering the light emitting layer 52 .

In some embodiments, the insulating layer 30 may adopt a single-layer structure, or may adopt a multi-layer structure. When the insulating layer 30 adopts a single-layer structure, materials with high dielectric constants such as Al ₂ O ₃ and SiO ₂ can be used, so that the capacitance formed by the gate 20, the first electrode 40 and the insulating layer 30 has a relatively high charge. storage capacity. When the insulating layer 30 includes multiple insulator layers, one of the insulator layers can be made of a material with a high dielectric constant, and the remaining insulator layers can be made of a material with a high breakdown field strength, so that the above-mentioned capacitor has a higher charge storage capacity and at the same time , to prevent the capacitor from being broken down by the electric field during the pressurization process. In one example, as shown in FIG. 1B , the insulating layer 30 includes at least a first insulating sublayer 31 and a second insulating sublayer 32, the first insulating sublayer 31 is located on the side of the second insulating sublayer 32 close to the substrate 10, and the first The dielectric constant of the insulating sublayer 31 is greater than that of the second insulating sublayer 32 , and the breakdown field strength of the first insulating sublayer 31 is smaller than that of the second insulating sublayer 32 . For example, the first insulating sublayer ₃₁ and the second insulating sublayer 32 are selected from _Ta2O3 layer and _SiO2 layer; or, _the first insulating sublayer 31 and the second insulating sublayer 32 are selected from _Y2O3 layer and _SiO2 layer; or, the first insulating sublayer 31 and the second insulating sublayer 32 are selected from an Al ₂ O ₃ layer and a SiO ₂ layer.

In some embodiments, the light-emitting transistor can be a bottom-emitting structure or a top-emitting structure. When the light-emitting transistor adopts a bottom-emitting structure, the second electrode 60 can be made of a metal material with high reflectivity, such as aluminum; the gate 20 can be made of a transparent conductive material such as indium tin oxide (ITO), and because the first The thickness of the electrode 40 is very small, so it will not affect the output of light. When the light-emitting transistor adopts a top-emitting structure, the gate 20 can be made of a metal material with high reflectivity, such as aluminum; the second electrode 60 can be made of a transparent conductive material such as ITO.

3 is a plan view of a first electrode of a light emitting transistor provided in some embodiments of the present disclosure. As shown in FIG. 3, the first electrode 40 includes a plurality of metal parts, and the plurality of metal parts include a plurality of first metal parts 40a arranged side by side in the first direction and a plurality of second metal parts 40a arranged side by side in the first direction. part 40b, the first metal part 40a and the second metal part 40b are alternately arranged one by one. The plurality of first metal parts 40a and the plurality of second metal parts 40b form a network structure. Wherein, the first metal part 40a and the second metal part 40b both include a plurality of first bending parts 401 and a plurality of second bending parts 402, in each metal part, the first bending part 401 and the second bending part 402 Alternately arranged in the second direction, and the first bending portion 401 and the second bending portion 402 are bent in opposite directions. The first direction crosses the second direction, for example, the first direction is perpendicular to the second direction. The plurality of first bent portions 401 and the plurality of second bent portions 402 of every two adjacent metal portions define a plurality of meshes of the grid structure. This mesh is the aforementioned through hole H1.

For the first electrode 40 shown in FIG. 3 , during fabrication, first a plurality of first metal portions 40a may be formed using a first mask, and then a plurality of second metal portions 40b may be formed using a second mask. , so as to obtain the first electrode 40 with a mesh structure.

FIG. 4A is a schematic diagram of a light-emitting transistor provided in some other embodiments of the present disclosure, and FIG. 4B is a scanning electron microscope diagram of a light-emitting transistor provided in some other embodiments of the present disclosure. The light-emitting transistor in FIG. 4A is the same as the light-emitting transistor in FIG. 1A Transistors are similar, and all include: a gate 20, an insulating layer 30, a first electrode 40, a light-emitting functional layer 50, and a second electrode 60 arranged in sequence along a direction away from the substrate 10, wherein the light-emitting functional layer 50 includes An electron transport layer 51, a light emitting layer 52, and a hole transport layer 53 arranged in sequence in the direction of the base substrate 10; or, the luminescent functional layer 50 includes a hole transport layer 53, a light emitting layer 52 arranged in sequence along a direction away from the base substrate 10 and electron transport layer 51 .

Like the light emitting transistor in FIG. 1A , the thickness of the first electrode 40 of the light emitting transistor in FIG. 4A is between 1 nm˜1000 nm. Preferably, the thickness of the first electrode 40 is between 1 nm˜20 nm, so as to facilitate the formation of the through hole H1 on the first electrode 40 . As shown in Figure 4B, the through holes H1 are divided into a plurality of through hole groups H0 distributed along the first direction, and each through hole group H0 includes a plurality of through holes H1 arranged along the second direction, the shape and size of the through holes H1 Reference may be made to the introduction to FIG. 1A above, and details will not be repeated here. The insulating layer 30 can adopt the single-layer structure shown in FIG. 1A , or can adopt the multi-layer structure shown in FIG. 1B . For specific materials, refer to the description of FIG. 1A and FIG. 1B above, which will not be repeated here.

Different from the light-emitting transistor in FIG. 1A, in the light-emitting transistor shown in FIG. 4A, a topological insulating pattern layer may also be included, and the topological insulating pattern layer includes a plurality of topological insulating pattern parts 41 arranged at intervals. The topological insulating pattern parts 41 are provided in one-to-one correspondence with the through holes H1 of the first electrode 40 . It should be noted that the one-to-one correspondence between the topological insulating pattern part 41 and the through hole H1 of the first electrode 40 means that each topological insulating pattern part 41 corresponds to one through hole H1, and different topological insulating pattern parts 41 correspond to different through holes H1. The hole H1, each topological insulation pattern portion 41 may be located in the corresponding through hole H1.

The material of the topological insulating pattern portion 41 includes a metal-organic topological insulator material, the material of the first electrode 40 includes a metal material, and the metal elements in the metal material are the same as the metal elements in the metal-organic topological insulator material. Using a metal-organic topological insulator material to make the topological insulating pattern portion 41 can prevent specific metal elements from growing on the surface of the topological insulating pattern portion 41, thereby facilitating the fabrication of the first electrode with multiple through holes H1.

For the light-emitting transistor shown in FIG. 4A , in the fabrication process of its first electrode 40 , a plurality of topological insulating pattern parts 41 can be formed on the insulating layer 30 first, wherein the topological insulating pattern parts 41 on the base substrate 10 The shape and size of the orthographic projection can be the same as the shape and size of the through hole H1 on the first electrode 40 to be formed, and the height of the topological insulating pattern part 41 can be greater than or equal to the thickness of the first electrode 40 to be formed. Afterwards, the metal material can be deposited by a physical vapor deposition (Physical Vapor Deposition, PVD) process, and the metal elements in the metal material are the same as the metal elements in the metal-organic topological insulator material, so that the metal material can be deposited on the topological insulating pattern part. 41, thereby forming the first electrode 40 with the through hole H1.

In some examples, the metal-organic topological insulating material includes MgAg-DCA (dicyanoanthracene). Figure 4C is a schematic diagram of the structure of the DCA molecule and the structure of the MgAg-DCA metal-organic lattice. In Figure 4C, different dots represent different atoms . When MgAg-DCA is used as the topological insulating material, the material of the first electrode 40 may include magnesium-silver alloy.

FIG. 5 is a schematic diagram of a light-emitting transistor provided in some other embodiments of the present disclosure. The light-emitting transistor in FIG. 5 is similar to the light-emitting transistor in FIG. , an insulating layer 30, a first electrode 40, a luminescent functional layer 50, and a second electrode 60, wherein the luminescent functional layer 50 includes an electron transport layer 51, a luminescent layer 52, and a hole transport layer arranged in sequence along a direction away from the substrate 10. layer 53 ; or, the light emitting functional layer 50 includes a hole transport layer 53 , a light emitting layer 52 and an electron transport layer 51 arranged in sequence along a direction away from the base substrate 10 .

Same as the light emitting transistor in FIG. 1A , the thickness of the first electrode 40 of the light emitting transistor in FIG. 5 is between 1 nm and 1000 nm. Preferably, the thickness of the first electrode 40 is between 1 nm and 20 nm, so as to facilitate the formation of the through hole H1 on the first electrode 40 . The shape and size of the through hole H1 and the structure and material of the insulating layer 30 can be described above for FIG. 1 , and will not be repeated here.

Different from the light-emitting transistor shown in FIG. 1A, in the light-emitting transistor shown in FIG. It may be integrally formed with at least a part of the insulating layer 30 . For example, when the insulating layer 30 is a single-layer structure, the insulating protrusion 31 and the insulating layer 30 can form an integral structure; The layers form an integral structure. Each insulating protrusion 31 may correspond to a through hole H1, and different insulating protrusions 31 may correspond to different through holes H1.

As shown in FIG. 5 , the light-emitting transistor includes a first metal layer, and the first metal layer includes a first electrode 40 and a plurality of redundant electrodes 42, and each redundant electrode 42 is correspondingly arranged on an insulating protrusion 31 away from the base substrate 10. On the surface of , different redundant electrodes 42 are arranged on different insulating protrusions 31 .

Wherein, the materials of the first electrode 40 and the redundant electrode 42 may include Ag, Cu, Al and other metal materials. When the redundant electrode 42 and the first electrode 40 are produced synchronously, the metal material is deposited on the base substrate 10 on which the insulating layer 30 and the insulating bump 31 are formed by a PVD process such as evaporation, and a part of the metal material is deposited on the insulating bump. 31, thereby forming the redundant electrode 42; another part of the metal material is deposited on the insulating layer 30 where the insulating protrusion 31 is not formed, thereby forming the first electrode 40 above. The height of the insulating protrusion 31 satisfies that when the first metal layer is formed by PVD process, the redundant electrode 42 is disconnected from the first electrode 40 . For example, the height of the insulating protrusion 31 is 1.2-2 times, or 2-4 times the thickness of the first electrode 40 .

Wherein, when forming the first electrode 40 and the redundant electrode 42 , the thickness of the deposited metal material is relatively thin, for example, not greater than 1000 nm, which is beneficial to disconnect the redundant electrode 42 from the first electrode 40 . Exemplarily, the thickness of the deposited metal material is between 1-500 nm; or between 1-200 nm; or between 1-100 nm; or between 1-50 nm; or between 1-30 nm. Preferably, the thickness of the metal material is between 1nm and 20nm. In addition, the cross-sectional area of the end of the insulating protrusion 31 close to the base substrate 10 is smaller than the cross-sectional area of the end of the insulating protrusion 31 away from the base substrate 10, which is also conducive to disconnecting the redundant electrode 42 from the first electrode 40. . In some examples, the longitudinal section of the insulating protrusion 31 is an inverted trapezoid or a "T" shape. It should be noted that the “cross-sectional area” refers to the area parallel to the cross-section of the base substrate 10 , and the “longitudinal cross-section” refers to the cross-section perpendicular to the base substrate 10 .

It should be noted that, in some embodiments, after the formation of the first electrode 40 and the redundant electrode 42 , the redundant electrode 42 may also be removed; or, the redundant electrode 42 and the insulating protrusion 31 may be removed together.

FIG. 6 is a flowchart of a method for manufacturing a light-emitting transistor provided in some embodiments of the present disclosure. As shown in FIG. 6 , the method for manufacturing a light-emitting transistor includes:

S1. Forming a gate on the base substrate.

S2, forming an insulating layer on a side of the gate away from the substrate.

S3, forming a first electrode on the side of the insulating layer away from the base substrate, the first electrode has a plurality of through holes, and the plurality of through holes of the first electrode are divided into a plurality of through holes arranged side by side in the first direction groups, each of the through hole groups includes a plurality of through holes arranged in a second direction, and the first direction intersects with the second direction.

S4, forming a light-emitting functional layer on the side of the first electrode away from the base substrate.

S5, forming a second electrode on a side of the light-emitting functional layer away from the base substrate.

Wherein, the first electrode may be a source, and the second electrode may be a drain.

In the manufacturing method provided by the embodiment of the present disclosure, the first electrode of the manufactured light-emitting transistor has a plurality of through holes, and the plurality of through holes are arranged regularly, so that the through holes H1 on the first electrode 40 are more distributed. Uniformity, thereby improving the uniformity and stability of the film formation of the first electrode, which is beneficial to improving the electrical switching characteristics of the light-emitting transistor.

The manufacturing method in the embodiments of the present disclosure will be specifically introduced below in conjunction with the accompanying drawings.

FIG. 7 is a schematic structural diagram corresponding to a method for manufacturing a light-emitting transistor provided in some embodiments of the present disclosure. As shown in FIG. 7 , the method for manufacturing a light-emitting transistor includes:

S11 , forming the gate 20 on the base substrate 10 .

In this step S11 , the gate 20 may be formed on the base substrate 10 by a PVD process, for example, the gate 20 may be formed by evaporation or sputtering. When the light-emitting transistor has a bottom-emitting structure, the gate 20 can be made of a transparent conductive material such as ITO.

S12 , forming an insulating layer 30 on a side of the gate 20 away from the base substrate 10 .

In this step S12, the insulating layer 30 may be formed by PVD or chemical vapor deposition (CVD) or atomic layer deposition (ALD) deposition process. The insulating layer 30 may be a single-layer structure, or may include multiple insulating sub-layers. For specific materials, please refer to the description above, which will not be repeated here.

S13 , using a PVD process to form a first electrode 40 on a side of the insulating layer 30 away from the base substrate 10 , and the first electrode 40 has a plurality of through holes H1 .

The first electrode 40 may have a grid structure as shown in FIG. 3 . In this case, the first electrode 40 having a through hole H1 may be formed by using a first mask and a second mask. 8 is a plan view of a first mask and a second mask provided in an embodiment of the present disclosure. As shown in FIG. The diaphragm 72 has a plurality of second openings 72h spaced apart from each other. In step S13, the first mask 71 can be used to deposit metal material on the insulating layer 30 to form a plurality of first metal parts 40a spaced apart from each other. For the specific shape of the first metal part 40a, refer to FIG. 3 above. Afterwards, using a second mask plate 72, metal material is deposited on the insulating layer 30 to form a plurality of second metal portions 40b spaced apart from each other. For the specific shape of the second metal portion 40b, refer to the above reference to FIG. 3 Described, a plurality of first metal parts 40 a and a plurality of second metal parts 40 b form a mesh-shaped first electrode 40 (as shown in FIG. 3 ). Wherein, when forming the first metal part 40a and the second metal part 40b, both the vapor deposition process can be used. That is, when forming the first metal part 40a, the first mask 71 is placed between the base substrate 10 and the evaporation source, and the metal material in the evaporation source is sublimated into gaseous particles after being heated, and transported to the Base substrate 10, and then form the first metal part 40a; when forming the second metal part 40b, the second mask is placed between the base substrate 10 and the evaporation source, and the metal material in the evaporation source is sublimated into a gaseous state after being heated The particles are transported to the base substrate 10 through the second opening 72h, thereby forming the second metal part 40b.

S14 , forming a light-emitting functional layer 50 on a side of the first electrode 40 away from the base substrate 10 .

For an inverted light emitting transistor, step S14 may include: sequentially forming an electron transport layer 51 , a light emitting layer 52 and a hole transport layer 53 along a direction away from the base substrate 10 . Of course, it is also possible to form the electron injection layer before forming the electron transport layer 51 and form the hole injection layer after forming the hole transport layer 53 .

For the positive light-emitting transistor, step S14 may include: sequentially forming a hole transport layer 53 , a light-emitting layer 52 and an electron transport layer 51 along a direction away from the base substrate 10 . Of course, the hole injection layer may be formed before the hole transport layer 53 and the electron injection layer may be formed after the electron transport layer 51 is formed.

S15 , forming a second electrode 60 on a side of the light emitting functional layer 50 away from the base substrate 10 .

In this step S15, the second electrode 60 may be formed on the base substrate 10 by a PVD process, for example, the second electrode 60 may be formed by an evaporation or sputtering process. When the light-emitting transistor has a bottom-emitting structure, the second electrode 60 can be made of a metal material, and when the light-emitting transistor has a top-emitting structure, the second electrode 60 can be made of a transparent conductive material such as ITO.

FIG. 9 is a schematic structural diagram corresponding to a method for manufacturing a light-emitting transistor provided in other embodiments of the present disclosure. As shown in FIG. 9 , the method for manufacturing a light-emitting transistor includes:

S21 , forming the gate 20 on the base substrate 10 . The process of this step S21 is the same as that of step S11, and will not be repeated here.

S22 , forming an insulating layer 30 on a side of the gate 20 away from the base substrate 10 . The process of step S22 is the same as step S12, and will not be repeated here.

S23 , using a PVD process to form a first electrode 40 on a side of the insulating layer 30 away from the base substrate 10 . Wherein, the PVD process may specifically be an evaporation process, and the step S23 may specifically include S231-S232:

S231, forming a topological insulating pattern layer on the side of the insulating layer 30 away from the base substrate 10, the topological insulating pattern layer includes a plurality of topological insulating pattern parts 41 spaced apart from each other, and the material of the topological insulating pattern parts 41 includes a metal-organic topological insulator Material.

In step S231, a plurality of topological insulating pattern parts 41 can be formed by evaporation. As shown in FIG. After being heated, they are sublimated into gaseous particles, and thus adhere to the insulating layer 30 through the opening of the mask plate 70 .

S232. Evaporate a metal material, the metal element in the metal material is the same as the metal element in the metal-organic topological insulator material, so as to prevent the metal material from being formed on the surface of the topological insulating pattern part 41, but deposited on the topologically unformed topological insulator The region of the insulating pattern portion 41 further forms the first electrode 40 having a through hole H1 , wherein the through hole H1 corresponds to the topological insulating pattern portion 41 one-to-one. In step S232 , metal material is set in the evaporation source 82 , and no mask plate needs to be set during evaporation.

S24 , forming a light-emitting functional layer 50 on a side of the first electrode 40 away from the base substrate 10 . The step S24 may be the same as the step S14, which will not be repeated here.

S25 , forming the second electrode 60 on the side of the light-emitting functional layer 50 away from the base substrate 10 . The step S25 may be the same as the step S15, which will not be repeated here.

FIG. 10 is a schematic structural diagram corresponding to the method for manufacturing a light-emitting transistor provided in some further embodiments of the present disclosure. As shown in FIG. 10 , the method for manufacturing a light-emitting transistor includes:

S31 , forming the gate 20 on the base substrate 10 . The step S31 may be the same as the step S11, which will not be repeated here.

S32 , forming an insulating layer 30 on a side of the gate 20 away from the base substrate 10 . The step S32 may be the same as the step S12, and will not be repeated here.

S33 , forming a plurality of insulating protrusions 31 on a side of the insulating layer 30 away from the base substrate 10 . Wherein, the height and size setting of the insulating protrusion 31 can refer to the above description in FIG. 5 , and will not be repeated here.

Specifically, this step S33 may include: forming an insulating material layer on a side of the insulating layer 30 away from the base substrate 10 , and etching the insulating material layer, thereby forming a plurality of insulating protrusions 31 . Alternatively, the insulating layer 30 formed in step S32 is etched to form a plurality of insulating protrusions 31 .

S34 , using a PVD process to form a first electrode 40 on a side of the insulating layer 30 away from the base substrate 10 , where the first electrode 40 is a metal electrode having a through hole H1 .

Specifically, step S34 may include: using a PVD process, depositing a metal material on the insulating layer 30 and the plurality of insulating protrusions 31, thereby forming a first metal layer, the first metal layer including the first electrode 40 and a plurality of redundant electrodes 42, each redundant electrode 42 is arranged on the surface of an insulating protrusion 31 away from the base substrate 10, the first electrode 40 is located in the area where the insulating protrusion 31 is not formed on the insulating layer, and the through hole H1 on the first electrode 40 There is a one-to-one correspondence with the insulating protrusions 31 .

It should be noted that the height of the insulating protrusion 31 formed in step S33 should meet the requirement that the first electrode 40 is disconnected from the redundant electrode 42 when the first metal layer is formed by the PVD process.

S35 , forming a light-emitting functional layer 50 on a side of the first electrode 40 away from the base substrate 10 . This step S35 may be the same as the above step S14, and will not be repeated here.

S36 , forming the second electrode 60 on the side of the light-emitting functional layer 50 away from the base substrate 10 . This step S36 may be the same as the above-mentioned step S15, which will not be repeated here.

In another embodiment, after the formation of the first metal layer, the redundant electrodes 42 on the insulating protrusions 31 may also be removed. Wherein, only the redundant electrode 42 may be removed, or the redundant electrode 42 and the insulating protrusion 31 may be removed together. For example, when making the insulating bump 31, the photoresist material that is easy to peel off is used to make the insulating bump 31, and when the redundant electrode 42 is removed, the insulating bump 31 and the redundant electrode are separated by stripping the photoresist. 42 are also removed.

In the manufacturing method provided by the embodiment of the present disclosure, the first electrode of the manufactured light-emitting transistor has a plurality of through holes, and the plurality of through holes are arranged regularly, so that the through holes H1 on the first electrode 40 are more distributed. Uniformity, thereby improving the uniformity and stability of the film formation of the first electrode, which is beneficial to improving the electrical switching characteristics of the light-emitting transistor. In addition, the first electrode 40 is made by PVD process. Compared with the solution method, the film formation uniformity and stability of the PVD process are better, which is beneficial to further improve the electrical switching characteristics of the light-emitting transistor.

Embodiments of the present disclosure also provide a display substrate, which includes a plurality of light-emitting transistors in the above embodiments.

The display substrate may include a plurality of sub-pixels, for example, a plurality of red sub-pixels, a plurality of green sub-pixels and a plurality of blue sub-pixels, each sub-pixel may be provided with the above-mentioned light-emitting transistor, and the areas of sub-pixels of different colors may be the same, It can also be different. When the sub-pixels of different colors have the same area, the total area of the through holes on the first electrodes in different sub-pixels can be the same; The total via area can be positively correlated with the area of the sub-pixel.

Since the electrical characteristics of the light emitting transistors in the embodiments of the present disclosure are better, the display effect of the display substrate using the light emitting transistors is better.

It can be understood that, the above implementations are only exemplary implementations adopted to illustrate the principle of the present disclosure, but the present disclosure is not limited thereto. For those skilled in the art, without departing from the spirit and essence of the present disclosure, various modifications and improvements can be made, and these modifications and improvements are also regarded as the protection scope of the present disclosure.

Claims

A light emitting transistor comprising:

The gate is arranged on the base substrate;

an insulating layer disposed on a side of the gate away from the base substrate;

The first electrode is arranged on the side of the insulating layer away from the base substrate, the first electrode has a plurality of through holes, and the plurality of through holes of the first electrode are divided to be arranged side by side in the first direction a plurality of via groups, each via group comprising a plurality of vias arranged in a second direction, the first direction intersecting the second direction;

A light-emitting functional layer disposed on a side of the first electrode away from the base substrate;

The second electrode is disposed on a side of the light-emitting functional layer away from the base substrate.
The light emitting transistor according to claim 1, wherein the light emitting transistor further comprises: a topological insulating pattern layer disposed on the insulating layer, the topological insulating pattern layer includes a plurality of topological insulating pattern parts arranged at intervals, so The topological insulating pattern part is provided in one-to-one correspondence with the through holes, the material of the topological insulating pattern part includes a metal-organic topological insulator material, the material of the first electrode includes a metal material, and the metal in the metal material The elements are the same as the metal elements in the metal-organic topological insulator material.
The light-emitting transistor according to claim 2, wherein the metal-organic topological insulating material comprises MgAg-DCA, and the material of the first electrode comprises magnesium-silver alloy.
The light-emitting transistor according to claim 1, wherein a plurality of insulating protrusions spaced apart from each other are provided on the surface of the insulating layer away from the base substrate, and the insulating protrusions correspond to the through holes one by one;

The light-emitting transistor includes a first metal layer, and the first metal layer includes the first electrode and a plurality of redundant electrodes; each of the redundant electrodes is arranged on one of the insulating protrusions away from the base substrate On the surface of , the redundant electrode is disconnected from the first electrode.
The light-emitting transistor according to claim 4, wherein a cross-sectional area of an end of the insulating protrusion close to the base substrate is smaller than a cross-sectional area of an end of the insulating protrusion away from the base substrate.
The light-emitting transistor according to claim 1, wherein the first electrode has a grid structure, and the grid structure includes a plurality of metal parts arranged side by side in the first direction, and every two adjacent metal parts The metal part is mirror-symmetrical, and the metal part includes: a plurality of first bent parts and a plurality of second bent parts, the first bent parts and the second bent parts are arranged alternately in the second direction, so The first curved portion and the second curved portion bend in opposite directions; wherein, the plurality of first curved portions and the plurality of second curved portions of every two adjacent metal portions define the grid structure multiple meshes.
The light-emitting transistor according to any one of claims 1 to 6, wherein the orthographic projection of the through hole on the base substrate is polygonal or substantially circular.
The light emitting transistor according to any one of claims 1 to 6, wherein the thickness of the first electrode is between 1 nm˜1000 nm.
The light-emitting transistor according to any one of claims 1 to 6, wherein the insulating layer at least includes: a first insulating sublayer and a second insulating sublayer, the first insulating sublayer is located close to the second insulating sublayer One side of the base substrate, the dielectric constant of the first insulating sublayer is greater than that of the second insulating sublayer, and the breakdown field strength of the first insulating sublayer is smaller than that of the second insulating sublayer. Wear strong.
The light-emitting transistor according to any one of claims 1 to 6, wherein the light-emitting functional layer comprises: an electron transport layer, a light-emitting layer, and a hole transport layer arranged in sequence along a direction away from the base substrate; or ,

The light-emitting functional layer includes: a hole transport layer, a light-emitting layer and an electron transport layer arranged in sequence along a direction away from the base substrate.
A method for manufacturing a light-emitting transistor, comprising:

forming a gate on the base substrate;

forming an insulating layer on a side of the gate away from the substrate;

A first electrode is formed on the side of the insulating layer away from the base substrate, the first electrode has a plurality of through holes, and the plurality of through holes of the first electrode are divided into a plurality of through holes arranged side by side in the first direction. a plurality of via groups, each via group comprising a plurality of vias arranged in a second direction, the first direction intersecting the second direction;

forming a light-emitting functional layer on the side of the first electrode away from the base substrate;

A second electrode is formed on a side of the light emitting functional layer away from the base substrate.
The manufacturing method according to claim 11, wherein forming the first electrode on the side of the insulating layer away from the base substrate specifically comprises:

A topological insulating pattern layer is formed on the side of the insulating layer away from the base substrate, the topological insulating pattern layer includes a plurality of topological insulating pattern parts arranged at intervals, and the material of the topological insulating pattern parts includes metal-organic topology Insulator material;

Depositing a metal material on the insulating layer, the metal element in the metal material is the same as the metal element in the metal-organic topological insulator material, so as to form a first electrode with a plurality of through holes, and the The through holes are in one-to-one correspondence with the topological insulation pattern parts.
The manufacturing method according to claim 12, wherein the topological insulating material comprises MgAg-DCA; the material of the first electrode comprises magnesium-silver alloy.
The manufacturing method according to claim 11, wherein forming the first electrode on the side of the insulating layer away from the base substrate specifically comprises:

forming a plurality of first metal parts spaced apart from each other on the insulating layer;

forming a plurality of second metal parts spaced apart from each other on the insulating layer;

Wherein, the plurality of first metal parts and the plurality of second metal parts form a first electrode of a grid structure, and the plurality of first metal parts and the plurality of second metal parts are arranged side by side in the first direction , each of the first metal parts is mirror-symmetrical to its adjacent second metal part, and each of the first metal part and the second metal part includes: a plurality of first metal parts alternately arranged in the second direction A bent part and a plurality of second bent parts, the first bent part and the second bent part are bent in opposite directions; wherein, each of the first metal parts and the number of adjacent second metal parts A first bend and a plurality of second bends define a plurality of cells of the lattice structure.
The manufacturing method according to claim 11, further comprising: forming a plurality of insulating protrusions spaced apart from each other on a side of the insulating layer away from the base substrate;

Forming a first electrode on a side of the insulating layer away from the base substrate, specifically includes:

Depositing a first metal layer on the insulating layer and the plurality of insulating protrusions, the first metal layer includes the first electrode and a plurality of redundant electrodes, the insulating protrusion and the first electrodes Each of the redundant electrodes is arranged on the surface of one of the insulating protrusions away from the base substrate, and the redundant electrodes are disconnected from the first electrodes.
The manufacturing method according to claim 15, wherein the cross-sectional area of the end of the insulating protrusion close to the base substrate is smaller than the cross-sectional area of the end of the insulating protrusion away from the base substrate.
The manufacturing method according to any one of claims 11 to 16, wherein the first electrode is formed by a physical vapor deposition process.
The manufacturing method according to any one of claims 11 to 16, wherein the physical vapor deposition process is an evaporation process.
The manufacturing method according to any one of claims 11 to 16, wherein forming an insulating layer on a side of the gate away from the base substrate specifically comprises:

forming a first insulating sublayer on a side of the gate away from the substrate;

forming a second insulating sublayer on a side of the first insulating sublayer away from the base substrate;

Wherein, the dielectric constant of the first insulating sublayer is greater than that of the second insulating sublayer, and the breakdown strength of the first insulating sublayer is smaller than that of the second insulating sublayer.
The manufacturing method according to any one of claims 11 to 16, wherein forming a light-emitting functional layer on the side of the first electrode away from the base substrate specifically includes:

Forming sequentially along a direction away from the base substrate: an electron transport layer, a light emitting layer and a hole transport layer; or,

Formed sequentially along the direction away from the base substrate: a hole transport layer, a light emitting layer and an electron transport layer.
A display substrate, comprising the light-emitting transistor described in any one of claims 1-10.