WO2023105089A1

WO2023105089A1 - Semiconductor structures and methods

Info

Publication number: WO2023105089A1
Application number: PCT/EP2022/085415
Authority: WO
Inventors: Gregory U'ren; Nicolas Pons
Original assignee: X-Fab France SAS
Priority date: 2021-12-10
Filing date: 2022-12-12
Publication date: 2023-06-15

Abstract

A semiconductor structure comprises:a silicon substrate comprising two adjoining device regions comprising a first device region comprising a bipolar junction transistor, BJT, and a second device region comprising a complementary metal oxide semiconductor, CMOS, device; anda buried oxide, BOX, layer located in said silicon substrate in said second device region and not located in at least part of said first device region.

Description

Semiconductor structures and methods

TECHNICAL FIELD

The invention relates to semiconductor structures formed from a silicon on insulator (SOI) substrate, and in particular structures where a region of the substrate has been reconstructed to remove the buried oxide layer of the SOI substrate

BACKGROUND

Complementary metal oxide semiconductor (CMOS) technology such as field effect transistors (FETs) can be used to form radio frequency (RF) devices such as low noise amplifiers (LNA). Preferably such devices are formed on a silicon on insulator (SOI) substrate for improved isolation. RF-SOI is the dominant technology for RF-front-end applications in RF mobile, where the application frequencies are < 6 GHz.

However, for high frequency (e.g. > 6 GHz) applications, a bipolar junction transistor (BJT) such as an NPN transistor may be preferable to the equivalent NFET. For example, a SiGe/SiGeC hetero bipolar transistor (HBT) outperforms Si N-MOS transistors with respect to the maximum transit frequency (Ft) and the minimum noise figure (NFmin). A BJT may be implemented together with CMOS technology on bulk Si, which is referred to as BiCMOS.

The BiCMOS technology has had modest success in niche application and is still developing.

SUMMARY

The present invention provides a semiconductor structure, a low noise amplifier comprising the semiconductor structure and a method of forming a semiconductor structure as set out in the appended claims.

Specific embodiments of the invention are set out below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

Figure 1 shows a schematic cross section of a semiconductor structure according to an embodiment;

Figure 2A shows a schematic diagram of a first step of a method of forming a semiconductor structure according to an embodiment;

Figure 2B shows a second step of the method;

Figure 2C shows a third step of the method;

Figure 2D shows a fourth step of the method;

Figure 2E shows a fifth step of the method;

Figure 2F shows a sixth step of the method;

Figure 3 shows a flow diagram illustrating the steps of a method of forming a semiconductor structure according to an embodiment;

Figure 4A shows a schematic diagram of a step of a method of forming a semiconductor structure according to an embodiment, wherein the active layer is oxidised before removing;

Figure 4B shows a subsequent step of the method after removing a part of the oxide layer;

Figure 4C shows a subsequent step of the method, after providing an epitaxial silicon layer; and

Figure 4D shows a subsequent step of the method, after planarization.

DETAILED DESCRIPTION Figure 1 shows a schematic diagram of a part of a low noise amplifier comprising a semiconductor structure 2 according to an embodiment. The semiconductor structure comprises a silicon on insulator (SOI) substrate 3 comprising a first region 4 with a heterojunction bipolar transistor (HBT) 6 and a second, adjoining region 8 comprising a complementary metal oxide semiconductor (CMOS) device 10. The two regions 4 and 8 are separated by shallow trench isolation (STI) 12. The SOI substrate 3 comprises three layers being a silicon handling wafer 14 located at the bottom, a buried oxide (BOX) layer 16 and a top silicon layer 18 above the BOX layer 16. The CMOS device 10 in the second region 8 is located in the top silicon layer 18, and benefits from the electrical insulation provided by the BOX layer 16. The BOX layer 16 of the SOI substrate 3 has been substantially removed from the first region 4. Instead, a doped epitaxial silicon layer 20 is located over the handling wafer 14 in the first region 4 of the substrate 3. The first region may be referred to as the “bulk” region, as it comprises bulk Si instead of SOI. The HBT 6 is formed in this epitaxial layer 20 (i.e. in the bulk). A HBT 6 such as an NPN transistor may require high heat dissipation compared to e.g. a field effect transistor (FET), and the heat dissipation through silicon dioxide (SiO2) is relatively low compared to bulk silicon (by about a factor of two). Hence, by forming the HBT 6 in the first region 4 where the BOX layer 16 has been removed, the heat dissipation from the HBT 6 can be significantly improved, while retaining the benefits of forming CMOS device 10 on SOI. Importantly, the HBT 6 is level with the CMOS device 10 (i.e. they are located at substantially the same height in the substrate 3).

The top silicon layer 18 of the SOI substrate 3 has a thickness in the range of about 145 nm. The underlying BOX layer 16 has a thickness of about 1000 nm. The thickness of the epitaxial silicon layer is determined by the thickness of the top silicon layer 18 and the thickness of the BOX layer 16 and is accordingly about 1145 nm in this embodiment.

The top silicon layer 18 has a resistivity of about 20 Q-cm, which is much lower than the silicon handling wafer, which has a resistivity of more than 3 kQ-cm. The doped epitaxial silicon layer 20 has a low resistivity of about 0.5 Q-cm.

In general the semiconductor structure 2 comprises further layers such as metal layers (not shown) for connecting the CMOS device 10 and to the HBT 6. Typically the structure 2 would comprise at least four metal layers (three thin layers and one thick topmost layer).

Figures 2A to 2F illustrate the steps of a method of forming a semiconductor structure. Whilst the method specifically shows the formation of a HBT, a 1.2 V CMOS on SOI and a 2.5 V CMOS on SOI, the method can be applied to form other CMOS devices starting with a SOI substrate.

In Figure 2A, a starting substrate being a SOI substrate 22 (e.g. a high resistivity SOI substrate with a 130 nm CMOS node) comprising a handling wafer 24, a BOX layer 26 and a top silicon layer 28. The substrate 22 may be cleaned and a pad oxide layer 30 and a nitride layer 32 formed thereon. The substrate 22 can be conceptually divided into three regions, in the first region 34 on the left the HBT device will be formed, in the second region 36 in the middle the 1.2 V CMOS device will be formed, and in the third region 38 on the right the 2.5 V CMOS device will be formed.

In Figure 2B, the top silicon layer 28 and the BOX layer 26 have been removed from a part of the first region 34. The layers may be removed by the following sequence of steps. First a MUV photo exposure where the bipolar device is intended to be constructed, the exposed oxide is removed with an RIE operation (reactive-ion etching operation) effectively creating a hard mask. The photoresist is removed and the exposed superficial Si is removed while all other regions are protected with the oxide hardmask with a RIE operation. To avoid lateral etch and preserve the intended dimensions, the majority of the BOX layer 26 is removed with a RIE operation. The fidelity of the underlying Si surface is critical. The remaining BOX 26 is removed with wet chemistry selective to Si. Removing the BOX layer 26 exposes the underlying handling wafer 24. The BOX layer 26 extends laterally on either side of the first region 34.

In Figure 2C, a doped epitaxial silicon layer 40 is formed in the first region 34 where the handle wafer 24 is exposed. The epitaxial layer 40 may be grown to a thickness of about 1800 nm so that it extends above the top silicon layer 28.

In Figure 2D, chemical mechanical planarization (CMP) is performed to level the epitaxial silicon layer 40. CMP may be followed by cleaning, oxidation to form an oxide layer 42 on the epitaxial layer 40, nitride removal for shallow trench isolation (STI) processing, nitride deposition to form nitride layer 44, and low pressure chemical vapour deposition (LPCVD) tetraethyl orthosilicate (TEOS) deposition to form a second oxide layer 46.

In Figure 2E, the epitaxial layer 40 and the top silicon layer 28 are patterned to separate HBT 48 and MOS devices 50 and 52 respectively. The patterning may comprise the following steps: DUV photo, HM open, strip, Si etch.

In Figure 2F, a dielectric layer 54 is formed to isolate the HBT and CMOS devices. The perimeter of the epitaxial layer 40 (i.e. of the bipolar active region) should be forced as STI to avoid fences. The process may comprise the following steps: cleaning, oxidation, HDP deposition, oxide CMP, cleaning, annealing, and nitride removal. A standard STI process may be used since the HBT region 34 is level with the MOS regions 36 and 38.

Figure 3 shows a flow diagram illustrating the steps of a method of forming a semiconductor structure such as the semiconductor structure illustrated in Figure 1 according to an embodiment. The method comprises providing a SOI substrate comprising a top silicon layer on a BOX layer on a silicon handle wafer (Step S1), removing said top silicon layer and said BOX layer in a first region of said SOI substrate to expose said silicon handle wafer (Step S2), performing doped silicon epitaxy to provide an epitaxial silicon layer on said silicon handle wafer in said first region (Step S3), and forming a BJT in said epitaxial silicon layer (Step S4).

Figures 4A to 4D illustrates the steps of a part of a method of forming a semiconductor structure. For example, Figure 4A may show a step of the method following the step illustrated in Figure 2A and before the step illustrated in Figure 2B above

Figure 4A illustrates a cross section of a part of a semiconductor structure comprising a SOI wafer 22 comprising a high resistivity silicon substrate 24, an active layer 28, and a BOX layer 26 inbetween. A pad oxide layer 30 and nitride layer 32 are provided on the active layer 28. The structure is divided into three laterally separated regions, being a first region 34 where the HBT device will be formed, a second region 36 where a 1.2 V CMOS device will be formed, and a third region 38 where a 2.5 V CMOS device will be formed. Following a hardmask open step to remove a part of the nitride layer 32 and oxide layer 30 to expose a corresponding part of the active layer 28 in the first region 34, local oxidation (LOCOS) is used to oxidise the exposed part of the active layer 28 to create an oxide layer 27 that goes all the way down to the BOX layer 26.

Figure 4B shows the structure after the majority of the oxide layer 27 and a part of the BOX layer 26 have been removed from the first region 34. The structure may be etched to expose the underlying silicon substrate 24. For example, the layers may be removed by the following sequence of steps. A MUV photo exposure is performed in the first region 34 where the bipolar device is intended to be constructed. The exposed oxide is removed with an RIE operation effectively creating a hard mask. To avoid lateral etch and preserve the intended dimensions, the majority of the BOX layer 26 is removed with a RIE operation. The fidelity of the underlying Si surface is critical. The remaining BOX 26 can be removed with wet chemistry selective to Si. Removing the BOX layer 26 exposes the underlying handling wafer 24. The BOX layer 26 extends laterally on either side of the first region 34. A part of the oxide layer 27 on either side of the etched trench remains and laterally covers the active layer 28 in the first region 34 after the etch step. Hence, the only exposed (single crystal) silicon is the handling wafer 24 at the bottom of the trench.

In Figure 4C, a doped epitaxial silicon layer 40 is formed in the first region 34 where the handle wafer 24 is exposed. The epitaxial layer 40 may be grown to a thickness of about 1800 nm so that it extends above the top silicon layer 28. The overgrowth of the epitaxial layer 40 allows levelling. The remaining oxide layer 27 on the sides protects the crystalline surfaces of the active layer 28 and prevents growth from these surfaces that could otherwise negatively affect the quality of the epitaxial layer 40.

In Figure 4D, chemical mechanical planarization (CMP) is performed to level the epitaxial silicon layer 40. CMP may be followed by cleaning, oxidation to form an oxide layer 42 on the epitaxial layer 40, nitride removal for shallow trench isolation (STI) processing, nitride deposition to form nitride layer 44, and low pressure chemical vapour deposition (LPCVD) tetraethyl orthosilicate (TECS) deposition to form a second oxide layer 46. The three regions (34, 36, 38) are coplanar (a.k.a. level), which can allow for more efficient device formation. For example, by being coplanar, a single STI process can be used to create isolation structures in all three regions. Following the step illustrated in Figure 4D, the method may continue as described in relation to Figures 2E to 2F above.

In general embodiments described herein may provide a semiconductor structure comprising a silicon substrate comprising a first device region comprising a bipolar junction transistor (BJT) and an adjoining, second device region comprising a complementary metal oxide semiconductor (CMOS) device (typically in an ultra-thin body, UTB, SOI substrate region). The structure further comprises a buried oxide (BOX) layer located in said silicon substrate in the second device region and not located (substantially removed) in said fist device region. By not having the BOX layer in the bipolar region, the heat dissipation can be significantly improved. Also, by removing the BOX layer, instead of e.g. forming the BJT on top of the SOI substrate, the BJT and CMOS can be level, which can make manufacturing easier.

Previously BiCMOS has only been successfully implemented on bulk Si (not SOI). A problem with implementing BiCMOS technology on SOI is a lack of performance (for thick SOI), and strong self-heating effects (on thin body SOI). Embodiments disclosed herein can solve both these problems by using the bulk region for the BJT to avoid selfheating, while the CMOS region is thin body SOI and is maintained as RF-SOI to preserve the performance advantages.

The BJT may be a HBT such as a silicon germanium (SiGe) heterojunction bipolar HBT (typically with some carbon, SiGeC). The BJT may be a NPN transistor. This can be useful for high frequency RF applications. Other devices may also be provided in the first device region (i.e. in the “bulk” region) such as hyper abrupt varactors and/or laterally-diffused metal-oxide semiconductors (LDMOS). The first device region (the bipolar/bulk region) typically comprises a doped epitaxial silicon layer. For example formed by selective n-doped silicon epitaxy. The BOX layer has then been replaced by epitaxial Si in that region, and the BJT is provided in the epitaxial Si. The BOX layer typically extends laterally on either side of said first device region. The first device region is thereby laterally isolated by BOX, and does not require deep trench isolation (DTI) as used in bulk technology. The BJT is not limited to the edge of the substrate, but may have CMOS on SOI located on either side of it. The structure typically comprises a number of metal layers, separated by interdielectric layers. In one embodiment the structure contains as few as four metal layers for electrically connecting to the BJT and CMOS device.

The first and second adjoining device regions can be separated by shallow trench isolation, STI, which may prevent fencing.

The BOX layer may have a thickness in the range of 400 nm to 2000 nm, e.g. 1000 nm. A top silicon layer above said BOX layer of said silicon substrate may have a thickness in the range of 75 nm to 350 nm, e.g. 145 nm.

Another embodiment provides a low noise amplifier, LNA, for RF applications comprising a semiconductor structure as described herein. The LNA may be configured for RF application at frequencies greater than 6 GHz, where a BJT may be particularly useful.

Other embodiments provide a method of forming a semiconductor structure. The method comprises providing a SOI substrate (typically a UTB SOI) comprising a top silicon layer on a BOX layer on a silicon handle wafer, removing said top silicon layer and said BOX layer in a first region of said SOI substrate to expose said silicon handle wafer, performing doped silicon epitaxy to provide an epitaxial silicon layer on said silicon handle wafer in said first region, and forming a bipolar junction transistor, BJT, in said epitaxial silicon layer.

The method may further comprise forming a CMOS device in said top silicon layer of said SOI substrate in a second region adjoining said first region.

The step of removing may comprise providing a patterned photoresist on said SOI substrate, dry etching said top silicon layer, dry etching said BOX layer, and wet etching said BOX layer. The step of performing epitaxy may comprise growing said epitaxial silicon layer to a thickness in the range of 1500 nm and 2000 nm, e.g. to about 1800 nm.

The method may further comprise performing CMP to flatten said epitaxial silicon layer so that it is substantially level with said top silicon layer of said SOI substrate. The method preferably comprises forming STI along two opposing sides of said epitaxial silicon layer. The STI is then formed at least between the bipolar region and the CMOS device region.

In some embodiments, the step of removing the top silicon layer comprises performing local oxidation of a part of said top silicon layer in said first region to create an oxide layer, and removing at least a part of said oxide layer. Typically the local oxidation may be performed as one or more LOCOS processes to oxidise through the entire thickness of the top silicon layer (down to the underlying BOX layer) in the first region. Preferably, a part of the oxide layer is left when etching in order to laterally cover the top silicon layer. Typically, the step of removing at least part of said oxide layer comprises removing a central part of said oxide layer so as to leave parts of said oxide layer covering side edges of said top silicon layer on opposite sides of said central part. Hence, the etch does not expose the top silicon layer, which can improve the epitaxial silicon layer.

While specific embodiments of the invention have been described above, it will be appreciated that the invention may be practiced otherwise than as described. The descriptions above are intended to be illustrative, not limiting. It will be apparent to one skilled in the art that modifications may be made to the invention as described without departing from the scope of the claims set out below.

Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims

CLAIMS:

1. A semiconductor structure comprising: a silicon substrate comprising two adjoining device regions comprising a first device region comprising a bipolar junction transistor, BJT, and a second device region comprising a complementary metal oxide semiconductor, CMOS, device; and a buried oxide, BOX, layer located in said silicon substrate in said second device region and not located in at least part of said first device region.

2. A semiconductor structure according to claim 1, wherein said BJT is a silicon germanium, SiGe, optionally with carbon, SiGeC, heterojunction bipolar transistor, HBT.

3. A semiconductor structure according to claim 1 or 2, wherein said first region comprises a doped epitaxial silicon layer.

4. A semiconductor structure according to claim 3, wherein said doped epitaxial silicon layer does not extend into said second device region.

5. A semiconductor structure according to any one of the preceding claims, wherein said BOX layer extends laterally on either side of said first device region.

6. A semiconductor structure according to any one of the preceding claims, wherein the BJT is a NPN transistor.

7. A semiconductor structure according to any one of the preceding claims, further comprising a plurality of metal layers for electrically connecting to the BJT and the CMOS device.

8. A semiconductor structure according to any one of the preceding claims, wherein said two adjoining device regions are separated by shallow trench isolation, STI.

9. A semiconductor structure according to any one of the preceding claims, wherein said BOX layer has a thickness in the range of 400 nm to 2000 nm.

10. A semiconductor structure according to any one of the preceding claims, wherein a top silicon layer above said BOX layer of said silicon substrate has a thickness in the range of 75 nm to 350 nm.

11. A low noise amplifier, LNA, for RF applications comprising a semiconductor structure according to any one of claims 1 to 10.

12. A method of forming a semiconductor structure, the method comprising: providing a silicon on insulator, SOI, substrate comprising a top silicon layer on a buried oxide, BOX, layer on a silicon handle wafer; removing said top silicon layer and said BOX layer in a first region of said SOI substrate to expose said silicon handle wafer; performing doped silicon epitaxy to provide an epitaxial silicon layer on said silicon handle wafer in said first region; and forming a bipolar junction transistor, BJT, in said epitaxial silicon layer.

13. A method according to claim 12, further comprising forming a complementary metal oxide semiconductor, CMOS, device in said top silicon layer of said SOI substrate in a second region adjoining said first region.

14. A method according to claim 12 or 13, wherein said step of removing comprises: providing a patterned photoresist on said SOI substrate; dry etching said top silicon layer; dry etching said BOX layer; and wet etching said BOX layer.

15. A method according to any one of claims 12 to 14, wherein said step of performing epitaxy comprises growing said epitaxial silicon layer to a thickness in the range of 1500 nm and 2000 nm.

16. A method according to any one of claims 12 to 15, further comprising performing chemical mechanical planarization, CMP, to flatten said epitaxial silicon layer so that it is substantially level with said top silicon layer of said SOI substrate.

17. A method according to according to any one of claims 12 to 16, further comprising forming shallow trench isolation, STI, along two opposing sides of said epitaxial silicon layer.

18. A method according to any one of claims 12 to 17, wherein said step of removing the top silicon layer comprises: performing local oxidation of a part of said top silicon layer in said first region to create an oxide layer; and removing at least a part of said oxide layer.

19. A method according to claim 18, wherein said step of removing at least a part of said oxide layer comprises leaving a part of said oxide layer to laterally cover the top silicon layer.

20. A method according to claim 18 or 19, wherein said step of removing at least part of said oxide layer comprises removing a central part of said oxide layer so as to leave parts of said oxide layer covering side edges of said top silicon layer on opposite sides of said central part.