WO2023103731A1 - 多主供电通信系统、方法及装置 - Google Patents

多主供电通信系统、方法及装置 Download PDF

Info

Publication number
WO2023103731A1
WO2023103731A1 PCT/CN2022/132430 CN2022132430W WO2023103731A1 WO 2023103731 A1 WO2023103731 A1 WO 2023103731A1 CN 2022132430 W CN2022132430 W CN 2022132430W WO 2023103731 A1 WO2023103731 A1 WO 2023103731A1
Authority
WO
WIPO (PCT)
Prior art keywords
power supply
data
bus
communication
module
Prior art date
Application number
PCT/CN2022/132430
Other languages
English (en)
French (fr)
Inventor
舒继锋
Original Assignee
舒继锋
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 舒继锋 filed Critical 舒继锋
Priority to EP22903154.7A priority Critical patent/EP4447389A1/en
Publication of WO2023103731A1 publication Critical patent/WO2023103731A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/00032—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries characterised by data exchange
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J1/00—Circuit arrangements for dc mains or dc distribution networks
    • H02J1/06—Two-wire systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40045—Details regarding the feeding of energy to the node from the bus

Definitions

  • the present invention relates to the technical field of communication, and in particular to a multi-master power supply communication system, method and device.
  • the power supply bus is a bus that can communicate and supply power at the same time, and it is the bus with the least communication physical lines (only two power lines).
  • the common ones are 1-wire, mbus, powerbus.
  • this resistor is connected in series on the main communication line, and the current flowing through it is equal to the consumption current of the slave. If the slave is a large current load such as a motor, the power consumption of this resistor is very large. Therefore, it is usually suitable for small current power supply occasions.
  • mbus adopts dual voltage to identify logic level, but its bus power supply capability and transmission distance are weaker than powerbus bus.
  • the powerbus bus is an advanced bus, and its master station can provide a maximum current of 20A.
  • it does not support multi-master communication, and adopts the master-slave communication method, which leads to low overall communication efficiency of the bus, heavy tasks of the master, and the power supply current of the slave station is generally lower than 1A (the diode of the slave station is one of the main reasons for current limitation) .
  • This is too small for the control of power devices such as motors.
  • the power bus acts as a voltage at the bottom and a current at the top. Due to the detection of the current, this will inevitably lead to the complexity of the main station circuit. Therefore, how to provide a multi-master power supply communication with strong driving capability is a technical problem that needs to be solved urgently.
  • the main purpose of the present invention is to provide a multi-master power supply communication system, method and device, aiming at solving the technical problems of lack of simplified multi-master power supply communication system and weak driving ability in the current bus communication mode.
  • the present invention provides a multi-master power supply communication system, the multi-master power supply communication system includes a power module and at least one functional module, and the power module and at least one functional module are connected to each other through a bus; wherein:
  • the power module sends charging data to the functional module through the bus, and the functional module receives the charging data through the bus and executes a charging action;
  • the power module performs a first sending action through the bus to send communication data to at least one of the functional modules; the functional module performs a second sending action through the bus to send communication data to the power module or another functional module The module sends communication data.
  • the present invention also provides a multi-master power supply communication method, which is used for the power supply module of the above-mentioned multi-master power supply communication system, and the multi-master power supply communication method includes the following steps:
  • charging data is sent to the bus to charge the functional module during a preset time period of the communication data transmission.
  • the present invention also provides a multi-master power supply communication method, which is used for the power supply module or functional module of the above-mentioned multi-master power supply communication system.
  • the multi-master power supply communication method includes the following steps:
  • the sending end corresponding to the second communication data sends a low level to the bus, and if no competition is detected, sends a low level to the receiving end corresponding to the second communication data
  • the function module sends a response request, so that the function module sends response data to the bus according to the response request.
  • the present invention also provides a multi-master power supply communication device, which is characterized in that the multi-master power supply communication device includes:
  • a power supply module includes a memory, a processor, and a multi-master power supply communication program stored on the memory and operable on the processor, and the multi-master power supply communication program is implemented when executed by the processor.
  • a functional module includes a memory, a processor, and a multi-master power supply communication program stored on the memory and operable on the processor, and the multi-master power supply communication program is implemented when executed by the processor.
  • the present invention connects the bus of the power supply module and the function module to realize the charging of the function module through the power supply module before and during the communication, so as to realize the multi-master power supply communication between multiple function modules by using two power lines, and solve the current problem In the bus communication mode, there is a lack of simplified multi-master power supply communication system and technical problems such as weak driving ability.
  • FIG. 1 is a schematic structural diagram of a multi-master power supply communication system according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a circuit principle of a power module according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a circuit principle of a functional module according to an embodiment of the present invention.
  • Fig. 4 is a schematic diagram of the working state of the power module according to the embodiment of the present invention.
  • Fig. 5 is a schematic diagram of the working state of the functional modules of the embodiment of the present invention.
  • FIG. 6 is a schematic flowchart of a first embodiment of a multi-master power supply communication method according to the present invention.
  • FIG. 7 is a schematic diagram of logic levels in which charging data is a power supply level according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of logic levels in which charging data is a supplementary potential according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of the logic levels of the supplementary potential according to the embodiment of the present invention.
  • FIG. 10 is a schematic diagram of an insertion position of an anti-misrecognition level according to an embodiment of the present invention.
  • FIG. 11 is a schematic flowchart of a second embodiment of the multi-master power supply communication method of the present invention.
  • FIG. 12 is a schematic diagram of a frame data structure of communication data according to an embodiment of the present invention.
  • Fig. 13 is a schematic diagram of a node sending data during an interval according to an embodiment of the present invention.
  • FIG. 14 is a schematic diagram of a node sending data during a power supply period according to an embodiment of the present invention.
  • FIG. 15 is a schematic diagram of contention arbitration in which a node receives a start bit but does not receive a synchronization bit according to an embodiment of the present invention.
  • FIG. 16 is a schematic diagram of contention arbitration of a node receiving a start bit unit and receiving data bits according to an embodiment of the present invention.
  • FIG. 17 is a schematic diagram of contention arbitration in which the first node receives a start bit and the first node fails to compete according to an embodiment of the present invention.
  • FIG. 18 is a schematic diagram of contention arbitration in which the first node receives a start bit and the second node fails to compete according to an embodiment of the present invention.
  • FIG. 19 is a schematic diagram of contention arbitration in which data has been received and has a high priority according to an embodiment of the present invention.
  • FIG. 20 is a schematic diagram of contention arbitration in which data has been received and the priority level is low according to an embodiment of the present invention.
  • Fig. 21 is a schematic diagram of contention arbitration in which data has been received and the priority levels are the same according to an embodiment of the present invention.
  • Fig. 22 is a schematic diagram of improving the driving capability of a functional module according to an embodiment of the present invention.
  • Fig. 23 is a schematic diagram of synchronizing multiple functional modules according to an embodiment of the present invention.
  • Fig. 24 is a schematic diagram of one situation in competition arbitration according to an embodiment of the present invention.
  • the power supply bus is a bus that can communicate and supply power at the same time, and it is the bus with the least communication physical lines (only two power lines).
  • the common ones are 1-wire, mbus, powerbus.
  • this resistor is connected in series on the main communication line, and the current flowing through it is equal to the consumption current of the slave. If the slave is a large current load such as a motor, the power consumption of this resistor is very large. Therefore, it is usually suitable for small current power supply occasions.
  • mbus adopts dual voltage to identify logic level, but its bus power supply capability and transmission distance are weaker than powerbus bus.
  • the powerbus bus is an advanced bus, and its master station can provide a maximum current of 20A.
  • it does not support multi-master communication, and adopts the master-slave communication method, which leads to low overall communication efficiency of the bus, heavy tasks of the master, and the power supply current of the slave station is generally lower than 1A (the diode of the slave station is one of the main reasons for current limitation) .
  • This is too small for the control of power devices such as motors.
  • the power bus acts as a voltage at the bottom and a current at the top. Due to the detection of the current, this will inevitably lead to the complexity of the main station circuit. Therefore, how to provide a multi-master power supply communication with strong driving capability is a technical problem that needs to be solved urgently.
  • the multi-master power supply communication system provided by the present invention realizes the charging of the functional modules through the power supply modules before and during the communication by connecting the power supply modules and the bus of the functional modules, so as to realize the utilization of two power lines to satisfy the communication between multiple functional modules.
  • Multi-master power supply communication solves the technical problems of lack of streamlined multi-master power supply communication system and weak driving ability in the current bus communication mode.
  • FIG. 1 is a schematic structural diagram of an embodiment of a multi-master power supply communication system according to the present invention.
  • the multi-master power supply communication system includes a power supply module and at least one functional module, and the power supply module and at least one functional module are connected to each other through a bus; wherein: the power supply module transmits to the functional module through the bus Charging data, the functional module receives the charging data through the bus, and executes the charging action; the power module executes the first sending action through the bus, and sends communication data to at least one of the functional modules; the functional module transmits the communication data through the bus The bus performs a second sending action, sending communication data to the power module or another functional module.
  • this embodiment includes that one power module communicates with multiple functional modules through power lines.
  • the power supply module provides electric energy for each functional module, each functional module executes its own function, and each functional module and the functional module and the power supply module can communicate with each other.
  • the power module includes a main power control unit, a charging unit, a power supply unit, a power supply unit, and a first power switch; wherein: the charging unit is used to transmit the first charging data to the bus; the power main The control unit is used to respectively control the power supply unit and the power supply unit to send charging data to the bus; the first power switch is connected to the power supply unit and the power supply unit, and is used to transmit the second charging data to the bus. data and third charging data.
  • the power supply module also includes a first sending module and a first receiving module; wherein: the first sending module includes a first sending unit and a first bit data encoder, and the first bit data encoder is used to convert logic data The bit and the charging data bit are encoded as communication data, and the first sending unit is used to send the communication data to the first power switch, so that the first power switch sends the communication data to the bus;
  • the first receiving module includes a first receiving unit and a first bit data decoder, the first receiving unit is used to receive communication data on the bus, and the first bit data decoder is used to decode the communication data into logic data bits and charging data bits.
  • FIG. 2 is a schematic diagram of a circuit principle of a power module.
  • the power module includes:
  • the charging unit is used to charge the functional modules of the bus with a constant current. After the power module is powered on, the main control unit works to enable the charging unit, and the charging unit charges the energy storage capacitors of the functional modules of the bus with a constant current until it is fully charged. The control unit disables this unit.
  • the power supply unit is used to supply power to each functional module on the bus, after the charging unit is completed, the main control unit enables this unit, the main control unit detects bus communication, disables this unit, and the main control unit detects the end of bus communication , to enable the unit.
  • the power supply unit the power supply unit is used to provide supplementary power to the bus during communication.
  • the power module When the function module sends data to the bus, the power module will provide supplementary power pulses to the bus.
  • the power module When the power module sends data to the bus, the power module will not Provide supplementary power pulses to the bus, because the data signal itself contains supplementary potential, it can supply power to each functional module.
  • Sending unit the sending unit is used to send data to the bus.
  • the sending unit is enabled to send data to the bus.
  • the main control unit detects that the bus is unexpectedly If the contention fails, stop sending the current data, and at the same time enable the power supply unit to supply power to the bus.
  • start the sending unit again to continue sending data to the bus.
  • the sending is over, set the corresponding flag bit for the user to use.
  • the receiving unit is used to receive bus data
  • the power supply module has been monitoring the bus data, when receiving the data associated with this module, set the corresponding receiving flag for the user to use. It should be noted that the receiving module does not affect the power supply module to provide constant current charging, power supply and supplementary power to the bus.
  • the input and output unit, the input and output unit is used to exchange data with the user. It has corresponding flags, such as the successful reception flag, the successful transmission flag, and the receiving/sending buffer flag: empty, half empty, full. wait. Interrupt pins, data bus pins, control pins, etc. are provided to users after receiving/transmitting is completed.
  • the power supply unit is used to provide electric energy to each unit in the power supply module.
  • Power switch the power switch is used to provide various types of pulses for the bus.
  • the power switch is directly controlled by the power supply unit, power supply unit, and sending unit to provide various types of pulse data for the bus.
  • Power main control unit the power main control unit is used to control the power module, which has a clock generator, control sequence circuit, bus level pulse width counter, data encoder, data decoder, priority identification, etc. inside.
  • the charging unit, the power supply unit and the power supply unit are used to perform charging actions at different time periods.
  • the functional module includes a functional main control unit, a second sending module, a second receiving module, and a second power switch; wherein: the functional main control unit is used to control the second sending module to perform a sending action, and Controlling the second receiving module to perform a receiving action; the second sending module includes a second sending unit and a second data encoder, and the second data encoder is used to encode logic data bits and charging data bits into communication data, the second sending unit is used to send the communication data to the second power switch, so that the second power switch sends the communication data to the bus; the second receiving module includes a second receiving unit and a second bit data decoder, the second receiving unit is used for receiving communication data on the bus, and the second bit data decoder is used for decoding the communication data into logical data bits and charging data bits.
  • the functional module also includes a power supply branch and an energy storage capacitor; wherein: the power supply branch is used to receive the charging data and charge the energy storage capacitor; the energy storage capacitor is connected to the power supply branch and storing the electric energy corresponding to the charging data received by the power supply branch.
  • FIG. 3 is a schematic diagram of a circuit principle of a functional module.
  • the functional modules include:
  • the power supply branch is used to provide a power supply circuit when the functional module is powered on, and the bus voltage passes through the power supply branch to charge the energy storage capacitor.
  • this power supply branch is the only power supply branch that can obtain power from the bus.
  • the power supply branch must be unidirectional, so it is usually a diode.
  • the power switch is used to provide various types of pulses for the bus, the power switch is controlled by the expansion unit, and the power switch is turned on within a specific period of time, which greatly reduces the on-resistance of the power supply branch, thereby increasing the load power of the functional module .
  • the specific time period includes: the potential supplementary time period of the bit data, the power supply pulse, the start pulse power switch is also controlled by the sending unit, and provides various types of pulse data for the bus.
  • Power switches usually use MOS tubes, whose internal resistance is much smaller than that of diodes.
  • Energy storage capacitor the energy storage capacitor is used to store electric energy on the bus for use by functional modules and loads.
  • Sending unit the sending unit is used to send data to the bus.
  • the sending unit is enabled to send data to the bus.
  • the main control unit detects that the bus is unexpectedly If the contention fails, stop sending the current data and release the bus. After the bus data transmission is completed, start the sending unit again to continue sending data to the bus. After the transmission is completed, set the corresponding flag bit for the user to query.
  • Receiving unit the receiving unit is used to receive bus data, the functional module has been monitoring the bus data, when receiving the data associated with this module, set the corresponding receiving flag for user query.
  • Bit data encoder and bit data decoder usually, under the positive logic system, logic 0 is represented by low level, and logic 1 is represented by high level.
  • logic 0 is represented by low level
  • logic 1 is represented by high level.
  • M-BUS, PowerBUS and other power supply buses usually use dual power supplies. High voltage on the bus indicates logic 1, and low voltage indicates logic 0. The low voltage is generally set at about 10V to ensure the normal operation of functional modules.
  • a bit data encoding format proposed by the bit data encoding/decoding unit in this embodiment logical bit + supplementary potential Among them, the logical bit is divided into two types: for the sending module, when the data is 0, it outputs a low level, and when the data is 1, it outputs a high level ;For a non-sending module, release the bus and output a low level; it should be noted that the sending module may be a power module or a functional module.
  • the power module it always outputs high level.
  • the functional module it will turn on the power switch tube at this time, which is beneficial for the power supply module to supply power to the functional module and improve the load capacity of the functional module.
  • This embodiment benefits from the superiority of this coding.
  • the power supply The module can always supply power to each functional module in time.
  • the main characteristic data of this embodiment power supply bit, start bit, three kinds of response bits, logic 0, logic 1 can be decomposed into the above format.
  • the power supply bit, the start bit and the data bit (including several bits of logic 0 or logic 1, but the number of consecutive logic 1s cannot exceed 6) mainly differ in pulse width, the start bit is wider than the power supply bit, and the power supply bit is wider than the power supply bit. Data bit width.
  • this embodiment adopts real-time communication, which has better communication flexibility.
  • the expansion unit is used to reduce the impedance of the power supply circuit and increase the load capacity of the functional module, and it enables the power switch to be turned on at a specific time.
  • the power supply unit is used to provide electric energy to each unit in the power supply module.
  • the input and output unit, the input and output unit is used to exchange data with the user. It has corresponding flags, such as the successful reception flag, the successful transmission flag, and the receiving/sending buffer flag: empty, half empty, full, etc. Interrupt pins, data bus pins, control pins, etc. are provided to users after receiving/transmitting is completed.
  • the clock regeneration unit is used to obtain the clock signal from the bus signal. Since it is multi-master communication, each module has its own clock. If the clocks have different frequencies and the same phase, the whole system will be confused. Usually, the clock of the power module is used as a reference, and each functional module can obtain the unique data waveform of the power module from the bus, and separate the clock signal as its own clock.
  • the unique data waveforms of the power module include power supply pulses and frame synchronization signals.
  • the functional main control unit is used to control the functional modules, and it has a clock generator, a control sequence circuit, a bus level pulse width counter, a data encoder, a data decoder, a priority identification, etc. inside.
  • the power module When powered on, the power module first enters the charging mode. It enables the charging unit to charge the functional modules on the bus with a constant current, and the main control unit in it detects the bus level, and when the bus level reaches the set value, it means it is fully charged. Then disable the charging unit, enable the power supply unit, and enter the power supply mode.
  • the power supply module continuously sends power supply pulses to the bus to continuously provide power to each functional module on the bus. Make each functional module supply power normally.
  • the internal main control unit detects whether the module wants to send data and whether there is an external module communicating at the same time.
  • the module When it is detected that the module wants to send data, it will enter the sending mode. If it is detected that the external module is communicating at this time, the internal main control unit will judge the priority level. If the local machine priority level is low, it will stop sending data and at the same time Enter the power supply mode and provide power supply pulses to the bus. After the data transmission of this frame is completed, the power module exits the power supply mode and resends the unsent data. After the data transmission is completed, exit the transmission mode and enter the power supply mode. Correspondingly, the machine has a high priority, and it continues to send data until the sending is completed, then exits the sending mode and enters the power supply mode.
  • the power module If in power supply mode, the power module only detects that the external module is communicating, it will enter the power supply mode and provide a power supply pulse to the bus. After the bus communication ends, the power module will enter the power supply mode.
  • Figure 2 and Figure 3 does not constitute a limitation on the power module and functional module, and may include more or less components than those shown in the illustration, or combine certain components, or be different layout of the components.
  • FIG. 6 is a schematic flowchart of a first embodiment of the multi-master power supply communication method according to the present invention.
  • the multi-master power supply communication method is used for the power supply module in the above-mentioned multi-master power supply communication system, and the multi-master power supply communication method includes the following steps:
  • Step S100 when it is detected that the power supply module is powered on or the bus has no communication data, sending charging data to the bus to charge at least one of the functional modules.
  • the power module charges the bus with a constant current to fully charge each The energy storage capacitor of the functional module.
  • the charging data is sent to the bus to charge at least one functional module.
  • the charging data is the power supply level + interval level data transmitted from the power module to the functional module, as shown in Figure 7, that is, the bus is a pulsating voltage.
  • the large-capacity capacitor on the node is usually an aluminum electrolytic capacitor, its frequency The characteristics are poor, so the power supply level can be set to a high level and a wide range, which is more conducive to charging it.
  • Step S200 if it is detected that the bus transmits communication data, sending charging data to the bus to charge the functional module during a preset time period of the communication data transmission.
  • the charging data sent by the power module to the bus is the level data of the supplementary potential. Potential, if not provided, the functional module may fail due to the energy stored in the energy storage capacitor dissipated.
  • the communication data includes at least one logical data bit
  • the charging data includes at least one charging data bit
  • the preset period is each logical data bit.
  • the step of sending charging data to the bus during the preset period of communication data transmission to charge the functional module specifically includes sending the charging data to the bus after each logical data bit of the communication data
  • the charging data is used to charge the functional module, so that the functional module turns on the second power switch when receiving the charging data, so as to increase the output current of the functional module.
  • the functional module should insert a logic 0, as shown in Figure 10, and this logic 0 should be removed when receiving. If this logic 0 is not inserted, the high level width of the bus will be wider, and at the same time, identification errors will be caused.
  • FIG. 11 is a schematic flowchart of a second embodiment of a multi-master power supply communication method according to the present invention. Based on the first embodiment of the multi-master power supply communication method shown in FIG.
  • the main power supply communication method is as follows:
  • step S300 when a first communication sending instruction is received, first communication data corresponding to the first communication sending instruction is sent to the bus.
  • Step S400 if it is detected that there is second communication data transmitted on the bus, determine whether the priority corresponding to the second communication data is higher than the priority of the first communication data.
  • Step S500 if yes, perform a sending waiting action until the transmission of the second communication data is completed, and return to the step of sending the first communication data corresponding to the first communication sending instruction to the bus.
  • Step S600 judging whether the transmission of the second communication data is completed, if so, the sending end corresponding to the second communication data sends a low level to the bus, and if no competition is detected, sends a signal to the receiving end of the second communication
  • the functional module corresponding to the data sends a response request, so that the functional module sends response data to the bus according to the response request.
  • a low level can be inserted after the sending module has sent all the data. If no competition is detected, it will enter the mode of receiving the response signal.
  • the response signal is jointly sent by the power supply module and the receiving module.
  • the power module sends a non-response bit, if the sending module receives this bit, it means that the receiving module is not found or the receiving module is damaged.
  • the receiving module receives and sends the success response bit successfully, otherwise sends the failure response signal.
  • the response method provided by this embodiment can more accurately distinguish whether the addressed receiver is already on the bus or whether the reception fails.
  • the bus in the multi-master power supply communication system is a broadcast type bus, which has independent receivers and transmitters inside, and each module on the bus can monitor the data transmitted on the bus.
  • the module When the device receives the start bit, the module enters the receiving data mode. When there is data to be sent, it will immediately enter the sending mode, that is to say, the sending mode takes precedence over the receiving mode. In the sending mode, if there is contention and contention If it fails, set the retransmission flag and enter the receiving mode. After the frame is completed, it will automatically retransmit. Before sending data, the bus is either in an idle state or in a communication state. The following describes the sending process of these two states.
  • the frame data structure of the communication data sent by the functional module to the bus can be: start bit + synchronization bit + command byte + parameter byte + CRC8 + response bit, as shown in Figure 12 .
  • the node sends data during the "interval", and the node wants to send data at this time, and waits for the completion of the "interval” before sending the "start bit”.
  • the node sends data during the "power supply bit”, and the node wants to send data at this time, and immediately sends the "start bit” (high level), and the previous high level ( t) time.
  • the data has been received and its priority is high, so stop sending data, and the priority of sending data bits is lower than that of receiving data, do not send, and enter the retransmission mode.
  • the function module when the function module sends data to the bus, the highest byte is sent first, and the lowest byte is sent last, and the highest bit is sent first, and the lowest bit is sent last.
  • the receiving stop action is performed; the fourth communication data corresponding to the second communication sending instruction is obtained, and the fourth communication data is transmitted to the bus.
  • the data to be sent by node 1 is 0x1F, and the upper 4 bits have been sent.
  • node 2 needs to send 0x81, which has a higher priority than node 1, but the highest bit received is 0, so the data must be Complete retransmission (if the received data is the same, you only need to send the next bit), therefore, node 2 starts to send the start bit, the bus is high level, but because node 1 is also sending high level behind, So it didn't find any contention and successfully entered the receiving response mode, and failed to seize the bus.
  • a low level can be inserted before receiving the response.
  • the bus is detected to be high, it means that there is competition, and then the retransmission flag is set to enter the receiving mode, and the bus is preempted.
  • the power switch tube Q1 of the power module and the function module must be large, which not only increases the number of power switch tubes, increases the cost, but also increases power consumption. In some cases this is not desirable.
  • an economical, safe and reliable communication can be realized by adding a power positive line, which is separately led to the load of the functional module, and another low-voltage low-power positive line is used for the power module and the functional module, and they share the same ground. .
  • an embodiment of the present invention also proposes a storage medium on which a multi-master power supply communication program is stored, and when the multi-master power supply communication program is executed by a processor, the above-mentioned multi-master power supply communication method is implemented. step. Therefore, details will not be repeated here. In addition, the description of the beneficial effect of adopting the same method will not be repeated here.
  • program instructions can be deployed to be executed on one computing device, or on multiple computing devices located at one site, or alternatively, on multiple computing devices distributed across multiple sites and interconnected by a communication network to execute.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)

Abstract

本发明公开了一种多主供电通信系统、方法及装置，该系统包括电源模块和至少一个功能模块，电源模块与至少一个功能模块通过总线相互连接，电源模块通过总线向功能模块发送充电数据，功能模块通过总线接收充电数据，执行充电动作；电源模块通过总线执行第一发送动作，向至少一个功能模块发送通信数据；功能模块通过总线执行第二发送动作，向电源模块或另一所述功能模块发送通信数据。本发明通过连接电源模块和功能模块的总线，实现在功能模块通信前以及通信中通过电源模块为其充电，以实现利用两根电源线满足多个功能模块之间的多主供电通信，解决目前总线通信方式中，缺少精简的多主供电通信系统以及驱动能力不强的技术问题。

Description

多主供电通信系统、方法及装置 技术领域
本发明涉及通信技术领域，尤其涉及到一种多主供电通信系统、方法及装置。
 背景技术
供电总线是能够同时进行通信和供电的一种总线，它是通信物理线路最少的总线(仅两根电源线)。常见的有1-wire，mbus，powerbus。
其中，1-wire由于上拉电阻的原因，如果要增大输出电流，则必须减小这个电阻，但同时增加了不必要的通信功率消耗。况且这个电阻是在串在通信干线上，流过它的电流等同从机的消耗电流，从机如果是大电流负载如电机等这电阻消耗功率很大。所以，通常适用于小电流供电场合。
mbus采用双电压识别逻辑电平，但它总线供电能力，传送距离弱于powerbus总线。
powerbus总线是一种先进的总线，它的主站最大可提供20A电流。但它不支持多主机通信，采用主从通信方式，这导致总线的总体通信效率低下，主机任务过重，而且从站供电电流一般低于1A(从站的二极管是电流受限主因之一)。这对于电机等功率器件控制显得过小了，powerbus下行为电压，上行为电流，由于要对电流的检测，这必然导致主站电路复杂。因此，如何提供一种具有较强驱动能力的多主供电通信，是一个亟需解决的技术问题。
上述内容仅用于辅助理解本发明的技术方案，并不代表承认上述内容是现有技术。
 技术问题
本发明的主要目的在于提供一种多主供电通信系统、方法及装置，旨在解决目前总线通信方式中，缺少精简的多主供电通信系统以及驱动能力不强的技术问题。
 技术解决方案
为实现上述目的，本发明提供一种多主供电通信系统，所述多主供电通信系统包括电源模块和至少一个功能模块，所述电源模块与至少一个功能模块通过总线相互连接；其中：
所述电源模块通过所述总线向所述功能模块发送充电数据，所述功能模块通过所述总线接收充电数据，执行充电动作；
所述电源模块通过所述总线执行第一发送动作，向至少一个所述功能模块发送通信数据；所述功能模块通过所述总线执行第二发送动作，向所述电源模块或另一所述功能模块发送通信数据。
此外，为了实现上述目的，本发明还提供了一种多主供电通信方法，用于如上所述的多主供电通信系统的电源模块，所述多主供电通信方法包括以下步骤：
当检测到电源模块上电或总线没有通信数据时，向总线发送充电数据，以对至少一个所述功能模块进行充电；
若检测到所述总线传输有通信数据，在所述通信数据传输的预设时段，向所述总线发送充电数据，以对所述功能模块进行充电。
此外，为了实现上述目的，本发明还提供了一种多主供电通信方法，用于如上所述的多主供电通信系统的电源模块或功能模块，所述多主供电通信方法包括以下步骤：
当接收到第一通信发送指令时，将所述第一通信发送指令对应的第一通信数据发送至所述总线；
若检测到总线传输有第二通信数据，判断所述第二通信数据对应的优先级是否高于所述第一通信数据的优先级；
若是，执行发送等待动作，直至所述第二通信数据传输完成，并返回执行将所述通信发送指令对应的第一通信数据发送至所述总线步骤；
判断所述第二通信数据是否传输完成，若是，第二通信数据对应的发送端，向所述总线发送一个低电平，若未检测到竟争，则向接收所述第二通信数据对应的功能模块发送应答请求，以使所述功能模块根据所述应答请求向所述总线发送应答数据。
此外，为了实现上述目的，本发明还提供了一种多主供电通信装置，其特征在于，所述多主供电通信装置包括：
电源模块，所述电源模块包括存储器、处理器及存储在所述存储器上并可在所述处理器上运行的多主供电通信程序，所述多主供电通信程序被所述处理器执行时实现如上所述的多主供电通信方法的步骤；
功能模块，所述功能模块包括存储器、处理器及存储在所述存储器上并可在所述处理器上运行的多主供电通信程序，所述多主供电通信程序被所述处理器执行时实现如上所述的多主供电通信方法的步骤。
 有益效果
本发明通过连接电源模块和功能模块的总线，实现在功能模块通信前以及通信中通过电源模块为其充电，以实现利用两根电源线满足多个功能模块之间的多主供电通信，解决目前总线通信方式中，缺少精简的多主供电通信系统以及驱动能力不强的技术问题。
 附图说明
图1为本发明实施例多主供电通信系统的结构体示意图结构示意图。
图2为本发明实施例电源模块的电路原理示意图。
图3为本发明实施例功能模块的电路原理示意图。
图4为本发明实施例电源模块的工作状态示意图。
图5为本发明实施例功能模块的工作状态示意图。
图6为本发明多主供电通信方法的第一实施例的流程示意图。
图7为本发明实施例充电数据为供电位的逻辑电平示意图。
图8为本发明实施例充电数据为补电位的逻辑电平示意图。
图9为本发明实施例补电位的逻辑电平示意图。
图10为本发明实施例防误识电平插入位置示意图。
图11为本发明多主供电通信方法的第二实施例的是流程示意图。
图12为本发明实施例通信数据的帧数据结构示意图。
图13为本发明实施例节点在间隔期间发送数据的示意图。
图14为本发明实施例节点在供电位期间发送数据的示意图。
图15为本发明实施例节点接收到起始位但未接收到同步位的竞争仲裁示意图。
图16为本发明实施例节点接收到起始位单位接收到数据位的竞争仲裁示意图。
图17为本发明实施例第一节点接收到起始位，第一节点竞争失败的竞争仲裁示意图。
图18为本发明实施例第一节点接收到起始位，第二节点竞争失败的竞争仲裁示意图。
图19为本发明实施例已接收到数据且优先级别高的竞争仲裁示意图。
图20为本发明实施例已接收到数据且优先级别低的竞争仲裁示意图。
图21为本发明实施例已接收到数据且优先级别相同的竞争仲裁示意图。
图22为本发明实施例提高功能模块驱动能力的示意图。
图23为本发明实施例多个功能模块同步的示意图。
图24为本发明实施例竞争仲裁中其一情况的示意图。
本发明目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
 本发明的最佳实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
供电总线是能够同时进行通信和供电的一种总线，它是通信物理线路最少的总线(仅两根电源线)。常见的有1-wire，mbus，powerbus。
其中，1-wire由于上拉电阻的原因，如果要增大输出电流，则必须减小这个电阻，但同时增加了不必要的通信功率消耗。况且这个电阻是在串在通信干线上，流过它的电流等同从机的消耗电流，从机如果是大电流负载如电机等这电阻消耗功率很大。所以，通常适用于小电流供电场合。
mbus采用双电压识别逻辑电平，但它总线供电能力，传送距离弱于powerbus总线。
powerbus总线是一种先进的总线，它的主站最大可提供20A电流。但它不支持多主机通信，采用主从通信方式，这导致总线的总体通信效率低下，主机任务过重，而且从站供电电流一般低于1A(从站的二极管是电流受限主因之一)。这对于电机等功率器件控制显得过小了，powerbus下行为电压，上行为电流，由于要对电流的检测，这必然导致主站电路复杂。因此，如何提供一种具有较强驱动能力的多主供电通信，是一个亟需解决的技术问题。
为了解决这一问题，提出本发明的多主供电通信系统的各个实施例。本发明提供的多主供电通信系统通过连接电源模块和功能模块的总线，实现在功能模块通信前以及通信中通过电源模块为其充电，以实现利用两根电源线满足多个功能模块之间的多主供电通信，解决目前总线通信方式中，缺少精简的多主供电通信系统以及驱动能力不强的技术问题。
参照图1，图1为本发明多主供电通信系统实施例的结构示意图。
在本实施例中，多主供电通信系统包括电源模块和至少一个功能模块，所述电源模块与至少一个功能模块通过总线相互连接；其中：所述电源模块通过所述总线向所述功能模块发送充电数据，所述功能模块通过所述总线接收充电数据，执行充电动作；所述电源模块通过所述总线执行第一发送动作，向至少一个所述功能模块发送通信数据；所述功能模块通过所述总线执行第二发送动作，向所述电源模块或另一所述功能模块发送通信数据。
容易理解的，本实施例包括一个电源模块与多个功能模块通过电源线通信。其中电源模块为各功能模块提供电能，各功能模块执行各自的功能，各功能模块之间，功能模块与电源模块之间可以相互通信。
具体而言，电源模块包括电源主控单元、充电单元、供电单元、补电单元和第一功率开关；其中：所述充电单元，用于向所述总线传输第一充电数据；所述电源主控单元，用于分别控制所述供电单元和补电单元向所述总线发送充电数据；所述第一功率开关，连接所述供电单元和补电单元，用于向所述总线传输第二充电数据和第三充电数据。
进一步的，电源模块还包括第一发送模块和第一接收模块；其中：所述第一发送模块包括第一发送单元和第一位数据编码器，所述第一位数据编码器用于将逻辑数据位与充电数据位编码为通信数据，所述第一发送单元用于将所述通信数据发送至所述第一功率开关，以使所述第一功率开关将所述通信数据发送至总线；所述第一接收模块包括第一接收单元和第一位数据解码器，所述第一接收单元用于接收总线上的通信数据，所述第一位数据解码器用于将所述通信数据解码为逻辑数据位与充电数据位。
在一些实施例中，如图2所示，图2为电源模块的电路原理示意图。在该实施例中，电源模块包括：
充电单元，充电单元用于恒流向总线各功能模块充电，电源模块上电后，主控单元工作，使能充电单元，充电单元恒流向总线各功能模块的储能电容充电，直到充滿，然后主控单元禁能此单元。
供电单元，供电单元用于为总线上各功能模块供电，在充电单元完成后，主控单元使能此单元，主控单元检测到总线通信，禁能此单元，主控单元检测到总线通信结束，使能此单元。
补电单元，补电单元用于在通信时电源模块向总线提供补电，功能模块向总线发送数据时，电源模块将向总线提供补电脉冲，电源模块向总线发送数据时，电源模块不会向总线提供补电脉冲，因为数据信号中本身含有补电位，它可以向各功能模块补电。
发送单元，发送单元用于向总线发送数据，当主控单元收到用户从用户输入输出单元送来的需要发送数据时，使能发送单元，向总线发送数据，当主控单元检测到总线竟争失败，则停止发送当前数据，同时使能补电单元，向总线补电。数据发送结束，再次启动发送单元，向总线继续发送数据，发送结束后，置位发送结束相应标志位，以供用户使用。
接收单元，接收单元用于接收总线数据，电源模块一直在监听总线数据，当接收到与本模块相关联的数据，置位相应的接收标志位，以供用户使用。注意的是，接收模块不影响电源模块向总线提供恒流充电，供电，补电。
输入输出单元，输入输出单元用于与用户交换数据，它有相对应的标志位，比如接收成功标志位，发送成功标志位，接收/发送缓存标志：空，半空，滿。等。接收/发送完成后向用户提供的中断管脚，数据总线管脚，控制管脚等。
电源单元，电源单元用于向电源模块内各单元提供电能。
功率开关，功率开关用于为总线提供各种类型脉冲，功率开关受供电单元，补电单元，发送单元的直接控制，为总线提供各种类型脉冲数据。
电源主控单元，电源主控单元用于控制电源模块，其内部有时钟发生器，控制时序电路，总线电平脉宽计数器，数据编码器，数据解码器，优先级识别等。
容易理解的，充电单元、供电单元和补电单元用于在不同时段执行充电动作。
具体而言，功能模块包括功能主控单元、第二发送模块、第二接收模块和第二功率开关；其中：所述功能主控单元，用于控制所述第二发送模块执行发送动作，以及控制所述第二接收模块执行接收动作；所述第二发送模块包括第二发送单元和第二位数据编码器，所述第二位数据编码器用于将逻辑数据位与充电数据位编码为通信数据，所述第二发送单元用于将所述通信数据发送至第二功率开关，以使所述第二功率开关将所述通信数据发送至总线；所述第二接收模块包括第二接收单元和第二位数据解码器，所述第二接收单元用于接收总线上的通信数据，所述第二位数据解码器用于将所述通信数据解码为逻辑数据位与充电数据位。
进一步的，功能模块还包括供电支路和储能电容；其中：所述供电支路，用于接收所述充电数据，为所述储能电容充电；所述储能电容，连接所述供电支路，存储所述供电支路接收的所述充电数据对应的电能。
在一些实施例中，如图3所示，图3为功能模块的电路原理示意图。在该实施例中，功能模块包括：
供电支路，供电支路用于功能模块上电时，提供供电回路，总线电压通过该供电支路，向储能电容充电。在初次接入总线时，由于本模块没电，所以各功能单元都不工作，此供电支路是唯一能够从总线获取电能的供电支路。供电支路必须是单向的，所以通常是一支二极管。
功率开关，功率开关用于为总线提供各种类型脉冲，功率开关受扩容单元控制，在特定的时间段内打开功率开关，大大降低了供电支路的导通电阻，从而提高了功能模块负载功率。特定的时间段包括：比特数据的补电位时间段，供电脉冲，启始脉冲功率开关还受发送单元的控制，为总线提供各种类型脉冲数据。功率开关通常采用MOS管，它的内阻远小于二极管。
储能电容，储能电容用于存储总线上的电能，供功能模块及负载使用。
发送单元，发送单元用于向总线发送数据，当主控单元收到用户从用户输入输出单元送来的需要发送数据时，使能发送单元，向总线发送数据，当主控单元检测到总线竟争失败，则停止发送当前数据，释放总线。总线数据发送结束，再次启动发送单元，向总线继续发送数据，发送结束后，置位发送结束相应标志位，以供用户查询。
接收单元，接收单元用于接收总线数据，功能模块一直在监听总线数据，当接收到与本模块相关联的数据，置位相应的接收标志位，以供用户查询。
位数据编码器和位数据解码器，通常，在正逻辑制下，逻辑0用低电平表示，逻辑1用高电平表示，在通信过程中，如果电源模块向功能模块输出的数据中逻辑1比较多，是可以给功能模块供电的，如是输出的逻辑0比较多，甚至全为逻辑0，则功能模块可能失电从而导致整个系统瘫痪。所以，M-BUS，PowerBUS等供电总线通常采用的双电源供电，总线上是高电压表示逻辑1，是低电压表示逻辑0，这个低电压一般设为10V左右，能保证功能模块正常工作。
但在功能模块与功能模块通信时，M-BUS，PowerBUS不能做到给他们供电，所以它们只能采用主从方式，只能是电源模块向功能模块发送信号，然后在一个短的时间段内功能模块以电流方式，应答电源模块。本实施例位数据编/解码单元提出的一种位数据编码格式：逻辑位+补电位其中，逻辑位分两种：对于发送模块，数据0时输出低电平，数据1时输出高电平；对于非发送模块，释放总线，输出低电平；需要说明的是，发送模块可能是电源模块，也可能是功能模块。补电位分两种：对于电源模块来说，它始终输出高电平。对于功能模块来说，它在此时会打开功率开关管，利于电源模块给功能模块供电，提高功能模块的负载能力。
本实施例得益于这个编码的优越性，在各种通信情况下电源模块到功能模块，功能模块到电源模块，功能模块到功能模块间数据通信以及通信数据即使全是逻辑0也无所谓，电源模块总能及时给各功能模块补电。
本实施例的主要特征数据：供电位，起始位，三种应答位，逻辑0，逻辑1都可以分解为上面的格式。其中供电位，起始位与数据位(包括若干位逻辑0或逻辑1，但连续逻辑1的个数不能超6个)主要区别是脉冲宽度不同，起始位比供电位宽，供电位比数据位宽。
另外，对比于M-BUS，PowerBUS采用的总线空闲时的通信方式，本实施例采用实时通信，具有更好的通信灵活性。
扩容单元，扩容单元用于降低供电回路阻抗，提高功能模块负载能力，其在特定时间使能功率开关导通。
电源单元，电源单元用于向电源模块内各单元提供电能。
输入输出单元，输入输出单元用于与用户交换数据，它有相对应的标志位，比如接收成功标志位，发送成功标志位，接收/发送缓存标志：空，半空，滿等。接收/发送完成后向用户提供的中断管脚，数据总线管脚，控制管脚等。
时钟再生单元，时钟再生单元用于从总线信号中获取时钟信号，由于是多主通信，各个模块都有各自的时钟，如果各时钟不同频同相，将会使整个系统混乱不堪。通常采用电源模块的时钟为基准，各功能模块可以从总线上获取电源模块独有的数据波形，从中分离出时钟信号作为各自的时钟。电源模块独有的数据波形包括供电脉冲，帧同步信号。
功能主控单元，功能主控单元用于控制功能模块，其内部有时钟发生器，控制时序电路，总线电平脉宽计数器，数据编码器，数据解码器，优先级识别等。
如图4和图5所示，本实施例的多主供电通信原理如下：
上电时，电源模块首先进入充电模式。它使能充电单元向总线上各功能模块恒流充电，其内主控单元检测总线电平，当总线电平达到设定值表示已充滿。然后禁能充电单元，使能供电单元，进入供电模式。
在供电模式下，电源模块不停向总线发送供电脉冲，向总线上各功能模块源源不断的提供电能。使各功能模块正常供电。在此模式下，其内主控单元同时检测本模块是否要发送数据和是否有外模块正在通信。
当检测到本模块要发送数据，将进入发送模式，如果此时检测到外模块正在通信，其内主控单元将作优先级别判断，如果本机优先级别低，它将停止发送数据，并同时进入补电模式，向总线提供补电脉冲。待本帧数据传送完成后电源模块退出补电模式，重发未发送的数据。数据发送完成后退出发送模式，进入供电模式。相应的，本机优先级别高，它继续发送数据，直到发送完成，然后退出发送模式，进入供电模式。
如果在供电模式下，电源模块仅检测到外部模块正在通信，它将进入补电模式，向总线提供补电脉冲。总线通信结束后，电源模块将进入供电模式。
容易理解的，本实施例通过连接电源模块和功能模块的总线，实现在功能模块通信前以及通信中通过电源模块为其充电，以实现利用两根电源线满足多个功能模块之间的多主供电通信，解决目前总线通信方式中，缺少精简的多主供电通信系统以及驱动能力不强的技术问题。
本领域技术人员可以理解，图2和图3中示出的结构并不构成对电源模块和功能模块的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。
本发明实施例提供了一种多主供电通信方法，参照图6，图6为本发明多主供电通信方法的第一实施例的流程示意图。
本实施例中，所述多主供电通信方法，用于上述多主供电通信系统中的电源模块，所述多主供电通信方法，包括以下步骤：
步骤S100，当检测到电源模块上电或总线没有通信数据时，向总线发送充电数据，以对至少一个所述功能模块进行充电。
具体而言，在电源模块上电后，为了避免因总线驱动电流大、总线所挂功能模块多，功能模块的储能电容大导致的损坏功率开关管，电源模块向总线恒流充电，充满各功能模块的储能电容。
在恒流充电后，检测总线中是否传输有通信数据，若否，向总线发送充电数据，以对至少一个功能模块进行充电。
其中，充电数据为电源模块向功能模块传输的供电位+间隔的电平数据，如图7所示，即总线上是脉动的电压，考虑到节点上大容量电容通常是铝电解电容，其频率特性较差，所以供电位可设置高电平较宽，更利于向其充电。
步骤S200，若检测到所述总线传输有通信数据，在所述通信数据传输的预设时段，向所述总线发送充电数据，以对所述功能模块进行充电。
具体而言，功能模块向总线传输数据时，电源模块向总线发送的充电数据为补电位的电平数据，如图8所示，功能模块向其它节点通信时，此时电源模块向总线提供补电位，如果不提供则功能模块可能会因其储能电容存储的能量耗散完从而出错。
需要说明的是，功能模块向总线发送通信数据时，如图9所示，通信数据包括至少一个逻辑数据位，所述充电数据包括至少一个充电数据位，所述预设时段为每个逻辑数据位之后；所述在所述通信数据传输的预设时段，向所述总线发送充电数据，以对所述功能模块进行充电步骤，具体包括在通信数据的每个逻辑数据位之后，向总线发送充电数据，对所述功能模块进行充电，以使所述功能模块在接收到充电数据时，打开所述第二功率开关，用以提高功能模块的输出电流。
另外，需要说明的是，功能模块在连续六个逻辑1后，要插入一个逻辑0，如图10所示，接收时要去掉这个逻辑0。若不插入这个逻辑0，会导致总线高电平宽度更宽，同时造成识别错误。
为了便于理解，参阅图11，图11为本发明多主供电通信方法的第二实施例的流程示意图。基于如图6所示的多主供电通信方法的第一实施例，本实施例提出多主供电通信方法的第二实施例，用于多主供电通信系统的电源模块或功能模块，所述多主供电通信方法具体如下：
步骤S300，当接收到第一通信发送指令时，将所述第一通信发送指令对应的第一通信数据发送至所述总线。
步骤S400，若检测到总线传输有第二通信数据，判断所述第二通信数据对应的优先级是否高于所述第一通信数据的优先级。
步骤S500，若是，执行发送等待动作，直至所述第二通信数据传输完成，并返回执行将所述第一通信发送指令对应的第一通信数据发送至所述总线步骤。
步骤S600，判断所述第二通信数据是否传输完成，若是，第二通信数据对应的发送端，向所述总线发送一个低电平，若未检测到竟争，则向接收所述第二通信数据对应的功能模块发送应答请求，以使所述功能模块根据所述应答请求向所述总线发送应答数据。
具体而言，判断总线传输的通信数据是否完成，可通过在发送模组发送完所有数据后，插入一个低电平(间隔)，如果未检测到竟争，则进入接收应答信号模式。应答信号由电源模组和接收模组共同发送。电源模组发送的是一个未应答位，如果发送模组接收到此位，则表示未找到接收模块或接收模块损坏。接收模块接收成功发送成功应答位，否则发送失败应答信号。
在本实施例中，相较与传统的应答方式，接收成功或失败，对于接收失败，是线路问题还是寻址的接收机未接入总线，这无法区分，多了一个未应答位，如果收到此应答表示寻址接收机不在总线上，如果收到失败应答位表示寻址接收机要总线上，但接收的数据不正确。所以本实施例提供的应答方式能够更精确的区分所寻址的接收机是否已在总线上或接收失败。
进一步的，在本实施例中，多主供电通信系统中总线是一个广播类型的总线，它内部有独立的接收器和发送器，总线上的各模块都可以监听总线上传输的数据，当接收器收到起始位，则本模块进入接收数据模式，当有数据需要发送时，它会马上进入发送模式，也就是说发送模式优先接收模式，在发送模式下，如果有竟争且竟争失败，则置重发标志并进入接收模式，待此帧完成后自动重发，发送数据前，总线要么是空闲状态，要么是通信状态，下面就这两种状态的发送过程进行说明。
进一步的，功能模块向总线发送通信数据的帧数据结构可以为：启始位+同步位+命令字节+参数字节+CRC8+应答位，如图12所示。
当总线处于空闲态，即此时没有通信，总线上仅有电源模块输出的供电位串。
第一种情况，如图13所示，节点在"间隔"期间发送数据，节点在此时要发送数据，等待"间隔"完成才开始发送"起始位"。
第二种情况，如图14所示，节点在"供电位"期间发送数据，节点在此时要发送数据，立即发送"起始位"(高电平)，要累加之前的高电平(t)时间。
当总线处于通信态时。
第一种情况，如图15所示，未接收到”起始位”，其它节点正发送”起始位”，节点竞争失败，停止发送数据，进入“自动重发模式”。
第二种情况，如图16所示，接收到”起始位”，但还未收到同步位。其它节点正在发送同步位”，节点竞争失败，停止发送数据，进入“自动重发模式”。
第三种情况，如图17所示，接收到”起始位”，但还未收到一个数据位。其它节点正在发送第一个数据位，第一节点竞争失败，停止发送数据，进入“自动重发”模式发送数据位余下部分。如图18所示，第二节点竞争失败，停止发送数据，进入“自动重发”模式发送数据位余下部分。
第四种情况，如图19所示，已接收到数据，其优先级别高，停止发送数据，发送数据位优先级别低于接收数据，不发送，进入重发模式。
第五种情况，如图20所示，已接收到数据，其优先级别低，发送“起始位”抢占总线。
第六种情况，如图21所示，已接收到数据，其优先级别相同，继续发送数据，节点竞争失败，停止发送数据，进入“自动重发”模式。
在一些实施例中，功能模块向总线发送数据时，先送最高字节，最后送最低字节，先送最高位，最后送最低位。
进一步的，如图22所示，为了提高功能模块驱动能力，总线高电平时，如果该功能模块不发送数据时，Q1是关断状态，这是只能通过二极管D1给储能电容充电。正是这个二极管导致功能模块输出电流不能太大。如果在逻辑数据编码的补电位时，打开Q1，由于场效应管的开关电阻极低，故大大提高了功能模块的输出电流。同时这也不会影响通信。
在另一实施例中，因为时多主通信总线，总模块什么时候发送数据不确定，各模块发送数据的时钟频率及相位不可能完全一样，总是有误差，如果这些因素叠加，可能会导致通信失败。如图23所示，为了实现多主通信中多个功能模块之间的同步，一种解决办法是在电源模块的供电位的第一个上升沿到来前，或同步位期间，各功能模块禁止打开各自的功率开关Q1，以此上升沿同步各处的时钟相位，并以相邻的两个上升沿时间计算各自的时钟频率。
另外，当接收总线传输的第三通信数据时，若检测到第二通信发送指令，执行接收停止动作；获取所述第二通信发送指令对应的第四通信数据，并将所述第四通信数据传输至所述总线。
在实际应用中，因为总线是抢占式优先级传送，当一个优先级别高的数据，完全可以抢占一个正在通信的低优先级的数据传送，因为线路的线或关系，所以逻辑1优先于逻辑0。如此之外，还有一种竞争仲裁情况，例如：
如图24所示，节点一要发送数据为0x1F，且已发送了高4位，这时节点二要发送0x81，这个优先级高于节点一，但已接收的最高位是0，所以数据要完全重发(如果已接收的数据相同，则只需接着发送下一位)，因此，节点二开始发送起始位，总线为高电平，但因节点一后面也全是发送高电平，所以它没发现有竟争并顺利进入接收应答模式，抢占总线失败。在本实施例中，可通过在接收应答前先插入一个低电平，这个时侯如果检测到总线是高电平，则说明有竞争，然后设置重发标志，进入接收模式，总线被抢占。
在本实施例中，对于总线上高压、超大电流的负载，电源模块和功能模块的功率开关管Q1都必须大，既增加了功率开关管的数量，增加了成本，同时也增加了电能消耗，某些情况下这是不可取的。本实施例可通过增加一条功率正极线，这条线单独引到功能模块的负载上，电源模块与功能模块用另一条低压小功率正极线，它们共地，进而实现经济，安全，可靠的通信。
此外，本发明实施例还提出一种存储介质，所述存储介质上存储有多主供电通信程序，所述多主供电通信程序被处理器执行时实现如上文所述的多主供电通信方法的步骤。因此，这里将不再进行赘述。另外，对采用相同方法的有益效果描述，也不再进行赘述。对于本申请所涉及的计算机可读存储介质实施例中未披露的技术细节，请参照本申请方法实施例的描述。确定为示例，程序指令可被部署为在一个计算设备上执行，或者在位于一个地点的多个计算设备上执行，又或者，在分布在多个地点且通过通信网络互连的多个计算设备上执行。

Claims (10)

  1. 一种多主供电通信系统，其特征在于，所述多主供电通信系统包括电源模块和至少一个功能模块，所述电源模块与至少一个功能模块通过总线相互连接；其中：
    所述电源模块通过所述总线向所述功能模块发送充电数据，所述功能模块通过所述总线接收充电数据，执行充电动作；
    所述电源模块通过所述总线执行第一发送动作，向至少一个所述功能模块发送通信数据；所述功能模块通过所述总线执行第二发送动作，向所述电源模块或另一所述功能模块发送通信数据。
  2. 如权利要求1所述的多主供电通信系统，其特征在于，所述电源模块包括电源主控单元、充电单元、供电单元、补电单元和第一功率开关；其中：
    所述充电单元，用于向所述总线传输第一充电数据；
    所述电源主控单元，用于分别控制所述供电单元和补电单元向所述总线发送充电数据；
    所述第一功率开关，连接所述供电单元和补电单元，用于向所述总线传输第二充电数据和第三充电数据。
  3. 如权利要求2所述的多主供电通信系统，其特征在于，所述电源模块还包括第一发送模块和第一接收模块；其中：
    所述第一发送模块包括第一发送单元和第一位数据编码器，所述第一位数据编码器用于将逻辑数据位与充电数据位编码为通信数据，所述第一发送单元用于将所述通信数据发送至所述第一功率开关，以使所述第一功率开关将所述通信数据发送至总线；
    所述第一接收模块包括第一接收单元和第一位数据解码器，所述第一接收单元用于接收总线上的通信数据，所述第一位数据解码器用于将所述通信数据解码为逻辑数据位与充电数据位。
  4. 如权利要求3所述的多主供电通信系统，其特征在于，所述功能模块包括功能主控单元、第二发送模块、第二接收模块和第二功率开关；其中：
    所述功能主控单元，用于控制所述第二发送模块执行发送动作，以及控制所述第二接收模块执行接收动作；
    所述第二发送模块包括第二发送单元和第二位数据编码器，所述第二位数据编码器用于将逻辑数据位与充电数据位编码为通信数据，所述第二发送单元用于将所述通信数据发送至第二功率开关，以使所述第二功率开关将所述通信数据发送至总线；
    所述第二接收模块包括第二接收单元和第二位数据解码器，所述第二接收单元用于接收总线上的通信数据，所述第二位数据解码器用于将所述通信数据解码为逻辑数据位与充电数据位。
  5. 如权利要求4所述的多主供电通信系统，其特征在于，所述功能模块还包括供电支路和储能电容；其中：
    所述供电支路，用于接收所述充电数据，为所述储能电容充电；
    所述储能电容，连接所述供电支路，存储所述供电支路接收的所述充电数据对应的电能。
  6. 一种多主供电通信方法，其特征在于，用于如权利要求5所述的多主供电通信系统的电源模块，所述多主供电通信方法包括以下步骤：
    当检测到电源模块上电或总线没有通信数据时，向总线发送充电数据，以对至少一个所述功能模块进行充电；
    若检测到所述总线传输有通信数据，在所述通信数据传输的预设时段，向所述总线发送充电数据，以对所述功能模块进行充电。
  7. 如权利要求6所述的多主供电通信方法，其特征在于，所述通信数据包括至少一个逻辑数据位，所述充电数据包括至少一个充电数据位，所述预设时段为每个逻辑数据位之后；所述在所述通信数据传输的预设时段，向所述总线发送充电数据，以对所述功能模块进行充电步骤，具体包括：
    在通信数据的每个逻辑数据位之后，向总线发送充电数据，对所述功能模块进行充电，以使所述功能模块在接收到充电数据时，打开所述第二功率开关，用以提高功能模块的输出电流。
  8. 一种多主供电通信方法，其特征在于，用于如权利要求5所述的多主供电通信系统的电源模块或功能模块，所述多主供电通信方法包括以下步骤：
    当接收到第一通信发送指令时，将所述第一通信发送指令对应的第一通信数据发送至所述总线；
    若检测到总线传输有第二通信数据，判断所述第二通信数据对应的优先级是否高于所述第一通信数据的优先级；
    若是，执行发送等待动作，直至所述第二通信数据传输完成，并返回执行将所述第一通信发送指令对应的第一通信数据发送至所述总线步骤；
    判断所述第二通信数据是否传输完成，若是，第二通信数据对应的发送端，向所述总线发送一个低电平，若未检测到竟争，则向接收所述第二通信数据对应的功能模块发送应答请求，以使所述功能模块根据所述应答请求向所述总线发送应答数据。
  9. 如权利要求8所述的多主供电通信方法，其特征在于，所述多主供电通信方法还包括：
    当接收总线传输的第三通信数据时，若检测到第二通信发送指令，执行接收停止动作；
    获取所述第二通信发送指令对应的第四通信数据，并将所述第四通信数据传输至所述总线。
  10. 一种多主供电通信装置，其特征在于，所述多主供电通信装置包括：
    电源模块，所述电源模块包括存储器、处理器及存储在所述存储器上并可在所述处理器上运行的多主供电通信程序，多主供电通信程序被所述处理器执行时实现如权利要求6或7中任一项所述的多主供电通信方法的步骤；
    功能模块，所述功能模块包括存储器、处理器及存储在所述存储器上并可在所述处理器上运行的多主供电通信程序，多主供电通信程序被所述处理器执行时实现如权利要求8或9中任一项所述的多主供电通信方法的步骤。
PCT/CN2022/132430 2021-12-10 2022-11-17 多主供电通信系统、方法及装置 WO2023103731A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP22903154.7A EP4447389A1 (en) 2021-12-10 2022-11-17 Multi-master power supply and communication system, method and device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111513927.1 2021-12-10
CN202111513927.1A CN114793186A (zh) 2021-12-10 2021-12-10 多主供电通信系统、方法及装置

Publications (1)

Publication Number Publication Date
WO2023103731A1 true WO2023103731A1 (zh) 2023-06-15

Family

ID=82460102

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/132430 WO2023103731A1 (zh) 2021-12-10 2022-11-17 多主供电通信系统、方法及装置

Country Status (3)

Country Link
EP (1) EP4447389A1 (zh)
CN (1) CN114793186A (zh)
WO (1) WO2023103731A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114793186A (zh) * 2021-12-10 2022-07-26 舒继锋 多主供电通信系统、方法及装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030065848A1 (en) * 2001-09-30 2003-04-03 Yoshiki Mori Transmission method and apparatus utilizing a two-line bus shared for power supply and data transmission
CN112003954A (zh) * 2020-10-27 2020-11-27 苏州纳芯微电子股份有限公司 数据通信方法、数据通信系统及计算机可读存储介质
CN212377855U (zh) * 2020-08-03 2021-01-19 江苏安科瑞电器制造有限公司 一种采用二总线供电通讯的可充电消防应急灯具
CN112737913A (zh) * 2021-02-02 2021-04-30 四川光慧新能源科技有限公司 一种充电桩内部总线连接的控制系统
CN113364076A (zh) * 2021-04-30 2021-09-07 南京富岛信息工程有限公司 一种基于PowerBus总线的铁鞋动态智能充电系统及其方法
CN114793186A (zh) * 2021-12-10 2022-07-26 舒继锋 多主供电通信系统、方法及装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104793590B (zh) * 2015-03-20 2018-04-10 云丁网络技术(北京)有限公司 一种智能家居系统及其功能模块的扩展方法
CN105182854B (zh) * 2015-09-21 2018-05-29 许继电源有限公司 一种充电桩分布式控制器
CN107147198B (zh) * 2017-05-27 2020-11-06 山东电洞网络科技有限公司 充电系统及充电方法
US20200180465A1 (en) * 2018-12-07 2020-06-11 Ohmenergy Limited System and method for controlling charging of an electric energy storage system of an electric vehicle
CN109696097B (zh) * 2019-02-16 2022-01-07 华夏世昌(北京)科技有限公司 基于双线总线的数码电子雷管芯片及控制方法
CN109941315B (zh) * 2019-03-29 2021-05-18 上海仁童电子科技有限公司 一种数据处理装置及方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030065848A1 (en) * 2001-09-30 2003-04-03 Yoshiki Mori Transmission method and apparatus utilizing a two-line bus shared for power supply and data transmission
CN212377855U (zh) * 2020-08-03 2021-01-19 江苏安科瑞电器制造有限公司 一种采用二总线供电通讯的可充电消防应急灯具
CN112003954A (zh) * 2020-10-27 2020-11-27 苏州纳芯微电子股份有限公司 数据通信方法、数据通信系统及计算机可读存储介质
CN112737913A (zh) * 2021-02-02 2021-04-30 四川光慧新能源科技有限公司 一种充电桩内部总线连接的控制系统
CN113364076A (zh) * 2021-04-30 2021-09-07 南京富岛信息工程有限公司 一种基于PowerBus总线的铁鞋动态智能充电系统及其方法
CN114793186A (zh) * 2021-12-10 2022-07-26 舒继锋 多主供电通信系统、方法及装置

Also Published As

Publication number Publication date
EP4447389A1 (en) 2024-10-16
CN114793186A (zh) 2022-07-26

Similar Documents

Publication Publication Date Title
US8694710B2 (en) Conversion of a two-wire bus into a single-wire bus
US8290103B2 (en) Method for transmitting parallelization signals of uninterruptible power supplies
CN102088386B (zh) 一种电路系统主从互联模块的串行总线
EP0287119B1 (en) Serial data processor capable of transferring data at a high speed
EP0020636A1 (en) DATA COMMUNICATION SYSTEM WITH AUTONOMOUS TERMINALS.
US20110087914A1 (en) I2c buffer clock delay detection method
CN1821913A (zh) 基于i2c的通信系统及通信方法
WO2023103731A1 (zh) 多主供电通信系统、方法及装置
CN1653406A (zh) 降低经由差分串行数据链路耦合的发送器和接收器的功率使用量的方法和设备
US8943254B2 (en) Conversion of a single-wire bus communication protocol
CN112003954B (zh) 数据通信方法、数据通信系统及计算机可读存储介质
CN213934874U (zh) 一种基于监听技术的rs485串行总线通信设备
CN108920401B (zh) 多主多从的i2c通信方法、系统及节点设备
CN105446837A (zh) 检测iic接口器件是否连接的方法、装置以及系统
US20200106299A1 (en) Shutdown Control System And Method
CN101383084B (zh) 一种隔离型总线供电通信系统
CN113792003A (zh) 单总线通信单元、系统及方法
CN104251536A (zh) 一种一对多的电流环通信方法及通讯装置
CN105354157A (zh) 配置iic器件的方法、装置和系统
CN113722254B (zh) 一种适用于工业控制现场的多主机通讯总线系统
CN112506839B (zh) 一种一对多spi总线切换方法及装置
US7071838B2 (en) Coupling signals via a coupling arrangement
CN109995632B (zh) 多机通信系统的通信方法、装置及系统
CN102868583A (zh) 一种具有故障诊断功能的FlexRay总线节
US20110087812A1 (en) Multi-master bi-directional i2c bus buffer

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22903154

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2022903154

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2022903154

Country of ref document: EP

Effective date: 20240710