WO2023103320A1

WO2023103320A1 - Building partitioning method, electronic device, and computer storage medium

Info

Publication number: WO2023103320A1
Application number: PCT/CN2022/098768
Authority: WO
Inventors: 崔岩; 常青玲; 徐世廷; 王昱涵
Original assignee: 五邑大学; 广东四维看看智能设备有限公司; 中德（珠海）人工智能研究院有限公司; 珠海市四维时代网络科技有限公司
Priority date: 2021-12-09
Filing date: 2022-06-14
Publication date: 2023-06-15
Also published as: CN114386138B; CN114386138A

Abstract

Disclosed are a building partitioning method, an electronic device, and a computer storage medium. The method comprises: obtaining an undirected graph corresponding to a building floor plan; searching according to the undirected graph to obtain the largest loop; generating a first adjacency matrix and a corresponding first degradation map according to the largest loop; searching according to the first degradation map to obtain the smallest loop; generating a second adjacency matrix and a corresponding second degradation map according to the smallest loop and the first adjacency matrix; updating the second degradation map to the first degradation map, and searching again to obtain the smallest loop so as to generate an updated second adjacency matrix and a corresponding second degradation map, until the updated second adjacency matrix is degraded to be empty; and obtaining, according to the largest loop and each smallest loop, a partitioning result corresponding to the building floor plan. The present invention can ensure the reliability of loop search, can effectively reduce the complexity of data processing, and thus can effectively increase the building partitioning speed.

Description

Building partition method, electronic equipment and computer storage medium

technical field

The invention relates to the field of house type data processing, in particular to a building partition method, electronic equipment and computer storage media.

Background technique

With the continuous improvement of people's living standards, the supporting products of the real estate home improvement industry are also gradually upgrading, and the smart home improvement design platform has emerged as the times require.

In related technologies, the smart home improvement design platform is mainly used for building layout design, home decoration design, etc. The division of rooms in a building is generally defined by the designer manually on the building floor plan. Some smart home decoration design The platform can be divided according to the floor plan of the building, but it is difficult to deal with the floor plan of the building with a complex room layout, and the zoning process needs to consume a lot of time, and the zoning efficiency is low.

Contents of the invention

The present invention aims to solve at least one of the technical problems existing in the prior art. Therefore, the present invention provides a building subdivision method, electronic equipment and computer storage medium, which can obtain the subdivision result of the building according to the floor plan of the building, and the subdivision efficiency is high.

The embodiment of the first aspect of the present invention provides a building partition method, including the following steps:

Obtain the undirected graph corresponding to the floor plan of the building;

According to the undirected graph, search for the largest loop;

Generate a first adjacency matrix and a corresponding first degradation graph according to the maximum loop;

According to the first degeneracy graph, the minimum circuit is obtained by searching;

Generate a second adjacency matrix and a corresponding second degeneration graph according to the minimum loop and the first adjacency matrix;

Updating the second degenerate graph to the first degenerate graph, re-searching to obtain the minimum loop, to generate the updated second adjacency matrix and the corresponding second degenerate graph, until the updated second adjacency matrix degenerates to empty;

According to the maximum loop and each minimum loop, the division result corresponding to the floor plan of the building is obtained.

According to the above-mentioned embodiment of the present invention, it has at least the following beneficial effects: the undirected graph generated by the building floor plan can effectively simplify the complexity of the graph, thereby effectively improving the partition processing speed, and the maximum loop sum can be obtained according to the undirected graph search. The smallest loop can be used to obtain the partition results of the building. During the partitioning process, an adjacency matrix is set to record and analyze the data, which can not only avoid repeated searches of the obtained loops, but also ensure the reliability of the loop search, and effectively reduce the The complexity of data processing, and thus the rapid judgment of the search end conditions can be realized, which can effectively improve the speed of building subdivision processing.

According to some embodiments of the first aspect of the present invention, obtaining an undirected graph corresponding to a building floor plan includes:

Obtain the floor plan of the building;

According to the building floor plan, an undirected graph is generated, wherein the center line of the wall projection of the building floor plan is the edge of the undirected graph, and the endpoint of the wall projection center line of the building floor plan is the vertex of the undirected graph.

According to some embodiments of the first aspect of the present invention, according to the undirected graph, the maximum cycle is obtained by searching, including:

According to the undirected graph, the vertex corresponding to the maximum or minimum value on the first coordinate axis is used as the first starting point, wherein the first coordinate axis is an axis parallel to the x-axis or the y-axis, and the first coordinate axis passes through the first starting point ;

Taking the first starting point as the first starting point, obtaining each first adjacent edge connected to the first starting point;

Taking the first coordinate axis as the first reference line, calculate the first direction factor corresponding to each first adjacent side, where the first direction factor is used to represent the first rotation angle relationship of the first adjacent side with respect to the first reference line ;

Comparing each first direction factor, the first adjacent edge corresponding to the smallest first direction factor is obtained as the first path;

updating the end point of the first path to the first starting point, and updating the first path to the first baseline until the updated end point of the first path coincides with the first starting point;

According to the plurality of first paths, a maximum loop is obtained.

According to some embodiments of the first aspect of the present invention, the first adjacency matrix and the corresponding first degradation graph are generated according to the maximum loop, including:

According to the maximum loop, input the value corresponding to each first path into the adjacency matrix to obtain the initial adjacency matrix, where the initial value of the adjacency matrix is 0, and each time the first path is traversed, the elements corresponding to the first path in the adjacency matrix plus 1;

According to the initial adjacency matrix, elements with a value of 2 in the initial adjacency matrix are deleted to generate a first adjacency matrix and a corresponding first degenerate graph, wherein the first degenerate graph is obtained by deleting the first path traversed twice from the undirected graph.

According to some embodiments of the first aspect of the present invention, according to the first degradation map, searching for the minimum loop includes:

According to the first degradation diagram, the vertex corresponding to the maximum or minimum value on the second coordinate axis is used as the second starting point, wherein the second coordinate axis is an axis parallel to the x-axis or the y-axis, and the second coordinate axis passes through the first two starting points;

Taking the second starting point as the second starting point, obtaining each second adjacent edge connected to the second starting point;

Taking the second coordinate axis as the second reference line, calculate the second direction factor corresponding to each second adjacent side, wherein the second direction factor is used to represent the second rotation angle relationship of the second adjacent side with respect to the second reference line ;

Comparing each second direction factor, the second adjacent edge corresponding to the smallest second direction factor is obtained as the second path;

Update the end point of the second path to the second starting point, and update the second path to the second reference line, and obtain the second adjacent edge corresponding to the largest second direction factor as the third path;

updating the end point of the third path to the second starting point until the updated end point of the third path coincides with the second starting point;

According to the second path and the plurality of third paths, a minimum circuit is obtained.

According to some embodiments of the first aspect of the present invention, according to the minimum loop and the first adjacency matrix, generating a second adjacency matrix and a corresponding second degeneration graph, including:

According to the minimum circuit, the numerical value corresponding to each second path is input into the first adjacency matrix to obtain an intermediate adjacency matrix, wherein, each time the second path is traversed, the element corresponding to the second path in the first adjacency matrix is increased by 1;

According to the intermediate adjacency matrix, delete the element whose value is 2 in the intermediate adjacency matrix, and generate the second adjacency matrix and the corresponding second degraded graph, wherein, the second degraded graph is obtained by deleting the second path traversed twice from the first degraded graph .

According to some embodiments of the first aspect of the present invention, according to the maximum loop and each minimum loop, before obtaining the segmentation result of the building floor plan, it also includes:

Get the connectivity of an undirected graph;

According to the connectivity of the undirected graph, the containment relationship between the largest loop and the smallest loop is obtained, wherein the inclusion relationship represents the association with the partition result.

According to some embodiments of the first aspect of the present invention, according to the connectivity of the undirected graph, the inclusion relationship between the largest loop and the smallest loop is obtained, including:

Updating the second degenerate graph to an undirected graph, re-searching to obtain the maximum loop and the minimum loop, until the updated second adjacency matrix and the second degenerate graph degenerate to empty at the same time;

When the undirected graph is a connected graph, the largest loop is one, and every smallest loop is included in the largest loop;

When the undirected graph is a disconnected graph, there are at least two maximum circuits, and obtaining the containment relationship between the maximum circuit and the minimum circuit includes the following steps:

Obtain the two largest loops whose value ranges overlap;

According to the two largest loops with overlapping value ranges, the largest loop with a smaller value range is the inner largest loop, and the largest loop with a larger value range is the outer largest loop;

According to each smallest loop in the outer largest loop and the inner largest loop, the smallest loop that overlaps with the value range of the inner largest loop is selected as the outer surrounding smallest loop, and the inner largest loop is included in the outer surrounding smallest loop.

The embodiment of the second aspect of the present invention provides an electronic device, including:

A memory, a processor, and a computer program stored on the memory and operable on the processor. When the processor executes the computer program, the building subdivision method of any one of the first aspect is realized.

Since the electronic equipment in the embodiment of the second aspect applies any one of the building subdivision methods in the first aspect, it has all the beneficial effects of the first aspect of the present invention.

According to a computer storage medium provided by an embodiment of the third aspect of the present invention, computer-executable instructions are stored, and the computer-executable instructions are used to execute the building subdivision method of any one of the first aspect.

Since the computer storage medium in the embodiment of the third aspect can implement any one of the building subdivision methods in the first aspect, it has all the beneficial effects of the first aspect of the present invention.

Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and understandable from the description of the embodiments in conjunction with the following drawings, wherein:

Fig. 1 is the main step diagram of the building subdivision method of the embodiment of the present invention;

Fig. 2 is a step diagram of obtaining an undirected graph in a method for partitioning a building according to an embodiment of the present invention;

Fig. 3 is a step diagram of searching for the largest loop in the building partition method of the embodiment of the present invention;

Fig. 4 is a step diagram of generating a first adjacency matrix and a first degradation graph in a building partition method according to an embodiment of the present invention;

Fig. 5 is a step diagram of searching for the smallest loop in the building partition method according to the embodiment of the present invention;

Fig. 6 is a step diagram of generating a second adjacency matrix and a second degradation graph in the method for partitioning buildings according to an embodiment of the present invention;

Fig. 7 is a connected undirected graph in the embodiment of the present invention;

Fig. 8 is the first degradation diagram after deleting bridges and overhangs in the embodiment of the present invention;

FIG. 9 is a schematic diagram of an initial adjacency matrix in an embodiment of the present invention;

FIG. 10 is a schematic diagram of a first adjacency matrix in an embodiment of the present invention;

Fig. 11 is a disconnected undirected graph in the embodiment of the present invention;

Fig. 12 is a schematic diagram of partition results of another disconnected undirected graph in an embodiment of the present invention.

Detailed ways

In the description of the present invention, unless otherwise clearly defined, words such as setting, installation, and connection should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above words in the present invention in combination with the specific content of the technical solution. In the description of the present invention, several means one or more, and multiple means more than two. Greater than, less than, exceeding, etc. are understood as not including the original number, and above, below, within, etc. are understood as including the original number. In addition, the features defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

Subdivision refers to the division and discrimination of the rooms inside the building, which can reflect the internal layout of the building and specifically express the number and location of the rooms. The partitioning method in the related art can only process simple floor plans of buildings, and the processing speed is slow, and its application is very limited.

The building subdivision method, electronic equipment and computer storage medium of the present invention will be described below with reference to FIGS. 1 to 12 .

As shown in Figure 1, a method for partitioning a building according to an embodiment of the first aspect of the present invention includes the following steps:

Step S100, obtaining the undirected graph corresponding to the floor plan of the building;

Step S200, according to the undirected graph, search for the largest loop;

Step S300, generating a first adjacency matrix and a corresponding first degradation graph according to the maximum loop;

Step S400, according to the first degradation map, search for the smallest loop;

Step S500, generating a second adjacency matrix and a corresponding second degradation graph according to the minimum loop and the first adjacency matrix;

Step S600, updating the second degenerate graph to the first degenerate graph, re-searching to obtain the minimum loop, to generate the updated second adjacency matrix and the corresponding second degenerate graph, until the updated second adjacency matrix degenerates to empty, Among them, if the adjacency matrix is empty, the value of all elements inside it is 0;

Step S700, according to the maximum loop and each minimum loop, obtain the division result corresponding to the floor plan of the building.

Generating an undirected graph through the building floor plan can effectively simplify the complexity of the graph, thereby effectively improving the processing speed of partitioning. According to the search of the undirected graph, the largest loop and the smallest loop can be obtained, and then the result of the partitioning of the building can be obtained. In the process, the adjacency matrix is set to record and analyze the data, which can not only avoid repeated search for the obtained loops, thus ensure the reliability of the loop search, but also effectively reduce the complexity of data processing, and then quickly realize the search end conditions. It is judged that the speed of building subdivision processing can be effectively improved.

It can be understood that, referring to FIG. 2, step S100, obtaining the undirected graph corresponding to the building floor plan includes the following steps:

Step S110, obtaining the floor plan of the building.

Step S120, generate an undirected graph according to the building floor plan, wherein the center line of the wall projection of the building floor plan is the edge of the undirected graph, and the endpoint of the wall projection center line of the building floor plan is the edge of the undirected graph vertex.

Specifically, after performing step S100, the undirected graph is preprocessed through the following steps: develop software based on visual studio code, select node. dimensional data storage adjacency matrix M. Among them, the data structure includes point, edge and loop. The point contains three attributes, the abscissa x, the ordinate y, and the first number id ₁ ; the edge also has three attributes, the starting point start, the end point end, and the second number id ₂ , The starting point start and the end point end are both types of points, and the corresponding value is the first number id ₁ of the point, and the information of the point and the edge are stored in json, and the second number id ₂ is the key; the loop includes points, Edges, sub-circuits and parent circuits, and use arrays to store circuits, each element in the array corresponds to an object in the circuit, sub-circuits and parent circuits represent the inclusion relationship between circuits.

An undirected graph refers to a graph whose edges have no direction, generally represented by G(V, E), where V is a non-empty set, V is called a vertex set, and E is a set of unordered binary groups composed of elements in V. E is called an edge set. The undirected graph generated according to the building floor plan only contains the wall information in the building floor plan, which can avoid the interference of other information other than the wall in the building floor plan to the room division, and can effectively simplify the processing process. Reduce the complexity of partition processing. If there is a path between any two vertices, the undirected graph G(V, E) is a connected graph; if there is no path between any two vertices, the undirected graph G(V, E) is a disconnected graph.

The largest circuit refers to the circuit containing all the vertices and edges in the connected graph, usually denoted as Cb _i ; referring to Figure 7, it is a connected undirected graph with bridges <V ₁₃ , V ₁₄ > and hanging branches< V ₁₉ ,V ₂₀ >, where the maximum loop is Cb ₁ =(V ₁ ,V ₂ ,V ₃ ,V ₄ ,V 13 ,V ₁₄ ,V ₁₅ ,V ₁₆ ,V ₁₇ ,V ₁₈ _, V ₁₄ ,V ₁₃ , V ₅ , V ₁₉ , V ₂₀ , V ₁₉ , V ₆ , V ₁ ), the largest circuit includes bridge <V ₁₃ , V ₁₄ > and suspension branch <V ₁₉ , V ₂₀ >.

It can be understood that, referring to FIG. 3, step S200, according to the undirected graph, searches for the maximum loop, including the following steps:

S210. According to the undirected graph, use the vertex corresponding to the maximum or minimum value on the first coordinate axis as the first starting point, wherein the first coordinate axis is an axis parallel to the x-axis or the y-axis, and the first coordinate axis passes through the first coordinate axis a starting point, and the end point of the first coordinate axis is the first starting point;

S220. Taking the first starting point as the first starting point, acquiring each first adjacent edge connected to the first starting point;

S230. Taking the first coordinate axis as the first reference line, calculate the first direction factor corresponding to each first adjacent side, wherein the first direction factor is used to indicate that the first adjacent side is in a vector state relative to the first reference line The first rotation angle relationship of the first adjacent side relative to the first reference line in the vector state is the first rotation angle α ₁ , the first direction factor is set to K ₁ =α ₁ /2π, α ₁ ∈(-π , π), when the first adjacent side rotates clockwise relative to the first reference line, α ₁ is a negative value, when the first adjacent side rotates counterclockwise relative to the first reference line, α ₁ is positive, when the first adjacent The edge is an arc edge, and its first direction factor is calculated through its tangent;

S240. Compare each first direction factor, and obtain the first adjacent edge corresponding to the smallest first direction factor as the first path;

S250. Update the end point of the first path to the first starting point, and update the first path to the first reference line until the updated end point of the first path coincides with the first starting point, wherein the end point of the first path is far from An endpoint of the first starting point before updating;

S260. Obtain a maximum loop according to the multiple first paths.

Step S200 will be described below. Referring to FIG. 7 which is an undirected graph, first perform steps S210 to S240, set the first coordinate axis parallel to the x-axis, and the x-axis parallel to <V ₁ , V ₂ > to obtain the first coordinate axis The vertex V ₁ corresponding to the minimum value is the first starting point; with the first starting point V ₁ as the first starting point, the first adjacent edges connected to V ₁ are <V ₁ , V ₂ > and <V ₁ , V ₆ >; Calculate the first rotation angles of the two first adjacent sides of vector V ₁ V ₂ and vector V ₁ V ₆ relative to the first reference line vector V ₁ V ₂ are α ₁₁ and α ₁₂ respectively, the first direction factor are K ₁₁ and K ₁₂ respectively; since α ₁₁ <α ₁₂ , it can be seen that the relationship between the two first direction factors is K ₁₁ <K ₁₂ , and <V ₁ , V ₂ > corresponding to K ₁₁ is the first path. Then go to step S250, update the end point V ₂ of the first path <V ₁ , V ₂ > as the first starting point, and update the first path <V ₁ , V ₂ > as the first reference line, and obtain the updated two The two first adjacent edges are respectively <V ₂ , V ₃ > and <V ₂ , V ₇ >, and the updated two first adjacent edge vectors V ₂ V ₃ and vector V ₂ V ₇ are relative to the first baseline vector The first rotation angles of V ₁ V ₂ are α ₁₃ and α ₁₄ respectively, and the first direction factors are K ₁₃ and K ₁₄ respectively. It can be seen that the relationship between their corresponding first direction factors is K ₁₃ <K ₁₄ , and K ₁₃ corresponds to The first adjacent edge <V ₂ , V ₃ > of is the updated first path; repeat the above steps until the end point corresponding to the updated first path coincides with the first starting point V ₁ . Finally, _step S260 is performed, according to multiple first paths, after connecting multiple first paths, the maximum circuit is Cb ₁ (V ₁ , V ₂ , V 3 , V ₄ , V ₁₃ , V ₁₄ , V ₁₅ , V ₁₆ , V ₁₇ , V ₁₈ , V ₁₄ , V ₁₃ , V ₅ , V ₁₉ , V ₂₀ , V ₁₉ , V ₆ , V ₁ ).

It can be understood that, referring to FIG. 4, step 300, according to the maximum loop, generates the first adjacency matrix and the corresponding first degradation map, including the following steps:

S310. According to the maximum loop, input the value corresponding to each first path into the adjacency matrix to obtain the initial adjacency matrix, wherein, the initial value of the adjacency matrix is 0, and each time the first path is traversed, the adjacency matrix corresponds to the first path add 1 to the element;

S320. According to the initial adjacency matrix, delete elements with a value of 2 in the initial adjacency matrix to generate the first adjacency matrix and the corresponding first degenerate graph, wherein the first degenerate graph is deleted from the undirected graph after traversing the first path twice get.

Referring to FIG. 7 is an undirected graph. After performing step S200, the largest circuit Cb ₁ (V ₁ , V ₂ , V ₃ , V 4 , _V ₁₃ , V ₁₄ , V ₁₅ , V ₁₆ , V ₁₇ , V ₁₈ , V ₁₄ , V ₁₃ , V ₅ , V ₁₉ , V ₂₀ , V ₁₉ , V ₆ , V ₁ ), when performing step S310, the corresponding element is incremented by 1 each time it is traversed, Input the first path of Cb ₁ traversal of the largest loop obtained from the search into the adjacency matrix whose initial value is 0, and obtain the initial adjacency matrix as shown in Figure 9, in which the bridge <V ₁₃ , V ₁₄ > and the overhang < V ₁₉ , V ₂₀ > have been traversed twice, so the value of the corresponding element in the initial adjacency matrix is 2; when performing step S320, the first path corresponding to the element with a value of 2 in the initial adjacency matrix is a bridge and a branch, After deleting the bridges and hanging branches in the undirected graph, the first degenerated graph is generated as shown in Figure 8, in which the isolated point V20 is also deleted, and the element with a value of 2 in the initial adjacency matrix is deleted at the same time, and the first degenerated graph as shown in Figure 10 is generated. An adjacency matrix, where the value 0 is omitted.

It can be understood that, referring to FIG. 5, step S400, according to the first degradation map, searches for the minimum loop, including:

S410. According to the first degradation diagram, use the vertex corresponding to the maximum or minimum value on the second coordinate axis as the second starting point, wherein the second coordinate axis is an axis parallel to the x-axis or the y-axis, and the second coordinate axis passing through the second starting point, and the end point of the second coordinate axis is the second starting point;

S420. Using the second starting point as the second starting point, obtain each second adjacent edge connected to the second starting point;

S430. Taking the second coordinate axis as the second reference line, calculate the second direction factor corresponding to each second adjacent side, wherein the second direction factor is used to indicate that the second adjacent side is in a vector state relative to the second reference line The second rotation angle relation of , the second rotation angle of the second adjacent side relative to the second reference line in the vector state is α ₂ , the second direction factor is set to K ₂ =α ₂ /2π, α ₂ ∈(-π , π), when the second adjacent side rotates clockwise relative to the second reference line, α ₂ is a negative value, when the second adjacent side rotates counterclockwise relative to the second reference line, α ₂ is positive, when the second adjacent The edge is an arc edge, and its second direction factor is calculated through its tangent;

S440. Compare each second direction factor, and obtain the second adjacent edge corresponding to the smallest second direction factor as the second path;

S450. Update the end point of the second path to the second starting point, and update the second path to the second reference line, and obtain the second adjacent edge corresponding to the largest second direction factor as the third path, wherein the second path's The end point is an end point away from the second starting point before the update;

S460. Update the end point of the third path to the second starting point until the updated end point of the third path coincides with the second starting point, wherein the end point of the third path is an end point away from the second starting point before updating;

S470. Obtain a minimum circuit according to the second path and multiple third paths.

Step S400 will be described below. Referring to FIG. 8 for the first degradation map, first perform steps S410 to S440, set the second coordinate axis parallel to the x-axis, and the x-axis is parallel to <V ₁ , V ₂ > to obtain the second coordinate axis The vertex V ₁ corresponding to the upper minimum value is the second starting point; with the second starting point V ₁ as the second starting point, the second adjacent edges connected to V ₁ are <V ₁ , V ₂ > and <V ₁ , V ₆ >; the calculated second rotation angles of the two second adjacent sides of vector V ₁ V ₂ and vector V ₁ V ₆ relative to the second reference line vector V ₁ V ₂ are α ₂₁ and α ₂₂ respectively, the first The two direction factors are K ₂₁ and K ₂₂ respectively; since α ₂₁ <α ₂₂ , it can be seen that the relationship between the two second direction factors is K ₂₁ <K ₂₂ , and <V ₁ , V ₂ > corresponding to K ₂₁ is the second path . Go to step S450 again, update the end point V ₂ of the second path <V ₁ , V ₂ > as the second starting point, and update the second path <V ₁ , V ₂ > as the second baseline, and obtain the updated two The two second adjacent edges are respectively <V ₂ , V ₃ > and <V ₂ , V ₇ >, and the updated two second adjacent edge vectors V ₂ V ₃ and V ₂ V ₇ are relative to the second baseline vector V ₁ The second rotation angles of V ₂ are α ₂₃ and α ₂₄ respectively, and the second direction factors are K ₂₃ and K ₂₄ respectively. It can be seen that their corresponding second direction factors are K ₂₃ <K ₂₄ , and the corresponding second direction factors of K ₂₄ are obtained. The two adjacent edges <V ₂ , V ₇ > are the third path. Then proceed to step S460, update the end point of the third path <V ₂ , V ₇ > to the second starting point, and obtain the updated two second adjacent edges as <V ₇ , V ₈ > and <V ₇ , V ₁₂ >, the second rotation angles of the updated two second adjacent edge vectors V ₇ V ₈ and V ₇ V ₁₂ relative to the second reference line vector V ₂ V ₇ are α ₂₅ and α ₂₆ respectively, and the second direction factors are respectively K ₂₅ and K ₂₆ , it can be seen that the relationship between their corresponding second direction factors is K ₂₅ >K ₂₆ , and the second adjacent edge <V ₇ , V ₈ > corresponding to K ₂₅ is the updated third path; repeat The above steps are performed until the end point corresponding to the updated third path coincides with the starting point V ₁ of the second coordinate axis. Finally, step S470 is performed, and the minimum circuit obtained after connecting the second path and multiple third paths is Cb _1S1 (V ₁ , V ₂ , V ₇ , V 8 , V ₉ , V ₁₀ , V ₁₁ , _{V 12} _, V ₇ ,V ₂ ,V ₃ ,V ₄ ,V ₅ ,V ₆ ,V ₁ ).

It can be understood that, referring to FIG. 6, step S500 generates a second adjacency matrix and a corresponding second degeneration map according to the minimum loop and the first adjacency matrix, including:

S510. According to the minimum loop, input the value corresponding to each second path into the first adjacency matrix to obtain an intermediate adjacency matrix, wherein, each time the second path is traversed, the element corresponding to the second path in the first adjacency matrix is incremented by 1;

S520. According to the intermediate adjacency matrix, delete the element whose value is 2 in the intermediate adjacency matrix, and generate the second adjacency matrix and the corresponding second degenerate graph, wherein, the second degenerate graph deletes the second path traversed twice from the first degenerate graph after getting.

Referring to FIG _. 8 is the first degradation diagram. After performing step S400, the minimum circuit that can finally obtain the first degradation diagram is Cb _1S1 (V ₁ , V ₂ , V 7 , V ₈ , V ₉ , V ₁₀ , V ₁₁ , V ₁₂ , V ₇ , V ₂ , V ₃ , V ₄ , V ₅ , V ₆ , V ₁ ), when performing step S510, add 1 to the corresponding element each time it is traversed, and the searched minimum circuit Cb _1S1 is input into the first adjacency matrix to obtain an intermediate adjacency matrix, wherein the partial path of the smallest circuit Cb _1S1 is the same as the partial path of the largest circuit Cb ₁ , and the value of the element in the corresponding intermediate adjacency matrix of these paths is 2; in step S520 When , delete the element whose value is 2 in the intermediate adjacency matrix, delete the path corresponding to the element whose value is 2 in the intermediate adjacency matrix in the first degenerate graph, generate the second degenerate graph, and delete the element whose value is 2 in the intermediate adjacency matrix , generating the second adjacency matrix.

Update the second degenerate graph to the first degenerate graph, and re-search to obtain the minimum cycle to generate the updated second adjacency matrix and the corresponding second degenerate graph until the updated second adjacency matrix degenerates to empty, that is, the second The elements in the adjacency matrix are all 0. At this time, it can be judged that all the minimum circuits in the maximum circuit Cb ₁ obtained by searching are Cb _1S1 (V ₁ , V ₂ , V ₇ , V ₈ , V ₉ , V ₁₀ , V ₁₁ ,V ₁₂ ,V ₇ ,V ₂ ,V ₃ ,V ₄ ,V ₅ ,V ₆ ,V ₁ ), Cb _1S2 (V ₁₂ ,V ₁₁ ,V ₈ ,V ₇ ,V ₁₂ ), Cb _1S3 (V ₁₁ , V ₁₀ , V ₉ , V ₈ , V ₁₁ ) and Cb _1S4 (V ₁₅ , V ₁₆ , V ₁₇ , V ₁₈ , V ₁₄ , V ₁₅ ).

In a disconnected graph, it is only possible that a maximum circuit is contained in a minimum circuit in a large range of maximum circuits. In this paper, due to the following properties: a maximum will contain all the minimum circuits in it, and all the minimum circuits in a maximum circuit There is no inclusion relationship between them, and the circuit formed by two connected subgraphs in a disconnected graph may have an inclusion relationship. It can be seen that only non-connected graphs have containment relations between circuits. If there are two connected subgraphs of different sizes in a certain non-connected graph, that is, the two largest circuits G (large) and H (small), if G and H contain relationship, then

Assuming that H is contained in two or more minimum circuits of G, then

Contradicts that G and H are two connected subgraphs in a disconnected graph; assuming only a certain minimum circuit of H is contained in G or the minimum circuit of G, then

Ditto contradictory. Therefore, there is an inclusion relationship between circuits only in a disconnected graph, and only a certain maximum circuit is contained in a certain minimum circuit.

It can be understood that, before step S700, that is, before obtaining the division result of the building floor plan according to the maximum loop and each minimum loop, the following steps are also included:

Get the connectivity of an undirected graph;

Specifically, obtaining the connectivity of an undirected graph includes the following steps:

When the second adjacency matrix degenerates to be empty, obtain the corresponding second degenerate graph;

Judging the connectivity of the undirected graph according to the second degenerated graph, wherein, when the second degenerated graph is an empty graph, the undirected graph is a connected graph, and when the second degenerated graph is a non-empty graph, the undirected graph is a disconnected graph.

It can be understood that, according to the connectivity of the undirected graph, obtaining the containment relationship between the largest loop and the smallest loop includes the following steps:

Updating the second degenerate graph to an undirected graph, and re-searching to obtain the maximum loop and the minimum loop, until the updated second adjacency matrix degenerates to empty and the second degenerate graph degenerates to an empty graph;

Obtain the two largest loops whose value ranges overlap;

Specifically, when the undirected graph is a disconnected graph and there are at least two maximum circuits, the second degenerate graph is updated to an undirected graph, and the maximum and minimum circuits are obtained by re-searching until the updated second adjacency matrix and the second The degradation graph degenerates to empty at the same time, after obtaining each maximum loop and minimum loop, the following steps are also included:

1. Calculate the value range (X _min , X _max ) and (Y _min , Y _max ) of the abscissa x and y coordinate y of a certain maximum loop, if

and

Choose the smaller value range among {X _min ≤ xCb _i ≤ X _max } and {X _min ≤ xCb _j ≤ X _max } to enter the next step.

2. Assuming that the value range of {X _min ≤ xCb _j ≤ X _max } is small, then calculate the value ranges of the x coordinates and y coordinates of all the minimum circuits of the largest circuit Cb _i , taking

and

k value at the same time, that is, to obtain the minimum circuit Cb _i s _k of a certain maximum circuit Cb _j included in the maximum circuit Cb _i , as shown in Figure 11, the maximum circuit Cb ₂ = (V ₁₃ , V ₁₄ , V ₁₅ , V ₁₆ , V ₁₃ ) is included in the smallest circuit _Cb ₁ s ₁ =(V ₁ , V ₂ , V ₁₀ , V ₉ , V ₁₂ , V ₆ , V ₇ , V ₈ , V ₁ ) of Cb 1 .

3. Repeat steps 1 and 2 to find the containment relationship between all circuits.

Referring to Figure 7, an undirected graph is a connected graph, so all its smallest circuits are contained in its largest circuits.

Referring to Figure 12, the undirected graph is a disconnected graph, update the second degenerated graph to an undirected graph, and re-search to obtain the largest loop and the smallest loop in it, until the updated second adjacency matrix and the second degenerated graph simultaneously degenerate into Empty to get all the maximum and minimum loops.

The maximum circuit is: Cb ₁ = (V ₁ , V ₂ , V ₃ , V ₄ , V ₅ , V ₆ , V ₇ , V ₈ , V ₉ , V ₂₀ , V ₁ ), Cb ₂ = (V _21, V ₂₂ , V ₂₃ , V ₂₄ , V ₂₅ , V ₂₆ , V ₂₁ ).

All the minimum circuits are: room 1: Cb ₁ s ₁ = (V ₁ , V ₂ , V ₁₂ , V ₁₁ , V ₁₀ , V ₁₆ , V ₉ , V ₂₀ , V ₁ ), room 2: Cb ₁ s ₂ =(V ₁₁ ,V ₁₂ ,V ₁₇ ,V ₁₆ ,V ₁₀ ,V ₁₁ ), room 5: Cb ₁ s ₃ =(V ₂ ,V 3 ,V ₁₃ ,V ₁₂ _, V ₂ ), room 4: Cb ₁ s ₄ = (V ₁₂ , V ₁₃ , V ₁₄ , V ₁₇ , V ₁₂ ), room 3: Cb ₁ s ₅ = (V ₁₇ , V ₁₄ , V 15 , V ₁₆ _, V ₁₇ ), room 8: Cb ₁ s ₆ =(V ₁₆ ,V ₁₅ ,V ₁₄ ,V ₁₈ ,V ₆ ,V ₇ ,V ₈ ,V ₁₉ ,V ₈ ,V ₉ ,V ₁₆ ), room 6: Cb ₁ s ₇ =(V ₃ ,V ₄ ,V ₁₈ ,V ₁₄ ,V ₁₃ ,V ₃ ), room 7: Cb ₁ s ₈ =(V ₄ ,V ₅ ,V ₆ ,V ₁₈ ,V ₄ ), room 9: Cb ₂ s ₁ = (V ₂₁ , V ₂₂ , V ₂₅ , V ₂₆ , V ₂₁ ), room 10: Cb ₂ s ₂ = (V ₂₂ , V ₂₃ , V ₂₄ , V ₂₅ , V ₂₂ ).

The inclusion relationship is that Cb ₂ is included in Cb ₁ s ₆ . It can be seen that no matter whether the room is a convex polygon or a concave polygon, the building division method of the present invention can successfully complete the loop search, and can efficiently complete the online real-time division of the building.

Using the building partition method of the present invention to carry out partition processing, once the edges in the undirected graph are traversed twice, they will be deleted. It can be seen from this that the time complexity is twice the number of edges in the undirected graph, that is, the time complexity is O(E), where E is the number of edges in the undirected graph. The containment relationship of the loop in the connected graph is clear, and no judgment processing is required. The judgment process of the containment relationship is only for the non-connected graph, not the connected graph. It only needs to compare the value ranges of the abscissa and ordinate of the loop vertices, so the time The complexity is O(V), where V is the number of vertices. Therefore, the total time complexity is O(E)+O(V), which can effectively ensure the partitioning efficiency of the building partitioning method of the present invention.

In addition, the embodiment of the second aspect of the present invention also provides an electronic device, which includes: a memory, a processor, and a computer program stored in the memory and operable on the processor.

The processor and memory can be connected by a bus or other means.

As a non-transitory computer-readable storage medium, memory can be used to store non-transitory software programs and non-transitory computer-executable programs. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory optionally includes memory located remotely from the processor, and these remote memories may be connected to the processor via a network. Examples of the aforementioned networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The non-transitory software programs and instructions required to realize the building subdivision method of the embodiment of the first aspect above are stored in the memory, and when executed by the processor, the building subdivision method in the above embodiment is executed, for example, executing Method steps S100 to S700 , method steps S110 to S120 , method steps S210 to S260 , method steps S310 to S320 , method steps S410 to S470 , and method steps S510 to S520 described above.

The device embodiments described above are only illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, an embodiment of the present invention also provides a computer-readable storage medium, the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are executed by a processor or a controller, for example, by the above-mentioned Execution by a processor in the device embodiment can cause the above-mentioned processor to execute the building division method in the above-mentioned embodiment, for example, perform the above-described method steps S100 to S700, method steps S110 to S120, and method steps S210 to S260 , method steps S310 to S320, method steps S410 to S470, method steps S510 to S520.

Those skilled in the art can understand that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware and an appropriate combination thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit . Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). As known to those of ordinary skill in the art, the term computer storage media includes both volatile and nonvolatile media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data. permanent, removable and non-removable media. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, tape, magnetic disk storage or other magnetic storage devices, or can Any other medium used to store desired information and which can be accessed by a computer. In addition, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media .

In the description of this specification, references to the terms "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific examples," or "some examples" are intended to mean that the implementation A specific feature, structure, material, or characteristic described by an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although the embodiments of the present invention have been shown and described, those skilled in the art can understand that various changes, modifications, substitutions and modifications can be made to these embodiments without departing from the principle and spirit of the present invention. The scope of the invention is defined by the claims and their equivalents.

Claims

The building partition method is characterized in that it comprises the steps of:

Obtain the undirected graph corresponding to the floor plan of the building;

According to the undirected graph, searching for the maximum loop;

Generate a first adjacency matrix and a corresponding first degradation graph according to the maximum loop;

According to the first degradation graph, searching for a minimum loop;

generating a second adjacency matrix and a corresponding second degradation graph according to the minimum loop and the first adjacency matrix;

updating the second degenerate graph to the first degenerate graph, re-searching to obtain the minimum loop, to generate the updated second adjacency matrix and the corresponding second degenerate graph, until the updated all The second adjacency matrix degenerates into empty;

According to the largest loop and each of the smallest loops, the division result corresponding to the floor plan of the building is obtained.
The method for partitioning buildings according to claim 1, wherein obtaining the undirected graph corresponding to the floor plan of the building comprises:

Obtain the floor plan of the building;

Generate the undirected graph according to the building floor plan, wherein the wall projection centerline of the building floor plan is an edge of the undirected graph, and the wall projection centerline of the building floor plan The endpoints of are the vertices of the undirected graph.
The method for partitioning buildings according to claim 1, wherein said searching for the maximum loop according to said undirected graph includes:

According to the undirected graph, the vertex corresponding to the maximum or minimum value on the first coordinate axis is used as the first starting point, wherein the first coordinate axis is an axis parallel to the x-axis or the y-axis, and the first The coordinate axis passes through the first starting point;

Taking the first starting point as a first starting point, acquiring each first adjacent edge connected to the first starting point;

Using the first coordinate axis as a first reference line, calculate a first direction factor corresponding to each of the first adjacent sides, wherein the first direction factor is used to indicate that the first adjacent side is relative to the The first rotation angle relationship of the first reference line;

Comparing each of the first direction factors to obtain the first adjacent edge corresponding to the smallest first direction factor as the first path;

updating the end point of the first path to the first starting point, and updating the first path to the first baseline until the updated end point of the first path coincides with the first starting point ;

According to a plurality of the first paths, the maximum loop is obtained.
The method for partitioning buildings according to claim 3, wherein said generating a first adjacency matrix and a corresponding first degradation graph according to said maximum loop comprises:

According to the maximum loop, input the value corresponding to each of the first paths into the adjacency matrix to obtain an initial adjacency matrix, wherein, the initial values of the adjacency matrix are all 0, and each time the first path is traversed, the Adding 1 to the element corresponding to the first path in the adjacency matrix;

According to the initial adjacency matrix, delete the element whose value is 2 in the initial adjacency matrix, generate the first adjacency matrix and the corresponding first degraded graph, wherein the first degraded graph is formed by the undirected The graph is obtained after deleting the first path traversed twice.
The method for partitioning buildings according to claim 1, wherein the searching for the smallest loop according to the first degradation map includes:

According to the first degradation diagram, the vertex corresponding to the maximum or minimum value on the second coordinate axis is used as the second starting point, wherein the second coordinate axis is an axis parallel to the x-axis or the y-axis, and the the second coordinate axis passes through the second starting point;

Taking the second starting point as a second starting point, acquiring each second adjacent edge connected to the second starting point;

Using the second coordinate axis as a second reference line, calculate a second direction factor corresponding to each of the second adjacent sides, wherein the second direction factor is used to indicate that the second adjacent side is relative to the The second rotation angle relationship of the second reference line;

Comparing each of the second direction factors to obtain the second adjacent edge corresponding to the smallest second direction factor as the second path;

updating the end point of the second path to the second starting point, and updating the second path to the second reference line, and obtaining the second adjacent edge corresponding to the largest second direction factor is third path;

updating the end point of the third path to the second starting point until the updated end point of the third path coincides with the second starting point;

The minimum loop is obtained according to the second path and the plurality of third paths.
The method for partitioning buildings according to claim 5, wherein, according to the minimum loop and the first adjacency matrix, a second adjacency matrix and a corresponding second degradation map are generated, including:

According to the minimum loop, the value corresponding to each second path is input into the first adjacency matrix to obtain an intermediate adjacency matrix, wherein, each time the second path is traversed, the corresponding value in the first adjacency matrix adding 1 to the elements of the second path;

According to the intermediate adjacency matrix, delete the elements whose value is 2 in the intermediate adjacency matrix to generate the second adjacency matrix and the corresponding second degraded graph, wherein the second degraded graph is formed by the first The degradation graph is obtained after deleting the second path traversed twice.
The building division method according to claim 6, wherein, before obtaining the division result of the building floor plan according to the maximum loop and each minimum loop, it also includes:

Obtain the connectivity of the undirected graph;

According to the connectivity of the undirected graph, an inclusion relationship between the largest loop and the smallest loop is obtained, wherein the inclusion relationship represents an association with the segmentation result.
The method for partitioning a building according to claim 7, wherein the inclusion relationship between the largest loop and the smallest loop is obtained according to the connectivity of the undirected graph, including:

When the undirected graph is a connected graph, the maximum loop is one, and each of the minimum loops is included in the maximum loop;

When the undirected graph is a disconnected graph, and there are at least two maximum circuits, the obtaining the inclusion relationship between the maximum circuit and the minimum circuit includes the following steps:

updating the second degenerate graph to the undirected graph, re-searching to obtain the maximum loop and the minimum loop, until the updated second adjacency matrix and the second degradation graph degenerate to empty at the same time;

Obtaining the two largest loops whose value ranges overlap;

According to the two maximum loops with overlapping value ranges, it is obtained that the maximum loop with a small value range is an internal maximum loop, and the maximum loop with a large value range is an external maximum loop;

According to each of the minimum circuits in the external maximum circuit and the internal maximum circuit, the minimum circuit that overlaps with the value range of the internal maximum circuit is selected as the outer enclosing minimum circuit, and the internal maximum circuit is obtained. A loop is included in the outer enclosing minimum loop.
An electronic device, characterized in that it comprises:

A memory, a processor, and a computer program stored on the memory and operable on the processor, when the processor executes the computer program, the building according to any one of claims 1 to 8 is realized Partition method.
A computer storage medium, which is characterized in that it stores computer executable instructions, and the computer executable instructions are used to execute the building subdivision method according to any one of claims 1 to 8.