WO2023102794A1

WO2023102794A1 - Apparatus and method for decoding a plurality of codewords

Info

Publication number: WO2023102794A1
Application number: PCT/CN2021/136602
Authority: WO
Inventors: Yaron Ben-Arie; Avner Epstein; Nadav BASSON; Shimon SHILO; Wen Li; Doron Ezri
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2021-12-08
Filing date: 2021-12-08
Publication date: 2023-06-15

Abstract

An apparatus for decoding a plurality of codewords. The apparatus comprises one or more decoding blocks associated with a clock having a clock cycle, such that each of the decoding blocks are configured to receive in input a plurality of codewords. A given decoding block comprises a plurality of decoding units arranged in series, each of the decoding unit in the plurality of decoding units being configured to run a decoding stage. The plurality of decoding units comprise M identical series of N decoding units, with M >1 and N >1 forming a series of N x M decoding units. The given decoding block is configured to receive in input each codeword, amongst the plurality of codewords, one after the other every C clock cycles, with 0 < C < N x M.

Description

APPARATUS AND METHOD FOR DECODING A PLURALITY OF CODEWORDS

TECHNICAL FIELD

The present disclosure relates generally to the field of communication transmission; and more specifically toan apparatus and method for decoding a plurality of codewords.

BACKGROUND

Communication transmission has evolved from phone calls to the internet, and now social media applications which facilitate communication. Such communication has also evolved from text to pictures and media files. This requires communication to be transmitted frequently, such that communication channels are available in real-time, which means that communication is required to be transmitted within nanoseconds. With the evolution of such communication, there arose a need for data error correction, such that communications through said communication channels could be effective and optimized. This paved way to the usage of encoders and decoders, which encode communication before transmitting at a sender’s end and decode the encoded communication after receiving it at the receiver’s end. Since communication channels are available in real-time, the encoding and decoding of communication is also required to happen at real-time.

Advanced transmission standards require high data rates, which means that a large amount of data must be seamlessly transmitted in short spans of time. Common decoders and encoders are therefore required to encode and decode communication in such short spans of time. However, such encoders and decoders require a large amount of time to encode or decode a single codeword, and causes delay in the communication channel. Generally, encoded codewords are received by the decoder at high rates (for example, one codeword every 70ns) , and in order to meet the high rate of codewords being received, a large amount of decoders are employed, which requires a lot of silicon area, increases complexity and increases heat dissipation in the area that such decoders are placed.

Therefore, in light of the foregoing discussion, there exists a need to overcome the aforementioned drawbacks associated with the conventional decoders and methods of decoding.

SUMMARY

The present disclosure seeks to provide an apparatus for decoding a plurality of codewordshaving an increased efficacy in decoding codewords. The present disclosure seeks to provide a solution to the existing problem ofsuboptimaldecoding of codewords due to suboptimal use of a decoding apparatus which requires a large number of decoders to meet the ultra high rate of the evolvingstandards, and utilizes a lot of space. An aim of the present disclosure is to provide a solution that overcomes at least partially the problems encountered in prior art, and provides an improved apparatus and method for decoding the plurality of codewordsthat improves the efficacy of decoding of codewords performed by the apparatus.

The object of the present disclosure is achieved by the solutions provided in the enclosed independent claims. Advantageous implementations of the present disclosure are further defined in the dependent claims.

In one aspect, the present disclosure provides an apparatus for decoding a plurality of codewords, comprising one or more decoding blocks associated with a clock having a clock cycle, each of the decoding blocks being configured to receive in input a plurality of codewords and comprising a plurality of decoding units arranged in serie, each of the decoding unit in the plurality of decoding units being configured to run a decoding stage, wherein the plurality of decoding units, in a given one of the one or more decoding blocks, comprises a serie of M identical series of N decoding units, with M > 1 and N >1, forming a serie of N x M decoding units, and the given decoding block is configured to receive in input each codeword, amongst the plurality of codewords, one after the other every C clock cycles, with 0 < C < N x M.

This is advantageous since the plurality of decoding units decode the plurality of codewords parallelly, such that the plurality of codewords are decoded simultaneously. This provides the one or more decoding blocks increased efficiency and a reduced time for processing the plurality of codewords. Moreover, a processing efficiency of a given decoding block is exponentially increased, reducing the requirement of excessive decoding blocks and saving area. Additionally, when the decoding is performed at a full clock speed, the plurality of codewords are decoded quickly, such that the clock speed is lowered considerably to meet requisite requirements, saving energy.

In an implementation form, the method further comprises the given decoding block being configured to receive the plurality of codewords at a given codeword rate, each of the codewords in the plurality of codewords having a codeword size, and wherein each of the decoding unit in the given decoding block is configured to decode a given codeword using a parity matrix, said parity matrix depending on the size of the given codeword and on the codeword rate.

This is advantageous since such apparatus links a plurality of decoding blocks, which provides a higher data rate as compared to when the decoding blocks are utilized separately. Additionally, multiple codewords for different users having different codebooks within multiple links are being decoded at the full clock rate herein, beneficially providing faster decoding as compared to when a given parity matrix was not selected depending on the codeword size.

In a further implementation form, C is equal to 1.

This is advantageous since decoding the given codeword at every clock cycle ensures that the plurality of codewords (having a plurality of codebooks) are being decoded at full clock rate, such that a processing capability of the given decoding unit is being utilized efficiently as compared to when the plurality of codewords are not decoded at every clock cycle.

In another further implementation form, the given decoding block is configured to receive in input the plurality of codewords at a given codeword rate, CW_rate, and wherein C depends on the number of decoding units N x M in the given decoding block, on the given codeword rate CW_rate, and on the clock cycle period, CLK.

This is advantageous since this allows the apparatus to dynamically save power since C is being adjusted.

In a further implementation form, C is the first integer greater or equal to N x M /L, where L is the first integer greater or equal to N x M x CW_rate x CLK.

This is advantageous since this allows the apparatus to work at the full clock rate while also dynamically saving power since C can be adjusted.

In another aspect, the present disclosure provides a method for decoding a plurality of codewords, comprising receiving the plurality of codewords in input into a decoding block associated with a clock having a clock cycle and comprising a plurality of decoding units arranged in serie, each of the decoding unit in the plurality of decoding units being configured to run a decoding stage, and decoding the plurality of codewords, comprising running each of the decoding stages on each of the codewords of the plurality of codewords, wherein decoding the plurality of codewords comprises running a serie of M identical series of N decoding stages corresponding to a serie of M identical series of N decoding units forming a serie of N x M decoding units in the decoding block, with M > 1 and N >1, and wherein receiving the plurality of codewords in input into the decoding block comprises receiving each codeword amongst the plurality of codewords, one after the other every C clock cycles, with 0 < C < N x M.

This is advantageous since the plurality of decoding units decode the plurality of codewords parallelly, such that at least 4 (2*2) codewords are decoded simultaneously. This assists the one or more decoding blocks with increased efficiency and a reduced time for processing the plurality of codewords. Moreover, a processing efficiency of a given decoding block is exponentially increased, reducing the requirement of excessive decoding blocks and saving area. Additionally, when the decoding is performed at a full clock speed, the plurality of codewords are decoded quickly, such that the clock speed may be lowered considerably to meet requisite requirements, saving energy.

In an implementation form, the plurality of codewords is received by the decoding block at a given codeword rate, each of the codewords of the plurality of codewords having a codeword size, and wherein running a decoding stage on a given codeword of the plurality of codewords comprises using a parity matrix, said parity matrix depending on the size of the given codeword and on the codeword rate.

This is advantageous since such method provides a higher data rate by decoding multiple codewords at the full clock rate herein, beneficially providing faster decoding as compared to when a given parity matrix was not selected depending on the codeword size.

In a further implementation form, the plurality of codewords is received by the decoding block at a given codeword rate, CW_rate, and wherein C depends on the number of decoding units N x M in the given decoding block, on the given codeword rate CW_rate, and on the clock cycle period, CLK.

This is advantageous since this allows dynamic saving of power since C is being adjusted. In a further implementation form, C is the first integer greater or equal to N x M /L, where L is the first integer greater or equal to N x M x CW_rate x CLK.

This is advantageous since this allows decoding to be performed at the full clock rate while also dynamically saving power since C can be adjusted.

In another implementation form, receiving the plurality of codewords in input into the decoding block comprises receiving multiple pluralities of codewords, each of the pluralities of codewords being received with a specific codeword rate, and wherein receiving the multiple pluralities of codewords in input into the decoding block comprises receiving in input, one after the other, and every C cycles, one codeword of each of the multiple pluralities of codewords.

This is advantageous since this allows multiple pluralities of codewords to get decoded simultaneously, providing a higher data rate since the multiple pluralities of codewords for different users having different codebooks within multiple links are decoded at the full clock rate herein, beneficially providing faster decoding as compared to when a given parity matrix was not selected depending on the codeword size.

In a further implementation form, for decoding a given codeword having a given codeword size and belonging to one of the multiple pluralities of codewords, each decoding stage uses a parity matrix depending on the size of the given codeword and on the specific codeword rate corresponding to the said one of the pluralities of codewords.

This is advantageous since this provides a higher data rate by decoding multiple pluralities of codewords for different users having different codebooks within multiple links at the full clock rate herein, beneficially providing faster decoding as compared to when a given parity matrix was not selected depending on the codeword size.

In a further implementation form, the method further comprises determining a given codeword rate, CW_rate, as being the sum of all specific codeword rates, and wherein C depends on the number of decoding units N x M in the given decoding block, on the given codeword rate CW_rate, and on the clock cycle period, CLK.

This is advantageous since this allows dynamic saving of power since C is being adjusted.

It has to be noted that all devices, elements, circuitry, units and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof. It will be appreciated that features of the present disclosure are susceptible to being combined in various combinations without departing from the scope of the present disclosure as defined by the appended claims.

Additional aspects, advantages, features and objects of the present disclosure would be made apparent from the drawings and the detailed description of the illustrative implementations construed in conjunction with the appended claims that follow.

BRIEF DESCRIPTION OF THE DRAWINGS

The summary above, as well as the following detailed description of illustrative embodiments, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the present disclosure, exemplary constructions of the disclosure are shown in the drawings. However, the present disclosure is not limited to specific methods and instrumentalities disclosed herein. Moreover, those in the art will understand that the drawings are not to scale. Wherever possible, like elements have been indicated by identical numbers.

Embodiments of the present disclosure will now be described, by way of example only, with reference to the following diagrams wherein:

FIG. 1 is a block diagram illustrating an apparatus for decoding a plurality of codewords, in accordance with an embodiment of the present disclosure;

FIG. 2 is a more detailed block diagram illustrating an apparatus for decoding a plurality of codewords, in accordance with an embodiment of the present disclosure;

FIG. 3 is a block diagram illustrating an implementation of an apparatus for decoding a plurality of codewords within a system having a set of parity matrices, in accordance with a multilink embodiment of the present disclosure;

FIG. 4 is a schematic diagram illustrating an apparatus for decoding a plurality of codewords for a plurality of users, having a decoding block, in accordance with an embodiment of the present disclosure;

FIG. 5 is a schematic diagram illustrating an exemplary apparatus for decoding a plurality of codewords, in accordance with an embodiment of the present disclosure, aiming more particularly at saving power; and

FIG. 6 is a flowchart of a method for decoding a plurality of codewords, in accordance with an embodiment of the present disclosure.

.In the accompanying drawings, an underlined number is employed to represent an item over which the underlined number is positioned or an item to which the underlined number is adjacent. A non-underlined number relates to an item identified by a line linking the non-underlined number to the item. When a number is non-underlined and accompanied by an associated arrow, the non-underlined number is used to identify a general item at which the arrow is pointing.

DETAILED DESCRIPTION OF EMBODIMENTS

The following detailed description illustrates embodiments of the present disclosure and ways in which they can be implemented. Although some modes of carrying out the present disclosure have been disclosed, those skilled in the art would recognize that other embodiments for carrying out or practicing the present disclosure are also possible.

FIG. 1 and 2 are block diagrams illustrating an apparatus for decoding a plurality of codewords, in accordance with an embodiment of the present disclosure..

With reference of FIG. 1 and 2, there is shown an apparatus 100 for decoding a plurality of codewords, comprising one or more decoding blocks 102 (102a, 102b, ….., 102m) associated with a clock having a clock cycle, each of the

decoding blocks

102a, 102b, ….., 102m configured to receive in input a plurality of codewords and comprising a plurality of decoding units 104 (104a, 104b, …, 104n) , 106 (106a, 106b, …, 106n) , 108 (108a, 108b, …, 108n) arranged in serie, each of the

decoding unit

104a, 104b, …, 104n, 106a, 106b, …, 106n, 108a, 108b, …, 108n in the plurality of decoding units being configured to run a decoding stage, wherein the plurality of decoding units, in a given one of the one or more decoding blocks, comprises a serie of M identical series of N decoding units, with M > 1 and N >1, forming a serie of N x M decoding units, and the given decoding block is configured to receive in input each codeword, amongst the plurality of codewords, one after the other every C clock cycles, with 0 < C < N x M.

Herein, the term “codeword” refers to an element of a code. Moreover, the clock displays the time digitally (i.e., in numerals and other symbols) , assisting a given decoding block by defining a time period when a given function is to be executed. Herein, the clock utilizes the clock cycle to define a period of time required to perform the given function. The decoding stage refers to a given function of a given decoding unit for decoding a given codeword.

As shown in FIG. 1 and 2, the one or more decoding blocks 102 (102a, 102b, ….., 102m) form M identical series, such that each decoding block comprises a serie of N decoding units. Since M>1 and N>1, the plurality of decoding units decode the plurality of codewords, such that each decoding unit decodes a first codeword. For example, if M=2 and N=3, there would be 2*3=6 decoding units, such that 6 first codewords are decoded. Additionally, a second codeword is provided as input to each decoding unit at every C clock cycle. Referring to the previous example, for 6 decoding units, C lies in a range of 1 to 5, since 0 < C < 6. Therefore, if C=1, the second codeword is provided to each decoding unit at every clock cycle, if C=2, the second codeword is provided to each decoding unit at every alternate clock cycle, and thereon.

Advantageously, the plurality of decoding units decode the plurality of codewords parallelly, such that at least 4 (2*2) codewords are decoded simultaneously. This assists the one or more decoding blocks with increased efficiency and a reduced time for processing the plurality of codewords. Moreover, a processing efficiency of a given decoding block is exponentially increased, reducing the requirement of excessive decoding blocks and saving area. Additionally, when the decoding is performed at a full clock speed, the plurality of codewords are decoded quickly, such that the clock speed may be lowered considerably to meet requisite requirements, saving energy. For example, if the apparatus comprises 10 decoding blocks having 80 decoding units each running at a full clock speed of 640 megahertz, 640M codewords may be decoded per second. However, a requirement of decoding is approximately 14M codewords per second. In this case, the clock speed may be lowered.

As can be seen from FIG. 1 and 2, the plurality of M identical blocks arranged in serie, each comprising a same plurality of N decoding units also arranged in serie, forms a decoding device with N x M decoding stages corresponding to the N x M decoding units, without any loop.

FIG. 3 is a block diagram illustrating an implementation of an apparatus 302for decoding a plurality of codewords within a system 300, in accordance with a multilink embodiment of the present disclosure. As shown in FIG. 3, the plurality of codewords are send by a plurality of receivers 304 (304a, 304b, …, 304n) to a collector 306, on a first-come, first-serve basis. Herein, the collector 306sends the plurality of codewords to the apparatus 302for decoding the plurality of codewords. The apparatus 302comprises the one or more decoding blocks associated with a clock 308having a clock cycle. Moreover, the apparatus 302is connected to a plurality of parity matrices 310. The apparatus 302sends decoded bits of information to a de-scrambler 312, wherein the de-scrambler 312is connected to a user index 314. The de-scrambler 312sends the decoded bits of information tagged with user information to a distributer 316, which thereon sends the decoded bits of information to a plurality of transmitters 318 (318a, 318b, …, 318n) , respectively.

In accordance with an embodiment, the given decoding block is configured to receive the plurality of codewords at a given codeword rate, each of the codewords in the plurality of codewords having a codeword size, and wherein each of the decoding unit in the given decoding block is configured to decode a given codeword using a parity matrix, said parity matrix depending on the size of the given codeword and on the codeword rate. Herein, the given codeword rate depends on the plurality of receivers 304 (304a, 304b, …, 304n) Typically, the size of a codeword is calculated by adding the number of non-zero elements in the codeword. Herein, a parity matrix from the plurality of parity matrices 310is selected, based on the size of the codeword. This means that different codewords of different sizes require different parity matrices for decoding. Advantageously, such apparatus links a plurality of decoding blocks, which provides a higher data rate as compared to when the decoding blocks are utilized separately. Additionally, multiple codewords for different users having different codebooks within multiple links are being decoded at the full clock rate herein, beneficially providing faster decoding as compared to when a given parity matrix was not selected depending on the codeword size.

In accordance with an embodiment, C is equal to 1. As discussed in the example above, when C=1, the second codeword is provided to each decoding unit at every clock cycle. This means that a given codeword is being decoded at every clock cycle for a given decoding unit. Advantageously, decoding the given codeword at every clock cycle ensures that the plurality of codewords (having a plurality of codebooks) are being decoded at full clock rate, such that a processing capability of the given decoding unit is being utilized efficiently as compared to when the plurality of codewords are not decoded at every clock cycle.

FIG. 4 is a schematic diagram illustrating an apparatus 400for decoding a plurality of codewordsC0, C1, C2, …., Cn, for a plurality of users, having a decoding block 402, in accordance with an embodiment of the present disclosure. As shown in FIG. 4, the plurality of codewords C0, C1, C2, …., Cn progress through the plurality of

decoding units

0, 1, 2, 3, …, N-1, N. In decoding block 402, at time t1, a first codeword C0 is loaded at the first decoding unit. At time t2, a second codeword C1 is loaded at the first decoding unit, such that the first codeword C0 is loaded at a second decoding unit. At time t3, a third codeword C2 is loaded at the first decoding unit, such that the second codeword C1 is loaded at the second decoding unit and the first codeword C0 is loaded at the third decoding unit. At time t4, eighteen codewords C0, C1, C2, C3, C4, …, C17 are loaded at eighteen decoding units, such that the first codeword C0 is loaded at the first decoding unit, the second codeword C1 is loaded at the second decoding unit, and so forth, until an eighteenth codeword C17 is loaded at an eighteenth decoding unit. At time t5, once the plurality of decoding units are loaded with the plurality of codewords, the plurality of codewords are processed using the plurality of parity matrices. As shown in FIG. 3, the first codeword C0 is decoded and thereby exits the decoding block 402.

In accordance with another embodiment, the given decoding block is configured to receive in input the plurality of codewords at a given codeword rate, CW_rate, and wherein C depends on the number of decoding units N x M in the given decoding block, on the given codeword rate CW_rate, and on the clock cycle period, CLK. Herein, the number of decoding units are calculated by multiplying the number of decoding blocks M with the number of decoding units N in one decoding block. For example, if there are 10 decoding blocks having 80 decoding units in each decoding block, the number of decoding units is 10 x 80 = 800. Further, the codeword rate CW_rate refers to the rate at which codewords are being received at the apparatus 400for decoding. Moreover, the clock cycle period CLK refers to the time taken for one clock cycle to be completed. For example, if one clock cycle is f = 640MHz, the clock cycle period is 1/f = 1/640 = 0.64usec. Herein, the given decoding block is configured to receive in input each codeword, amongst the plurality of codewords, one after the other every C clock cycles, depending on the number of decoding units N x M, the given codeword rate CW_rate and the clock cycle period CLK. This means that C can be calculated dynamically depending on the above criterion. Advantageously, this allows the apparatus 400to dynamically save power since C is being adjusted.

In accordance with an embodiment, C is the first integer greater or equal to N x M /L, where L is the first integer greater or equal to N x M x CW_rate x CLK. Herein, C is dependent on the number of decoding units N x M, the given codeword rate CW_rate and the clock cycle period CLK. For example, if there are 10 decoding blocks having 80 decoding units in each decoding block, the number of decoding units is 10 x 80 = 800, the CW_rate is 14.3M CW/sec, and the CLK is approximately 70 ns; L can be calculated as 800 x 14.3 x 70 x 10 ⁹ = 0.000. Since L is an integer, L=1, such that C can be calculated by 10 x 80 /1 = 800. Advantageously, this allows the apparatus 400to work at the full clock rate while also dynamically saving power since C can be adjusted.

FIG. 5 is a schematic diagram illustrating an exemplary apparatus for decoding a plurality of codewords, in accordance with an embodiment of the present disclosure, aiming more particularly at saving power. As shown in FIG. 5, the exemplary apparatus 500for decoding a plurality of codewords comprises ten decoding blocks 502a, …, 502j, such that 502ais the first decoding block and 502jis the tenth decoding block. Additionally, each of the ten decoding blocks 502a, …, 502jcomprise eighty decoding units A0, A1, A2, …, A79, ….., J0, J1, J2, …. J79. Optionally, when C is dependent on the number of decoding units N x M, the given codeword rate CW_rate and the clock cycle period CLK, G decoding units from the plurality of decoding units are unified as a super stage, wherein logic being utilized at the G decoding units are combined and assigned to a register. As shown in the figure, for eighty decoding units, G may be 40, such that every 40 decoding units are combined along with the logic being utilized therein, and assigned to the register X0, Y0, …, X9, Y9. Advantageously, such combining of the G decoding units provides much easier timing closure, and smaller usage of library cells during synthesis, such that area and power is saved, as compared to when the G decoding units were not unified as the super stage.

FIG. 6 is a flowchart of a method for decoding a plurality of codewords, in accordance with an embodiment of the present disclosure. As shown in FIG. 6, at step 602, a plurality of codewords are received in input into a decoding block associated with a clock having a clock cycle and comprising a plurality of decoding units arranged in serie, each of the decoding unit in the plurality of decoding units being configured to run a decoding stage. At step 604, the plurality of codewords are decoded, comprising running each of the decoding stages on each of the codewords of the plurality of codewords, wherein decoding the plurality of codewords comprises running a serie of M identical series of N decoding stages corresponding to a serie of M identical series of N decoding units forming a serie of N x M decoding units in the decoding block, with M > 1 and N >1, and wherein receiving the plurality of codewords in input into the decoding block comprises receiving each codeword amongst the plurality of codewords, one after the other every C clock cycles, with 0 < C < N x M. Since M>1 and N>1, the plurality of decoding units decode the plurality of codewords, such that each decoding unit decodes a first codeword. For example, if M=4 and N=5, there would be 4*5=20 decoding units, such that 20 first codewords are decoded. Additionally, a second codeword is provided as input to each decoding unit at every C clock cycle. Referring to the previous example, for 20 decoding units, C lies in a range of 1 to 19, since 0 < C < 20. Therefore, if C=1, the second codeword is provided to each decoding unit at every clock cycle, if C=2, the second codeword is provided to each decoding unit at every alternate clock cycle, and thereon.

Advantageously, the plurality of decoding units decode the plurality of codewords parallelly, such that at least 4 (2*2) codewords are decoded simultaneously. This assists the one or more decoding blocks with increased efficiency and a reduced time for processing the plurality of codewords. Moreover, a processing efficiency of a given decoding block is exponentially increased, reducing the requirement of excessive decoding blocks and saving area. Additionally, when the decoding is performed at a full clock speed, the plurality of codewords are decoded quickly, such that the clock speed may be lowered considerably to meet requisite requirements, saving energy.

In accordance with a first embodiment, the plurality of codewords is received by the decoding block at a given codeword rate, each of the codewords of the plurality of codewords having a codeword size, and wherein running a decoding stage on a given codeword of the plurality of codewords comprises using a parity matrix, said parity matrix depending on the size of the given codeword and on the codeword rate. Advantageously, such method provides a higher data rate by decoding multiple codewords at the full clock rate herein, beneficially providing faster decoding as compared to when a given parity matrix was not selected depending on the codeword size.

In accordance with an embodiment, the plurality of codewords is received by the decoding block at a given codeword rate, CW_rate, and wherein C depends on the number of decoding units N x M in the given decoding block, on the given codeword rate CW_rate, and on the clock cycle period, CLK. Advantageously, this allows dynamic saving of power since C is being adjusted.

In accordance with an embodiment, C is the first integer greater or equal to N x M /L, where L is the first integer greater or equal to N x M x CW_rate x CLK. Advantageously, this allows decoding to be performed at the full clock rate while also dynamically saving power since C can be adjusted.

In accordance with a second embodiment, receiving the plurality of codewords in input into the decoding block comprises receiving multiple pluralities of codewords, each of the pluralities of codewords being received with a specific codeword rate, and wherein receiving the multiple pluralities of codewords in input into the decoding block comprises receiving in input, one after the other, and every C cycles, one codeword of each of the mutiple pluralities of codewords. Herein, multiple pluralities of codewords are being received as input into the decoding block, such that each plurality of codewords is received with the specific codeword rate. Advantageously, this allows multiple pluralities of codewords to get decoded simultaneously, providing a higher data rate since the multiple pluralities of codewords for different users having different codebooks within multiple links are decoded at the full clock rate herein, beneficially providing faster decoding as compared to when a given parity matrix was not selected depending on the codeword size.

In accordance with an embodiment, for decoding a given codeword having a given codeword size and belonging to one of the multiple pluralities of codewords, each decoding stage uses a parity matrix depending on the size of the given codeword and on the specific codeword rate corresponding to the said one of the pluralities of codewords. Advantageously, this provides a higher data rate by decoding multiple pluralities of codewords for different users having different codebooks within multiple links at the full clock rate herein, beneficially providing faster decoding as compared to when a given parity matrix was not selected depending on the codeword size.

In accordance with an embodiment, the method further comprises determining a given codeword rate, CW_rate, as being the sum of all specific codeword rates, and wherein C depends on the number of decoding units N x M in the given decoding block, on the given codeword rate CW_rate, and on the clock cycle period, CLK. Advantageously, this allows dynamic saving of power since C is being adjusted.

Modifications to embodiments of the present disclosure described in the foregoing are possible without departing from the scope of the present disclosure as defined by the accompanying claims. Expressions such as "including" , "comprising" , "incorporating" , "have" , "is" used to describe and claim the present disclosure are intended to be construed in a non-exclusive manner, namely allowing for items, components or elements not explicitly described also to be present. Reference to the singular is also to be construed to relate to the plural. The word "exemplary" is used herein to mean "serving as an example, instance or illustration" . Any embodiment described as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments and/or to exclude the incorporation of features from other embodiments. The word "optionally" is used herein to mean "is provided in some embodiments and not provided in other embodiments" . It is appreciated that certain features of the present disclosure, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the present disclosure, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable combination or as suitable in any other described embodiment of the disclosure.

Claims

An apparatus (100, 302, 400, 500) for decoding a plurality of codewords (C0-Cn) , comprising one or more decoding blocks (102a-102m, 402, 502a-502j) associated with a clock (308) having a clock cycle, each of the decoding blocks (102a-102m, 402, 502a-502j) being configured to receive in input a plurality of codewords (C0-Cn) and comprising a plurality of decoding units (104a-104n, 106a-106n, 108a-108n, 0-N, A0-A79, J0-J79) arranged in serie, each of the decoding unit in the plurality of decoding units (104a-104n, 106a-106n, 108a-108n) being configured to run a decoding stage, wherein the plurality of decoding units (104a-104n, 106a-106n, 108a-108n) , in a given one of the one or more decoding blocks (102a-102m, 402, 502a-502j) , comprises a serie of M identical series of N decoding units, with M > 1 and N >1, forming a serie of N x M decoding units, and the given decoding block (102a-102m, 402, 502a-502j) is configured to receive in input each codeword, amongst the plurality of codewords (C0-Cn) , one after the other every C clock cycles, with 0 < C < N x M.
An apparatus (100, 302, 400, 500) according to claim 1, wherein the given decoding block (102a-102m, 402, 502a-502j) is configured to receive the plurality of codewords (C0-Cn) at a given codeword rate, each of the codewords in the plurality of codewords (C0-Cn) having a codeword size, and wherein each of the decoding unit (104a-104n, 106a-106n, 108a-108n, 0-N, A0-A79, J0-J79) in the given decoding block (102a-102m, 402, 502a-502j) is configured to decode a given codeword using a parity matrix (310) , said parity matrix (310) depending on the size of the given codeword and on the codeword rate.
An apparatus (100, 302, 400, 500) according to any of claims 1 and 2, wherein C is equal to 1.
An apparatus (100, 302, 400, 500) according to any of claims 1 and 2, wherein the given decoding block (102a-102m, 402, 502a-502j) is configured to receive in input the plurality of codewords (C0-Cn) at a given codeword rate, CW_rate, and wherein C depends on the number of decoding units N x M in the given decoding block (102a-102m, 402, 502a-502j) , on the given codeword rate CW_rate, and on the clock cycle period, CLK.
An apparatus (100, 302, 400, 500) according to claim 4, wherein C is the first integer greater or equal to N x M /L, where L is the first integer greater or equal to N x M x CW_rate x CLK.
A method for decoding a plurality of codewords, comprising:

receiving the plurality of codewords (C0-Cn) in input into a decoding block (102a-102m, 402, 502a-502j) associated with a clock (308) having a clock cycle and comprising a plurality of decoding units (104a-104n, 106a-106n, 108a-108n, 0-N, A0-A79, J0-J79) arranged in serie, each of the decoding unit in the plurality of decoding units (104a-104n, 106a-106n, 108a-108n, 0-N, A0-A79, J0-J79) being configured to run a decoding stage,

decoding the plurality of codewords (C0-Cn) , comprising running each of the decoding stages on each of the codewords of the plurality of codewords (C0-Cn) ,

wherein decoding the plurality of codewords (C0-Cn) comprises running a serie of M identical series of N decoding stages corresponding to a serie of M identical series of N decoding units forming a serie of N x M decoding units in the decoding block (102a-102m, 402, 502a-502j) , with M > 1 and N >1, and wherein receiving the plurality of codewords (C0-Cn) in input into the decoding block (102a-102m, 402, 502a-502j) comprises receiving each codeword amongst the plurality of codewords (C0-Cn) , one after the other every C clock cycles, with 0 < C < N x M.
A method according to claim 6, wherein the plurality of codewords (C0-Cn) is received by the decoding block (102a-102m, 402, 502a-502j) at a given codeword rate, each of the codewords of the plurality of codewords (C0-Cn) having a codeword size, and wherein running a decoding stage on a given codeword of the plurality of codewords (C0-Cn) comprises using a parity matrix (310) , said parity matrix (310) depending on the size of the given codeword and on the codeword rate.
A method according to any of claims 6 and 7, wherein the plurality of codewords (C0-Cn) is received by the decoding block (102a-102m, 402, 502a-502j) at a given codeword rate, CW_rate, and wherein C depends on the number of decoding units N x M in the given decoding block (102a-102m, 402, 502a-502j) , on the given codeword rate CW_rate, and on the clock cycle period, CLK.
A method according to claim 8, wherein C is the first integer greater or equal to N x M /L, where L is the first integer greater or equal to N x M x CW_rate x CLK.
A method according to claim 6, wherein receiving the plurality of codewords (C0-Cn) in input into the decoding block (102a-102m, 402, 502a-502j) comprises receiving multiple pluralities of codewords, each of the pluralities of codewords (C0-Cn) being received with a specific codeword rate, and wherein receiving the multiple pluralities of codewords in input into the decoding block (102a-102m, 402, 502a-502j) comprises receiving in input, one after the other, and every C cycles, one codeword of each of the mutiple pluralities of codewords.
A method according to claim 10, wherein, for decoding a given codeword having a given codeword size and belonging to one of the multiple pluralities of codewords, each decoding stage uses a parity matrix (310) depending on the size of the given codeword and on the specific codeword rate corresponding to the said one of the pluralities of codewords (C0-Cn) .
A method according to any of claims 10 and 11, wherein the method further comprises determining a given codeword rate, CW_rate, as being the sum of all specific codeword rates, and wherein C depends on the number of decoding units N x M in the given decoding block (102a-102m, 402, 502a-502j) , on the given codeword rate CW_rate, and on the clock cycle period, CLK.
A method according to claim 12, wherein C is the first integer greater or equal to N x M /L, where L is the first integer greater or equal to N x M x CW_rate x CLK.