WO2023098405A1 - 一种存储系统、数据处理方法及装置 - Google Patents

一种存储系统、数据处理方法及装置 Download PDF

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Publication number
WO2023098405A1
WO2023098405A1 PCT/CN2022/130150 CN2022130150W WO2023098405A1 WO 2023098405 A1 WO2023098405 A1 WO 2023098405A1 CN 2022130150 W CN2022130150 W CN 2022130150W WO 2023098405 A1 WO2023098405 A1 WO 2023098405A1
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Prior art keywords
data
controller
memory
cache
interface device
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PCT/CN2022/130150
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English (en)
French (fr)
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冯锐
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华为技术有限公司
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Publication of WO2023098405A1 publication Critical patent/WO2023098405A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns

Definitions

  • the present application relates to the field of computer technology, and in particular to a storage system, data processing method and device.
  • the dual-control storage system includes at least one dual-control unit, and each dual-control unit includes at least two controllers sharing storage resources.
  • FIG. 1 exemplarily shows a dual-control storage system.
  • the dual control unit may include a first controller and a second controller, and the first controller and the second controller share at least one memory.
  • the first controller may write data into the shared memory according to the write request sent by the application server. Once the first controller fails, the second controller can query the data written by the first controller in the shared memory, so as to ensure the availability of the data written by the first controller.
  • the controller Since the memory access latency of the cache is usually much smaller than that of the external memory, the controller generally uses its own cache to asynchronously store data in the shared memory.
  • the update data of the local cache of the first controller needs to be synchronized to the cache of the second controller in real time, In this way, the second controller can query the data in its own cache and shared memory, and return the query result to the application server.
  • the synchronization process needs to transmit redundant data across controller nodes in the storage system, which wastes transmission resources and storage resources of the storage system.
  • the present application provides a storage system, data processing method and device, which are used to improve the efficiency and reliability of data services without redundant data transmission across controller nodes.
  • the present application provides a storage system
  • the storage system includes a first controller and a second controller, and the first controller and the second controller respectively pass a shared interface device provided with a cache communicate with at least one memory.
  • the first controller is configured to send a write instruction to the shared interface device.
  • the shared interface device is configured to temporarily store in the cache the first data to be written indicated by the write instruction, and is also used to asynchronously write the first data temporarily stored in the cache into the at least one The first memory in memory.
  • the first memory may include one or more memories.
  • the first data may be all or a part of the writing instruction indicated to be written.
  • the present application does not limit the manner in which the shared interface device stores other data other than the first data indicated by the write instruction.
  • the shared interface device may synchronously write the other data indicated by the write instruction into the first memory or at least one memory other than the first memory.
  • the second controller is configured to send a write instruction indicating to write the third data to the shared interface device.
  • the shared interface device is further configured to temporarily store the third data in the cache, and is also used to asynchronously write the third data temporarily stored in the cache into one or more of the at least one memory. Multiple memories, for example, a shared interface device may asynchronously write the third data into the first memory.
  • the third data may be all or a part of the write instruction instruction.
  • the present application does not limit the way the shared interface device stores data other than the third data indicated by the write instruction.
  • the shared interface device may synchronously write the other data indicated by the write instruction into the first memory or at least one memory other than the first memory.
  • the first controller and the second controller can jointly use the cache of the shared interface device to asynchronously write data to the first memory connected to the shared interface device, which is conducive to improving the utilization rate of the cache resource of the shared interface device and the memory resource connected to it. .
  • the second controller is configured to send a read instruction to the shared interface device after the first controller fails, the read instruction indicates to query second data, and the second The data may be all or part of the first data.
  • the shared interface device is further configured to acquire all or a part of the second data from the cache and provide them to the second controller according to the read instruction. If the shared interface device obtains a part of the second data in the cache, and other data in the second data is persisted or backed up, the shared interface device can query and obtain the second data in the connected storage (such as the first storage). other data.
  • the second data may be all or a part of the read instruction instruction to read.
  • the present application does not limit the manner in which the shared interface device acquires data other than the second data indicated by the read instruction.
  • the shared interface device may obtain the other data from one or more memories of at least one memory.
  • the shared interface device uses the cache to temporarily store the first data for the first controller, so as to asynchronously store the first data
  • Writing to the first memory connected to itself is beneficial to reducing the storage delay of the first data and improving the efficiency of data services provided by the storage system.
  • the second controller does not need to mirror the data written in the cache by the first controller.
  • the shared interface device can provide the data written in the cache by the first controller. For the second controller, in this way, it is beneficial to ensure the availability of data in the cache without increasing the transmission of redundant data across nodes, and improve the reliability of data services provided by the storage system.
  • the cache includes a first partition and a second partition, the first partition is used to temporarily store data for the first controller, and the second partition is used to temporarily store data for the second controller data, where the shared interface device acquires all or part of the second data in the cache, including the first partition and the second partition.
  • the difference between the first partition and the second partition means that the corresponding storage spaces in the cache of the first partition and the second partition do not overlap, which is beneficial to reduce the conflict of shared interface devices writing data for different controllers in the cache and improve the storage system. Reliability of data services provided.
  • the query range for the shared interface device to query the second data may include the first partition and the second partition. It is beneficial for the second controller to obtain the data written in the cache for the first controller and the second controller.
  • the write instruction indicates to write the data into the first memory.
  • the shared interface device is specifically configured to temporarily store the first data in the first partition, and temporarily store the third data in the second partition.
  • the first data temporarily stored in the first partition and the third data temporarily stored in the second partition are continuously sent to the first memory.
  • the write instruction sent by the first controller may indicate to write the first data into the first memory
  • the write instruction sent by the second controller may indicate to write the third data into the first memory.
  • Continuously sending the data to be written into the same memory in the first partition and the second partition to the first memory is beneficial for the first memory to continuously execute the writing task of the first data and the second data, if the first data and the second data
  • the storage positions in the first memory are adjacent or even continuous, which is beneficial to reduce the change of the writing position of the first memory and improve the storage efficiency of the first memory.
  • the at least one memory further includes a second memory, and the memory access delay of the second memory is shorter than that of the first memory; the shared interface device is further configured to, after receiving the write instruction , synchronously backing up the first data to the second memory.
  • the shared interface device may acquire all or a part of the second data from the second memory according to the read instruction and provide it to the second controller.
  • the shared interface device can still query the data in the second storage, It is beneficial to improve the availability of data in the cache and improve the reliability of data services provided by the storage system.
  • the storage system further includes a third memory connected to the first controller, and the first controller is further configured to: back up the first data to the third memory, when the When an exception occurs in the cache, the data backed up in the third memory is forwarded to the fourth memory in the at least one memory through the shared interface device.
  • the shared interface device is further configured to: when an exception occurs in the cache, according to the read instruction, obtain all or a part of the second data from the fourth memory and provide it to the first Two controllers.
  • the fourth memory may be the first memory or the second memory or other memory connected to the shared interface device.
  • the shared interface device can still query the data in the cache in at least one memory, which is conducive to improving the availability of data in the cache and improving the data service provided by the storage system reliability.
  • the data includes service data and/or metadata of the service data, wherein the service data is the data requested to be written in the data write request received by the first controller.
  • the shared interface device is an interface card or a hard disk enclosure, wherein the interface card is set (for example, plugged into) the first controller or the second controller, and the hard disk enclosure uses for installing the at least one memory.
  • the shared interface device communicates with the first controller through the PCIE Express protocol or the Serial Attached Small Computer System Interface SAS protocol.
  • the shared interface device communicates with the second controller through a PCIE protocol or a SAS protocol.
  • each memory in the at least one memory has only a single port for communicating with the shared interface device, and there is no need to modify the ports of the memory, which is beneficial to saving costs.
  • the present application provides a data processing method, the method can be applied to a storage system, the storage system includes a first controller and a second controller, the first controller and the second controller Communicate with at least one memory through shared interface devices provided with buffer respectively.
  • the method may include: the first controller sends a write instruction to the shared interface device.
  • the shared interface device temporarily stores in the cache the first data to be written indicated by the write instruction, and then asynchronously writes the first data temporarily stored in the cache to the first data in the at least one memory. memory.
  • the second controller may send a write instruction indicating to write the third data to the shared interface device, and the shared interface device may temporarily store the third data in the cache, and write the third data to the shared interface device.
  • the third data temporarily stored in the cache is asynchronously written to one or more memories of the at least one memory, for example, the third data may be asynchronously written to the first memory.
  • the second controller sends a read instruction to the shared interface device, the read instruction instructs to query second data, and the second data is the all or part of the first data.
  • the shared interface device acquires all or a part of the second data from the cache according to the read instruction and provides it to the second controller.
  • the cache includes a first partition and a second partition, the first partition is used to temporarily store data for the first controller, and the second partition is used to temporarily store data for the second controller data, where the shared interface device acquires all or part of the second data in the cache, including the first partition and the second partition.
  • temporarily storing the first data in the cache by the shared interface device includes: temporarily storing the first data in the first partition by the shared interface device.
  • Temporarily storing the third data in the cache by the shared interface device includes: temporarily storing the third data in the second partition by the shared interface device.
  • Asynchronously writing, by the shared interface device, the first data and the third data temporarily stored in the cache into the first memory may include: writing the first data temporarily stored in the first partition by the shared interface device
  • the data and the third data temporarily stored in the second partition are continuously sent to the first memory.
  • the write instruction sent by the first controller may indicate to write the first data into the first memory
  • the write instruction sent by the second controller may indicate to write the third data into the first memory.
  • the at least one memory further includes a second memory, and the memory access delay of the second memory is smaller than that of the first memory, and the method further includes: when the shared interface device receives the write After the instruction, synchronously back up the first data to the second memory; when an exception occurs in the cache, the shared interface device acquires the second data in the second memory according to the read instruction All or a part of and provided to the second controller.
  • the storage system further includes a third memory connected to the first controller, and the method further includes: the first controller backs up the first data to the third memory; when When the cache is abnormal, the first controller forwards the data backed up in the third memory to the fourth memory in the at least one memory through the shared interface device; when the shared interface device receives the After the read instruction, when an exception occurs in the cache, the shared interface device obtains all or part of the second data from the fourth memory according to the read instruction and provides it to the second controller device.
  • the data includes service data and/or metadata of the service data, where the service data is the data requested to be written in the data write request received by the first controller.
  • the shared interface device is an interface card or a hard disk enclosure, wherein the interface card is plugged into the first controller or the second controller, and the hard disk enclosure is used to install the at least a memory.
  • the shared interface device communicates with the first controller and/or the second controller through a PCIE protocol.
  • each of said at least one memory has only a single port for communicating with said shared interface device.
  • the technical effect of the method provided by the second aspect can refer to the aforementioned The technical effects obtained by the corresponding storage system will not be repeated here.
  • the present application provides a data processing method, the method can be applied to a shared interface device in a storage system, the storage system includes a first controller and a second controller, the first controller and the The second controller respectively communicates with at least one memory through the shared interface device provided with a cache, and the method includes: the shared interface device receives a write instruction sent by the first controller to write the first data Instruction: the shared interface device temporarily stores the first data in the cache, and then asynchronously writes the first data temporarily stored in the cache into the first memory in the at least one memory.
  • the method further includes: the shared interface device receiving a write command sent by the second controller indicating to write the third data; the shared interface device temporarily storing the first data in the cache Three data, and then asynchronously write the third data temporarily stored in the cache into one or more memories (such as the first memory) in the at least one memory.
  • the shared interface device receives a read instruction sent by the second controller, the read instruction indicates to query second data, and the second data is All or a part of the first data; the shared interface device obtains all or a part of the second data from the cache according to the read instruction and provides it to the second controller.
  • the cache includes a first partition and a second partition, the first partition is used to temporarily store data for the first controller, and the second partition is used to temporarily store data for the second controller data, where the shared interface device acquires all or part of the second data in the cache, including the first partition and the second partition.
  • temporarily storing the first data in the cache by the shared interface device includes: temporarily storing the first data in the first partition by the shared interface device.
  • Temporarily storing the third data in the cache by the shared interface device includes: temporarily storing the third data in the second partition by the shared interface device.
  • Asynchronously writing, by the shared interface device, the first data and the third data temporarily stored in the cache into the first memory may include: writing the first data temporarily stored in the first partition by the shared interface device
  • the data and the third data temporarily stored in the second partition are continuously sent to the first memory.
  • the write instruction sent by the first controller may indicate to write the first data into the first memory
  • the write instruction sent by the second controller may indicate to write the third data into the first memory.
  • the at least one memory further includes a second memory, and the memory access delay of the second memory is smaller than that of the first memory, and the method further includes: when the shared interface device receives the write After the instruction, synchronously back up the first data to the second memory; when an exception occurs in the cache, the shared interface device acquires the second data in the second memory according to the read instruction All or a part of and provided to the second controller.
  • the storage system further includes a third memory connected to the first controller, and the method further includes: after the shared interface device receives the read instruction, when an exception occurs in the cache The shared interface device obtains all or a part of the second data from the connected fourth memory according to the read instruction and provides it to the second controller. Wherein, all or a part of the second data in the fourth memory is forwarded by the first controller from the third memory to the fourth memory through the shared interface device after an exception occurs in the cache In, the data in the third memory includes the first data backed up by the first controller.
  • the data includes service data and/or metadata of the service data, where the service data is the data requested to be written in the data write request received by the first controller.
  • the shared interface device is an interface card or a hard disk enclosure, wherein the interface card is plugged into the first controller or the second controller, and the hard disk enclosure is used to install the at least a memory.
  • the shared interface device communicates with the first controller and/or the second controller through a PCIE protocol.
  • each of said at least one memory has only a single port for communicating with said shared interface device.
  • the technical effect of the method provided by the third aspect can refer to the technical effect obtained by the aforementioned corresponding storage system, which is not repeated here repeat.
  • the present application provides a shared interface device, and the shared interface device may be provided with a cache.
  • the shared interface device may include a receiving module, a storage module, and a query module; the receiving module is configured to receive a write instruction sent by the first controller indicating to write the first data, and the first controller and the second controller are respectively
  • the shared interface device communicates with at least one memory; the memory module is used to temporarily store the first data in its own cache, and is also used to asynchronously write the first data temporarily stored in the cache into the at least one The first memory in memory.
  • the receiving module is also used to receive a write instruction sent by the second controller indicating to write the third data; the storage module is used to temporarily store the first data in its own cache, and also use To asynchronously write the third data temporarily stored in the cache into one or more memories of the at least one memory, for example, the storage module may asynchronously write the third data into the first memory.
  • the receiving module is further configured to receive a read instruction sent by the second controller after the first controller fails, the read instruction indicates to query the second data, and the second The data is all or a part of the first data; the query module is configured to obtain all or a part of the second data in the cache according to the read instruction and provide it to the second control device.
  • the cache includes a first partition and a second partition, the first partition is used to temporarily store data for the first controller, and the second partition is used to temporarily store data for the second controller data, the query module acquires all or part of the second data in the cache including the first partition and the second partition.
  • the storage module is specifically configured to: temporarily store the first data in the first partition, temporarily store the third data in the second partition, and store the temporarily stored data in the first partition
  • the first data and the third data temporarily stored in the second partition are continuously sent to the first memory.
  • the write instruction sent by the first controller may indicate to write the first data into the first memory
  • the write instruction sent by the second controller may indicate to write the third data into the first memory.
  • the at least one memory further includes a second memory, the memory access delay of the second memory is shorter than that of the first memory, and the memory module is further configured to: after receiving the write instruction, synchronously backing up the first data to the second memory; when an exception occurs in the cache, according to the read instruction, obtain all or part of the second data in the second memory and provide it to the Describe the second controller.
  • the storage system further includes a third memory connected to the first controller, and the query module is further configured to: after the receiving module receives the read instruction, when the cache appears Abnormally, according to the read instruction, obtain all or part of the second data from the connected fourth memory and provide it to the second controller.
  • all or a part of the second data in the fourth memory is forwarded by the first controller from the third memory to the fourth memory through the shared interface device after an exception occurs in the cache
  • the data in the third memory includes the first data backed up by the first controller.
  • the data includes service data and/or metadata of the service data, where the service data is the data requested to be written in the data write request received by the first controller.
  • the shared interface device is an interface card or a hard disk enclosure, wherein the interface card is plugged into the first controller or the second controller, and the hard disk enclosure is used to install the at least a memory.
  • the shared interface device communicates with the first controller and/or the second controller through a PCIE protocol.
  • each of said at least one memory has only a single port for communicating with said shared interface device.
  • the shared interface device provided by the fourth aspect can have the function of the shared interface device in the storage system provided by the first aspect, so the technical effect of the shared interface device provided by the fourth aspect can refer to the technology obtained by the corresponding shared interface device mentioned above effects, which will not be repeated here.
  • the present application provides a computing device, the first controller and the second controller respectively communicate with at least one memory through the computing device, the computing device includes a memory and a processor, and the memory includes a cache
  • the processor executes the computer instructions stored in the memory, so that the computing device executes the method described in any possible implementation manner of the third aspect.
  • the computing device is an interface card or a hard disk enclosure, wherein the interface card is plugged into the first controller or the second controller, and the hard disk enclosure is used to install the at least one memory.
  • the computing device communicates with the first controller and/or the second controller through a PCIE protocol.
  • the present application provides a computer-readable storage medium, including instructions, which, when run on a computing device, cause the computing device to execute the method described in any possible implementation manner in the third aspect.
  • the eleventh aspect of the present application provides a computer program product.
  • the program code contained in the computer program product is executed by a computer device, the method described in any possible implementation manner of the third aspect of the present application can be implemented.
  • each device provided by this application can be used to execute the method steps performed by the shared interface device in the aforementioned storage system, the technical effects obtained by each device of this application can refer to the technical effects obtained by the aforementioned storage system, and will not be repeated here repeat.
  • the first controller and the second controller involved in the claims of the present application and the summary of the invention may be, for example, any two different controllers of the storage node in the specific implementation manners of the present application.
  • the first controller may be the control controller a
  • the second controller may be controller b
  • the first controller may be controller b
  • the second controller may be controller a.
  • the shared interface device involved in the claims of the present application and the summary of the invention may be, for example, any one of the storage nodes in the specific embodiments of the present application connected to at least two shared interface devices of the controllers, for example, the shared interface device may be a shared interface Device a or shared interface device b. Taking the shared interface device as shared interface device a as an example, the shared interface device may specifically be interface card a or hard disk enclosure a.
  • the at least one memory involved in the claims of the present application and the summary of the invention can be, for example, the at least one memory connected to the shared interface device a or the shared interface device b in the specific implementation manner of the present application, taking the shared interface device as the interface card a as an example , the at least one memory may include a memory a1, a memory a2, and a memory a3.
  • the first memory involved in the claims of the present application and the summary of the invention can be, for example, any one or more memories connected to the shared interface device a or the shared interface device b in the specific implementation manner of the present application, and the shared interface device is used as an interface card a as an example, the first storage may include storage a2.
  • the input instruction can be, for example, the write instruction 1 or the write instruction 1-1 mentioned in the specific embodiment of the application
  • the write instruction sent by the second controller can be, for example, the write instruction mentioned in the specific embodiment of the application. 2 or write instruction 2-2.
  • the first controller and the second controller are respectively the controller a and the controller b mentioned in the specific embodiments of the present application
  • the data may be, for example, the target data 1 and target data 2 mentioned in the specific embodiments of the present application, respectively.
  • the read instruction involved in the claims of the present application and the summary of the invention can be, for example, the read instruction 1 or the read instruction 1-1 or the read instruction 2 or the read instruction 2-1 mentioned in the detailed description of the present application .
  • the second data involved in the claims of the present application and the summary of the invention may be, for example, the target data 3 or the target data 4 mentioned in the detailed description of the present application.
  • target data 3 or target data 4 may be all or part of target data 1
  • target data 3 or target data 4 may be all or part of target data 2 .
  • the third memory involved in the claims of the present application and the summary of the invention may, for example, include the memory connected to the controller a in the specific embodiment of the present application c1.
  • the third memory involved in the claims of the present application and the summary of the invention may, for example, include the memory connected to the controller b in the specific embodiment of the present application c2.
  • the second memory involved in the claims and summary of the invention of the present application may, for example, include the memory a1 in the specific embodiment of the present application.
  • the first partition and the second partition can be, for example, the partitions in the cache of the interface card a, respectively. 1 and partition 2.
  • Fig. 1 schematically shows the structure of an existing storage system
  • FIG. 2 exemplarily shows a possible system architecture applicable to the embodiment of the present application
  • Figure 3-1, Figure 3-2, and Figure 3-3 respectively illustrate a possible structure of a storage node in the storage system of this application;
  • FIG. 4 exemplarily shows a possible data processing method performed by the storage node of the present application
  • FIG. 5 exemplarily shows a process in which the interface card a persists the data in the cache to the memory
  • Fig. 6, Fig. 7 and Fig. 8 respectively illustrate another possible data processing method executed by the storage node of the present application
  • FIG. 9 exemplarily shows a possible structure of the shared interface device of the present application.
  • Embodiments of the present application provide a storage system, a data processing method, and a device.
  • the system architecture applicable to the embodiment of the present application is firstly introduced below with reference to FIG. 2 .
  • FIG. 2 exemplarily shows a system architecture applicable to this embodiment of the present application.
  • the system architecture corresponding to FIG. 2 includes a storage system and at least one application server, and the application server and the storage system may be connected through a communication network.
  • the storage system may include a storage node, and a storage control unit and one or more memories are arranged in the storage node.
  • the storage may be a hard disk drive (hard disk drive, HDD), a solid state drive (solid state drive, SSD), a storage class memory (storage class memory, SCM) or other types of storage disks.
  • the storage may be a storage server, or other types of computing devices for providing storage services.
  • FIG. 2 is only an exemplary illustration but does not limit the applicable system architecture of this embodiment of the present application.
  • the system architecture corresponding to FIG. 2 may include more or fewer application servers or storage nodes.
  • the embodiments of the present application may be applied to a centralized storage system or a distributed storage system.
  • the system architecture applicable to this embodiment of the present application may include one or more storage nodes such as shown in FIG. 2 .
  • the storage nodes shown in FIG. 2 may be understood as storage arrays or storage servers.
  • the embodiment of the present application does not limit each storage node in the distributed storage system to be the storage node shown in FIG. 2 .
  • the storage control unit of the storage node shown in FIG. 2 may include at least two controllers. Taking two controllers in the storage control unit as an example, the storage node shown in Figure 2 can be specifically shown in Figure 3-1.
  • the storage node may include a controller a and a controller b.
  • the controller a and the controller b may be understood as controllers in a storage array, or controllers in a storage server.
  • the storage node may also include a shared interface device a and a shared interface device b. Wherein, the shared interface device a and the shared interface device b are respectively used to connect at least one memory.
  • the storage connected to the shared interface device a is called storage a
  • the storage connected to the shared interface device b is called storage b.
  • the memory a and the memory b can be understood as the memory in at least one memory shown in FIG. 2 .
  • the controller a and the controller b can communicate with at least one memory a under the shared interface device a through the shared interface device a, and the controller a and the controller b can communicate with at least one memory b under the shared interface device b through the shared interface device b communication.
  • shared interface device a and shared interface device b may be provided with caches.
  • the controller a and the controller b may be respectively connected to the shared interface device a, so as to jointly access the cache in the shared interface device a and the connected memory a.
  • the controller a and the controller b may also be respectively connected to the shared interface device b, so as to jointly access the cache in the shared interface device b and the connected memory b.
  • the cache in shared interface device a may implement power conservation through controller a and/or controller b, and the cache in shared interface device b may implement power conservation through controller a and/or controller b.
  • the cache in shared interface device a can be powered by controller a
  • the cache in shared interface device b can be powered by controller b.
  • the controller a fails, the cache in the shared interface device a and the cache in the shared interface device b can realize power conservation through the controller b.
  • Figure 3-1 exemplifies but does not limit the structure of a storage node.
  • the storage node corresponding to FIG. 3-1 may include more controllers, may include more or less shared interface devices, and may include more or less storage a or storage b.
  • the storage node corresponding to FIG. 3-1 may not include shared interface device b and storage b under shared interface device b.
  • the shared interface device a or shared interface device b shown in FIG. 3-1 is used to perform at least one of the following operations on the data between the controller and the memory: cache, process and transfer. Among them, "transit" may refer to transparent transmission or protocol format conversion.
  • Figure 3-2 and Figure 3-3 respectively illustrate the possible structure of the storage node corresponding to Figure 3-1. The following describes two different types of shared interfaces in combination with the storage nodes shown in Figure 3-2 and Figure 3-3. equipment.
  • the shared interface device is an interface card
  • shared interface device a may be interface card a connected to controller a
  • shared interface device b may be interface card b connected to controller b
  • the shared interface device a is connected to the controller a in the form of a plug.
  • the interface card a may be connected to a peripheral component interconnect standard (peripheral component interconnect, PCI) transfer device of the controller a.
  • PCI peripheral component interconnect
  • the shared interface device b can be connected to the controller b in the form of plugging, for example, the interface card b can be connected to the PCIE conversion device of the controller b.
  • controller a and controller b may respectively include a processor, a cache, and a switching device, and interface card a and interface card b may respectively include a processor, a cache, and multiple ports.
  • the processor may be composed of one or more general-purpose processors, such as a central processing unit (central processing unit, CPU), or a combination of a CPU and a hardware chip.
  • the aforementioned hardware chip may be an application-specific integrated circuit (application-specific integrated circuit, ASIC), a programmable logic device (programmable logic device, PLD) or a combination thereof.
  • ASIC application-specific integrated circuit
  • PLD programmable logic device
  • the above-mentioned PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), a general array logic (generic array logic, GAL) or any combination thereof.
  • Figure 3-2 takes the adapter device in controller a or controller b as an example of a PCIE adapter device, which can be other types of adapter devices, such as extended industry standard architecture (extended industry standard architecture, EISA) switching equipment, etc.
  • the switching device can also be called a bus, which can include an address bus, a data bus, a control bus, and the like.
  • the cache may include volatile memory, such as random access memory (RAM).
  • Cache can also include non-volatile memory (non-volatile memory), such as read-only memory (read-only memory, ROM), flash memory (flash memory), hard disk (hard disk drive, HDD) or solid-state drive (solid state drive) -state drive, SSD); the cache can also include a combination of the above.
  • the PCIE transfer device may include multiple ports.
  • each square marked with a number represents a port.
  • the multiple ports in the PCIE conversion device may include port 11 , port 12 , port 13 and port 14 .
  • the multiple ports of interface card a and interface card b may include port 21 , port 22 and port 23 respectively.
  • the processor of controller a can access interface card a through port 11 and port 12 of controller a and port 21 of interface card a in order to realize the connection between controller a and interface Card a communication connection.
  • the processor of controller b can be accessed through port 11 and port 14 of controller b, port 14 and port 13 of controller a, and port 22 of interface card a in sequence interface card a, so as to realize the communication connection between controller b and interface card a.
  • the processor of controller b may sequentially access interface card b through port 11 and port 12 of controller b and port 21 of interface card b, so as to implement communication connection between controller b and interface card b.
  • the processor of controller a can access interface card b through port 11 and port 14 in controller a, port 14 and port 13 in controller b, and port 22 of interface card b in order to realize controller a and interface Card b is connected.
  • interface card a and interface card b can be connected upwardly to controller a and controller b respectively.
  • interface card a can also be connected downwardly to one or more memory a through ports
  • interface card b can also be It is connected to one or more storage b downwards through the port.
  • interface card a can be connected to port 31 of hard disk enclosure a through port 23, and then access storage a1, storage a2, and storage a3 installed in hard disk enclosure a.
  • Interface card b can connect to hard disk enclosure a through port 23.
  • b is connected, and then accesses storage b1, storage b2 and storage b3 in hard disk enclosure b.
  • each of the memory a1, the memory a2 and the memory a3 can be understood as a memory a
  • each of the memory b1, the memory b2 and the memory b3 can be understood as a memory b.
  • interface card a and/or interface card b may be a serial attached SCSI (serial attached SCSI, SAS) card or an independent redundant disk array (redundant array of independent disk, RAID) card, wherein, SCSI is a small computer Abbreviation for smallcomputer system interface.
  • the connection between the interface card a and the controller a can be based on the peripheral component interconnect express (PCIE) protocol, and the connection between the interface card a and the storage a
  • PCIE peripheral component interconnect express
  • the connection can be based on SAS protocol or Fiber Channel (Fibre Channel, FC) protocol or Gigabit Ethernet (Gigabit Ethernet, GE) protocol, etc.
  • the connection between the interface card b and the controller b may be based on the PCIE protocol
  • the connection between the interface card b and the storage b may be based on the SAS protocol, the FC protocol, or the GE protocol.
  • the controller a and the controller b can not only share the memory a under the interface card a, but also share the cache in the interface card a by being respectively connected to the interface card a.
  • the controller a and the controller b can not only share the memory b under the interface card b, but also share the cache in the interface card b by being connected to the interface card b.
  • controller a and controller b only need one port of an interface card (such as interface card a or interface card b), and can share the memory under the interface card, which is conducive to saving the ports of the interface card resources, which is beneficial for the interface card to connect more memories and expand the storage resources shared by the controller a and the controller b.
  • the memory connected to the interface card can be provided with only one port for connecting the interface card, and can communicate with the controller a and the controller b respectively, without port modification of the memory, which is beneficial to cost saving.
  • the hard disk enclosure and the storage under the hard disk enclosure in Figure 3-2 can be understood as a single storage. The hard disk enclosure can communicate with controller a and controller b respectively only by setting a port connected to the interface card. Retrofit the ports of the hard disk enclosure.
  • Figure 3-2 uses the communication between the interface card and the storage disk through the hard disk enclosure as an example without limitation.
  • the interface card can be directly connected to a single-port hard disk.
  • the interface card may communicate with other types of computing devices for providing storage services, such as storage servers.
  • Figure 3-2 illustrates but does not limit the structure of a storage node.
  • the storage node corresponding to Figure 3-2 may include more controllers, may include more or fewer interface cards, may include more or fewer memories, for example, may not include interface card b and interface Memory under card b.
  • the shared interface device is a hard disk enclosure
  • shared interface device a can be hard disk enclosure a
  • shared interface device b can be hard disk enclosure b
  • one or more storage devices a connected to the hard disk enclosure may be installed in the hard disk enclosure a
  • one or more storage devices b connected to the hard disk enclosure may be installed in the hard disk enclosure b.
  • the one or more storages a may include at least one type of storage disk among HDD and SSD.
  • the one or more storage devices b may include at least one type of storage disk among HDD and SSD.
  • controller a and controller b may include processors and caches, respectively, and hard disk enclosures a and hard disk enclosures may include processors, caches, multiple ports, and hard disk installation mechanisms (for example, as shown in Figure 3-3 groove shown).
  • the multiple ports of disk enclosure a and disk enclosure b may include port 21 and port 22 respectively.
  • the storage (such as the storage a1, the storage a2 or the storage a3) is arranged behind the installation mechanism of the hard disk enclosure a, and can be connected to the processors of the hard disk enclosure a through communication.
  • the storage (such as the storage b1, the storage b2 or the storage b3) is arranged behind the installation mechanism of the hard disk enclosure b, and can communicate with the processors of the hard disk enclosure b respectively.
  • the controller a can access the hard disk enclosure a through ports 21 and 22 of the interface card a and port 31 of the hard disk enclosure a in sequence, so as to realize the communication connection between the controller a and the hard disk enclosure a.
  • Controller b can access hard disk enclosure a through port 21 and port 23 of interface card b and port 32 of hard disk enclosure a in sequence, so as to implement communication connection between controller b and hard disk enclosure a.
  • the controller b can access the hard disk enclosure b through the ports 21 and 22 of the interface card b and the port 31 of the hard disk enclosure b in sequence, so as to realize the communication connection between the controller b and the hard disk enclosure b.
  • Controller a can access hard disk enclosure b through port 21 and port 23 of interface card a and port 32 of hard disk enclosure b in sequence, so as to implement communication connection between controller a and hard disk enclosure b.
  • disk enclosure a and disk enclosure b can be connected upwards to controller a and controller b respectively.
  • disk enclosure a can also be connected downwards to one or more storage devices a through ports, and disk enclosure b can also be connected to It is connected to one or more storage b downwards through the port.
  • disk enclosure a can access storage a1, storage a2, and storage a3 installed in disk enclosure a
  • disk enclosure b can access storage b1, storage b2, and storage b3 installed in disk enclosure b.
  • each of the memory a1, the memory a2 and the memory a3 can be understood as a memory a
  • each of the memory b1, the memory b2 and the memory b3 can be understood as a memory b.
  • controller a and controller b can share not only storage a under disk enclosure a but also the cache in disk enclosure a by connecting to disk enclosure a respectively.
  • controller a and controller b can not only share storage b under disk enclosure b, but also share the cache in disk enclosure b by connecting controller a and controller b to disk enclosure b.
  • Disk enclosure a and disk enclosure b can be connected to controller a respectively.
  • the connection between disk enclosure a and disk enclosure b and controller a can be based on the SAS protocol, Fiber Channel (FC) protocol, or Gigabit Ethernet ( Gigabit Ethernet, GE) protocol, etc.
  • disk enclosure b and disk enclosure a are respectively connected to controller b, and the connection between disk enclosure b and controller b can be based on the SAS protocol, Fiber Channel (Fibre Channel, FC) protocol, or Gigabit Ethernet (Gigabit Ethernet, GE) agreement, etc.
  • Figure 3-3 illustrates but does not limit the structure of a storage node.
  • the storage node corresponding to Figure 3-3 may include more controllers, more or fewer interface cards, more or fewer hard disk enclosures, and more or fewer memories .
  • the storage node in Figure 3-3 may not include disk enclosure b and the storage in disk enclosure b.
  • interface card a or interface card b may be connected to more storage.
  • a line between ports may represent one or more connection links.
  • the connection link represented by the connection may include a PCIE bus for transmitting data signals and a control bus for transmitting control signals.
  • the control bus may, for example, transmit control signals, handshake information and status information of the controller a and the interface card a.
  • This control signal can comprise the starting signal that makes interface card a start working, and this starting signal can for example comprise the presence signal of interface card a (for judging whether interface card a has been inserted into the correct slot), power-on enabling signal, Clock signal and reset signal etc.
  • the handshake information can be used for port negotiation between the controller a and the interface card a to determine the transmission bandwidth and transmission rate of the transmission channel between the two.
  • connection link between controller a and controller b, for example, for transmitting heartbeat information to Monitor the other party's status.
  • connection links required for controller a and controller b to call shared interface devices are introduced.
  • shared interface devices such as shared interface device a and shared interface device b
  • the embodiment of the present application does not limit the calling mode of the controller in the storage node to the shared interface device.
  • the calling mode may be an active-standby mode or a dual-active mode.
  • each controller in the storage node has a different status for the shared interface device, and is divided into a master controller and a standby controller for the shared interface device.
  • controller a and controller b are the active controller and standby controller of shared interface device a respectively. Under normal working conditions, controller a can call shared interface device a to perform data storage and data query services, but controller b cannot call shared interface device a to perform data storage and data query services. When controller a fails, controller b can take over shared interface device a to call shared interface device a to execute data storage service and/or data query service, thereby ensuring the cache of shared interface device a and the availability of data in memory a.
  • the port 21 of the interface card a is in an active state, and the port 22 is in an inactive state, so that the interface card a can be called by the controller a, but cannot be called by the controller b.
  • controller a can notify controller b through a heartbeat signal or a power-off interrupt signal with controller b, and controller b can compete to be the master controller of interface card a.
  • Controller b can notify interface card a of the active/standby switchover event, make port 21 of interface card a enter the inactive state, stop calling for controller a, make port 22 of interface card a enter the active state, and start being called by controller b .
  • the controllers in the storage nodes have the same status for the shared interface devices.
  • the controller a and the controller b may call the shared interface device a or the shared interface device b alternately in time division.
  • controller b can call shared interface device a and/or shared interface device b to perform data query services, thereby ensuring that the data and data in the cache of shared interface device a and/or shared interface device b and Availability of data in attached storage.
  • the controller in the storage node can take over the corresponding shared interface device when the call condition for the shared interface device is met, so as to use the cache of the corresponding shared interface device and the memory connected to it to provide data storage and data query services.
  • the following describes the process of the controller in the storage node calling the shared interface device to provide data storage services and data query services.
  • controller a providing data storage services through interface card a.
  • FIG. 4 exemplarily shows the flow of the method for storing data by the controller a through the interface card a.
  • the structure other than the application server in Figure 4 can be, for example, the storage node shown in Figure 3-2. out of the PCIE transfer device in controller a.
  • a possible embodiment of the data processing method provided in this application may include the following steps S401-S404.
  • the application server sends a write request 1 to the controller a;
  • the application server may send a data write request 1 (referred to as write request 1 ) to the controller a, where the write request 1 is used to request to store service data 1 .
  • the storage system involved in this embodiment of the application can provide data storage services through software systems such as file systems, block storage systems, or object storage systems.
  • the business data requested by write request 1 can be files, data blocks, or data in the form of objects.
  • Step S401 is an optional step, and this embodiment of the present application does not limit that the write request 1 is sent by the application server.
  • the write request 1 may be sent by a client in the terminal, or by a software system adopted by the storage system.
  • the service data 1 may be user data or system data generated by the software system.
  • the embodiment of the present application does not limit the location where the software system is deployed.
  • the software system may be deployed in controller a or controller b or other controllers, or the software system may be deployed in an application server, or the software system The system is deployed in a separate server.
  • the controller a sends a write instruction 1 to the interface card a;
  • the controller a may send a write instruction 1 to the interface card a according to the write request 1 , where the write instruction 1 is used to instruct to store data 1 .
  • data 1 includes but not limited to business data 1 .
  • controller a may generate metadata 1 describing service data 1, and data 1 may include service data 1 and metadata 1 accordingly.
  • metadata 1 may describe the storage location of business data 1 in storage a2.
  • the storage location can be a logical address or a physical address.
  • the interface card a uses the cache and the memory a2 to store the data 1 indicated by the write instruction 1;
  • the interface card a After the interface card a receives the write instruction, it can use the cache and memory a2 to store the data 1 . Since controller a and controller b share the cache of interface card a, in order to reduce the conflict of controller a and controller b writing data to the cache of interface card a, optionally, the cache of interface card a can be divided into control
  • the write partition of controller a (referred to as partition 1) and the write partition of controller b (referred to as partition 2).
  • Partition 1 and partition 2 are two different storage spaces in the cache of interface card a, and the difference between partition 1 and partition 2 may mean that the storage space corresponding to partition 1 and the storage space corresponding to partition 2 do not overlap.
  • interface card a may use partition 1 and memory a2 in its own cache to store data 1.
  • the interface card a After receiving the write instruction 1, the interface card a can asynchronously write the target data 1 in the data 1 into the memory a2 through the cache.
  • the write instruction 1 may indicate a persistent address of the data to be written, and the persistent address may point to at least one memory under the interface card a.
  • the write instruction 1 indicates that the persistent address of the target data 1 points to the memory a2 as an example.
  • the persistent address may be a logical address or a physical address in the memory a2.
  • the persistent address may be a logical block addressing mode (logical block addressing, LBA).
  • Interface card a asynchronously writes target data 1 into memory a2 through the cache may refer to that interface card a temporarily stores target data 1 in the cache (for example, partition 1), and then writes target data 1 into memory a2, and, after writing target After the data 1 is written into the cache, before the target data 1 is written into the memory a2, the interface card a will send a success notification to the controller a.
  • the success notification is used to notify the controller a that the write command 1 has been completed and the target data has been stored 1.
  • the controller a may consider that the target data 1 has been persisted in the storage a2 according to the success notification.
  • target data 1 may be all data in data 1 .
  • the target data 1 may be part of the data in the data 1, and the interface card a may store other data in the data 1 other than the target data 1 in other storage methods.
  • interface card a can synchronously write the other data into memory a2.
  • Synchronously writing the other data into the memory a2 by the interface card a means that after the interface card a writes the other data into the memory a2, it will send a success notification to the controller a to notify the controller a that the other data has been stored.
  • the interface card a persists the target data 1 and other data in the memory a2 as an example.
  • the interface card a may store the data written by the write instruction 1 in multiple memories a, for example, Persist target data 1 in storage a2, and persist other data in storage a3.
  • the write instruction 1 may include one or more instructions, for example, the write instruction 1 may include a write instruction 1-1 indicating to write target data 1 and a write instruction 1 indicating to write other data -2.
  • the interface card a may determine the target data 1 according to the data type, for example, the target data 1 may be metadata 1, and other data may be service data 1. Or, optionally, the interface card a may determine the target data 1 according to the data length. For example, assuming that the data length of the write command 1-1 is less than the length threshold, and the data length of the write command 1-2 is less than the length threshold, the interface card a The data written indicated by the write instruction 1-1 may be persisted asynchronously through the cache, and the data written indicated by the write instruction 1-2 may be persisted synchronously. Since the data length of the metadata is generally small, and if the length of the service data 1 is also small, the target data 1 may include the metadata 1 and the service data 1 at the same time.
  • the write command 1 may indicate a storage mode
  • the interface card a may store data according to the storage mode indicated by the write command 1 .
  • write instruction 1-1 indicates asynchronous storage
  • write instruction 1-2 indicates synchronous storage.
  • Interface card a can asynchronously store the data written by write instruction 1-1 in memory a2 through its own cache, and write The input command 1-2 indicates that the written data is stored in the memory a2 synchronously.
  • the interface card a writes the target data 1 asynchronously into the memory a2 through the cache, and it is not limited that the interface card a fetches the target data 1 from the write command 1-1, and then only stores the target data 1 in the cache.
  • the interface card a can store the write instruction 1-1 in the cache, and after sending a successful notification to the controller a, send the write instruction 1-1 in the cache to the memory a2, and the memory a2 can read from Object data 1 is parsed and stored in instruction 1-1.
  • the interface card a synchronously writes other data into the memory a2, and it is not limited that the interface card a fetches the other data from the write command 1-2, and then only sends the other data to the memory a2.
  • the interface card a may send the write command 1-2 to the memory a2, and the memory a2 may parse and store the other data from the write command 1-2.
  • the communication protocol for example, PCIE protocol
  • the communication protocol for example, SAS protocol
  • interface card a Before the sent write command is sent to the memory a2, the format of the write command may be converted, for example, the write command 1 is converted from the PCIE protocol format to the SAS protocol format.
  • Steps S4031-S4033 shown in FIG. 4 exemplarily show a possible process for the interface card a to asynchronously write the target data 1 into the memory a2 through buffering.
  • a possible refinement step of step S403 may include:
  • the interface card a temporarily stores the target data 1 in the partition 1;
  • the interface card a may write the target data 1 indicated by the write command 1 into the partition 1.
  • the cache of interface card a may include partition 1 and partition 2, and S4031 takes interface card a writing target data 1 into partition 1 in its own cache as an example without limitation.
  • the write instruction 1 may also indicate the cache address of the target data 1 in the partition 1 .
  • the cache address can be a logical address or a physical address.
  • Interface card a may store target data 1 in partition 1 according to the cache address indicated by write instruction 1 .
  • the interface card a sends a success notification 1 to the controller a;
  • the interface card a may send a success notification to the controller a, notifying the controller a that the write command 1 has been completed and the target data 1 is successfully stored.
  • the interface card a writes the target data 1 in the partition 1 into the memory a2;
  • the interface card a may asynchronously write the first data temporarily stored in the cache into the memory connected to the interface card a. For example, after the interface card a notifies the controller a that the target data 1 has been successfully stored, it may write the target data 1 in the cache into the memory a2 to persist the target data 1 . Optionally, referring to FIG. 4 , the interface card a may store the target data 1 in the memory a2 through the hard disk enclosure a.
  • the interface card a may write the target data 1 into the memory a2 when the persistence condition is satisfied.
  • the persistence condition may be related to at least one of the following factors: the size of the available storage space of the cache, the total length of the data to be written into the memory a2 in the cache, and whether the memory a2 is free.
  • the interface card a may aggregate and send the target data 1 in the partition 1 and other data in the cache to the memory a2.
  • the other data may include data indicated by other write instructions other than the write instruction 1 received in S402.
  • the embodiment of the present application does not limit the location of the other data in the cache.
  • this other data may include data in Partition 1 and/or Partition 2.
  • the partition 2 of the buffer memory of the interface card a also stores the target data 2 instructed to be written by the write instruction 2 sent by the controller b, and in addition, the partition 1 also stores the write data sent by the controller a.
  • the target data m indicated by the instruction m and the target data n indicated by the write instruction n, and the target data p indicated by the write instruction p sent by the controller b is also stored in the partition 2 .
  • m, n and p are positive integers greater than 2, and m, n and p are not equal to each other.
  • the interface card a may aggregate and send the target data 1 in the partition 1, the target data m and the target data 2 in the partition 2 to the memory a2.
  • the interface card a may aggregate and send the target data 1, the target data 2 and the target data m to the memory a2.
  • the persistent address of the target data in the cache may be the storage address indicated by the corresponding write instruction described above.
  • the interface card a may aggregate and send data with adjacent persistent addresses to the memory a2.
  • the persistent address (LBAn) of target data n and the persistent address (LBAp) of target data p also point to memory a2, however, since the storage space indicated by LBA1 is different from the storage space indicated by LBA2 and LBAm The spaces are adjacent, but the storage space indicated by LBA1 is not adjacent to the storage space indicated by LBAn or LBAp. Therefore, the interface card a may not aggregate and send the target data 1 and target data n or target data p to the memory a2.
  • the interface card a aggregates the target data 1, target data 2 and target data m to the memory a2 may mean that the interface card a sends the target data 1, target data 2 and target data m to the memory a2 through an instruction, optional , the interface card a can send the target data n and the target data p to the memory a2 through other instructions.
  • interface card a aggregates and sends target data 1, target data 2 and target data m to memory a2 may mean that interface card a sends target data 1, target data 2 and target data m to the memory through multiple consecutive instructions a2, no instruction for storing other data (such as object data n or object data p or data synchronously stored in the memory a2) is included between the plurality of instructions.
  • the interface card a aggregates and sends the target data 1, target data 2 and target data m to the memory a2, which can be understood as continuously sending the target data 1, target data 2 and target data m to the memory a2, which is beneficial to the continuous processing of the memory a2
  • the interface card a aggregates and sends the target data 1, target data 2 and target data m to the memory a2, which can be understood as continuously sending the target data 1, target data 2 and target data m to the memory a2, which is beneficial to the continuous processing of the memory a2
  • the interface card a aggregates and sends the target data 1, target data 2 and target data m to the memory a2, which can be understood as continuously sending the target data 1, target data 2 and target data m to the memory a2, which is beneficial to the continuous processing of the memory a2
  • the large jump of the write address of memory a2 can be reduced, saving The addressing time is long, thereby improving the storage efficiency of the memory a2.
  • interface card a or controller a may determine whether the persistence condition is satisfied.
  • the write instruction 1 may also instruct to aggregate and send the target data 1, target data 2 and target data m to the memory a2.
  • the controller a sends a write success response 1 to the application server
  • the controller a After the controller a successfully stores the data 1 through the interface card a, it can send a write success response 1 to the application server, and the write success response 1 can notify that the write request 1 has been completed and store the service data 1.
  • the controller a may determine that the service data 1 has been successfully stored.
  • the interface card a can use the cache to asynchronously write the data 1 into the memory a2, and, after writing the data 1 into the cache, before writing the data 1 into the memory a2, notify Controller a has stored data 1.
  • the controller a can send the write success response 1 to the application server before the data 1 is persisted to the storage a2, thereby helping to reduce the data perceived by the application server storage delay.
  • the interface card a can use the cache to asynchronously write the target data 1 (such as metadata 1) into the memory a2, after writing the target data 1 into the cache, after writing the target data 1 Before writing to the memory a2, notify the controller a that the target data 1 has been stored.
  • the interface card a can synchronously write other data (such as business data 1) in the data 1 other than the target data 1 into the memory a2, and after writing the other data into the memory a2, more specifically, successfully store After the other data, notify controller a that the other data has been stored.
  • the controller a may send a write success response 1 to the application server, and write all the data in the data 1 Compared with synchronous persistence to storage a2, it is beneficial to reduce the data storage delay perceived by the application server.
  • the method in this embodiment of the present application may further include S405.
  • the interface card a synchronously backs up the target data 1 to the memory a1;
  • the interface card a After receiving the write instruction 1, the interface card a can synchronously write the target data 1 to the memory a1. That is to say, after the interface card a writes the target data 1 into both the cache and the memory a1, before writing the target data 1 into the memory a2, step S4032 is executed. By backing up the data written in the cache to the storage a1 connected to the interface card a, even if the cache is abnormal, for example, the unpersisted data in the cache is lost, the interface card a can still query the data in the cache in the storage a1, It is beneficial to improve the availability of data in the cache and improve the reliability of data services provided by the storage system.
  • the access latency of the memory a1 may be smaller than the access latency of the memory a2.
  • the storage a1 may be an SSD, and the storage a2 may be an HDD.
  • FIG. 4 is only an example where the storage a1 and the storage a2 are connected to the interface card a through a hard disk enclosure.
  • the storage a1 and/or the storage a2 may be directly connected to the interface card a.
  • the method in this embodiment of the present application may further include S406 and S407.
  • the controller a stores the target data 1 in the memory c1;
  • the controller a forwards the target data 1 to the memory a2 through the interface card a.
  • the storage system further includes a memory c1 connected to the controller a, and the controller a is further configured to write the target data 1 into the memory c1 after receiving the write request.
  • the controller a double-writes the target data 1 to the buffer memory and the memory c1 of the interface card a, it will determine that the target data 1 is successfully stored.
  • the controller a may forward the data in the memory c1 (including the target data 1 ) to the memory under the interface card a through the interface card a, such as the memory a2 or other memory.
  • the interface card a can still query the data in the cache in at least one memory, which is conducive to improving the availability of data in the cache and improving the data provided by the storage system. Service reliability.
  • controller b providing data storage services through interface card a.
  • FIG. 6 exemplarily shows the flow of the method for storing data by the controller b through the interface card a.
  • the structure other than the application server in Figure 6 can be, for example, the storage node shown in Figure 3-2.
  • Figure 6 does not specifically show the interface card b and the memory under the interface card b, nor does it show the controller a and the PCIE transfer device in controller b.
  • Another possible embodiment of the data processing method provided in this application may include the following steps S601-S604.
  • the application server sends a write request 2 to the controller b;
  • Step S601 can be understood with reference to the previous step S401 , for example, the write request 2 can be understood with reference to the relevant description of the write request 1 .
  • This embodiment of the present application does not limit that the write request 1 and the write request 2 are from the same device, for example, the two may come from different application servers, or one is from the application server and the other is from a software system.
  • service data 1 corresponding to the write request 1 and the service data 2 corresponding to the write request 2 are the same type of data.
  • service data 1 may be user data
  • service data 2 may be system data.
  • the controller b sends the write instruction 2 to the interface card a;
  • the controller b may send a write instruction 2 to the interface card a according to the write request 2, and the write instruction 2 indicates to store data 2.
  • Step S602 can be understood with reference to step S402.
  • the write command 2 can be understood with reference to the relevant description of the write command 1, and the data 2 can be understood with reference to the previous data 1.
  • the interface card a uses the cache and the memory a3 to store the data 2 indicated by the write instruction 2;
  • the interface card a After receiving the write instruction 2, the interface card a can store the data 2 using the cache and the memory a3. In this embodiment of the present application, the difference between the memory a3 and the memory a2 is taken as an example without limitation. Optionally, the interface card a may use the cache and the memory a2 to store the data 2 .
  • Step S603 can be understood with reference to step S403.
  • the interface card b may asynchronously write the target data 2 in the data 2 into the memory a3 through the cache.
  • target data 2 may be all data in data 2 .
  • the target data 2 may be part of the data in the data 2
  • the interface card b may store other data in the data 2 other than the target data 2 in other storage methods.
  • interface card b can synchronously write the other data into memory a3.
  • the write instruction 2 may include one or more instructions, for example, the write instruction 2 may include a write instruction 2-1 indicating to write target data 2 and a write instruction 2-2 indicating to write other data.
  • a possible refinement step of step S603 may include:
  • the interface card a temporarily stores the target data 2 in the partition 2;
  • the interface card a sends a success notification 2 to the controller b;
  • the interface card a writes the target data 2 in the partition 2 into the memory a3;
  • Partition 2 can be understood by referring to the partition 2 mentioned in step S403, and S6031-S6033 can be understood by referring to the above S4031-S4033 respectively.
  • the controller b sends a write success response 2 to the application server;
  • the controller b After the controller b successfully stores the data 2 through the interface card a, it can send a write success response to the application server to complete the data storage service. Optionally, after the interface card a notifies the controller b that the data 2 has been stored, the controller b may determine that the data 2 has been successfully stored.
  • the interface card a can use the cache to asynchronously write data 2 into the storage a3, and after writing the data 2 into the cache and before writing the data 2 into the storage a3, notify Controller b has stored data 2.
  • the controller b can send a write success response 2 to the application server, thereby helping to reduce the data perceived by the application server storage delay.
  • the interface card a can use the cache to asynchronously write the target data 2 (such as metadata 2) into the memory a3, and after writing the target data 2 into the cache, the target data 2 Before writing to the memory a3, the controller b is notified that the target data 2 has been stored.
  • the interface card a can synchronously write data other than the target data 2 in the data 2 into the memory a3, and after writing the other data into the memory a3, more specifically, successfully store the data in the memory a3 After the other data, the controller b is notified that the other data has been stored.
  • the controller b can send a write success response 2 to the application server, and write all the data in the data 2 Compared with synchronous persistence to the storage a3, it is beneficial to reduce the data storage delay perceived by the application server.
  • the method in this embodiment of the present application may further include S605.
  • the interface card a synchronously writes the target data 2 into the memory a1;
  • the access latency of the memory a1 may be smaller than the access latency of the memory a2.
  • the storage a1 may be an SSD, and the storage a2 may be an HDD.
  • FIG. 6 is only an example where the storage a1 and the storage a2 are connected to the interface card a through a hard disk enclosure.
  • the storage a1 and/or the storage a2 may be directly connected to the interface card a.
  • the method in this embodiment of the present application may further include S606 and S607.
  • the controller b stores the target data 2 in the memory c;
  • the controller b forwards the target data 2 to the memory a3 through the interface card a.
  • the storage system further includes a memory c2 connected to the controller b, and the controller b is further configured to write the target data 2 into the memory c2 after receiving the write request.
  • the controller b can forward the data in the memory c2 (including the target data 2 ) to the memory under the interface card a through the interface card a, such as the memory a3 or other memory.
  • the interface card a can still query the data in the cache in at least one memory, which is conducive to improving the availability of data in the cache and improving the data provided by the storage system. Service reliability.
  • Controller b can provide data storage services through interface card b.
  • interface card b is plugged into controller b
  • the process of controller b providing data storage services through interface card b can refer to Figure 4.
  • the steps performed by controller b can be understood with reference to the steps performed by controller a in the embodiment corresponding to FIG. 4
  • the steps performed by interface card b can be understood with reference to the interface in the embodiment corresponding to FIG. 4
  • the steps performed by card a are understood.
  • Controller a can provide data storage services through interface card b.
  • interface card b Since interface card b is plugged into controller b, the process of controller a providing data storage services through interface card b can be referred to in Figure 6.
  • the steps executed by controller a can be understood with reference to the steps executed by controller b in the embodiment corresponding to FIG. 6
  • the steps executed by interface card b can be understood by referring to the interface in the embodiment corresponding to FIG. 6
  • the steps performed by card a are understood.
  • controller a providing data query services through interface card a.
  • FIG. 7 exemplarily shows the flow of the method for the controller a to query data through the interface card a.
  • the structure other than the application server in Figure 7 can be, for example, the storage node shown in Figure 3-2. out of the PCIE transfer device in controller a.
  • Another possible embodiment of the data processing method provided in this application may include the following steps S701-S704.
  • the application server sends a read request 1 to the controller a;
  • the application server may send a data read request 1 (read request 1 for short) to the controller a, and the read request 1 is used to request to read service data 3 .
  • the service data 3 may be the service data 1 introduced in S401 or the service data 2 introduced in S601. This embodiment of the present application exemplifies but does not limit that the read request 1 is sent by the application server. For other possible sources of the read request 1, refer to related content of S401.
  • the controller a sends a read instruction 1 to the interface card a;
  • the controller a may send a read instruction 1 to the interface card a, where the read instruction 1 is used to instruct the query data 3.
  • Data 3 may be business data 2, or include business data 2 and other data other than business data 2.
  • the interface card a queries the data 3 indicated by the read instruction 1 in the cache and the connected memory and provides it to the controller a;
  • the interface card a After the interface card a receives the read instruction 1, it can query the data 3, and the query scope can include the cache of the interface card a and the memory connected to the interface card a (such as the memory a1, the memory a2 and the memory a3).
  • interface card a may traverse the cache, storage a1, storage a2 and storage a3 to query data 3, and then interface card a may return one or more query results to controller a.
  • the interface card a may sequentially access the cache and the connected memory according to a certain order, and once the data 3 is queried, it will not continue to search. For example, interface card a may first search for data 3 in the cache, if found, return data 3 to controller a, and if not found, continue to search for data 3 in memory a1.
  • controller a can return the first data 3 found to controller a, and does not continue to search for data 3. If the controller a does not find the data 3 in all search ranges, the controller a may notify the controller that the query fails.
  • the data 3 may include target data 3, and the target data 3 may be all or part of the first target data.
  • the first target data may be the target data 1 mentioned in S403 or the target data 2 mentioned in S603. Since the interface card a temporarily stores the first target data through the cache, if the interface card a receives the read command 1 before the first target data is persisted, the interface card a can obtain the target data 3 in the cache according to the read command 1 all or part of it.
  • the cache of interface card a can be divided into partition 1 and partition 2 shown in FIG. 7 , partition 1 can be used to store data for controller a, and partition 2 can be used to store data for controller b.
  • the query scope for the interface card a to query the target data 3 in the cache may include partition 1 and partition 2 . If target data 3 is all or part of target data 1, interface card a can obtain all or part of target data 3 in partition 1; if target data 3 is all or part of target data 2, interface card a can obtain all or part of target data 2 in partition 2 Acquire all or part of the target data 3.
  • the solid line with arrows between the processor and partition 2 in Figure 7 can indicate that the processor finds the target data 3 in partition 2, and the dotted line with arrows between the processor and partition 1 or disk enclosure a can indicate The range in which the processor searches for the target data 3 includes partition 1 and disk enclosure a.
  • the interface card a can obtain the target data 3 in the connected memory (such as the memory a1 or the memory a2 or the memory a3) according to the read instruction 1 all or part of it.
  • step S405 or S605 assuming that the interface card a synchronously backs up the first target data to the memory a1, then, if the target data 3 in the cache has not been persisted or all of them have not been persisted yet, and the cache is abnormal, the interface card a can store the first target data in the memory Obtaining all or part of the target data 3 in a1 is beneficial to improving the availability of data in the cache.
  • controller a backs up target data 1 to storage c1 or controller b backs up target data 2 to storage c2, and after a cache exception occurs, controller a backs up the backed up
  • the data is transferred to the storage a2, or the controller b transfers the backed-up data to the storage a3, then, if the target data 3 in the cache has not been persisted or all of them have not been persisted yet, and the cache has an exception, the interface card a can store it in the storage a2 Or all or a part of the target data 3 is acquired in the memory a3, which is beneficial to improve the availability of the data in the cache.
  • the read instruction 1 may indicate the search range of the data 3, for example, indicate to query the data 3 in the cache of the interface card a and the memory under the hard disk enclosure a.
  • the embodiment of the present application does not limit the way that interface card a queries data other than the target data 3 in data 3.
  • interface card a can also query the other data in the cache and connected memory, or can only connect Query for this other data in the memory of . After the interface card a queries the other data, it may return the other data to the controller a, and if the other data is not found, the controller a may notify the controller that the query fails.
  • the read instruction 1 may include one or more instructions.
  • the read instruction 1 may include a read instruction 1-1 indicating the query target data 3 and a read instruction indicating other data other than the query target data 3.
  • Fetch instructions 1-2 may indicate to query the target data 3 in the cache of the interface card a and the memory under the interface card a, and the read instruction 1-2 indicates to query the other data in the memory under the interface card a.
  • the target data 3 as the metadata 3 describing the service data 3 as an example, assuming that the metadata 3 describes the storage location of the service data 3 in the storage a3, after the interface card a can obtain the metadata 3 from the cache, it can 3 Acquire the service data 3 in the storage a3.
  • the controller a sends the query result 1 to the application server.
  • the controller a If the controller a receives the data 3 returned by the interface card a, the controller a can obtain the service data 3 therefrom, and send the query result 1 carrying the service data 3 to the application server.
  • controller a may send query result 1 that does not carry business data 3 to the application server, indicating that the query result cannot Find business data 3.
  • the target data 3 is stored in the partition 2, it can be understood that the target data 3 is the data stored by the interface card a for the controller b.
  • interface card a can query the data of controller b in partition 2 for controller a, and send it to the application server by controller a, it is beneficial to ensure that the controller in the cache of interface card a b's data availability, which is conducive to improving the reliability of the storage system.
  • controller b providing data query services through interface card a.
  • FIG. 8 exemplarily shows the flow of the method for the controller b to query data through the interface card a.
  • the structure other than the application server in Figure 8 can be, for example, the storage node shown in Figure 3-2.
  • Figure 8 does not specifically show the interface card b and the memory under the interface card b, nor does it show the controller a and the PCIE transfer device in controller b.
  • Another possible embodiment of the data processing method provided in this application may include the following steps S801-S804.
  • the application server sends a read request 2 to the controller b;
  • Step S801 can be understood with reference to the previous step S701 , for example, read request 2 can be understood with reference to the relevant description of read request 1 .
  • This embodiment of the present application does not limit that the read request 1 and the read request 2 come from the same device, for example, the two may come from different application servers, or one is from the application server and the other is from a software system.
  • the controller b sends the read instruction 2 to the interface card a;
  • the controller b may send a read instruction 2 to the interface card a, where the read instruction 2 is used to instruct the query data 4.
  • Step S802 can be understood with reference to step S702. Different from S702, referring to the connection mode shown in Figure 3-2, since the interface card a is plugged into the controller a, the line through which the controller b sends the read command 2 to the interface card a is the same as that from the controller a to the interface card a The lines through which the read command 1 is sent are different.
  • the interface card a queries the data 4 indicated by the read instruction 2 in the cache and the connected memory and provides it to the controller b;
  • the interface card a After the interface card a receives the read instruction 2, it can query the data 4 indicated by the read instruction 2 in the cache and connected memories (such as the memory a1, the memory a2, and the memory a3).
  • Step S803 can be understood with reference to step S703.
  • data 4 may include target data 4, and target data 4 may be all or part of the first target data.
  • the first target data may be the target data 1 mentioned in S403 or the target data 2 mentioned in S603. Since the interface card a temporarily stores the first target data through the cache, if the interface card a receives the read command 2 before the first target data is persisted, the interface card a can acquire the target data 4 in the cache according to the read command 2 all or part of it.
  • the read instruction 2 may include one or more instructions, for example, the read instruction 2 may include a read instruction 2-1 indicating the query target data 4 and a read instruction 2-1 indicating other data other than the query target data 4. 2.
  • the read instruction 2-1 may indicate to query the target data 4 in the cache of the interface card a and the memory under the interface card a, and the read instruction 2-2 indicates to query the other data in the memory under the interface card a.
  • the interface card a can obtain the target data in the connected memory (such as memory a1 or memory a2 or memory a3) according to the read instruction 2 All or part of 4.
  • step S405 or S605 assuming that the interface card a synchronously backs up the first target data to the memory a1, then, if the target data 4 in the cache has not been persisted or all of them have not been persisted, and the cache is abnormal, the interface card a can Obtaining all or part of the target data 4 in the memory a1 is beneficial to improve the availability of data in the cache.
  • steps S406 and S407 or refer to steps S606 and S607, assuming that controller a backs up target data 1 to memory c1 or controller b backs up target data 2 to memory c2, and, after a cache exception, controller a will The backup data is transferred to the storage a2, or the controller b transfers the backup data to the storage a3, then, if the target data 4 in the cache has not been persisted or all of them have not been persisted yet, and the cache is abnormal, the interface card a can Obtaining all or a part of the target data 4 in the storage a2 or the storage a3 is beneficial to improve the availability of the data in the cache.
  • the controller b sends the query result 2 to the application server.
  • the controller b can obtain the service data 4 therefrom, and send a query result carrying the service data 4 to the application server.
  • controller b If controller b does not receive the data 4 returned by interface card a within a certain period of time, or interface card a feedbacks that the query fails, controller b can send a query result that does not carry business data 4 to the application server, and the query result indicates that it cannot be found to business data 4.
  • the target data 4 is stored in the partition 1, it can be understood that the target data 4 is the data stored by the interface card a for the controller a.
  • interface card a can query the data of controller a in partition 1 for controller b, and send it to the application server by controller b, it is beneficial to ensure that the controller in the cache of interface card a a's data availability, which is conducive to improving the reliability of the storage system.
  • Controller b can provide data query services through interface card b.
  • interface card b is plugged into controller b
  • the process of controller b providing data query services through interface card b can be referred to in Figure 7.
  • the steps executed by controller b can be understood with reference to the steps executed by controller a in the embodiment corresponding to FIG. 7
  • the steps executed by interface card b can be understood by referring to the interface in the embodiment corresponding to FIG. 7
  • the steps performed by card a are understood.
  • Controller a can provide data query services through interface card b.
  • interface card b Since interface card b is plugged into controller b, the process of controller a providing data storage services through interface card b can be referred to in Figure 8. Specifically, the steps performed by controller a can be understood with reference to the steps performed by controller b in the embodiment corresponding to FIG. 8 , and the steps performed by interface card b can be understood with reference to the interface in the embodiment corresponding to FIG. 8 The steps performed by card a are understood.
  • FIG. 9 is a schematic structural diagram of a shared interface device provided by an embodiment of the present application.
  • the shared interface device may be shared interface device a or shared interface device b in the method embodiment in FIG. 3-1 above, or , interface card a or interface card b in the method embodiment in FIG. 3-2 or FIG. 3-3 can execute the method and steps in which the corresponding shared interface device is the execution subject in the method in the corresponding embodiment.
  • the first controller and the second controller respectively communicate with at least one memory through a shared interface device.
  • the shared interface device 900 includes a receiving module 901 , a storage module 902 and a query module 903 .
  • the receiving module 901 is configured to receive the write instruction sent by the first controller.
  • the receiving module 901 is configured to receive the write instruction sent by the first controller.
  • the storage module 902 is configured to temporarily store the first data to be written as instructed by the write instruction in its own cache, and is also configured to asynchronously write the first data temporarily stored in the cache to the first memory in the at least one memory.
  • step S403 for example, specifically refer to the relevant description of step S4031 or step S4031 to step S4033, or refer to the relevant description of step S603, for example, specifically refer to the relevant description of step S6031 or S6031 to S6033, here No longer.
  • the receiving module 901 is also configured to receive a read instruction sent by the second controller after the first controller fails, the read instruction instructs to query the second data, and the second data is all or part of the first data.
  • the read instruction instructs to query the second data
  • the second data is all or part of the first data.
  • the query module 903 is configured to obtain all or part of the second data from the cache according to the read instruction and provide them to the second controller.
  • the query module 903 is configured to obtain all or part of the second data from the cache according to the read instruction and provide them to the second controller.
  • step S703 in FIG. 7 or refer to the relevant description of step S803 in FIG. 8 , which will not be repeated here.
  • the cache includes a first partition and a second partition, the first partition is used to temporarily store data for the first controller and not temporarily store data for the second controller, and the second partition is used to temporarily store data for the second controller
  • the stored data is not temporarily stored data for the first controller, and the query module 903 acquires all or part of the second data in the cache including the first partition and the second partition.
  • the write instruction indicates to write the first data into the first memory
  • the storage module 902 is specifically configured to temporarily store the first data in the first partition.
  • the storage module 902 is further configured to: continuously send the first data temporarily stored in the first partition and the second data temporarily stored in the second partition to the first memory, and the first data includes instructions written by the first controller into the first memory
  • the second data includes the data that the second controller instructs to write into the first memory.
  • At least one of the memories further includes a second memory, the access delay of the second memory is shorter than that of the first memory, and the storage module 902 is also used to: synchronously back up the first data to the second memory after receiving the write instruction.
  • Memory when an exception occurs in the cache, all or part of the second data is acquired from the second memory and provided to the second controller according to the read instruction.
  • the storage system further includes a third memory connected to the first controller
  • the query module 903 is further configured to: after the receiving module 901 receives the read instruction, when an exception occurs in the cache, according to the read instruction, the connected All or part of the second data is obtained from the fourth memory and provided to the second controller.
  • all or part of the second data in the fourth memory is forwarded by the first controller from the third memory to the fourth memory through the shared interface device after an exception occurs in the cache, and the data in the third memory includes the first The first data backed up by the controller.
  • the data includes service data and/or metadata of the service data, where the service data is the data requested to be written in the data write request received by the first controller.
  • the shared interface device is an interface card or a hard disk enclosure, where the interface card is plugged into the first controller or the second controller, and the hard disk enclosure is used to install at least one storage device.
  • the shared interface device communicates with the first controller and/or the second controller through the PCIE protocol.
  • the embodiment of the present application also provides a computing device, the first controller and the second controller respectively communicate with at least one memory through the computing device, the computing device includes a memory and a processor, the memory includes a cache, and the processor executes the computer instructions stored in the memory , so that the computing device executes the method performed by the shared interface device a or the shared interface device b described above.
  • the computing device may be, for example, interface card a or interface card b shown in FIG. 3-2 , or, for example, hard disk enclosure a or hard disk enclosure b shown in FIG. 3-3 .
  • the present application also provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, part or all of any one of the above-mentioned method embodiments can be realized. step.
  • An embodiment of the present invention also provides a computer program, the computer program includes instructions, and when the computer program is executed by a computer, the computer can execute some or all steps of any method for issuing regional resources.
  • the aforementioned computer-readable storage medium includes: U disk, mobile hard disk, magnetic disk, optical disk, RAM, SSD or non-volatile memory (non-volatile memory), etc., which can store program codes. non-transitory machine-readable media.
  • the disclosed device can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the above units is only a logical function division.
  • there may be other division methods for example, multiple units or components can be combined or integrated. to another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical or other forms.
  • the units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

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Abstract

公开了一种存储系统、数据处理方法及装置，用于在无需跨控制器节点传输冗余数据的情况下，提高数据服务的高效性和可靠性。该存储系统包括第一、第二两个控制器，两个控制器通过共享同一个接口卡与存储器通信。共享接口卡把来自第一控制器的数据存入自身缓存以及从自身缓存中的数据异步持久化于存储器中。对于第一控制器通过共享接口设备所存储的数据，在第一控制器发生故障后，可以被接口设备从自身缓存(或者存储器)中读出，并提供给第二控制器。

Description

一种存储系统、数据处理方法及装置 技术领域
本申请涉及计算机技术领域，尤其涉及一种存储系统、数据处理方法及装置。
背景技术
为了向用户提供可靠的数据服务，双控存储系统得到广泛应用。双控存储系统包括至少一个双控单元，每个双控单元包括共享存储资源的至少两个控制器。图1示例性示出一种双控存储系统。如图1所示，双控单元可以包括第一控制器和第二控制器，并且，第一控制器和第二控制器共享至少一个存储器。第一控制器可以根据应用服务器发送的写请求将数据写入共享的存储器。一旦第一控制器发生故障，第二控制器可以在共享的存储器中查询第一控制器写入的数据，以保证第一控制器写入数据的可用性。
由于缓存的访存时延通常远小于外接存储器的访存时延，因此，控制器一般使用自身的缓存将数据异步存储在共享的存储器中。在图1所示的双控单元中，为了保证在第一控制器发生故障后其缓存中数据的可用性，第一控制器对本地缓存的更新数据需要实时同步到第二控制器的缓存中，这样第二控制器可以在自身缓存和共享的存储器中查询到数据数据，并将查询结果返回应用服务器。该同步过程需要在存储系统中跨控制器节点传输冗余数据，浪费了存储系统的传输资源和存储资源。
发明内容
本申请提供一种存储系统、数据处理方法及装置，用于在无需跨控制器节点传输冗余数据的情况下，提高数据服务的高效性和可靠性。
第一方面，本申请提供了一种存储系统，所述存储系统包括第一控制器和第二控制器，所述第一控制器和所述第二控制器分别通过设置有缓存的共享接口设备与至少一个存储器通信。所述第一控制器用于向所述共享接口设备发送写入指令。所述共享接口设备，用于在所述缓存中暂存所述写入指令所指示写入的第一数据，还用于把所述缓存中暂存的第一数据异步写入所述至少一个存储器中的第一存储器。第一存储器可以包括一个或多个存储器。
第一数据可以为写入指令指示写入的全部或一部分。当第一数据为写入指令指示写入的一部分时，本申请不限定共享接口设备对写入指令指示写入的第一数据以外的其他数据的存储方式。可选的，共享接口设备可以将写入指令指示写入的该其他数据同步写入第一存储器或至少一个存储器中第一存储器以外的其他存储器。
可选的，所述第二控制器，用于向所述共享接口设备发送指示写入第三数据的写入指令。所述共享接口设备，还用于在所述缓存中暂存所述第三数据，还用于把所述缓存中暂存的所述第三数据异步写入所述至少一个存储器中的一个或多个存储器，例如，共享接口设备可以将第三数据异步写入所述第一存储器。
第三数据可以为写入指令指示写入的全部或一部分。当第三数据为写入指令指示写入的一部分时，本申请不限定共享接口设备对写入指令指示写入的第三数据以外的其他数据的存储方式。可选的，共享接口设备可以将写入指令指示写入的该其他数据同步写入第一存储器或至少一个存储器中第一存储器以外的其他存储器。
第一控制器和第二控制器可以共同使用共享接口设备的缓存向与共享接口设备相连的第一存储器异步写入数据，有利于提高共享接口设备的缓存资源和与其相连的存储器资源的利用率。
可选的，所述第二控制器，用于在所述第一控制器发生故障后，向所述共享接口设备发送读取指令，所述读取指令指示查询第二数据，所述第二数据可以为所述第一数据中的全部或一部分。所述共享接口设备，还用于根据所述读取指令，在所述缓存中获取所述第二数据的全部或者一部分并提供给所述第二控制器。若共享接口设备在缓存中获取第二数据的一部分，第二数据中的其他数据被持久化或备份，共享接口设备可以在相连的存储器(例如第一存储器)中查询并获取第二数据中的其他数据。
第二数据可以为读取指令指示读取的全部或一部分。当第二数据为读取指令指示读取的一部分时，本申请不限定共享接口设备对读取指令指示读取的第二数据以外的其他数据的获取方式。可选的，共享接口设备可以在至少一个存储器中的一个或多个存储器中获取该其他数据。
一方面，由于共享接口设备的缓存的访问时延小于与共享接口设备相连的存储器的访问时延，因此，共享接口设备使用缓存为第一控制器暂存第一数据，以将第一数据异步写入与自身相连的第一存储器，有利于减少第一数据的存储时延，提高存储系统提供的数据服务的高效性。另一方面，第二控制器无需对第一控制器写入该缓存的数据进行镜像备份，在第一控制器发生故障后，共享接口设备可以将缓存中为第一控制器写入的数据提供给第二控制器，这样，有利于在不增加跨节点传输冗余数据的前提下保证缓存中数据的可用性，提高存储系统提供的数据服务的可靠性。
可选的，所述缓存包括第一分区和第二分区，所述第一分区用于为所述第一控制器暂存数据，所述第二分区用于为所述第二控制器暂存数据，所述共享接口设备在所述缓存中获取所述第二数据的全部或者一部分的查询范围包括所述第一分区和所述第二分区。
第一分区和第二分区不同，是指第一分区和第二分区在缓存中对应的存储空间无交叠，有利于减少共享接口设备在缓存中为不同控制器写数据的冲突，提高存储系统提供的数据服务的可靠性。共享接口设备接收到读取指令后，可能难以确定第二数据在缓存中的位置，为了提高缓存中数据的可用性，共享接口设备查询第二数据的查询范围可以包括第一分区和第二分区，有利于为第二控制器获取到缓存中为第一控制器和第二控制器写入的数据。
可选的，所述写入指令指示将所述数据写入所述第一存储器。
可选的，所述共享接口设备具体用于：在所述第一分区暂存所述第一数据，在所述第二分区暂存所述第三数据。将所述第一分区中暂存的第一数据和所述第二分区中暂存的第三数据连续发送至所述第一存储器。可选的，第一控制器发送的写入指令可以指示将第一数据写入所述第一存储器，第二控制器发送的写入指令可以指示将第三数据写入所述第一存储器。
将第一分区和第二分区中待写入同一存储器的数据连续发送至第一存储器，有利于第一存储器连续执行第一数据和第二数据的写入任务，若第一数据和第二数据在第一存储器中的存储位置相邻甚至连续，有利于减少第一存储器写入位置的变化，提高第一存储器的存储效率。
可选的，所述至少一个存储器还包括第二存储器，所述第二存储器的访存时延小于所述第一存储器；所述共享接口设备还用于，在接收到所述写入指令后，将所述第一数据同步备份至所述第二存储器。可选的，当所述缓存出现异常，共享接口设备可以根据所述读取指令， 在所述第二存储器中获取所述第二数据的全部或一部分并提供给所述第二控制器。
通过将写入缓存的数据同步备份至与共享接口设备相连的第二存储器，即使缓存出现异常，例如，缓存丢失尚未持久化的数据，共享接口设备在第二存储器中仍然可以查询到该数据，有利于提高缓存中数据的可用性，提高存储系统提供的数据服务的可靠性。
可选的，所述存储系统还包括与所述第一控制器相连的第三存储器，所述第一控制器还用于：将所述第一数据备份至所述第三存储器，当所述缓存出现异常，将所述第三存储器中备份的数据通过所述共享接口设备转发至所述至少一个存储器中的第四存储器。可选的，所述共享接口设备还用于：当所述缓存出现异常，根据所述读取指令，在所述第四存储器中获取所述第二数据的全部或一部分并提供给所述第二控制器。第四存储器可以为第一存储器或第二存储器或与共享接口设备相连的其他存储器。
这样，即使缓存出现异常，例如，缓存丢失尚未持久化的数据，共享接口设备在至少一个存储器中仍然可以查询到缓存中的数据，有利于提高缓存中数据的可用性，提高存储系统提供的数据服务的可靠性。
可选的，所述数据包括业务数据和/或业务数据的元数据，其中，所述业务数据为所述第一控制器接收的数据写入请求所请求写入的数据。
可选的，所述共享接口设备为接口卡或硬盘框，其中，所述接口卡设置于(例如插接于)所述第一控制器或所述第二控制器中，所述硬盘框用于安装所述至少一个存储器。
可选的，所述共享接口设备与所述第一控制器通过快捷外设互连PCIE协议或串行连接小型计算机系统接口SAS协议通信。
可选的，所述共享接口设备与所述第二控制器通过快捷外设互连PCIE协议或SAS协议通信。
可选的，所述至少一个存储器中的每个存储器仅有单个与所述共享接口设备通信的端口，无需对存储器进行端口改造，有利于节约成本。
第二方面，本申请提供一种数据处理方法，所述方法可以应用于存储系统，所述存储系统包括第一控制器和第二控制器，所述第一控制器和所述第二控制器分别通过设置有缓存的共享接口设备与至少一个存储器通信。所述方法可以包括：所述第一控制器向共享接口设备发送写入指令。所述共享接口设备在所述缓存中暂存所述写入指令所指示写入的第一数据，之后把所述缓存中暂存的第一数据异步写入所述至少一个存储器中的第一存储器。
可选的，所述第二控制器可以向所述共享接口设备发送指示写入第三数据的写入指令，所述共享接口设备可以在所述缓存中暂存所述第三数据，把所述缓存中暂存的所述第三数据异步写入所述至少一个存储器中的一个或多个存储器，例如，可以将第三数据异步写入第一存储器。
可选的，所述第二控制器在所述第一控制器发生故障后，向所述共享接口设备发送读取指令，所述读取指令指示查询第二数据，所述第二数据为所述第一数据中的全部或一部分。所述共享接口设备根据所述读取指令，在所述缓存中获取所述第二数据中的全部或一部分并提供给所述第二控制器。
可选的，所述缓存包括第一分区和第二分区，所述第一分区用于为所述第一控制器暂存数据，所述第二分区用于为所述第二控制器暂存数据，所述共享接口设备在所述缓存中获取所述第二数据的全部或者一部分的查询范围包括所述第一分区和所述第二分区。
可选的，所述共享接口设备在所述缓存中暂存第一数据，包括：所述共享接口设备在所 述第一分区暂存所述第一数据。所述共享接口设备在所述缓存中暂存第三数据，包括：所述共享接口设备在所述第二分区暂存所述第三数据。所述共享接口设备把缓存中暂存的所述第一数据、所述第三数据异步写入所述第一存储器可以包括：所述共享接口设备将所述第一分区中暂存的第一数据和所述第二分区中暂存的第三数据连续发送至所述第一存储器。可选的，第一控制器发送的写入指令可以指示将第一数据写入所述第一存储器，第二控制器发送的写入指令可以指示将第三数据写入所述第一存储器。
可选的，所述至少一个存储器还包括第二存储器，所述第二存储器的访存时延小于所述第一存储器，所述方法还包括：所述共享接口设备在接收到所述写入指令后，将所述第一数据同步备份至所述第二存储器；当所述缓存出现异常，所述共享接口设备根据所述读取指令，在所述第二存储器中获取所述第二数据的全部或一部分并提供给所述第二控制器。
可选的，所述存储系统还包括与所述第一控制器相连的第三存储器，所述方法还包括：所述第一控制器将所述第一数据备份至所述第三存储器；当所述缓存出现异常，所述第一控制器将所述第三存储器中备份的数据通过所述共享接口设备转发至所述至少一个存储器中的第四存储器；在所述共享接口设备接收到所述读取指令后，当所述缓存出现异常，所述共享接口设备根据所述读取指令，在所述第四存储器中获取所述第二数据的全部或一部分并提供给所述第二控制器。
可选的，所述数据包括业务数据和/或所述业务数据的元数据，其中，所述业务数据为所述第一控制器接收的数据写入请求所请求写入的数据。
可选的，所述共享接口设备为接口卡或硬盘框，其中，所述接口卡插接于所述第一控制器或所述第二控制器中，所述硬盘框用于安装所述至少一个存储器。
可选的，所述共享接口设备与所述第一控制器和/或所述第二控制器通过快捷外设互连PCIE协议通信。
可选的，所述至少一个存储器中的每个存储器仅有单个与所述共享接口设备通信的端口。
由于第一方面所提供的存储系统中的第一控制器、第二控制器和共享接口设备可以用于执行第二方面所提供的方法，因此第二方面所提供的方法的技术效果可参考前述对应的存储系统所获得的技术效果，此处不再赘述。
第三方面，本申请提供一种数据处理方法，所述方法可以应用于存储系统中的共享接口设备，所述存储系统包括第一控制器和第二控制器，所述第一控制器和所述第二控制器分别通过设置有缓存的所述共享接口设备与至少一个存储器通信，所述方法包括：所述共享接口设备接收所述第一控制器发送的指示写入第一数据的写入指令；所述共享接口设备在所述缓存中暂存所述第一数据，之后把所述缓存中暂存的第一数据异步写入所述至少一个存储器中的第一存储器。
可选的，所述方法还包括：所述共享接口设备接收所述第二控制器发送的指示写入第三数据的写入指令；所述共享接口设备在所述缓存中暂存所述第三数据，之后把所述缓存中暂存的第三数据异步写入所述至少一个存储器中一个或多个存储器(例如第一存储器)。
可选的，在所述第一控制器发生故障后，所述共享接口设备接收所述第二控制器发送的读取指令，所述读取指令指示查询第二数据，所述第二数据为所述第一数据中的全部或一部分；所述共享接口设备根据所述读取指令，在所述缓存中获取所述第二数据中的全部或一部并提供给所述第二控制器。
可选的，所述缓存包括第一分区和第二分区，所述第一分区用于为所述第一控制器暂存 数据，所述第二分区用于为所述第二控制器暂存数据，所述共享接口设备在所述缓存中获取所述第二数据的全部或者一部分的查询范围包括所述第一分区和所述第二分区。
可选的，所述共享接口设备在所述缓存中暂存所述第一数据，包括：所述共享接口设备在所述第一分区暂存所述第一数据。所述共享接口设备在所述缓存中暂存所述第三数据，包括：所述共享接口设备在所述第二分区暂存所述第三数据。所述共享接口设备把缓存中暂存的所述第一数据、所述第三数据异步写入所述第一存储器可以包括：所述共享接口设备将所述第一分区中暂存的第一数据和所述第二分区中暂存的第三数据连续发送至所述第一存储器。可选的，第一控制器发送的写入指令可以指示将第一数据写入所述第一存储器，第二控制器发送的写入指令可以指示将第三数据写入所述第一存储器。
可选的，所述至少一个存储器还包括第二存储器，所述第二存储器的访存时延小于所述第一存储器，所述方法还包括：所述共享接口设备在接收到所述写入指令后，将所述第一数据同步备份至所述第二存储器；当所述缓存出现异常，所述共享接口设备根据所述读取指令，在所述第二存储器中获取所述第二数据的全部或一部分并提供给所述第二控制器。
可选的，所述存储系统还包括与所述第一控制器相连的第三存储器，所述方法还包括：在所述共享接口设备接收到所述读取指令后，当所述缓存出现异常，所述共享接口设备根据所述读取指令，在相连的第四存储器中获取所述第二数据的全部或一部分并提供给所述第二控制器。其中，第四存储器中所述第二数据的全部或一部分为所述第一控制器在所述缓存出现异常后，通过所述共享接口设备从所述第三存储器中转发至所述第四存储器中的，所述第三存储器中的数据包括所述第一控制器备份的第一数据。
可选的，所述数据包括业务数据和/或所述业务数据的元数据，其中，所述业务数据为所述第一控制器接收的数据写入请求所请求写入的数据。
可选的，所述共享接口设备为接口卡或硬盘框，其中，所述接口卡插接于所述第一控制器或所述第二控制器中，所述硬盘框用于安装所述至少一个存储器。
可选的，所述共享接口设备与所述第一控制器和/或所述第二控制器通过快捷外设互连PCIE协议通信。
可选的，所述至少一个存储器中的每个存储器仅有单个与所述共享接口设备通信的端口。
由于第一方面所提供的共享接口设备可以用于执行第三方面所提供的方法，因此第三方面所提供的方法的技术效果可参考前述对应的存储系统所获得的技术效果，此处不再赘述。
第四方面，本申请提供一种共享接口设备，共享接口设备可以设置有缓存。共享接口设备可以包括接收模块、存储模块和查询模块；所述接收模块用于接收第一控制器发送的指示写入第一数据的写入指令，所述第一控制器和第二控制器分别通过所述共享接口设备与至少一个存储器通信；所述存储模块用于在自身的缓存中暂存所述第一数据，还用于把缓存中暂存的第一数据异步写入所述至少一个存储器中的第一存储器。
可选的，所述接收模块还用于接收第二控制器发送的指示写入第三数据的写入指令；所述存储模块用于在自身的缓存中暂存所述第一数据，还用于把缓存中暂存的第三数据异步写入所述至少一个存储器中的一个或多个存储器，例如，存储模块可以将第三数据异步写入所述第一存储器。
可选的，所述接收模块还用于在所述第一控制器发生故障后，接收所述第二控制器发送的读取指令，所述读取指令指示查询第二数据，所述第二数据为所述第一数据中的全部或一部分；所述查询模块用于根据所述读取指令，在所述缓存中获取所述第二数据中的全部或一 部分并提供给所述第二控制器。
可选的，所述缓存包括第一分区和第二分区，所述第一分区用于为所述第一控制器暂存数据，所述第二分区用于为所述第二控制器暂存数据，所述查询模块在所述缓存中获取所述第二数据的全部或者一部分的查询范围包括所述第一分区和所述第二分区。
可选的，所述存储模块具体用于：在所述第一分区暂存所述第一数据，在所述第二分区暂存所述第三数据，将所述第一分区中暂存的第一数据和所述第二分区中暂存的第三数据连续发送至所述第一存储器。可选的，第一控制器发送的写入指令可以指示将第一数据写入所述第一存储器，第二控制器发送的写入指令可以指示将第三数据写入所述第一存储器。
可选的，所述至少一个存储器还包括第二存储器，所述第二存储器的访存时延小于所述第一存储器，所述存储模块还用于：在接收到所述写入指令后，将所述第一数据同步备份至所述第二存储器；当所述缓存出现异常，根据所述读取指令，在所述第二存储器中获取所述第二数据的全部或一部分并提供给所述第二控制器。
可选的，所述存储系统还包括与所述第一控制器相连的第三存储器，所述查询模块还用于：在所述接收模块接收到所述读取指令后，当所述缓存出现异常，根据所述读取指令，在相连的第四存储器中获取所述第二数据的全部或一部分并提供给所述第二控制器。其中，第四存储器中所述第二数据的全部或一部分为所述第一控制器在所述缓存出现异常后，通过所述共享接口设备从所述第三存储器中转发至所述第四存储器中的，所述第三存储器中的数据包括所述第一控制器备份的第一数据。
可选的，所述数据包括业务数据和/或所述业务数据的元数据，其中，所述业务数据为所述第一控制器接收的数据写入请求所请求写入的数据。
可选的，所述共享接口设备为接口卡或硬盘框，其中，所述接口卡插接于所述第一控制器或所述第二控制器中，所述硬盘框用于安装所述至少一个存储器。
可选的，所述共享接口设备与所述第一控制器和/或所述第二控制器通过快捷外设互连PCIE协议通信。
可选的，所述至少一个存储器中的每个存储器仅有单个与所述共享接口设备通信的端口。
第四方面所提供的共享接口设备可以具有第一方面提供的存储系统中共享接口设备的功能，因此第四方面所提供的共享接口设备的技术效果可参考前述对应的共享接口设备所获得的技术效果，此处不再赘述。
第五方面，本申请提供一种计算设备，第一控制器和所述第二控制器分别通过所述计算设备与至少一个存储器通信，所述计算设备包括存储器和处理器，所述存储器包括缓存，所述处理器执行存储器存储的计算机指令，以使所述计算设备执行第三方面中任意一种可能的实现方式所描述的方法。
可选的，所述计算设备为接口卡或硬盘框，其中，所述接口卡插接于所述第一控制器或所述第二控制器中，所述硬盘框用于安装所述至少一个存储器。
可选的，所述计算设备与所述第一控制器和/或所述第二控制器通过快捷外设互连PCIE协议通信。
第六方面，本申请提供一种计算机可读存储介质，包括指令，当其在计算设备上运行时，使得所述计算设备执行第三方面中任意一种可能的实现方式所描述的方法。
本申请第十一方面提供一种计算机程序产品，该计算机程序产品包含的程序代码被计算机设备执行时，以实现如本申请能够执行第三方面中任意一种可能的实现方式所描述的方法。
由于本申请提供的各装置可用于执行前述存储系统中共享接口设备所执行的方法步骤，因此本申请各装置所能获得到的技术效果可参考前述存储系统所获得的技术效果，此处不再赘述。
本申请权利要求书和发明内容中所涉及的第一控制器和第二控制器可以例如为本申请具体实施方式中存储节点的任意两个不同的控制器，例如，第一控制器可以为控制器a，第二控制器可以为控制器b，或者，第一控制器可以为控制器b，第二控制器可以为控制器a。
本申请权利要求书和发明内容中所涉及的共享接口设备可以例如为本申请具体实施方式中存储节点的任意一个连接至少两个控制器的共享接口设备，例如，该共享接口设备可以为共享接口设备a或共享接口设备b。以共享接口设备为共享接口设备a为例，该共享接口设备可以具体为接口卡a或硬盘框a。
本申请权利要求书和发明内容中所涉及的至少一个存储器可以例如为本申请具体实施方式中共享接口设备a或共享接口设备b所连接的至少一个存储器，以共享接口设备为接口卡a为例，该至少一个存储器可以包括存储器a1、存储器a2和存储器a3。
本申请权利要求书和发明内容中所涉及的第一存储器可以例如为本申请具体实施方式中共享接口设备a或共享接口设备b所连接的任意一个或多个存储器，以共享接口设备为接口卡a为例，该第一存储器可以包括存储器a2。
以第一控制器和第二控制器分别为本申请具体实施方式中提到的控制器a和控制器b为例，本申请权利要求书和发明内容中所涉及的第一控制器发送的写入指令可以例如为本申请具体实施方式中提到的写入指令1或写入指令1-1，第二控制器发送的写入指令可以例如为本申请具体实施方式中提到的写入指令2或写入指令2-2。
继续以第一控制器和第二控制器分别为本申请具体实施方式中提到的控制器a和控制器b为例，本申请权利要求书和发明内容中所涉及的第一数据和第三数据可以分别例如为本申请具体实施方式中提到的目标数据1和目标数据2。
本申请权利要求书和发明内容中所涉及的读取指令可以例如为本申请具体实施方式中提到的读取指令1或读取指令1-1或读取指令2或读取指令2-1。本申请权利要求书和发明内容中所涉及的第二数据可以例如为本申请具体实施方式中提到的目标数据3或目标数据4。其中，可选的，目标数据3或目标数据4可以为目标数据1中的全部或一部分，或者，目标数据3或目标数据4可以为目标数据2中的全部或一部分。
以第一控制器为本申请具体实施方式中的控制器a为例，本申请权利要求书和发明内容中所涉及的第三存储器可以例如包括本申请具体实施方式中与控制器a相连的存储器c1。
以第一控制器为本申请具体实施方式中的控制器b为例，本申请权利要求书和发明内容中所涉及的第三存储器可以例如包括本申请具体实施方式中与控制器b相连的存储器c2。
以第一控制器为本申请具体实施方式中的控制器a为例，本申请权利要求书和发明内容中所涉及的第二存储器可以例如包括本申请具体实施方式中的存储器a1。
以本申请权利要求书和发明内容中所涉及的共享接口设备为本申请具体实施方式中的接口卡a为例，该第一分区和第二分区可以分别例如为接口卡a的缓存中的分区1和分区2。
附图说明
图1示例性示出现有存储系统的结构；
图2示例性示出本申请实施例适用的一种可能的系统架构；
图3-1、图3-2和图3-3分别示例性示出本申请存储系统中存储节点一种可能的结构；
图4示例性示出本申请存储节点所执行的一种可能的数据处理方法；
图5示例性示出接口卡a将缓存中的数据持久化至存储器中的过程；
图6、图7和图8分别示例性示出本申请存储节点所执行的另一种可能的数据处理方法；
图9示例性示出本申请共享接口设备一种可能的结构。
具体实施方式
本申请实施例提供一种存储系统、数据处理方法及装置。下面首先结合图2示例性介绍本申请实施例适用的系统架构。
图2示例性示出了本申请实施例适用的一种系统架构。图2对应的系统架构包括存储系统和至少一个应用服务器，应用服务器和存储系统之间可以通过通信网络连接。参考图2，存储系统可以包括一个存储节点，该存储节点内设置有存储控制单元和一个或多个存储器。存储器可以为硬盘(hard disk drive，HDD)，固态硬盘(solid state drive，SSD)，存储类内存(storage class memory,SCM)或其他类型的存储盘。或者，存储器可以为存储服务器，或其他类型的用于提供存储服务的计算设备。
图2仅示例性示出而非限定本申请实施例适用的系统架构。图2对应的系统架构可以包括更多或更少的应用服务器或存储节点。本申请实施例可以应用于集中式存储系统，也可以应用于分布式存储系统。可选的，本申请实施例适用的系统架构可以包括一个或多个例如图2所示的存储节点。图2所示的存储节点可以理解为存储阵列或存储服务器。本申请实施例不限定分布式存储系统中每个存储节点为图2所示的存储节点。
为了提高存储系统的可靠性，图2所示的存储节点的存储控制单元可以包括至少两个控制器。以存储控制单元中设置两个控制器为例，图2所示的存储节点可以具体如图3-1所示。
参考图3-1，该存储节点可以包括控制器a和控制器b。该控制器a和控制器b可以理解为存储阵列中的控制器，或者为存储服务器中的控制器。该存储节点还可以包括共享接口设备a和共享接口设备b。其中，共享接口设备a和共享接口设备b分别用于连接至少一个存储器。为了便于区分，将连接至共享接口设备a的存储器称作存储器a，将连接至共享接口设备b的存储器称作存储器b。存储器a和存储器b可以理解为图2所示的至少一个存储器中的存储器。控制器a和控制器b可以通过共享接口设备a与共享接口设备a下的至少一个存储器a通信，控制器a和控制器b可以通过共享接口设备b与共享接口设备b下的至少一个存储器b通信。
参考图3-1，共享接口设备a和共享接口设备b可以设置有缓存。控制器a和控制器b可以分别与共享接口设备a相连，以共同访问共享接口设备a中的缓存和相连的存储器a。控制器a和控制器b还可以分别与共享接口设备b相连，以共同访问共享接口设备b中的缓存和相连的存储器b。
可选的，共享接口设备a中的缓存可以通过控制器a和/或控制器b实现保电，共享接口设备b中的缓存可以通过控制器a和/或控制器b实现保电。例如，当控制器a和控制器b均正常的情况下，共享接口设备a中的缓存可以通过控制器a实现保电，共享接口设备b中的 缓存可以通过控制器b实现保电。当控制器a发生故障后，共享接口设备a中的缓存和共享接口设备b中的缓存可以通过控制器b实现保电。
图3-1示例性而非限定存储节点的结构。可选的，图3-1对应的存储节点可以包括更多控制器，可以包括更多或更少的共享接口设备，可以包括更多或更少的存储器a或存储器b。例如，图3-1对应的存储节点可以不包括共享接口设备b和共享接口设备b下的存储器b。
图3-1所示的共享接口设备a或共享接口设备b用于将控制器与存储器之间的数据进行如下至少一种操作：缓存、处理和中转。其中，“中转”可以指透传或协议格式的转换。图3-2和图3-3分别示例性示出图3-1对应的存储节点可能的结构，下面结合图3-2和图3-3所示的存储节点介绍两种不同类型的共享接口设备。
一、共享接口设备为接口卡
在图3-2对应的存储节点中，共享接口设备a可以为与控制器a相连的接口卡a，共享接口设备b可以为与控制器b相连的接口卡b。可选的，共享接口设备a以插接的形式与控制器a相连。例如，接口卡a可以与控制器a的外设部件互连标准(peripheral component interconnect，PCI)转接设备相连。类似的，共享接口设备b可以以插接的形式与控制器b相连，例如，接口卡b可以与控制器b的PCIE转接设备相连。
参考图3-2，控制器a和控制器b可以分别包括处理器、缓存和转接设备，接口卡a和接口卡b可以分别包括处理器、缓存和多个端口。
处理器可以由一个或者多个通用处理器构成，例如中央处理器(central processing unit，CPU)，或者CPU和硬件芯片的组合。上述硬件芯片可以是专用集成电路(application-specific integrated circuit，ASIC)、可编程逻辑器件(programmable logic device，PLD)或其组合。上述PLD可以是复杂可编程逻辑器件(complex programmable logic device，CPLD)、现场可编程逻辑门阵列(field-programmable gate array，FPGA)、通用阵列逻辑(generic array logic，GAL)或其任意组合。
图3-2以控制器a或控制器b中的转接设备为PCIE转接设备为例，该转接设备可以是其他类型的转接设备，例如为扩展工业标准结构(extended industry standard architecture，EISA)转接设备等。转接设备也可称作总线，可以包括地址总线、数据总线和控制总线等。
缓存可以包括易失性存储器(volatile memory)，例如随机存取存储器(random access memory，RAM)。缓存也可以包括非易失性存储器(non-volatile memory)，例如只读存储器(read-only memory，ROM)、快闪存储器(flash memory)、硬盘(hard disk drive，HDD)或固态硬盘(solid-state drive，SSD)；缓存还可以包括上述种类的组合。
其中，PCIE转接设备可以包括多个端口。图3-2中，每个标识有数字的方形代表一个端口。参考图3-2，PCIE转接设备中的多个端口可以包括端口11、端口12、端口13和端口14。接口卡a和接口卡b的多个端口可以分别包括端口21、端口22和端口23。
参考图3-2中的实线连线，控制器a的处理器可以依次通过控制器a中的端口11和端口12以及接口卡a的端口21访问接口卡a，以实现控制器a与接口卡a通信连接。参考图3-2中的虚线连线，控制器b的处理器可以依次通过控制器b中的端口11和端口14、控制器a 中的端口14和端口13、以及接口卡a的端口22访问接口卡a，以实现控制器b与接口卡a通信连接。
类似的，可选的，控制器b的处理器可以依次通过控制器b中的端口11和端口12以及接口卡b的端口21访问接口卡b，以实现控制器b与接口卡b通信相连。控制器a的处理器可以依次通过控制器a中的端口11和端口14、控制器b中的端口14和端口13、以及接口卡b的端口22访问接口卡b，以实现控制器a与接口卡b相连。
如前文介绍的，接口卡a和接口卡b可以分别向上与控制器a和控制器b相连，此外，接口卡a还可以通过端口向下与一个或多个存储器a相连，接口卡b还可以通过端口向下与一个或多个存储器b相连。参考图3-2，接口卡a可以通过端口23与硬盘框a的端口31相连，进而访问安装于硬盘框a中的存储器a1、存储器a2和存储器a3，接口卡b可以通过端口23与硬盘框b相连，进而访问硬盘框b中的存储器b1、存储器b2和存储器b3相连。其中，存储器a1、存储器a2和存储器a3中的每个存储器均可以理解为一个存储器a，存储器b1、存储器b2和存储器b3中的每个存储器均可以理解为一个存储器b。
可选的，接口卡a和/或接口卡b可以为串行连接SCSI(serial attached SCSI，SAS)卡或独立冗余磁盘阵列(redundant array of independent disk，RAID)卡，其中，SCSI是小型计算机系统接口(smallcomputer system interface)的缩写。图3-2对应的存储节点中，可选的，接口卡a与控制器a之间的连接可以基于快捷外设互连(peripheral component interconnect express，PCIE)协议，接口卡a与存储器a之间的连接可以基于SAS协议或光纤通道(Fibre Channel，FC)协议或千兆以太网(Gigabit Ethernet，GE)协议等。类似的，接口卡b与控制器b之间的连接可以基于PCIE协议，接口卡b与存储器b之间的连接可以基于SAS协议或FC协议或GE协议等。
由于接口卡a设置有缓存，控制器a和控制器b通过分别与接口卡a相连，不仅可以共享接口卡a下的存储器a，还可以共享接口卡a中的缓存。同样的，由于接口卡b设置有缓存，控制器a和控制器b通过与接口卡b相连，不仅可以共享接口卡b下的存储器b，还可以共享接口卡b中的缓存。
继续参阅图3-2，控制器a和控制器b只需一个接口卡(例如接口卡a或接口卡b)的一个端口，便可以共享该接口卡下的存储器，有利于节约接口卡的端口资源，从而有利于接口卡连接更多的存储器，扩大控制器a和控制器b共享的存储资源。并且，与接口卡相连的存储器可以仅设置一个用于连接接口卡的端口，便可以分别与控制器a和控制器b通信，无需对存储器进行端口改造，有利于节约成本。例如，可以将图3-2中的硬盘框和硬盘框下的存储器理解为一个存储器，硬盘框只需设置一个与接口卡相连的端口，便可以分别与控制器a和控制器b通信，无需对硬盘框进行端口改造。
图3-2以接口卡通过硬盘框与存储盘通信为例而非限定，可选的，接口卡可以与单端口的硬盘直接连接。可选的，接口卡可以与存储服务器等其他类型的用于提供存储服务的计算设备通信。
图3-2示例性而非限定存储节点的结构。可选的，图3-2对应的存储节点可以包括更多控制器，可以包括更多或更少的接口卡，可以包括更多或更少的存储器，例如，可以不包括接口卡b和接口卡b下的存储器。
二、共享接口设备为硬盘框
在图3-3对应的存储节点中，共享接口设备a可以为硬盘框a，共享接口设备b可以为硬盘框b。可选的，与硬盘框相连的一个或多个存储器a可以安装于硬盘框a中，与硬盘框相连的一个或多个存储器b可以安装于硬盘框b中。可选的，该一个或多个存储器a可以包括HDD和SSD中至少一种类型的存储盘。同样的，可选的，该一个或多个存储器b可以包括HDD和SSD中至少一种类型的存储盘。
参考图3-3，控制器a和控制器b可以分别包括处理器和缓存，硬盘框a和硬盘框b可以包括处理器、缓存、多个端口和硬盘的安装机构(例如图3-3所示的凹槽)。该处理器和缓存可以分别参考图3-2中的相关内容，此处不再赘述。参考图3-3，硬盘框a和硬盘框b的多个端口可以分别包括端口21和端口22。存储器(例如存储器a1、存储器a2或存储器a3)设置在硬盘框a的安装机构后，可以分别与硬盘框a的处理器通信连接。存储器(例如存储器b1、存储器b2或存储器b3)设置在硬盘框b的安装机构后，可以分别与硬盘框b的处理器通信连接。
可选的，控制器a可以依次通过接口卡a的端口21和端口22以及硬盘框a的端口31访问硬盘框a，以实现控制器a与硬盘框a通信相连。控制器b可以依次通过接口卡b的端口21和端口23以及硬盘框a的端口32访问硬盘框a，以实现控制器b与硬盘框a通信相连。
类似的，可选的，控制器b可以依次通过接口卡b的端口21和端口22以及硬盘框b的端口31访问硬盘框b，以实现控制器b与硬盘框b通信相连。控制器a可以依次通过接口卡a的端口21和端口23以及硬盘框b的端口32访问硬盘框b，以实现控制器a与硬盘框b通信相连。
如前文介绍的，硬盘框a和硬盘框b可以分别向上与控制器a和控制器b相连，此外，硬盘框a还可以通过端口向下与一个或多个存储器a相连，硬盘框b还可以通过端口向下与一个或多个存储器b相连。参考图3-3，硬盘框a可以访问安装于硬盘框a中的存储器a1、存储器a2和存储器a3，硬盘框b可以访问安装于硬盘框b中的存储器b1、存储器b2和存储器b3。其中，存储器a1、存储器a2和存储器a3中的每个存储器均可以理解为一个存储器a，存储器b1、存储器b2和存储器b3中的每个存储器均可以理解为一个存储器b。
由于硬盘框a设置有缓存，控制器a和控制器b通过分别与硬盘框a相连，不仅可以共享硬盘框a下的存储器a，还可以共享硬盘框a中的缓存。同样的，由于硬盘框b设置有缓存，控制器a和控制器b通过与硬盘框b相连，不仅可以共享硬盘框b下的存储器b，还可以共享硬盘框b中的缓存。
硬盘框a和硬盘框b可以分别连接控制器a，硬盘框a和硬盘框b分别与控制器a之间的连接可以基于SAS协议或光纤通道(Fibre Channel，FC)协议或千兆以太网(Gigabit Ethernet，GE)协议等。类似的，硬盘框b和硬盘框a分别连接控制器b，硬盘框b与控制器b之间的连接可以基于SAS协议或光纤通道(Fibre Channel，FC)协议或千兆以太网(Gigabit Ethernet，GE)协议等。
图3-3示例性而非限定存储节点的结构。可选的，图3-3对应的存储节点可以包括更多控制器，可以包括更多或更少的接口卡，可以包括更多或更少的硬盘框，可以包括更多或更少的存储器。例如，图3-3对应的存储节点可以不包括硬盘框b和硬盘框b中的存储器，例如，接口卡a或接口卡b可以连接更多的存储器。
在图3-1或图3-2或图3-3所示的存储节点中，端口之间的一条连线可以代表一条或多条连接链路。以图3-2中端口12和端口21之间的连线为例，该连线所代表的连接链路可以 包括用于传输数据信号的PCIE总线和用于传输控制信号的控制总线。其中，控制总线可以例如传输控制器a和接口卡a的控制信号、握手信息和状态信息。该控制信号可以包括使接口卡a开始工作的启动信号，该启动信号可以例如包括接口卡a的在位信号(用于判断接口卡a是否已经插入正确的插槽)、上电使能信号、时钟信号和复位信号等。握手信息可以用于控制器a和接口卡a进行端口协商，确定二者之间的传输通道的传输带宽和传输速率等。
可选的，在图3-1或图3-2或图3-3所示的存储节点中，控制器a和控制器b之间可以具有连接链路，例如用于传输心跳信息，以实时监控对方状态。
以上，通过图3-1、图3-2和图3-3介绍了控制器a和控制器b调用共享接口设备(例如共享接口设备a和共享接口设备b)所需的连接链路，下面结合控制器a和控制器b的对共享接口设备的调用模式来举例介绍控制器调用共享接口设备的控制逻辑。
本申请实施例不限定存储节点中控制器对共享接口设备的调用模式，可选的，该调用模式可以为主备模式或双活模式。
1)主备模式
在主备模式下，存储节点中各控制器对于共享接口设备的地位不一样，分为共享接口设备的主控制器和备控制器。
假设控制器a和控制器b分别为共享接口设备a的主控制器和备控制器。正常工作状态下，控制器a可以调用共享接口设备a执行数据存储业务和数据查询业务，控制器b无法调用共享接口设备a执行数据存储业务和数据查询业务。当控制器a出现故障，控制器b可以接管共享接口设备a，以调用共享接口设备a执行数据存储业务和/或数据查询业务，从而保证共享接口设备a的缓存和存储器a中数据的可用性。
以图3-2所示的存储节点为例，介绍一种可能的具体主备切换过程。正常工作状态下，接口卡a的端口21处于激活状态，端口22处于非激活状态，从而接口卡a可以被控制器a调用，无法被控制器b调用。当控制器a出现故障时，控制器a可以通过与控制器b之间心跳信号或掉电中断信号通知控制器b，控制器b可以竞争为接口卡a的主控制器。控制器b可以通知接口卡a该主备切换事件，令接口卡a的端口21进入非激活状态，停止为控制器a调用，令接口卡a的端口22进入激活状态，开始被控制器b调用。
2)双活模式
在双活模式下，存储节点中各控制器对于共享接口设备的地位是一样的。可选的，控制器a和控制器b可以分时交替调用共享接口设备a或共享接口设备b。当控制器a发生异常无法工作后，控制器b可以调用共享接口设备a和/或共享接口设备b执行数据查询业务，从而保证共享接口设备a和/或共享接口设备b的缓存中的数据和连接的存储器中的数据的可用性。
存储节点中的控制器在满足对共享接口设备的调用条件的情况下可以接管相应共享接口设备，以使用相应共享接口设备的缓存和与其连接的存储器提供数据存储和数据查询业务。下面介绍存储节点中控制器调用共享接口设备提供数据存储业务和数据查询业务的过程。
以下介绍控制器a通过接口卡a提供数据存储业务的过程。
图4示例性示出控制器a通过接口卡a存储数据的方法流程。图4中应用服务器以外的结构可以例如为图3-2所示的存储节点，为了简化附图，图4未具体示出控制器b、接口卡b 以及接口卡b下的存储器，也未示出控制器a中的PCIE转接设备。本申请提供的数据处理方法一种可能的实施例可以包括如下步骤S401-S404。
S401、应用服务器向控制器a发送写请求1；
应用服务器可以向控制器a发送数据写入请求1(简称写请求1)，该写请求1用于请求存储业务数据1。本申请实施例所涉及的存储系统可以通过文件系统或块存储系统或对象存储系统等软件系统来提供数据存储业务，相应的，写请求1所请求写入的业务数据可以为文件或数据块或对象等形式的数据。
步骤S401为可选步骤，本申请实施例不限定写请求1为应用服务器发送的。可选的，写请求1可以为终端中的客户端发送的，或者为存储系统所采用的软件系统发送的。可选的，业务数据1可以为用户数据或者为该软件系统产生的系统数据。本申请实施例不限定该软件系统部署的位置，例如，该软件系统可以部署在控制器a或控制器b或其他控制器中，或者，该软件系统可以部署在应用服务器中，或者，该软件系统部署在单独的服务器中。
S402、控制器a向接口卡a发送写入指令1；
控制器a可以根据写请求1向接口卡a发送写入指令1，写入指令1用于指示存储数据1。
其中，数据1包括但不限于业务数据1。可选的，控制器a可以生成描述业务数据1的元数据1，相应的，数据1可以包括业务数据1和元数据1。例如，当业务数据1被持久化于存储器a2中，元数据1可以描述业务数据1在存储器a2中的存储位置。该存储位置可以为逻辑地址或物理地址。
S403、接口卡a使用缓存和存储器a2存储写入指令1指示写入的数据1；
接口卡a接收到写入指令后，可以使用缓存和存储器a2存储数据1。由于控制器a和控制器b共享接口卡a的缓存，为了减少控制器a和控制器b向接口卡a的缓存中写数据的冲突，可选的，接口卡a的缓存可以被划分出控制器a的写入分区(称作分区1)和控制器b的写入分区(称作分区2)。其中，分区1和分区2为接口卡a的缓存中不同的两个存储空间，分区1和分区2不同可以指分区1对应的存储空间和分区2对应的存储空间不交叠。作为举例，步骤S403中，接口卡a可以使用自身缓存中的分区1和存储器a2存储数据1。
接口卡a接收到写入指令1后，可以通过缓存将数据1中的目标数据1异步写入存储器a2。可选的，写入指令1可以指示待写数据的持久化地址，该持久化地址可以指向接口卡a下的至少一个存储器。本申请实施例以写入指令1指示目标数据1的持久化地址指向存储器a2为例。该持久化地址可以是存储器a2中的逻辑地址或物理地址。例如，该持久化地址可以为逻辑块寻址模式(logical block addressing，LBA)。
接口卡a通过缓存将目标数据1异步写入存储器a2可以指，接口卡a先将目标数据1暂存在缓存(例如分区1)，之后将目标数据1写入存储器a2中，并且，在将目标数据1写入缓存后，在将目标数据1写入存储器a2之前，接口卡a便会向控制器a发送成功通知，成功通知用于通知控制器a已完成写入指令1，已存储目标数据1。可选的，控制器a可以根据成功通知认为目标数据1已持久化于存储器a2中。
可选的，目标数据1可以是数据1中的全部数据。或者，可选的，目标数据1可以是数据1中的部分数据，接口卡a可以通过其他存储方式对数据1中目标数据1以外的其他数据进行存储。例如，接口卡a可以将该其他数据同步写入存储器a2。
接口卡a将该其他数据同步写入存储器a2是指，接口卡a将该其他数据写入存储器a2之后，才会向控制器a发送成功通知，以通知控制器a已存储该其他数据。
本申请实施例以接口卡a将目标数据1和其他数据持久化于存储器a2为例，可选的，接口卡a可以将写入指令1指示写入的数据存储多个存储器a中，例如，将目标数据1持久化于存储器a2中，将其他数据持久化于存储器a3中。
本申请实施例中，写入指令1可以包括一条或多条指令，例如，写入指令1可以包括指示写入目标数据1的写入指令1-1和指示写入其他数据的写入指令1-2。
可选的，接口卡a可以根据数据类型确定目标数据1，例如，目标数据1可以为元数据1，其他数据可以为业务数据1。或者，可选的，接口卡a可以根据数据长度确定目标数据1，例如，假设写入指令1-1的数据长度小于长度阈值，写入指令1-2的数据长度小于长度阈值，接口卡a可以通过缓存将写入指令1-1所指示写入的数据异步持久化，将写入指令1-2所指示写入的数据同步持久化。由于元数据的数据长度通常较小，并且，若业务数据1的长度也较小，目标数据1可以同时包括元数据1和业务数据1。
可选的，写入指令1可以指示存储方式，接口卡a可以根据写入指令1所指示的存储方式存储数据。例如，写入指令1-1指示异步存储，写入指令1-2指示同步存储，接口卡a可以通过自身缓存将写入指令1-1指示写入的数据异步存储在存储器a2中，将写入指令1-2指示写入的数据同步存储在存储器a2中。
本申请实施例中，接口卡a通过缓存将目标数据1异步写入存储器a2，并未限定接口卡a从写入指令1-1中取出目标数据1，之后仅在缓存中存储目标数据1。可选的，接口卡a可以将写入指令1-1存储在缓存中，向控制器a发送成功通知后，将缓存中的写入指令1-1发送给存储器a2，存储器a2可以从写入指令1-1中解析并存储目标数据1。
类似的，接口卡a将其他数据同步写入存储器a2，并未限定接口卡a从写入指令1-2中取出该其他数据，之后仅将该其他数据发送给存储器a2。可选的，接口卡a可以将写入指令1-2发送给存储器a2，存储器a2可以从写入指令1-2中解析并存储该其他数据。
由于接口卡a与控制器a之间的通信协议(例如PCIE协议)与接口卡a与存储器a2或硬盘框a之间的通信协议(例如SAS协议)通常不同，接口卡a在将控制器a发送的写入指令发送至存储器a2之前，可以对写入指令进行格式转换，例如，将写入指令1从PCIE协议格式转换为SAS协议格式。
图4所示的步骤S4031-S4033示例性示出接口卡a通过缓存将目标数据1异步写入存储器a2一种可能的流程。参阅图4，步骤S403一种可能的细化步骤可以包括：
S4031、接口卡a在分区1暂存目标数据1；
接口卡a接收到写入指令1后，可以将写入指令1所指示写入的目标数据1写入分区1。结合前文的介绍，可选的，接口卡a的缓存可以包括分区1和分区2，S4031以接口卡a将目标数据1写入自身缓存中的分区1为例而非限定。
可选的，写入指令1还可以指示目标数据1在分区1中的缓存地址。该缓存地址可以是逻辑地址或物理地址。接口卡a可以根据写入指令1指示的缓存地址在分区1存储目标数据1。
S4032、接口卡a向控制器a发送成功通知1；
目标数据1成功写入缓存后，接口卡a可以向控制器a发送成功通知，通知控制器a已完成写入指令1，成功存储目标数据1。
S4033、接口卡a将分区1中的目标数据1写入存储器a2；
接口卡a可以将缓存中暂存的第一数据异步写入接口卡a连接的存储器。例如，接口卡a通知控制器a已成功存储目标数据1后，可以将缓存中目标数据1写入存储器a2，以持久化目标数据1。可选的，参考图4，接口卡a可以通过硬盘框a将目标数据1存储在存储器a2中。
可选的，接口卡a在通知控制器a已成功存储目标数据1后，可以在满足持久化条件时，将目标数据1写入存储器a2。该持久化条件可以与如下至少一种因素有关：缓存的可用存储空间的大小、缓存中待写入存储器a2的数据的总长度和存储器a2是否空闲。
为了提高存储器a2的存储效率，可选的，接口卡a可以将分区1中的目标数据1与缓存中的其他数据聚合发送至存储器a2。该其他数据可以包括S402所接收到的写入指令1以外的其他写入指令所指示写入的数据。本申请实施例不限定该其他数据在缓存中的位置。例如，该其他数据可以包括分区1和/或分区2中的数据。
参考图5，假设接口卡a的缓存的分区2中还存储有控制器b发送的写入指令2所指示写入的目标数据2，此外，分区1中还存储有控制器a发送的写入指令m所指示写入的目标数据m和写入指令n所指示写入的目标数据n，分区2中还存储有控制器b发送的写入指令p所指示写入的目标数据p。其中，m、n和p为大于2的正整数，并且，m、n和p互不相等。可选的，接口卡a可以将分区1中的目标数据1、目标数据m和分区2中的目标数据2聚合发送至存储器a2。
作为举例，假设目标数据1的持久化地址(LBA1)、目标数据2的持久化地址(LBA2)和目标数据m的持久化地址(LBAm)均指向存储器a2，当目标数据1、目标数据2和目标数据m的总长度达到阈值时，接口卡a可以将目标数据1、目标数据2和目标数据m聚合发送至存储器a2。可选的，缓存中目标数据的持久化地址可以为前文介绍的相应写入指令所指示的存储地址。
为了进一步提高存储器a2的存储效率，可选的，接口卡a可以将持久化地址相邻的数据聚合发送至存储器a2。继续参考图5，假设目标数据n的持久化地址(LBAn)和目标数据p的持久化地址(LBAp)虽然同样指向存储器a2，但是，由于LBA1所指示的存储空间与LBA2和LBAm所指示的存储空间相邻，而LBA1所指示的存储空间与LBAn或LBAp所指示的存储空间不相邻，因此，接口卡a可以不将目标数据1与目标数据n或目标数据p聚合发送至存储器a2。
接口卡a将目标数据1、目标数据2和目标数据m聚合发送至存储器a2可以指，接口卡a将目标数据1、目标数据2和目标数据m通过一条指令下发至存储器a2，可选的，接口卡a可以将目标数据n和目标数据p通过其他指令下发至存储器a2。或者，接口卡a将目标数据1、目标数据2和目标数据m聚合发送至存储器a2可以指，接口卡a将目标数据1、目标数据2和目标数据m通过连续的多条指令下发至存储器a2，在该多条指令之间不包括用于存储其他数据(例如目标数据n或目标数据p或同步存储至存储器a2的数据)的指令。
可见，接口卡a将目标数据1、目标数据2和目标数据m聚合发送至存储器a2，可以理解为将目标数据1、目标数据2和目标数据m连续发送至存储器a2，有利于存储器a2连续处理目标数据1、目标数据2和目标数据m的存储任务，当目标数据1、目标数据2和目标数据m的持久化地址相邻甚至连续时，可以减少存储器a2写入地址的大幅跳转，节约寻址时长，从而提高存储器a2的存储效率。
可选的，接口卡a或控制器a可以判断是否满足持久化条件。可选的，写入指令1还可以指示将目标数据1、目标数据2和目标数据m聚合发送至存储器a2。
S404、控制器a向应用服务器发送写成功响应1；
控制器a通过接口卡a成功存储数据1之后，可以向应用服务器发送写成功响应1，写成功响应1可以通知已完成写请求1，存储业务数据1。可选的，在接口卡a通知控制器a已存储数据1之后，控制器a可以确定已成功存储业务数据1。
如前文步骤S403所提到的，可选的，接口卡a可以使用缓存将数据1异步写入存储器a2，并且，在将数据1写入缓存后，在将数据1写入存储器a2之前，通知控制器a已存储数据1。相应的，控制器a可以在数据1写入接口卡a的缓存后，在数据1持久化至存储器a2之前，便可以向应用服务器发送写成功响应1，从而有利于减少应用服务器感知到的数据存储时延。
如前文步骤S403所提到的，可选的，接口卡a可以使用缓存将目标数据1(例如元数据1)异步写入存储器a2，在将目标数据1写入缓存后，在将目标数据1写入存储器a2之前，通知控制器a已存储目标数据1。并且，接口卡a可以将数据1中目标数据1以外的其他数据(例如业务数据1)同步写入存储器a2，在将该其他数据写入存储器a2后，更为具体的，在存储器a2成功存储该其他数据后，通知控制器a已存储该其他数据。相应的，控制器a可以在目标数据1写入接口卡a的缓存后，并且，在该其他数据持久化至存储器a2后，向应用服务器发送写成功响应1，和将数据1中的全部数据同步持久化至存储器a2相比，有利于减少应用服务器感知到的数据存储时延。
为了尽量避免接口卡a的缓存出错后缓存中的数据不可用，可选的，步骤S402后，本申请实施例方法还可包括S405。
S405、接口卡a将目标数据1同步备份至存储器a1；
在接收到写入指令1后，接口卡a可以向存储器a1同步写入目标数据1。也就是说，接口卡a向缓存和存储器a1均写入目标数据1后，在向存储器a2写入目标数据1之前，执行步骤S4032。通过将写入缓存的数据备份至与接口卡a相连的存储器a1，即使缓存出现异常，例如，缓存中尚未持久化的数据丢失，接口卡a在存储器a1中仍然可以查询到缓存中的数据，有利于提高缓存中数据的可用性，提高存储系统提供的数据服务的可靠性。
可选的，存储器a1的访存时延可以小于存储器a2的访存时延。例如，存储器a1可以为SSD，存储器a2可以为HDD。图4仅以存储器a1和存储器a2通过硬盘框与接口卡a相连为例，可选的，存储器a1和/或存储器a2可以与接口卡a直连。
为了尽量避免接口卡a的缓存出错后缓存中的数据不可用，可选的，步骤S401后，本申请实施例方法还可包括S406和S407。
S406、控制器a向存储器c1存储目标数据1；
S407、当缓存出现异常，控制器a将目标数据1通过接口卡a转发至存储器a2。
可选的，存储系统还包括与控制器a相连的存储器c1，控制器a接收到写请求后，还用于将目标数据1写入存储器c1。可选的，控制器a在将目标数据1双写至接口卡a的缓存和存储器c1后，才会判定成功存储目标数据1。
在缓存出现异常后，控制器a可以将存储器c1中的数据(包括目标数据1)通过接口卡a转发至接口卡a下的存储器，例如存储器a2或其他存储器。这样，即使缓存出现异常，例 如，缓存中尚未持久化的数据丢失，接口卡a在至少一个存储器中仍然可以查询到缓存中的数据，有利于提高缓存中数据的可用性，提高存储系统提供的数据服务的可靠性。
以下介绍控制器b通过接口卡a提供数据存储业务的过程。
图6示例性示出控制器b通过接口卡a存储数据的方法流程。图6中应用服务器以外的结构可以例如为图3-2所示的存储节点，为了简化附图，图6未具体示出接口卡b和接口卡b下的存储器，也未示出控制器a和控制器b中的PCIE转接设备。本申请提供的数据处理方法另一种可能的实施例可以包括如下步骤S601-S604。
S601、应用服务器向控制器b发送写请求2；
步骤S601可以参考前文步骤S401理解，例如，写请求2可以参考写请求1的相关描述进行理解。
本申请实施例不限定写请求1和写请求2来自同一个设备，例如，二者可以来自不同的应用服务器，或者，一个来自应用服务器，另一个来自软件系统。
本申请实施例不限定写请求1对应的业务数据1和写请求2对应的业务数据2为同种类型的数据。例如，业务数据1可以为用户数据，业务数据2可以为系统数据。
S602、控制器b向接口卡a发送写入指令2；
控制器b可以根据写请求2向接口卡a发送写入指令2，写入指令2指示存储数据2。步骤S602可以参考步骤S402理解，例如，写入指令2可以参考写入指令1的相关描述进行理解，数据2可以参考前文的数据1进行理解。
和S402不同的，参考图3-2所示的连接方式，由于接口卡a插接于控制器a，控制器b向接口卡a发送写入指令2所经过的线路与控制器a向接口卡a发送写入指令1所经过的线路不同。
S603、接口卡a使用缓存和存储器a3存储写入指令2指示写入的数据2；
接口卡a在接收到写入指令2后，可以使用缓存和存储器a3存储数据2。本申请实施例以存储器a3与存储器a2不同为例而非限定，可选的，接口卡a可以使用缓存和存储器a2存储数据2。
步骤S603可以参考步骤S403理解。例如，接口卡b接收到写入指令2后，可以通过缓存将数据2中的目标数据2异步写入存储器a3。可选的，目标数据2可以是数据2中的全部数据。或者，可选的，目标数据2可以是数据2中的部分数据，接口卡b可以通过其他存储方式对数据2中目标数据2以外的其他数据进行存储。例如，接口卡b可以将该其他数据同步写入存储器a3。写入指令2可以包括一条或多条指令，例如，写入指令2可以包括指示写入目标数据2的写入指令2-1和指示写入其他数据的写入指令2-2。
和步骤S403类似的，参阅图6，步骤S603一种可能的细化步骤可以包括：
S6031、接口卡a在分区2暂存目标数据2；
S6032、接口卡a向控制器b发送成功通知2；
S6033、接口卡a将分区2中的目标数据2写入存储器a3；
分区2可以参考步骤S403中所提到的分区2进行理解，S6031-S6033可以分别参考前文S4031-S4033进行理解。
S604、控制器b向应用服务器发送写成功响应2；
控制器b通过接口卡a成功存储数据2之后，可以向应用服务器发送写成功响应，完成数据存储业务。可选的，在接口卡a通知控制器b已存储数据2之后，控制器b可以确定已成功存储数据2。
如前文步骤S603所提到的，可选的，接口卡a可以使用缓存将数据2异步写入存储器a3，并且，在将数据2写入缓存后，在将数据2写入存储器a3之前，通知控制器b已存储数据2。相应的，控制器b可以在数据2写入接口卡a的缓存后，在数据2持久化至存储器a3之前，便可以向应用服务器发送写成功响应2，从而有利于减少应用服务器感知到的数据存储时延。
如前文步骤S603所提到的，可选的，接口卡a可以使用缓存将目标数据2(例如元数据2)异步写入存储器a3，在将目标数据2写入缓存后，在将目标数据2写入存储器a3之前，通知控制器b已存储目标数据2。并且，接口卡a可以将数据2中目标数据2以外的其他数据(例如业务数据2)同步写入存储器a3，在将该其他数据写入存储器a3后，更为具体的，在存储器a3成功存储该其他数据后，通知控制器b已存储该其他数据。相应的，控制器b可以在目标数据2写入接口卡a的缓存后，并且，在该其他数据持久化至存储器a3后，向应用服务器发送写成功响应2，和将数据2中的全部数据同步持久化至存储器a3相比，有利于减少应用服务器感知到的数据存储时延。
为了尽量避免接口卡a的缓存出错后缓存中的数据不可用，可选的，步骤S602后，本申请实施例方法还可包括S605。
S605、接口卡a向存储器a1同步写入目标数据2；
步骤S605可以参考步骤S405，此处不再赘述。例如，可选的，存储器a1的访存时延可以小于存储器a2的访存时延。作为举例，存储器a1可以为SSD，存储器a2可以为HDD。图6仅以存储器a1和存储器a2通过硬盘框与接口卡a相连为例，可选的，存储器a1和/或存储器a2可以与接口卡a直连。
为了尽量避免接口卡a的缓存出错后缓存中的数据不可用，可选的，步骤S601后，本申请实施例方法还可包括S606和S607。
S606、控制器b向存储器c存储目标数据2；
S607、当缓存出现异常，控制器b将目标数据2通过接口卡a转发至存储器a3。
可选的，存储系统还包括与控制器b相连的存储器c2，控制器b接收到写请求后，还用于将目标数据2写入存储器c2。在缓存出现异常后，控制器b可以将存储器c2中的数据(包括目标数据2)通过接口卡a转发至接口卡a下的存储器，例如存储器a3或其他存储器。这样，即使缓存出现异常，例如，缓存中尚未持久化的数据丢失，接口卡a在至少一个存储器中仍然可以查询到缓存中的数据，有利于提高缓存中数据的可用性，提高存储系统提供的数据服务的可靠性。
控制器b可以通过接口卡b提供数据存储业务，参考图3-2，由于接口卡b插接于控制器b，因此，控制器b通过接口卡b提供数据存储业务的过程可以参考图4对应的实施例，具体的，控制器b所执行的步骤可以参考图4对应的实施例中控制器a所执行的步骤进行理解，接口卡b所执行的步骤可以参考图4对应的实施例中接口卡a所执行的步骤进行理解。
控制器a可以通过接口卡b提供数据存储业务，参考图3-2，由于接口卡b插接于控制器b，因此，控制器a通过接口卡b提供数据存储业务的过程可以参考图6对应的实施例， 具体的，控制器a所执行的步骤可以参考图6对应的实施例中控制器b所执行的步骤进行理解，接口卡b所执行的步骤可以参考图6对应的实施例中接口卡a所执行的步骤进行理解。
以下介绍控制器a通过接口卡a提供数据查询业务的过程。
图7示例性示出控制器a通过接口卡a查询数据的方法流程。图7中应用服务器以外的结构可以例如为图3-2所示的存储节点，为了简化附图，图7未具体示出控制器b、接口卡b以及接口卡b下的存储器，也未示出控制器a中的PCIE转接设备。本申请提供的数据处理方法另一种可能的实施例可以包括如下步骤S701-S704。
S701、应用服务器向控制器a发送读请求1；
应用服务器可以向控制器a发送数据读取请求1(简称读请求1)，该读请求1用于请求读取业务数据3。该业务数据3可以为S401所介绍的业务数据1或S601所介绍的业务数据2。本申请实施例举例而非限定读请求1为应用服务器发送的，读请求1的其他可能来源可以参考S401的相关内容。
S702、控制器a向接口卡a发送读取指令1；
控制器a接收到读请求1后，可以向接口卡a发送读取指令1，读取指令1用于指示查询数据3。数据3可以为业务数据2，或包括业务数据2和业务数据2以外的其他数据。
S703、接口卡a在缓存和相连的存储器中查询读取指令1指示读取的数据3并提供给控制器a；
接口卡a接收到读取指令1后，可以查询数据3，查询范围可以包括接口卡a的缓存和接口卡a相连的存储器(例如存储器a1、存储器a2和存储器a3)。
本申请实施例不限定接口卡a在查询范围内的查询方式。可选的，接口卡a可以遍历缓存、存储器a1、存储器a2和存储器a3来查询数据3，之后，接口卡a可以向控制器a返回查询到的一个或多个结果。或者，可选的，接口卡a可以按照一定顺序依次访问缓存和相连的存储器，一旦查询到数据3便不再继续查找。例如，接口卡a可以先在缓存中查找数据3，若找到，则向控制器a返回数据3，若未找到，则继续在存储器a1中查找数据3。若接口卡a在存储器a1中找到数据3，则向控制器a返回数据3，若未找到，则继续在存储器a2中查找目标数据3。以此类推，控制器a可以将查找到的第一个数据3返回控制器a，并且不再继续查找数据3。若控制器a在所有查找范围内均未找到数据3，控制器a可以通知控制器查询失败。
本申请实施例，数据3可以包括目标数据3，目标数据3可以为第一目标数据的全部或一部分。其中，第一目标数据可以为S403所提到的目标数据1或S603所提到的目标数据2。由于接口卡a通过缓存暂存第一目标数据，若接口卡a在第一目标数据持久化之前接收到读取指令1，接口卡a可以根据读取指令1，在缓存中获取目标数据3的全部或一部分。
参阅S403中的内容，接口卡a的缓存可以被划分出图7所示的分区1和分区2，分区1可以用于为控制器a存储数据，分区2可以用于为控制器b存储数据。接口卡a在缓存中查询目标数据3的查询范围可以包括分区1和分区2。若目标数据3为目标数据1的全部或一部分，接口卡a可以在分区1中获取目标数据3的全部或一部分；若目标数据3为目标数据2的全部或一部分，接口卡a可以在分区2中获取目标数据3的全部或一部分。图7中处理器和分区2之间的带有箭头的实线可以表示处理器在分区2中查找到目标数据3，处理器和 分区1或硬盘框a之间的带有箭头的虚线可以表示处理器查找目标数据3的范围包括分区1和硬盘框a。
若接口卡a在第一目标数据持久化后接收到读取指令1，接口卡a可以根据读取指令1，在相连的存储器(例如存储器a1或存储器a2或存储器a3)中获取目标数据3的全部或一部分。
参考步骤S405或S605，假设接口卡a将第一目标数据同步备份至存储器a1，那么，若缓存中的目标数据3尚未持久化或尚未全部持久化，而缓存出现异常，接口卡a可以在存储器a1中获取到目标数据3的全部或一部分，有利于提高缓存中数据的可用性。
参考步骤S406和S407，或者参考步骤S606和S607，假设控制器a将目标数据1备份存储器c1或控制器b将目标数据2备份至存储器c2，并且，在缓存异常后，控制器a将备份的数据转移至存储器a2，或者，控制器b将备份的数据转移至存储器a3，那么，若缓存中的目标数据3尚未持久化或尚未全部持久化，而缓存出现异常，接口卡a可以在存储器a2或存储器a3中获取到目标数据3的全部或一部分，有利于提高缓存中数据的可用性。
可选的，读取指令1可以指示数据3的查找范围，例如指示在接口卡a的缓存和硬盘框a下的存储器中查询数据3。本申请实施例不限定接口卡a查询数据3中目标数据3以外的其他数据的方式，可选的，接口卡a同样可以在缓存和相连的存储器中查询该其他数据，或者，可以仅在相连的存储器中查询该其他数据。接口卡a查询到该其他数据后，可以向控制器a返回该其他数据，若未找到该其他数据，控制器a可以通知控制器查询失败。
本申请实施例中，读取指令1可以包括一条或多条指令，例如，读取指令1可以包括指示查询目标数据3的读取指令1-1和指示查询目标数据3以外的其他数据的读取指令1-2。读取指令1-1可以指示在接口卡a的缓存和接口卡a下的存储器中查询目标数据3，读取指令1-2指示在接口卡a下的存储器中查询该其他数据。
以目标数据3为描述业务数据3的元数据3为例，假设元数据3描述了业务数据3在存储器a3中的存储位置，接口卡a可以缓存中获取到元数据3之后，可以根据元数据3在存储器a3中获取业务数据3。
S704、控制器a向应用服务器发送查询结果1。
若控制器a接收到接口卡a返回的数据3，控制器a可以从中获取到业务数据3，向应用服务器发送携带业务数据3的查询结果1。
若控制器a在一定时长内未接收到接口卡a返回的数据3，或者接口卡a反馈查询失败，控制器a可以向应用服务器发送未携带业务数据3的查询结果1，该查询结果指示无法查找到业务数据3。
参考图7，假设目标数据3保存在分区2中，可以理解为目标数据3为接口卡a为控制器b存储的数据。这样，即使控制器b发生故障，由于接口卡a可以为控制器a在分区2中查询控制器b的数据，并由控制器a发送给应用服务器，有利于保证接口卡a的缓存中控制器b的数据的可用性，从而有利于提高存储系统的可靠性。
以下介绍控制器b通过接口卡a提供数据查询业务的过程。
图8示例性示出控制器b通过接口卡a查询数据的方法流程。图8中应用服务器以外的结构可以例如为图3-2所示的存储节点，为了简化附图，图8未具体示出接口卡b和接口卡 b下的存储器，也未示出控制器a和控制器b中的PCIE转接设备。本申请提供的数据处理方法另一种可能的实施例可以包括如下步骤S801-S804。
S801、应用服务器向控制器b发送读请求2；
步骤S801可以参考前文步骤S701理解，例如，读请求2可以参考读请求1的相关描述进行理解。
本申请实施例不限定读请求1和读请求2来自同一个设备，例如，二者可以来自不同的应用服务器，或者，一个来自应用服务器，另一个来自软件系统。
S802、控制器b向接口卡a发送读取指令2；
控制器b接收到读请求2后，可以向接口卡a发送读取指令2，读取指令2用于指示查询数据4。
步骤S802可以参考步骤S702理解。和S702不同的，参考图3-2所示的连接方式，由于接口卡a插接于控制器a，控制器b向接口卡a发送读取指令2所经过的线路与控制器a向接口卡a发送读取指令1所经过的线路不同。
S803、接口卡a在缓存和相连的存储器中查询读取指令2指示读取的数据4并提供给控制器b；
接口卡a接收到读取指令2后，可以在缓存和相连的存储器(例如存储器a1、存储器a2和存储器a3)中查询读取指令2指示读取的数据4。
步骤S803可以参考步骤S703理解。
例如，数据4可以包括目标数据4，目标数据4可以为第一目标数据的全部或一部分。其中，第一目标数据可以为S403所提到的目标数据1或S603所提到的目标数据2。由于接口卡a通过缓存暂存第一目标数据，若接口卡a在第一目标数据持久化之前接收到读取指令2，接口卡a可以根据读取指令2，在缓存中获取目标数据4的全部或一部分。
例如，读取指令2可以包括一条或多条指令，例如，读取指令2可以包括指示查询目标数据4的读取指令2-1和指示查询目标数据4以外的其他数据的读取指令2-2。读取指令2-1可以指示在接口卡a的缓存和接口卡a下的存储器中查询目标数据4，读取指令2-2指示在接口卡a下的存储器中查询该其他数据。
例如，若接口卡a在第一目标数据持久化后接收到读取指令2，接口卡a可以根据读取指令2，在相连的存储器(例如存储器a1或存储器a2或存储器a3)中获取目标数据4的全部或一部分。
例如，参考步骤S405或S605，假设接口卡a将第一目标数据同步备份至存储器a1，那么，若缓存中的目标数据4尚未持久化或尚未全部持久化，而缓存出现异常，接口卡a可以在存储器a1中获取到目标数据4的全部或一部分，有利于提高缓存中数据的可用性。
例如，参考步骤S406和S407，或者参考步骤S606和S607，假设控制器a将目标数据1备份存储器c1或控制器b将目标数据2备份至存储器c2，并且，在缓存异常后，控制器a将备份的数据转移至存储器a2，或者，控制器b将备份的数据转移至存储器a3，那么，若缓存中的目标数据4尚未持久化或尚未全部持久化，而缓存出现异常，接口卡a可以在存储器a2或存储器a3中获取到目标数据4的全部或一部分，有利于提高缓存中数据的可用性。
S804、控制器b向应用服务器发送查询结果2。
若控制器b接收到接口卡a返回的数据4，控制器b可以从中获取到业务数据4，向应用服务器发送携带业务数据4的查询结果。
若控制器b在一定时长内未接收到接口卡a返回的数据4，或者接口卡a反馈查询失败，控制器b可以向应用服务器发送未携带业务数据4的查询结果，该查询结果指示无法查找到业务数据4。
参考图8，假设目标数据4保存在分区1中，可以理解为目标数据4为接口卡a为控制器a存储的数据。这样，即使控制器a发生故障，由于接口卡a可以为控制器b在分区1中查询控制器a的数据，并由控制器b发送给应用服务器，有利于保证接口卡a的缓存中控制器a的数据的可用性，从而有利于提高存储系统的可靠性。
控制器b可以通过接口卡b提供数据查询业务，参考图3-2，由于接口卡b插接于控制器b，因此，控制器b通过接口卡b提供数据查询业务的过程可以参考图7对应的实施例，具体的，控制器b所执行的步骤可以参考图7对应的实施例中控制器a所执行的步骤进行理解，接口卡b所执行的步骤可以参考图7对应的实施例中接口卡a所执行的步骤进行理解。
控制器a可以通过接口卡b提供数据查询业务，参考图3-2，由于接口卡b插接于控制器b，因此，控制器a通过接口卡b提供数据存储业务的过程可以参考图8对应的实施例，具体的，控制器a所执行的步骤可以参考图8对应的实施例中控制器b所执行的步骤进行理解，接口卡b所执行的步骤可以参考图8对应的实施例中接口卡a所执行的步骤进行理解。
图3-3对应的存储节点中各控制器所提供的数据存储业务和数据查询业务可以分别参考前文介绍的图3-2对应的存储节点中相应控制器所提供的相应业务。例如，通过将图4对应的实施例中的接口卡a替换为硬盘框a，可以确定图3-3所示的控制器a通过硬盘框a提供数据存储业务的过程。
上述详细阐述了本申请实施例提供的存储系统和存储系统所涉及的数据处理方法，为了便于更好的实施本申请实施例的上述方案，相应地，下面还提供用于配合实施上述方案的相关设备。
参见图9，图9是本申请实施例提供的一种共享接口设备的结构示意图，该共享接口设备可以是上述图3-1的方法实施例中的共享接口设备a或共享接口设备b，或，图3-2或图3-3的方法实施例中的接口卡a或接口卡b，可以执行相应实施例方法中相应共享接口设备为执行主体的方法和步骤。第一控制器和第二控制器分别通过共享接口设备与至少一个存储器通信。如图9所示，该共享接口设备900包括接收模块901、存储模块902和查询模块903。
其中，接收模块901用于接收第一控制器发送的写入指令。具体实现方式请参考图4中步骤S402的相关描述，或者参考图6中步骤S602的相关描述，此处不再赘述。
存储模块902用于在自身的缓存中暂存写入指令所指示写入的第一数据，还用于把缓存中暂存的第一数据异步写入至少一个存储器中的第一存储器。具体实现方式请参考步骤S403的相关描述，例如具体参考步骤S4031或步骤S4031至步骤S4033的相关描述，或者，参考步骤S603的相关描述，例如具体参考步骤S6031或S6031至S6033的相关描述，此处不再赘述。
接收模块901还用于在第一控制器发生故障后，接收第二控制器发送的读取指令，读取指令指示查询第二数据，第二数据为第一数据中的全部或一部分。具体实现方式请参考图7中步骤S702的相关描述，或者，参考图8中步骤S802的相关描述，此处不再赘述。
查询模块903用于根据读取指令，在缓存中获取第二数据中的全部或一部并提供给第二控制器。具体实现方式请参考图7中步骤S703的相关描述，或者，参考图8中步骤S803的相关描述，此处不再赘述。
可选的，缓存包括第一分区和第二分区，第一分区用于为第一控制器暂存数据不为所述第二控制器暂存数据，第二分区用于为第二控制器暂存数据不为所述第一控制器暂存数据，查询模块903在缓存中获取第二数据的全部或者一部分的查询范围包括第一分区和第二分区。
可选的，写入指令指示将第一数据写入第一存储器，存储模块902具体用于：在第一分区暂存第一数据。存储模块902还用于：将第一分区中暂存的第一数据和第二分区中暂存的第二数据连续发送至第一存储器，第一数据包括第一控制器指示写入第一存储器的数据，第二数据包括第二控制器指示写入第一存储器的数据。
可选的，至少一个存储器还包括第二存储器，第二存储器的访存时延小于第一存储器，存储模块902还用于：在接收到写入指令后，将第一数据同步备份至第二存储器；当缓存出现异常，根据读取指令，在第二存储器中获取第二数据的全部或一部分并提供给第二控制器。
可选的，存储系统还包括与第一控制器相连的第三存储器，查询模块903还用于：在接收模块901接收到读取指令后，当缓存出现异常，根据读取指令，在相连的第四存储器中获取第二数据的全部或一部分并提供给第二控制器。其中，第四存储器中第二数据的全部或一部分为第一控制器在缓存出现异常后，通过共享接口设备从第三存储器中转发至第四存储器中的，第三存储器中的数据包括第一控制器备份的第一数据。
可选的，数据包括业务数据和/或业务数据的元数据，其中，业务数据为第一控制器接收的数据写入请求所请求写入的数据。
可选的，共享接口设备为接口卡或硬盘框，其中，接口卡插接于第一控制器或第二控制器中，硬盘框用于安装至少一个存储器。
可选的，共享接口设备与第一控制器和/或第二控制器通过快捷外设互连PCIE协议通信。
本申请实施例还提供一种计算设备，第一控制器和第二控制器分别通过计算设备与至少一个存储器通信，计算设备包括存储器和处理器，存储器包括缓存，处理器执行存储器存储的计算机指令，以使计算设备执行前文介绍的共享接口设备a或共享接口设备b所执行的方法。可选的，该计算设备可以例如为图3-2所示的接口卡a或接口卡b，或者，例如为图3-3所示的硬盘框a或硬盘框b。
本申请还提供一种计算机可读存储介质，其中，计算机可读存储介质存储有计算机程序，当该计算机程序被处理器执行时，可以实现上述方法实施例中记载的任意一种的部分或全部步骤。
本发明实施例还提供一种计算机程序，该计算机程序包括指令，当该计算机程序被计算机执行时，使得计算机可以执行任意一种发放区域资源的方法的部分或全部步骤。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其它实施例的相关描述。
本领域普通技术人员可以理解，前述的计算机可读存储介质包括：U盘、移动硬盘、磁碟、光盘、RAM、SSD或者非易失性存储器(non-volatile memory)等各种可以存储程序代码的非短暂性的(non-transitory)机器可读介质。
需要说明的是，对于前述的各方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本申请并不受所描述的动作顺序的限制，因为依据本申请，某些步骤可能可以采用其它顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作和模块并不一定是本申请所必须的。本申请实施例涉及的“A和/或B”可以理解为包括“A和B”以及“A或B”这两种方案。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”和“第四”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的术语在适当情况下可以互换，这仅仅是描述本申请的实施例中对相同属性的对象在描述时所采用的区分方式。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置，可通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如上述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性或其它的形式。
上述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制。

Claims (28)

  1. 一种存储系统，其特征在于，所述存储系统包括第一控制器和第二控制器，所述第一控制器和所述第二控制器分别通过设置有缓存的共享接口设备与至少一个存储器通信；
    所述第一控制器，用于向所述共享接口设备发送指示写入第一数据的写入指令；
    所述共享接口设备，用于在所述缓存中暂存所述第一数据，还用于把所述缓存中暂存的所述第一数据异步写入所述至少一个存储器中的第一存储器；
    所述第二控制器，用于在所述第一控制器发生故障后，向所述共享接口设备发送读取指令，所述读取指令指示查询第二数据，所述第二数据为所述第一数据中的全部或一部分；
    所述共享接口设备，还用于根据所述读取指令，在所述缓存中获取所述第二数据的全部或者一部分并提供给所述第二控制器。
  2. 根据权利要求1所述的存储系统，其特征在于：
    所述第二控制器，还用于向所述共享接口设备发送指示写入第三数据的写入指令；
    所述共享接口设备，还用于在所述缓存中暂存所述第三数据，还用于把所述缓存中暂存的所述第三数据异步写入所述第一存储器。
  3. 根据权利要求2所述的存储系统，其特征在于，所述缓存包括第一分区和第二分区，所述第一分区用于为所述第一控制器暂存数据，所述第二分区用于为所述第二控制器暂存数据，所述共享接口设备在所述缓存中获取所述第二数据的全部或者一部分的查询范围包括所述第一分区和所述第二分区。
  4. 根据权利要求3所述的存储系统，其特征在于，所述共享接口设备具体用于：
    在所述第一分区暂存所述第一数据，在所述第二分区暂存所述第三数据；
    将所述第一分区中暂存的所述第一数据和所述第二分区中暂存的所述第三数据连续发送至所述第一存储器。
  5. 根据权利要求1至4中任一项所述的存储系统，其特征在于，所述至少一个存储器还包括第二存储器，所述第二存储器的访存时延小于所述第一存储器，所述共享接口设备还用于：
    在接收到所述写入指令后，将所述第一数据同步备份至所述第二存储器；
    当所述缓存出现异常，根据所述读取指令，在所述第二存储器中获取所述第二数据的全部或一部分并提供给所述第二控制器。
  6. 根据权利要求1至5中任一项所述的存储系统，其特征在于，所述存储系统还包括与所述第一控制器相连的第三存储器，所述第一控制器还用于：
    将所述第一数据备份至所述第三存储器；
    当所述缓存出现异常，将所述第三存储器中备份的数据通过所述共享接口设备转发至所述至少一个存储器中的第四存储器；
    所述共享接口设备还用于：
    当所述缓存出现异常，根据所述读取指令，在所述第四存储器中获取所述第二数据的全 部或一部分并提供给所述第二控制器。
  7. 根据权利要求1至6中任一项所述的存储系统，其特征在于，所述数据包括业务数据和/或所述业务数据的元数据，其中，所述业务数据为所述第一控制器接收的数据写入请求所请求写入的数据。
  8. 根据权利要求1至7中任一项所述的存储系统，其特征在于，所述共享接口设备为接口卡或硬盘框，其中，所述接口卡插接于所述第一控制器或所述第二控制器中，所述硬盘框用于安装所述至少一个存储器。
  9. 根据权利要求1至8中任一项所述存储系统，其特征在于，所述共享接口设备与所述第一控制器和/或所述第二控制器通过快捷外设互连PCIE协议通信。
  10. 根据权利要求1至9中任一项所述的存储系统，其特征在于，所述至少一个存储器中的每个存储器仅有单个与所述共享接口设备通信的端口。
  11. 一种存储系统，其特征在于，所述存储系统包括第一控制器和第二控制器，所述第一控制器和所述第二控制器分别通过设置有缓存的共享接口设备与至少一个存储器通信；
    所述第一控制器，用于向所述共享接口设备发送指示写入第一数据的写入指令；
    所述第二控制器，用于向所述共享接口设备发送指示写入第三数据的写入指令；
    所述共享接口设备，还用于在所述缓存中暂存所述第一数据以及所述第三数据，还用于把所述缓存中暂存的所述第一数据、所述第三数据异步写入所述至少一个存储器中的第一存储器。
  12. 一种数据处理方法，其特征在于，存储系统包括第一控制器和第二控制器，所述第一控制器和所述第二控制器分别通过设置有缓存的共享接口设备与至少一个存储器通信，所述方法包括：
    所述第一控制器向所述共享接口设备发送知识写入第一数据的写入指令；
    所述共享接口设备在所述缓存中暂存所述第一数据，把所述缓存中暂存的所述第一数据异步写入所述至少一个存储器中的第一存储器；
    所述第二控制器在所述第一控制器发生故障后，向所述共享接口设备发送读取指令，所述读取指令指示查询第二数据，所述第二数据为所述第一数据中的全部或一部分；
    所述共享接口设备根据所述读取指令，在所述缓存中获取所述第二数据中的全部或一部分并提供给所述第二控制器。
  13. 根据权利要求12所述的方法，其特征在于，所述方法还包括：
    所述第二控制器向所述共享接口设备发送指示写入第三数据的写入指令；
    所述共享接口设备在所述缓存中暂存所述第三数据，把所述缓存中暂存的所述第三数据异步写入所述第一存储器。
  14. 根据权利要求13所述的方法，其特征在于，所述缓存包括第一分区和第二分区，所述第一分区用于为所述第一控制器暂存数据，所述第二分区用于为所述第二控制器暂存数据，所述共享接口设备在所述缓存中获取所述第二数据的全部或者一部分的查询范围包括所述第一分区和所述第二分区。
  15. 根据权利要求14所述的方法，其特征在于，所述共享接口设备在所述缓存中暂存所述第一数据以及所述第三数据，包括：
    所述共享接口设备在所述第一分区暂存所述第一数据，在所述第二分区暂存所述第三数据；
    所述共享接口设备把所述缓存中暂存的所述第一数据以及所述第三数据异步写入所述第一存储器，包括：
    所述共享接口设备将所述第一分区中暂存的所述第一数据和所述第二分区中暂存的所述第三数据连续发送至所述第一存储器。
  16. 根据权利要求12至15中任一项所述的方法，其特征在于，所述至少一个存储器还包括第二存储器，所述第二存储器的访存时延小于所述第一存储器，所述方法还包括：
    所述共享接口设备在接收到所述写入指令后，将所述第一数据同步备份至所述第二存储器；
    当所述缓存出现异常，所述共享接口设备根据所述读取指令，在所述第二存储器中获取所述第二数据的全部或一部分并提供给所述第二控制器。
  17. 根据权利要求12至16中任一项所述的方法，其特征在于，所述存储系统还包括与所述第一控制器相连的第三存储器，所述方法还包括：
    所述第一控制器将所述第一数据备份至所述第三存储器；
    当所述缓存出现异常，所述第一控制器将所述第三存储器中备份的数据通过所述共享接口设备转发至所述至少一个存储器中的第四存储器；
    在所述共享接口设备接收到所述读取指令后，当所述缓存出现异常，所述共享接口设备根据所述读取指令，在所述第四存储器中获取所述第二数据的全部或一部分并提供给所述第二控制器。
  18. 根据权利要求12至17中任一项所述的方法，其特征在于，所述数据包括业务数据和/或所述业务数据的元数据，其中，所述业务数据为所述第一控制器接收的数据写入请求所请求写入的数据。
  19. 根据权利要求12至18中任一项所述的方法，其特征在于，所述共享接口设备为接口卡或硬盘框，其中，所述接口卡插接于所述第一控制器或所述第二控制器中，所述硬盘框用于安装所述至少一个存储器。
  20. 根据权利要求12至19中任一项所述的方法，其特征在于，所述共享接口设备与所述第一控制器和/或所述第二控制器通过快捷外设互连PCIE协议通信。
  21. 根据权利要求12至20中任一项所述的方法，其特征在于，所述至少一个存储器中的每个存储器仅有单个与所述共享接口设备通信的端口。
  22. 一种数据处理方法，其特征在于，存储系统包括第一控制器和第二控制器，所述第一控制器和所述第二控制器分别通过设置有缓存的共享接口设备与至少一个存储器通信，所述方法包括：
    所述第一控制器向所述共享接口设备发送指示写入第一数据的写入指令；
    所述第二控制器向所述共享接口设备发送指示写入第三数据的写入指令；
    所述共享接口设备在所述缓存中暂存所述第一数据以及所述第三数据，把所述缓存中暂存的所述第一数据、所述第三数据异步写入所述至少一个存储器中的第一存储器。
  23. 一种数据处理方法，其特征在于，存储系统包括第一控制器和第二控制器，所述第一控制器和所述第二控制器分别通过设置有缓存的共享接口设备与至少一个存储器通信，所述方法包括：
    所述共享接口设备接收所述第一控制器发送的指示写入第一数据的写入指令；
    所述共享接口设备在所述缓存中暂存所述第一数据，把所述缓存中暂存的所述第一数据异步写入所述至少一个存储器中的第一存储器；
    在所述第一控制器发生故障后，所述共享接口设备接收所述第二控制器发送的读取指令，所述读取指令指示查询第二数据，所述第二数据为所述第一数据中的全部或一部分；
    所述共享接口设备根据所述读取指令，在所述缓存中获取所述第二数据中的全部或一部并提供给所述第二控制器。
  24. 一种共享接口设备，其特征在于，包括接收模块、存储模块和查询模块；
    所述接收模块用于接收第一控制器发送的指示写入第一数据的写入指令，所述第一控制器和第二控制器分别通过所述共享接口设备与至少一个存储器通信；
    所述存储模块用于在自身的缓存中暂存所述第一数据，把所述缓存中暂存的所述第一数据异步写入所述至少一个存储器中的第一存储器；
    所述接收模块还用于在所述第一控制器发生故障后，接收所述第二控制器发送的读取指令，所述读取指令指示查询第二数据，所述第二数据为所述第一数据中的全部或一部分；
    所述查询模块用于根据所述读取指令，在所述缓存中获取所述第二数据中的全部或一部并提供给所述第二控制器。
  25. 一种数据处理方法，其特征在于，存储系统包括第一控制器和第二控制器，所述第一控制器和所述第二控制器分别通过设置有缓存的共享接口设备与至少一个存储器通信，所述方法包括：
    所述共享接口设备接收所述第一控制器发送的指示写入第一数据的写入指令，以及所述第二控制器发送的指示写入第三数据的写入指令；
    所述共享接口设备在所述缓存中暂存所述第一数据以及所述第三数据，把所述缓存中暂存的所述第一数据、所述第三数据异步写入所述至少一个存储器中的第一存储器。
  26. 一种共享接口设备，其特征在于，包括接收模块、存储模块和查询模块；
    所述接收模块接收所述第一控制器发送的指示写入第一数据的写入指令，以及所述第二控制器发送的指示写入第三数据的写入指令，所述第一控制器和第二控制器分别通过所述共享接口设备与至少一个存储器通信；
    所述存储模块用于在自身的缓存中暂存所述第一数据以及所述第三数据，把所述缓存中暂存的所述第一数据、所述第三数据异步写入所述至少一个存储器中的第一存储器。
  27. 一种计算设备，其特征在于，第一控制器和所述第二控制器分别通过所述计算设备与至少一个存储器通信，所述计算设备包括存储器和处理器，所述存储器包括缓存，所述处理器执行存储器存储的计算机指令，使得所述计算设备执行权利要求23或25所述的方法。
  28. 根据权利要求27所述的计算设备，其特征在于，所述计算设备为接口卡或硬盘框，其中，所述接口卡插接于所述第一控制器或所述第二控制器中，所述硬盘框用于安装所述至少一个存储器。
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