WO2023098256A1 - Procédé et appareil de fonctionnement de réseau de neurones artificiels, puce, dispositif électronique, et support de stockage - Google Patents

Procédé et appareil de fonctionnement de réseau de neurones artificiels, puce, dispositif électronique, et support de stockage Download PDF

Info

Publication number
WO2023098256A1
WO2023098256A1 PCT/CN2022/121427 CN2022121427W WO2023098256A1 WO 2023098256 A1 WO2023098256 A1 WO 2023098256A1 CN 2022121427 W CN2022121427 W CN 2022121427W WO 2023098256 A1 WO2023098256 A1 WO 2023098256A1
Authority
WO
WIPO (PCT)
Prior art keywords
sub
convolution
convolution kernel
input data
result
Prior art date
Application number
PCT/CN2022/121427
Other languages
English (en)
Chinese (zh)
Inventor
徐东
熊先奎
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Publication of WO2023098256A1 publication Critical patent/WO2023098256A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/15—Correlation function computation including computation of convolution operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0464—Convolutional networks [CNN, ConvNet]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the data rearrangement mode corresponding to the first sub-convolution kernel group is set so that the position of each part of the data in the input data remains unchanged.
  • the operation of the ith sub-convolution kernel group after the operation of the ith sub-convolution kernel group is completed, it is necessary to judge the size of the i value, and when the i value is less than Wk*Hk, update the i value to i+1, and load the i+1th Sub-convolution kernel group, execute the operation step again; when the value of i is equal to Wk*Hk, the operation step ends at this time, and the data at the effective position in the i-th accumulation result will be used as the output result of the neural network operation.
  • step division of the above various methods is only for the sake of clarity of description. During implementation, it can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent. ; Adding insignificant modifications or introducing insignificant designs to the algorithm or process, but not changing the core design of the algorithm and process are all within the scope of protection of this patent.
  • the convolution unit is used to convolve each sub-convolution kernel group and the rearranged input data corresponding to each sub-convolution kernel group to obtain a convolution result corresponding to each sub-convolution kernel group, and to convolve each sub-convolution kernel group
  • the corresponding convolution result is output to the addition unit;

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Biophysics (AREA)
  • Health & Medical Sciences (AREA)
  • Software Systems (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Molecular Biology (AREA)
  • Artificial Intelligence (AREA)
  • Computational Linguistics (AREA)
  • General Health & Medical Sciences (AREA)
  • Evolutionary Computation (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Neurology (AREA)
  • Algebra (AREA)
  • Databases & Information Systems (AREA)
  • Complex Calculations (AREA)

Abstract

La présente demande concerne un procédé et un appareil de fonctionnement de réseau de neurones artificiels, une puce, un dispositif électronique et un support de stockage. Le procédé de fonctionnement de réseau de neurones artificiels consiste à : acquérir des données d'entrée et des groupes de noyaux de sous-convolution Wk*Hk pour une opération de réseau de neurones artificiels, et exécuter une étape d'opération, N noyaux de convolution Wk*Hk*C de l'opération de réseau de neurones artificiels étant divisés en noyaux de sous-convolution N*Wk*Hk 1*1*C, et les noyaux de sous-convolution N*Wk*Hk 1*1*C étant divisés en groupes de noyaux de sous-convolution Wk*Hk. L'étape d'opération consiste à : réarranger les données d'entrée sur la base d'un mode de réarrangement de données correspondant à chaque groupe de noyaux de sous-convolution de façon à obtenir des données d'entrée réarrangées correspondant à chaque groupe de noyaux de sous-convolution ; et effectuer une convolution pour chaque groupe de noyaux de sous-convolution avec les données d'entrée réarrangées correspondant au groupe de noyaux de sous-convolution pour obtenir un résultat de convolution du groupe de noyaux de sous-convolution ; cumuler les résultats de convolution des groupes de noyaux de sous-convolution pour obtenir un résultat d'accumulation, et prendre des données situées à une position valide dans le résultat d'accumulation en tant que résultat de sortie de l'opération de réseau de neurones artificiels.
PCT/CN2022/121427 2021-12-03 2022-09-26 Procédé et appareil de fonctionnement de réseau de neurones artificiels, puce, dispositif électronique, et support de stockage WO2023098256A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111466758.0A CN116306840A (zh) 2021-12-03 2021-12-03 神经网络运算方法、装置、芯片、电子设备和存储介质
CN202111466758.0 2021-12-03

Publications (1)

Publication Number Publication Date
WO2023098256A1 true WO2023098256A1 (fr) 2023-06-08

Family

ID=86611499

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/121427 WO2023098256A1 (fr) 2021-12-03 2022-09-26 Procédé et appareil de fonctionnement de réseau de neurones artificiels, puce, dispositif électronique, et support de stockage

Country Status (2)

Country Link
CN (1) CN116306840A (fr)
WO (1) WO2023098256A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116861149A (zh) * 2023-09-05 2023-10-10 之江实验室 卷积运算的优化方法、装置及处理器

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116881618A (zh) * 2023-08-25 2023-10-13 之江实验室 通用矩阵乘计算优化方法、装置及处理器

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108241890A (zh) * 2018-01-29 2018-07-03 清华大学 一种可重构神经网络加速方法及架构
US20190065896A1 (en) * 2017-08-23 2019-02-28 Samsung Electronics Co., Ltd. Neural network method and apparatus
US20190188237A1 (en) * 2017-12-18 2019-06-20 Nanjing Horizon Robotics Technology Co., Ltd. Method and electronic device for convolution calculation in neutral network
CN111260037A (zh) * 2020-02-11 2020-06-09 深圳云天励飞技术有限公司 图像数据的卷积运算方法、装置、电子设备及存储介质
CN112215745A (zh) * 2020-09-30 2021-01-12 深圳云天励飞技术股份有限公司 图像处理方法、装置及电子设备

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190065896A1 (en) * 2017-08-23 2019-02-28 Samsung Electronics Co., Ltd. Neural network method and apparatus
US20190188237A1 (en) * 2017-12-18 2019-06-20 Nanjing Horizon Robotics Technology Co., Ltd. Method and electronic device for convolution calculation in neutral network
CN108241890A (zh) * 2018-01-29 2018-07-03 清华大学 一种可重构神经网络加速方法及架构
CN111260037A (zh) * 2020-02-11 2020-06-09 深圳云天励飞技术有限公司 图像数据的卷积运算方法、装置、电子设备及存储介质
CN112215745A (zh) * 2020-09-30 2021-01-12 深圳云天励飞技术股份有限公司 图像处理方法、装置及电子设备

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116861149A (zh) * 2023-09-05 2023-10-10 之江实验室 卷积运算的优化方法、装置及处理器
CN116861149B (zh) * 2023-09-05 2024-01-09 之江实验室 卷积运算的优化方法、装置及处理器

Also Published As

Publication number Publication date
CN116306840A (zh) 2023-06-23

Similar Documents

Publication Publication Date Title
WO2023098256A1 (fr) Procédé et appareil de fonctionnement de réseau de neurones artificiels, puce, dispositif électronique, et support de stockage
CN112214726B (zh) 运算加速器
CN109102065B (zh) 一种基于PSoC的卷积神经网络加速器
EP3757901A1 (fr) Module de distribution de tenseurs en fonction d'un calendrier
CN109447241B (zh) 一种面向物联网领域的动态可重构卷积神经网络加速器架构
JP7074831B2 (ja) ネットワークオンチップによるデータ処理方法及び装置
WO2019205617A1 (fr) Procédé et appareil de calcul pour la multiplication de matrices
US20190212982A1 (en) Processor, information processing apparatus and operation method for processor
CN111461311B (zh) 基于众核处理器的卷积神经网络运算加速方法及装置
CN110222818B (zh) 一种用于卷积神经网络数据存储的多bank行列交织读写方法
CN107742150A (zh) 一种卷积神经网络的数据处理方法和装置
CN109993293B (zh) 一种适用于堆叠式沙漏网络的深度学习加速器
US11579921B2 (en) Method and system for performing parallel computations to generate multiple output feature maps
CN111047036B (zh) 神经网络处理器、芯片和电子设备
US20200364047A1 (en) High throughput neural network operations using inter-layer memory layout transformation
WO2023065983A1 (fr) Appareil informatique, dispositif de traitement de réseau neuronal, puce et procédé de traitement de données
CN110991619A (zh) 神经网络处理器、芯片和电子设备
US20200225884A1 (en) Machine perception and dense algorithm integrated circuit
CN110377874B (zh) 卷积运算方法及系统
CN110414672B (zh) 卷积运算方法、装置及系统
CN115328439A (zh) 一种面向hpc/ai应用的增量式矩阵乘加速器
KR20200138413A (ko) 네트워크 온칩 데이터 처리 방법 및 장치
CN116431562B (zh) 一种基于加速处理器的多头注意力机制融合计算分配方法
CN111047035B (zh) 神经网络处理器、芯片和电子设备
US20230128421A1 (en) Neural network accelerator

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22900064

Country of ref document: EP

Kind code of ref document: A1