WO2023098207A1 - 多Pass编程NAND的RAID优化方法、装置及计算机设备 - Google Patents

多Pass编程NAND的RAID优化方法、装置及计算机设备 Download PDF

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WO2023098207A1
WO2023098207A1 PCT/CN2022/117585 CN2022117585W WO2023098207A1 WO 2023098207 A1 WO2023098207 A1 WO 2023098207A1 CN 2022117585 W CN2022117585 W CN 2022117585W WO 2023098207 A1 WO2023098207 A1 WO 2023098207A1
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programming
pass
raid
nand
completed
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PCT/CN2022/117585
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French (fr)
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王猛
徐伟华
郭芳芳
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深圳忆联信息系统有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0689—Disk arrays, e.g. RAID, JBOD
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0608—Saving storage space on storage systems
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the technical field of storage systems, in particular to a RAID optimization method, device, computer equipment and storage medium for multi-pass programming NAND.
  • SSD Solid State Disk, solid state disk
  • HDD Hard Disk Drive, hard disk drive
  • RAID is generally used to improve reliability.
  • N pieces of user data one piece of verification data is generated by the RAID engine and written into the NAND. Due to the requirement of multi-pass programming, RAID verification data must also be transmitted to NAND multiple times, so the corresponding verification data needs to be buffered until all the pass programming of the corresponding page is completed, thus increasing the demand for SSD memory.
  • the RAID engine uses a high-speed memory (such as SRAM) inside the SOC, its space is limited, and the verification data needs to be backed up to a slow memory (such as DRAM). This copy process has a great impact on performance.
  • a kind of RAID optimization method of multi-Pass programming NAND, described method comprises:
  • the Parity buffer can be released after the programming of the corresponding pass is completed, and there is no need to keep it until all the programming of the pass is completed.
  • the method also includes:
  • the user data of the RAID stripe is encoded by the RAID engine to generate the corresponding Parity data
  • the corresponding Parity buffer can be released.
  • the method also includes:
  • each Pass programming of each Page is interleaved
  • the method also includes:
  • a RAID optimization device for multi-Pass programming NAND comprising:
  • Obtaining module described obtaining module is used for obtaining the RAID optimization request of multi-Pass programming NAND;
  • described coding module is used for according to the RAID optimization request of described multi-Pass programming NAND when each Pass programming, utilizes the user data of belonging RAID stripe cache to carry out RAID engine coding again;
  • Generating module described generating module is used for generating corresponding Parity data in real time by RAID engine coding
  • a release module which is used to release Parity after the programming of the corresponding Pass is completed
  • the buffer does not need to be kept until all Pass programming is completed.
  • the device also includes a programming module, and the programming module is used for:
  • the user data of the RAID stripe is encoded by the RAID engine to generate the corresponding Parity data
  • the corresponding Parity buffer can be released.
  • the programming module is also used for:
  • each Pass programming of each Page is interleaved
  • the device further includes a judging module, and the judging module is used for:
  • a computer device includes a memory, a processor, and a computer program stored in the memory and operable on the processor, and the processor implements the steps of any one of the above methods when executing the computer program.
  • a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of any one of the above-mentioned methods are realized.
  • the RAID optimization method, device, computer equipment and storage medium of above-mentioned multi-Pass programming NAND obtain the RAID optimization request of multi-Pass programming NAND;
  • the cached user data is re-coded by the RAID engine;
  • the corresponding Parity data is generated in real time through the RAID engine code;
  • the Parity buffer can be released after the programming of the corresponding Pass is completed, and there is no need to keep it until all the Pass programming is completed.
  • This application aims at the scenario of multi-pass programming.
  • RAID verification data is dynamically generated without caching the corresponding verification data. Real-time generation of RAID verification data reduces the impact on SOC Memory requirements, thereby improving the performance of solid-state drives and reducing costs.
  • Fig. 1 is a schematic diagram of a traditional Multi-Pass NAND RAID model
  • Figure 2 is another traditional Multi-Pass NAND Schematic diagram of the RAID model
  • Fig. 3 is the schematic flow chart of the RAID optimization method of multi-Pass programming NAND in an embodiment
  • Fig. 4 is a schematic flow chart of the corresponding NAND multi-Pass writing process in one embodiment
  • Fig. 5 is the schematic flow sheet of the RAID optimization method of multi-Pass programming NAND in another embodiment
  • Fig. 6 is the schematic diagram of the RAID model when Multi-Pass NAND programming in an embodiment
  • Fig. 7 is the structural block diagram of the RAID optimization device of multi-Pass programming NAND in an embodiment
  • Fig. 8 is the structural block diagram of the RAID optimization device of multi-Pass programming NAND in another embodiment
  • Fig. 9 is the structural block diagram of the RAID optimization device of multi-Pass programming NAND in yet another embodiment
  • Figure 10 is a diagram of the internal structure of a computer device in one embodiment.
  • the typical NAND composition includes: DIE, a unit that can be operated independently and concurrently; Block, a unit that can be erased independently, after the data in each physical location in it is written, the entire Block must be erased before the next write; Page, Read and write unit, pages in the same physical block must be programmed in sequence: 0-> 1 -> 2 -> 3....
  • DIE a unit that can be operated independently and concurrently
  • Block a unit that can be erased independently, after the data in each physical location in it is written, the entire Block must be erased before the next write
  • Page Read and write unit, pages in the same physical block must be programmed in sequence: 0-> 1 -> 2 -> 3....
  • Page programming model is becoming more and more complex. Taking QLC as an example, it needs to program Page multiple times according to certain rules to reach a stable state. During this period, the data to be stored needs to be transferred to the NAND multiple times.
  • FIG. 1 it is a traditional Multi-Pass NAND Schematic diagram of the RAID model.
  • Data 0_0, Data 0_1, Data 0_2 .... Data 0_N-1 are N pieces of user data belonging to the same RAID stripe (called stripe 0).
  • the user data of RAID stripe 0 is encoded by the RAID engine to generate corresponding Parity data (Parity 0_N).
  • This N (user data) + 1 (RAID Parity data) is transferred to Page 0 of Block X of each DIE of the SSD for Pass 1 programming; and since the RAID Parity data needs to be transferred to NAND in the subsequent Pass, it is necessary to Keep the cache in memory.
  • FIG 2 it is another traditional Multi-Pass NAND Schematic diagram of the RAID model.
  • RAID is also required to be cached parity data.
  • the Parity data generated by the RAID engine will be backed up to the slow memory (large space, generally such as DRAM). This process can reduce SOC cost, but frequent memory copies have a great impact on overall performance.
  • this application proposes a RAID optimization method for multi-pass programming NAND, aiming at reducing the demand for SOC Memory in the multi-pass programming scenario.
  • a kind of RAID optimization method of multi-pass programming NAND is provided, and the method comprises:
  • Step 302 obtaining a RAID optimization request for multi-pass programming NAND
  • Step 304 according to the RAID optimization request of multi-pass programming NAND, when programming each pass, use the user data in the RAID stripe cache to re-encode the RAID engine;
  • Step 306 generating corresponding Parity data in real time through RAID engine encoding
  • step 308 the Parity buffer can be released after the programming of the corresponding Pass is completed, and there is no need to keep it until all the programming of the Pass is completed.
  • a RAID optimization method for multi-pass programming NAND is provided.
  • the method is aimed at the scene of multi-pass programming.
  • N user data needs to be transmitted to NAND multiple times, it is inevitable Need buffering.
  • one piece of RAID verification data corresponding to the N pieces of user data is regenerated each time, eliminating the need for cache backup of the RAID Parity Buffer.
  • the method further includes: judging whether all Pass programming of Page0 has been completed; if not, continue to initiate each DIE Page0 corresponding to Pass user data programming; if so, complete Page0 programming of each DIE.
  • FIG. 4 it is a corresponding NAND multi-pass writing flowchart in this embodiment.
  • the specific implementation steps are as follows:
  • the RAID engine encodes the user data of the RAID stripe to generate RAID verification data.
  • the RAID engine code is re-encoded by using the user data in the RAID stripe cache to generate the verification data in real time.
  • the Parity buffer can be released, and there is no need to keep it until all the programming of the pass is completed.
  • the RAID optimization request of the multi-Pass programming NAND by obtaining the RAID optimization request of the multi-Pass programming NAND; according to the RAID optimization request of the multi-Pass programming NAND, when programming each Pass, utilize the user data of the RAID stripe cache to re-encode the RAID engine;
  • the RAID engine code generates the corresponding Parity data in real time; the Parity buffer can be released after the programming of the corresponding Pass is completed, and there is no need to keep it until all the Pass programming is completed.
  • the above solution is aimed at the scenario of multi-pass programming.
  • the RAID verification data is dynamically generated without caching the corresponding verification data. By generating the RAID verification data in real time, the demand for SOC Memory is reduced, thereby improving the performance of solid-state drives. performance and reduce costs.
  • a RAID optimization method for multi-pass programming NAND is provided, the method also includes:
  • Step 502 generating corresponding Parity data by encoding the user data of RAID stripe 0 through the RAID engine
  • Step 504 transfer the user data and Parity data to Page 0 of each DIE of the SSD for Pass 1 programming;
  • Step 506 after Pass 1 programming is completed, the corresponding Parity buffer can be released;
  • Step 508 under the multi-Pass programming model, each Pass programming of each Page is interleaved
  • Step 510 after Pass 1 of all related interleaved programming Pages is completed, continue the programming of Pass 2 of RAID stripe 0 again.
  • Data 0_0, Data 0_1, Data 0_2 ... Data 0_N-1 are N pieces of user data belonging to the same RAID stripe (called stripe 0).
  • the user data of RAID stripe 0 is encoded by the RAID engine to generate corresponding Parity data (Parity 0_N).
  • N user data passes through the RAID engine again to generate Parity 0_N. Transfer to Block X Page 0 of each DIE of the SSD for Pass 2 programming, and release the Parity 0_N buffer after completion.
  • FIGS. 1-6 are shown sequentially as indicated by the arrows, these steps are not necessarily executed sequentially in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in Figures 1-6 may include a plurality of sub-steps or stages, these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, these sub-steps or stages The order of execution is not necessarily performed sequentially, but may be performed alternately or alternately with at least a part of other steps or sub-steps or stages of other steps.
  • a RAID optimization device 700 for multi-pass programming NAND comprising:
  • the encoding module 702 is used to re-encode the RAID engine by using the user data in the RAID stripe buffer of the belonging RAID stripe when programming each Pass according to the RAID optimization request of the multi-Pass programming NAND;
  • Generating module 703 is used for generating corresponding Parity data in real time by RAID engine coding
  • the release module 704 is configured to release the Parity buffer after the programming of the corresponding Pass is completed, without keeping it until all the programming of the Pass is completed.
  • a RAID optimization device 700 for multi-pass programming NAND is provided, and the device also includes a programming module 705 for:
  • the corresponding Parity buffer can be released.
  • programming module 705 is also used to:
  • each Pass programming of each Page is interleaved
  • a RAID optimization device 700 for multi-pass programming NAND is provided, and the device also includes a judging module 706 for:
  • a computer device in one embodiment, is provided, and its internal structure diagram may be as shown in FIG. 10 .
  • the computer device includes a processor, a memory, and a network interface connected by a device bus. Wherein, the processor of the computer device is used to provide calculation and control capabilities.
  • the memory of the computer device includes a non-volatile storage medium and an internal memory.
  • the non-volatile storage medium stores operating devices, computer programs and databases.
  • the internal memory provides an environment for operating devices and computer programs in the non-volatile storage medium.
  • the network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a RAID optimization method for multi-pass programming NAND is realized.
  • FIG. 10 is only a block diagram of a part of the structure related to the solution of this application, and does not constitute a limitation to the computer equipment on which the solution of this application is applied.
  • the specific computer equipment can be More or fewer components than shown in the figures may be included, or some components may be combined, or have a different arrangement of components.
  • a computer device including a memory, a processor, and a computer program stored in the memory and operable on the processor.
  • the processor executes the computer program, the steps in the above method embodiments are implemented.
  • a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps in each of the above method embodiments are implemented.
  • Nonvolatile memory can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory.
  • Volatile memory can include random access memory (RAM) or external cache memory.
  • RAM random access memory
  • RAM is available in many forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Chain Synchlink DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

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Abstract

本申请涉及一种多Pass编程NAND的RAID优化方法、装置、计算机设备及存储介质，其中该方法包括：获取多Pass编程NAND的RAID优化请求；根据所述多Pass编程NAND的RAID优化请求在每个Pass编程时，利用所属RAID条带缓存的用户数据重新进行RAID引擎编码；通过RAID引擎编码实时生成对应的Parity数据；在对应Pass的编程完成后即可释放Parity 缓冲区，无需保持到所有Pass编程完成。本申请针对多Pass编程的场景，在各个Pass编程时，动态生成RAID校验数据而不缓存对应的校验数据，通过实时生成RAID校验数据减少了对SOC Memory的需求，进而提高了固态硬盘的性能，降低了成本。

Description

多Pass编程NAND的RAID优化方法、装置及计算机设备
本申请要求于2021年11月30日在中国专利局提交的、申请号为202111444258.7的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储系统技术领域，特别是涉及一种多Pass编程NAND的RAID优化方法、装置、计算机设备及存储介质。
 背景技术
随着固态硬盘技术的发展，SSD（Solid State Disk，固态硬盘）已经被广泛应用于各种场合，在PC市场已经逐步替代传统的HDD（Hard Disk Drive，硬盘驱动器），从可靠性和性能方面为用户提供较好的体验。随着NAND工艺的演进，其编程模型越来越复杂，从早先的单Pass 编程到最近的多Pass编程。对于多Pass编程的颗粒来说，每个Pass编程的时候，所有的页面数据都需要传输到NAND，相应地，对应的数据需要缓存在SSD内存中。
目前，在现有的SSD设计中，一般都会使用RAID来提升可靠性。对于N笔用户数据，通过RAID引擎生成1笔校验数据，且写入到NAND中。由于多Pass编程的需求，RAID 校验数据也必需多次传输到NAND，故需要缓冲对应的校验数据，直到对应页面的所有Pass编程完成，由此增加了对SSD内存的需求。进一步地，由于RAID引擎使用的为SOC内部的高速Memory(如SRAM)，其空间有限，需要将校验数据备份到慢速内存中（如DRAM），此拷贝过程对性能影响较大。
 技术问题
基于此，有必要针对上述技术问题，提供一种多Pass编程NAND的RAID优化方法、装置、计算机设备及存储介质。
 技术解决方案
一种多Pass编程NAND的RAID优化方法，所述方法包括：
获取多Pass编程NAND的RAID优化请求；
根据所述多Pass编程NAND的RAID优化请求在每个Pass编程时，利用所属RAID条带缓存的用户数据重新进行RAID引擎编码；
通过RAID引擎编码实时生成对应的Parity数据；
在对应Pass的编程完成后即可释放Parity 缓冲区，无需保持到所有Pass编程完成。
在其中一个实施例中，所述方法还包括：
将RAID条带的用户数据经过RAID引擎编码生成对应的Parity数据；
将用户数据和Parity数据传输到SSD各个DIE的Page 上进行Pass 1编程；
在所述Pass 1编程完成后即可释放对应的Parity缓冲区。
在其中一个实施例中，所述方法还包括：
在多Pass编程模型下交错进行各个Page的每个Pass编程；
待所有相关交错编程Page的Pass 1完成后，再重新继续RAID条带的Pass 2编程。
在其中一个实施例中，所述方法还包括：
判断Page所有Pass编程是否已经完成；
若否则继续发起各个DIE Page对应Pass用户数据编程；若是则完成各个DIE的Page编程。
一种多Pass编程NAND的RAID优化装置，所述装置包括：
获取模块，所述获取模块用于获取多Pass编程NAND的RAID优化请求；
编码模块，所述编码模块用于根据所述多Pass编程NAND的RAID优化请求在每个Pass编程时，利用所属RAID条带缓存的用户数据重新进行RAID引擎编码；
生成模块，所述生成模块用于通过RAID引擎编码实时生成对应的Parity数据；
释放模块，所述释放模块用于在对应Pass的编程完成后即可释放Parity 缓冲区，无需保持到所有Pass编程完成。
在其中一个实施例中，所述装置还包括编程模块，所述编程模块用于：
将RAID条带的用户数据经过RAID引擎编码生成对应的Parity数据；
将用户数据和Parity数据传输到SSD各个DIE的Page上进行Pass 1编程；
在所述Pass 1编程完成后即可释放对应的Parity缓冲区。
在其中一个实施例中，所述编程模块还用于：
在多Pass编程模型下交错进行各个Page的每个Pass编程；
待所有相关交错编程Page的Pass 1完成后，再重新继续RAID条带的Pass 2编程。
在其中一个实施例中，所述装置还包括判断模块，所述判断模块用于：
判断Page所有Pass编程是否已经完成；
若否则继续发起各个DIE Page对应Pass用户数据编程；若是则完成各个DIE的Page编程。
一种计算机设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现上述任意一项方法的步骤。
一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现上述任意一项方法的步骤。
 有益效果
上述多Pass编程NAND的RAID优化方法、装置、计算机设备及存储介质通过获取多Pass编程NAND的RAID优化请求；根据所述多Pass编程NAND的RAID优化请求在每个Pass编程时，利用所属RAID条带缓存的用户数据重新进行RAID引擎编码；通过RAID引擎编码实时生成对应的Parity数据；在对应Pass的编程完成后即可释放Parity 缓冲区，无需保持到所有Pass编程完成。本申请针对多Pass编程的场景，在各个Pass编程时，动态生成RAID校验数据而不缓存对应的校验数据，通过实时生成RAID校验数据减少了对SOC Memory的需求，进而提高了固态硬盘的性能，降低了成本。
 附图说明
图1为一个传统的Multi-Pass NAND RAID模型的示意图；
图2为另一个传统的Multi-Pass NAND RAID模型的示意图；
图3为一个实施例中多Pass编程NAND的RAID优化方法的流程示意图；
图4为一个实施例中对应的NAND多Pass写入过程的流程示意图；
图5为另一个实施例中多Pass编程NAND的RAID优化方法的流程示意图；
图6为一个实施例中Multi-Pass NAND 编程时的RAID模型的示意图；
图7为一个实施例中多Pass编程NAND的RAID优化装置的结构框图；
图8为另一个实施例中多Pass编程NAND的RAID优化装置的结构框图；
图9为再一个实施例中多Pass编程NAND的RAID优化装置的结构框图；
图10为一个实施例中计算机设备的内部结构图。
 本发明的实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
目前，典型的NAND组成包括： DIE，可独立并发操作的单元； Block，可独立擦除的单元，其内各个物理位置的数据写入后在下一次写之前必须要将整个Block擦除； Page，读写单元，同一物理块内的Page必需按顺序编程: 0-> 1 -> 2 -> 3…。随着NAND 技术的演进，其Page编程模型越来越复杂。以QLC为例，其需要按照一定的规则对Page进行多次编程才能达到稳定的状态。期间，需要存储的数据需要多次传输到NAND上。
如图1所示，为一个传统的Multi-Pass NAND RAID模型的示意图。其中，Data 0_0、Data 0_1、Data 0_2 …. Data 0_N-1为属于同一RAID条带(称为条带0)的N笔用户数据。RAID条带0的用户数据经过RAID引擎编码，生成对应的Parity数据（Parity 0_N）。此N(用户数据)+1（RAID Parity数据）传输到SSD各个DIE 的Block X的Page 0上，进行Pass 1编程；且由于RAID Parity数据还需在后续的Pass中传输到NAND中，则需要在内存中继续保持缓存。在多Pass 编程模型下，各个Page的各个Pass编程是交错进行的，依次进行RAID 条带1的Parity 生成，以及写入各个DIE 的Block X的Page 1。所有相关交错编程的Page的Pass 1完成后，再重新继续RAID 条带0的Pass 2编程，此时对应的校验数据直接使用缓存的RAID Parity数据。依次进行RAID 条带1的Pass 2编程，此时也依然使用内存中缓存的Parity数据。循环上述序列，直到所有相关的交错编程的条带完成所有Pass的数据写入。在此过程中，由于每个Pass编程都需要所有数据传输到NAND上，故对于RAID条带数据，需要保持在RAID Parity 缓存中（一般为高速的SOC 内部SRAM），直到所有交错编程的Page完成所有Pass的编程才能释放。此过程对于RAID Parity缓存的要求很大，极大地增加了SOC成本。
如图2所示，为另一个传统的Multi-Pass NAND RAID模型的示意图。在此过程中，同图1中的模型类似，也需要缓存RAID parity数据。但考虑到高速的SOC SRAM成本较高，所以一般在Pass 1编程，经过RAID引擎生成的Parity数据会备份到慢速的内存（空间大，一般如DRAM）。此过程可以降低SOC成本，但是频繁的内存拷贝，对整体性能影响较大。
基于此，本申请提出一种多Pass编程NAND的RAID优化方法，旨在能够针对多Pass编程的场景可以降低对SOC Memory的需求。
在一个实施例中，如图3所示，提供了一种多Pass编程NAND的RAID优化方法，该方法包括：
步骤302，获取多Pass编程NAND的RAID优化请求；
步骤304，根据多Pass编程NAND的RAID优化请求在每个Pass编程时，利用所属RAID条带缓存的用户数据重新进行RAID引擎编码；
步骤306，通过RAID引擎编码实时生成对应的Parity数据；
步骤308，在对应Pass的编程完成后即可释放Parity 缓冲区，无需保持到所有Pass编程完成。
在本实施例中，提供了一种多Pass编程NAND的RAID优化方法，该方法针对多Pass编程的场景，在每个Pass 编程时，由于N笔用户数据需要多次传输给NAND，故其必然需要缓冲。相应地，对该N笔用户数据对应的1笔RAID校验数据每次重新生成，消除了RAID Parity Buffer的缓存备份需求。
在一个实施例中，方法还包括：判断Page0所有Pass编程是否已经完成；若否则继续发起各个DIE Page0对应Pass用户数据编程；若是则完成各个DIE的Page0编程。
参考图4所示，为本实施例中对应的NAND 多Pass写入流程图。具体的实现步骤如下：
首先，发起各个DIE Page 0 Pass 1用户数据编程。接着，将RAID条带的用户数据经过RAID引擎编码，生成RAID校验数据。
然后，将各个DIE 的数据（含用户数据、备份的RAID校验数据）发送给NAND，并发起对应Pass的编程；交错进行各个DIE Page 1/2/3 Pass 1编程。
最后，再判断是否Page 0所有Pass编程完成。若是，则完成各个DIE Page 0编程；若否，继续发起各个DIE Page 0 对应Pass用户数据编程。
在此过程中，在每个Pass 编程时，利用所属RAID条带缓存的用户数据重新进行RAID引擎编码，实时生成校验数据。在对应Pass的编程完成后，即可释放Parity 缓冲区，无需保持到所有Pass编程完成。
在上述实施例中通过获取多Pass编程NAND的RAID优化请求；根据所述多Pass编程NAND的RAID优化请求在每个Pass编程时，利用所属RAID条带缓存的用户数据重新进行RAID引擎编码；通过RAID引擎编码实时生成对应的Parity数据；在对应Pass的编程完成后即可释放Parity 缓冲区，无需保持到所有Pass编程完成。上述方案针对多Pass编程的场景，在各个Pass编程时，动态生成RAID校验数据而不缓存对应的校验数据，通过实时生成RAID校验数据减少了对SOC Memory的需求，进而提高了固态硬盘的性能，降低了成本。
在一个实施例中，如5图所示，提供了一种多Pass编程NAND的RAID优化方法，该方法还包括：
步骤502，将RAID条带0的用户数据经过RAID引擎编码生成对应的Parity数据；
步骤504，将用户数据和Parity数据传输到SSD各个DIE的Page 0上进行Pass 1编程；
步骤506，在Pass 1编程完成后即可释放对应的Parity缓冲区；
步骤508，在多Pass编程模型下交错进行各个Page的每个Pass编程；
步骤510，待所有相关交错编程Page的Pass 1完成后，再重新继续RAID条带0的Pass 2编程。
参考图6所示，在本实施例中引入的Multi-Pass NAND 编程时的RAID模型，其具体的实现步骤如下：
6.1、Data 0_0、Data 0_1、Data 0_2 …Data 0_N-1为属于同一RAID条带(称为条带0)的N笔用户数据。
6.2、RAID条带0的用户数据经过RAID引擎编码，生成对应的Parity数据（Parity 0_N）。
6.3、此N(用户数据)+1（RAID Parity数据）传输到SSD各个DIE的Block X的Page 0上进行Pass 1编程；编程完成后即可释放Parity 0_N缓冲区。
6.4、在多Pass编程模型下，各个Page的各个Pass编程是交错进行的，依次进行RAID条带1的Parity生成以及写入各个DIE的Block X的Page 1。
6.5、所有相关交错编程的Page的Pass 1完成后，再重新继续RAID 条带0的Pass 2编程：
此时同Pass 1一样，N笔用户数据重新经过RAID引擎，重新生成Parity 0_N。传输到SSD各个DIE的Block X Page 0进行Pass 2编程，完成后即释放Parity 0_N缓冲区。
6.6、依次进行RAID 条带1的Pass 2编程，此时也是重新经由RAID引擎生成相应的校验数据并写入NAND。
6.7、循环上述序列，直到所有相关的交错编程的条带完成所有Pass的数据写入。
在本实施例中，由于用户数据总是缓存在内存中，通过在每个Pass编程时，实时重新生成对应的RAID parity数据，大大降低了对SOC Parity Buffer大小的需求，降低了成本；且无需触发memory的拷贝备份，不会影响性能。
应该理解的是，虽然图1-6的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图1-6中的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些子步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。
在一个实施例中，如图7所示，提供了一种多Pass编程NAND的RAID优化装置700，该装置包括：
获取模块701，用于获取多Pass编程NAND的RAID优化请求；
编码模块702，用于根据所述多Pass编程NAND的RAID优化请求在每个Pass编程时，利用所属RAID条带缓存的用户数据重新进行RAID引擎编码；
生成模块703，用于通过RAID引擎编码实时生成对应的Parity数据；
释放模块704，用于在对应Pass的编程完成后即可释放Parity 缓冲区，无需保持到所有Pass编程完成。
在一个实施例中，如图8所示，提供了一种多Pass编程NAND的RAID优化装置700，该装置还包括编程模块705，用于：
将RAID条带0的用户数据经过RAID引擎编码生成对应的Parity数据；
将用户数据和Parity数据传输到SSD各个DIE的Page 0上进行Pass 1编程；
在所述Pass 1编程完成后即可释放对应的Parity缓冲区。
在一个实施例中，编程模块705还用于：
在多Pass编程模型下交错进行各个Page的每个Pass编程；
待所有相关交错编程Page的Pass 1完成后，再重新继续RAID条带0的Pass 2编程。
在一个实施例中，如图9所示，提供了一种多Pass编程NAND的RAID优化装置700，该装置还包括判断模块706，用于：
判断Page0所有Pass编程是否已经完成；
若否则继续发起各个DIE Page0对应Pass用户数据编程；若是则完成各个DIE的Page0编程。
关于多Pass编程NAND的RAID优化装置的具体限定可以参见上文中对于多Pass编程NAND的RAID优化方法的限定，在此不再赘述。
在一个实施例中，提供了一种计算机设备，其内部结构图可以如图10所示。该计算机设备包括通过装置总线连接的处理器、存储器以及网络接口。其中，该计算机设备的处理器用于提供计算和控制能力。该计算机设备的存储器包括非易失性存储介质、内存储器。该非易失性存储介质存储有操作装置、计算机程序和数据库。该内存储器为非易失性存储介质中的操作装置和计算机程序的运行提供环境。该计算机设备的网络接口用于与外部的终端通过网络连接通信。该计算机程序被处理器执行时以实现一种多Pass编程NAND的RAID优化方法。
本领域技术人员可以理解，图10中示出的结构，仅仅是与本申请方案相关的部分结构的框图，并不构成对本申请方案所应用于其上的计算机设备的限定，具体的计算机设备可以包括比图中所示更多或更少的部件，或者组合某些部件，或者具有不同的部件布置。
在一个实施例中，提供了一种计算机设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，处理器执行计算机程序时实现以上各个方法实施例中的步骤。
在一个实施例中，提供了一种计算机可读存储介质，其上存储有计算机程序，计算机程序被处理器执行时实现以上各个方法实施例中的步骤。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的计算机程序可存储于一非易失性计算机可读取存储介质中，该计算机程序在执行时，可包括如上述各方法的实施例的流程。其中，本申请所提供的各实施例中所使用的对存储器、存储、数据库或其它介质的任何引用，均可包括非易失性和/或易失性存储器。非易失性存储器可包括只读存储器（ROM）、可编程ROM（PROM）、电可编程ROM（EPROM）、电可擦除可编程ROM（EEPROM）或闪存。易失性存储器可包括随机存取存储器（RAM）或者外部高速缓冲存储器。作为说明而非局限，RAM以多种形式可得，诸如静态RAM（SRAM）、动态RAM（DRAM）、同步DRAM（SDRAM）、双数据率SDRAM（DDRSDRAM）、增强型SDRAM（ESDRAM）、同步链路（Synchlink） DRAM（SLDRAM）、存储器总线（Rambus）直接RAM（RDRAM）、直接存储器总线动态RAM（DRDRAM）、以及存储器总线动态RAM（RDRAM）等。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种多Pass编程NAND的RAID优化方法，其特征在于，所述方法包括：
    获取多Pass编程NAND的RAID优化请求；
    根据所述多Pass编程NAND的RAID优化请求在每个Pass编程时，利用所属RAID条带缓存的用户数据重新进行RAID引擎编码；
    通过RAID引擎编码实时生成对应的Parity数据；
    在对应Pass的编程完成后即可释放Parity 缓冲区，无需保持到所有Pass编程完成。
  2. 根据权利要求1所述的多Pass编程NAND的RAID优化方法，其特征在于，所述方法还包括：
    将RAID条带的用户数据经过RAID引擎编码生成对应的Parity数据；
    将用户数据和Parity数据传输到SSD各个DIE的Page上进行Pass 1编程；
    在所述Pass 1编程完成后即可释放对应的Parity缓冲区。
  3. 根据权利要求2所述的多Pass编程NAND的RAID优化方法，其特征在于，所述方法还包括：
    在多Pass编程模型下交错进行各个Page的每个Pass编程；
    待所有相关交错编程Page的Pass 1完成后，再重新继续RAID条带的Pass 2编程。
  4. 根据权利要求3所述的多Pass编程NAND的RAID优化方法，其特征在于，所述方法还包括：
    判断Page所有Pass编程是否已经完成；
    若否则继续发起各个DIE Page对应Pass用户数据编程；若是则完成各个DIE的Page编程。
  5. 一种多Pass编程NAND的RAID优化装置，其特征在于，所述装置包括：
    获取模块，所述获取模块用于获取多Pass编程NAND的RAID优化请求；
    编码模块，所述编码模块用于根据所述多Pass编程NAND的RAID优化请求在每个Pass编程时，利用所属RAID条带缓存的用户数据重新进行RAID引擎编码；
    生成模块，所述生成模块用于通过RAID引擎编码实时生成对应的Parity数据；
    释放模块，所述释放模块用于在对应Pass的编程完成后即可释放Parity 缓冲区，无需保持到所有Pass编程完成。
  6. 根据权利要求5所述的多Pass编程NAND的RAID优化装置，其特征在于，所述装置还包括编程模块，所述编程模块用于：
    将RAID条带的用户数据经过RAID引擎编码生成对应的Parity数据；
    将用户数据和Parity数据传输到SSD各个DIE的Page上进行Pass 1编程；
    在所述Pass 1编程完成后即可释放对应的Parity缓冲区。
  7. 根据权利要求6所述的多Pass编程NAND的RAID优化装置，其特征在于，所述编程模块还用于：
    在多Pass编程模型下交错进行各个Page的每个Pass编程；
    待所有相关交错编程Page的Pass 1完成后，再重新继续RAID条带的Pass 2编程。
  8. 根据权利要求7所述的多Pass编程NAND的RAID优化装置，其特征在于，所述装置还包括判断模块，所述判断模块用于：
    判断Page所有Pass编程是否已经完成；
    若否则继续发起各个DIE Page对应Pass用户数据编程；若是则完成各个DIE的Page编程。
  9. 一种计算机设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，其特征在于，所述处理器执行所述计算机程序时实现权利要求1至4中任一项所述方法的步骤。
  10. 一种计算机可读存储介质，其上存储有计算机程序，其特征在于，所述计算机程序被处理器执行时实现权利要求1至4中任一项所述的方法的步骤。
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