WO2023092535A9 - Display substrate - Google Patents

Abstract

A display substrate. The display substrate is provided with multiple subpixels (P) arranged in an array, and comprises a driving circuit substrate (110), multiple first electrodes (130), a pixel definition layer (140), and a light-emitting material layer (150). The driving circuit substrate (110) comprises multiple pixel driving circuits (120) and a protective insulating layer (112); the protective insulating layer (112) comprises multiple first via holes (112A) exposing output ends (121) of the multiple pixel driving circuits (120); and the multiple first electrodes (130) are electrically connected to the output ends (121) of the multiple pixel driving circuits (120) by means of the multiple first via holes (112A), respectively. The pixel definition layer (140) is at least disposed on the side of each of the multiple first electrodes (130) away from the driving circuit substrate (110), and comprises multiple subpixel openings (141) that respectively expose the multiple first electrodes (130) and at least one partition structure (142) that is provided on the pixel definition layer (140). The light-emitting layer (150) is disposed on the side of the pixel definition layer (140) away from the driving circuit substrate (110) and is at least located in the multiple subpixel openings (141). The pixel definition layer (140) comprises a fist pixel definition sublayer (1401) and a second pixel definition sublayer (1402); and the width of the second pixel definition sublayer (1402) is greater than that of the first pixel definition sublayer (1401). In the display substrate, the problem of lateral electrical crosstalk between adjacent subpixels (P) does not occur, thereby achieving a good display effect.

Description

display substrate technical field

Embodiments of the present disclosure relate to a display substrate.

Background technique

Silicon-based micro-display organic light-emitting display panels have the advantages of miniaturization and high pixel density (Pixel Per Inch, PPI for short), and have gradually become the focus of attention in the display field. Silicon-based microdisplay organic light-emitting display panels, for example, can be used in virtual reality (Virtual Reality, referred to as VR) technology and augmented reality (Augmented Reality, referred to as AR) technology, which can achieve excellent display effects.

Contents of the invention

At least one embodiment of the present disclosure provides a display substrate, which has a plurality of sub-pixels arranged in an array, and includes a driving circuit substrate, a plurality of first electrodes, a pixel defining layer, and a light-emitting material layer. A plurality of pixel driving circuits for a sub-pixel and a protective insulating layer covering the plurality of pixel driving circuits, wherein the protective insulating layer includes a plurality of first via holes exposing the output terminals of the plurality of pixel driving circuits, and a plurality of The first electrodes are arranged on the driving circuit substrate, and are respectively electrically connected to the output terminals of the plurality of pixel driving circuits through the plurality of first via holes; the pixel defining layer is arranged at least on the plurality of first electrodes. The side away from the driving circuit substrate includes a plurality of sub-pixel openings respectively exposing the plurality of first electrodes and at least one partition structure arranged on the pixel defining layer; a luminescent material layer is arranged on the pixel defining layer A side away from the driving circuit substrate and located at least in the plurality of sub-pixel openings, wherein the pixel defining layer includes a first pixel defining sublayer and a second pixel defining sublayer, and the second pixel defining sublayer A layer is disposed on a side of the first pixel defining sublayer away from the driving circuit substrate, and the width of the second pixel defining sublayer is greater than that of the first pixel defining sublayer.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the protective insulating layer is a planar structure at the position of the at least one isolation structure except for the first via hole.

For example, in the display substrate provided by at least one embodiment of the present disclosure, each side wall of the at least one partition structure has a first notch.

For example, in the display substrate provided by at least one embodiment of the present disclosure, at the position of the at least one isolation structure, the first pixel defining sublayer is retracted relative to the second pixel defining sublayer to form the first pixel defining sublayer. a notch.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the width of the second pixel defining sublayer is smaller than the width between adjacent first electrodes.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the first pixel defining sublayer includes an inorganic insulating material, and the second pixel defining sublayer includes an inorganic insulating material or a metal oxide material.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the thickness of the first pixel defining sublayer is greater than the thickness of the second pixel defining sublayer.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the at least one isolation structure includes a plurality of first isolation structures, the plurality of first isolation structures respectively surround the plurality of sub-pixel openings, and the plurality of The first notches of the first isolation structure respectively open toward the plurality of sub-pixels.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the distance between the surface of the first pixel defining sublayer close to the driving circuit substrate and the driving circuit substrate is greater than the distance between the plurality of first electrodes. The distance between the surface of the driving circuit substrate and the driving circuit substrate.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the at least one isolation structure further includes a plurality of second isolation structures, and the plurality of second isolation structures are respectively arranged in the plurality of first isolation structures. Between two adjacent first partition structures.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the distance between the plurality of first isolation structures and the drive circuit substrate is equal to the distance between the plurality of second isolation structures and the drive circuit substrate; or the distance between the plurality of second isolation structures and the drive circuit substrate; The distance between the plurality of first isolation structures and the driving circuit substrate is greater than the distance between the plurality of second isolation structures and the driving circuit substrate.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the second pixel defining sublayer has a first slope angle on the sidewalls of the plurality of first isolation structures, and the first slope angle is 30°- 75°; the second pixel defining sublayer has a second slope angle on the sidewalls of the plurality of second isolation structures, and the second slope angle is 30°-80°.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the slope angle of the first pixel defining sublayer on the sidewalls of the plurality of first isolation structures is larger than that of the second pixel defining sublayer on the plurality of sidewalls. The slope angle of the side wall of the first partition structure.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the luminescent material layer is disconnected at the first notch, and the luminescent material layer includes a first part for emitting light and a second part not for emitting light. part, the luminescent material layer is disconnected at the position of the second part, and the slope angle of the first part is larger than the slope angle of the second part at the disconnected position.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the depth of the first notch in a direction parallel to the board surface of the base substrate is greater than that of the first pixel defining sublayer and the second pixel. The thickness of the sublayer in a direction perpendicular to the board surface of the base substrate is defined.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the thickness of the luminescent material layer is greater than the thickness of the first pixel defining sublayer and greater than the thickness of the second pixel defining sublayer.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the luminescent material layer further includes a third slope portion away from the disconnection position, and the slope angle of the third slope portion is smaller than that of the first portion close to the cut-off position. The slope angle at the disconnection position is smaller than the slope angle at the position where the second part is close to the disconnection position.

For example, in the display substrate provided by at least one embodiment of the present disclosure, at a position corresponding to the third slope, the pixel defining layer includes a fourth slope, and the slope angle of the fourth slope is larger than that of the first slope. The slope angle of the three-slope section.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the slope angle of the fourth slope portion is smaller than the slope angle of the first portion near the break position.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the slope angle of the fourth slope portion is smaller than the slope angle of the second slope angle near the disconnection position.

For example, the display substrate provided in at least one embodiment of the present disclosure further includes a first auxiliary electrode layer disposed on the side of the first pixel defining sublayer close to the driving circuit substrate and exposed by the plurality of second isolation structures. .

For example, in the display substrate provided by at least one embodiment of the present disclosure, the first pixel defining sublayer covers an edge of the first auxiliary electrode layer.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the width of the first auxiliary electrode layer is greater than the depth of the first recess in a direction parallel to the board surface of the base substrate.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the at least one isolation structure includes a plurality of second isolation structures, and the plurality of second isolation structures are respectively arranged between the plurality of first electrodes.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the distance between the surface of the first pixel defining sublayer that is far away from the driving circuit substrate and the driving circuit substrate is smaller than the distance from the plurality of first electrodes. The distance between the surface of the driving circuit substrate and the driving circuit substrate.

For example, the display substrate provided in at least one embodiment of the present disclosure further includes: a first auxiliary electrode disposed on the side of the first pixel defining sublayer close to the driving circuit substrate and exposed by the plurality of second isolation structures layer; and/or a second auxiliary electrode layer disposed on a side of the second pixel defining sublayer away from the driving circuit substrate.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the first pixel defining sublayer is set back by 10 nm-200 nm relative to the second pixel defining sublayer.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the sidewall of each of the plurality of second partition structures further has a second notch, and the second notch is disposed on the first notch. The side away from the driving circuit substrate.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the pixel defining layer further includes a third pixel defining sublayer and a fourth pixel defining sublayer arranged in layers, wherein the third pixel defining sublayer is arranged On the side of the second pixel defining sublayer away from the driving circuit substrate, the fourth pixel defining sublayer is arranged on the side of the third pixel defining sublayer away from the driving circuit substrate, on the side of the third pixel defining sublayer far away from the driving circuit substrate, At the positions of the plurality of second isolation structures, the third pixel defining sublayer is retracted relative to the fourth pixel defining sublayer, so as to form the second notch.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the luminescent material layer includes at least one charge generation layer or hole injection layer.

For example, the display substrate provided in at least one embodiment of the present disclosure further includes: a first auxiliary electrode disposed on the side of the first pixel defining sublayer close to the driving circuit substrate and exposed by the plurality of second isolation structures layer; and/or the second auxiliary electrode layer disposed on the side of the second pixel defining sublayer away from the driving circuit substrate; and/or disposed on the fourth pixel defining sublayer away from the driving circuit The third auxiliary electrode layer on one side of the substrate.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the material of the first auxiliary electrode layer and/or the second auxiliary electrode layer and/or the third auxiliary electrode layer includes Al, Ti, TiN, At least one of Ag, Mo, ITO and IZO.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the second pixel defining sublayer is separated by a first distance at the position of the first notch, and the fourth pixel defining sublayer is separated from the second pixel defining sublayer by a first distance. The positions of the notches are separated by a second distance; the second distance being greater than the first distance by 100nm-500nm.

For example, the display substrate provided in at least one embodiment of the present disclosure further includes: a first auxiliary electrode disposed on the side of the first pixel defining sublayer close to the driving circuit substrate and exposed by the plurality of second isolation structures layer, wherein the width of the first auxiliary electrode layer is greater than the first distance.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the first pixel defining sublayer is set back by 50nm-200nm relative to the second pixel defining sublayer; The fourth pixel defines sub-layers with an inset of 50nm-200nm.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the first auxiliary electrode and at least part of the plurality of first electrodes are arranged in the same layer and at intervals.

For example, the display substrate provided in at least one embodiment of the present disclosure further includes: a second electrode layer disposed on a side of the luminescent material layer away from the driving circuit substrate and at least located in the plurality of sub-pixel openings, wherein, The second electrode layer is arranged continuously.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the second electrode layer includes a fifth slope and a third slope at the disconnection position and the third slope corresponding to the first portion, respectively. Six slopes, the slope angle of the fifth slope is smaller than the slope angle of the first portion at the disconnection position, and the slope angle of the sixth slope is smaller than the slope angle of the third slope.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the luminescent material layer has a flat structure between the disconnection position of the first part and the third slope, and the second electrode layer There is a flat structure between the fifth slope and the sixth slope.

For example, the display substrate provided in at least one embodiment of the present disclosure further includes: a light extraction layer disposed on a side of the second electrode layer away from the driving circuit substrate, wherein the light extraction layer has a refractive index of 1.3 ~1.7.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the material of the light extraction layer includes at least one of LiF, SiOx and Al ₂ O ₃ .

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present disclosure more clearly, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure .

FIG. 1A is a schematic cross-sectional view of a display substrate;

FIG. 1B is another schematic cross-sectional view of a display substrate;

FIG. 2 is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure;

3 is a schematic cross-sectional view of the display substrate along the M-M line in FIG. 2;

4A-24 are various structural schematic diagrams of partition structures in a display substrate provided by at least one embodiment of the present disclosure;

FIG. 25 is a schematic cross-sectional view of another part of the display substrate along line M-M in FIG. 2;

26-28 are various structural schematic diagrams of light emitting devices in a display substrate provided by at least one embodiment of the present disclosure;

FIG. 29 is a schematic plan view of a plurality of sub-pixels in a display substrate provided by at least one embodiment of the present disclosure; and

FIG. 30 is a partial cross-sectional view of a display substrate provided by at least one embodiment of the present disclosure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by persons of ordinary skill in the art without creative effort fall within the protection scope of the present disclosure.

Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by those skilled in the art to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Comprising" or "comprising" and similar words mean that the elements or items appearing before the word include the elements or items listed after the word and their equivalents, without excluding other elements or items. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right" and so on are only used to indicate the relative positional relationship. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

Micro OLED is a silicon-based display device. Due to the excellent electrical characteristics and extremely fine device size of silicon-based devices, it is beneficial to realize high integration. For example, FIG. 1A shows a schematic cross-sectional view of a silicon-based display substrate. As shown in FIG. 1A , the silicon-based display substrate includes a driving circuit substrate 10 and a plurality of light emitting devices 50 and other structures.

For example, the silicon-based display substrate includes a plurality of sub-pixels arranged in an array, each sub-pixel includes a light emitting device 50 and a driving circuit 20 disposed in the driving circuit substrate 10, and the driving circuit 20 is configured to drive the light emitting device 50 to emit light. The light emitting device 50 includes an anode 51 , a luminescent material layer 52 and a cathode 53 , and the anode 21 is connected to the driving circuit 20 through a through hole in the insulating layer 30 . A pixel defining layer 40 is disposed on the anode 51, the pixel defining layer 40 has a plurality of sub-pixel openings, and each sub-pixel opening exposes the anode 51 of a light-emitting device 50, thereby defining the light-emitting area of the light-emitting device 50, that is, defining the sub-pixel The effective light emitting area is the area other than the orthographic projection of the pixel defining layer 40 on the anode 51 .

For example, FIG. 1B shows another schematic cross-sectional view of a silicon-based display substrate. In some embodiments, as shown in FIG. 1B , the driving circuit 20 includes structures such as a driving transistor T1 and a connecting electrode 70 . The driving transistor T1 includes a source electrode S, a drain electrode D, and a semiconductor layer M between the source electrode S and the drain electrode D, and one of the source electrode S and the drain electrode D (here, the drain electrode D) is connected through the connection electrode 70 is electrically connected to the anode 51. The semiconductor layer M is a channel region formed between the source electrode S and the drain electrode D, for example.

For example, as shown in FIG. 1B , the driving transistor T1 further includes a gate electrode G, and the gate electrode G, the source electrode S and the drain electrode D respectively correspond to three electrode connection parts. For example, the gate electrode G is electrically connected to the gate electrode connection portion 10g, the source electrode S is electrically connected to the source electrode connection portion 10s, and the drain electrode D is electrically connected to the drain electrode connection portion 10d. For example, the drain electrode D of the drive transistor T1 is electrically connected to the connection electrode 70 through the drain electrode connection portion 10d, and the gate electrode G and the source electrode S are electrically connected to the scanning line and the power supply line through the gate electrode connection portion 10g and the source electrode connection portion 10s, respectively. . The scan line provides an on signal, the drive transistor T1 is in the on state, and the electrical signal provided by the power line can be transmitted to the anode 51 through the drain electrode D of the drive transistor T1 , the drain electrode connection part 102d and the connection electrode 70 . Due to the voltage difference formed between the anode 51 and the cathode 53, an electric field is formed between the two, and the luminescent material layer 52 emits light under the action of the electric field.

For example, as shown in FIG. 1A and FIG. 1B , the silicon-based display substrate may further include an encapsulation layer 60 disposed on the light emitting device 50 and a color filter 70 disposed on the encapsulation layer 60 . The encapsulation layer 60 can encapsulate and protect the light emitting device 50, for example, can also play a role of planarization to provide a flat surface. For example, the light-emitting device 50 of each sub-pixel can emit white light. At this time, the colors of the color filters 70 arranged on the light-emitting device 50 of each sub-pixel are different, such as red, green and blue, so as to realize full-color display. or, the light-emitting device 50 of each sub-pixel can emit light of different colors, such as red, green and blue, etc., at this time, the color of the color filter 70 arranged on the light-emitting device 50 of each sub-pixel is consistent with the light emitting The colors of the light emitted by the devices 50 are the same, so that the color purity of the light emitted by the light emitting device 50 can be improved.

The inventors of the present disclosure found in research that, in the above-mentioned display substrate, due to the high sub-pixel density (for example, greater than 3000PPI), the distance between adjacent sub-pixels is small, and the light-emitting material layers 52 of the plurality of light-emitting devices 50 are usually continuous. setting, there is usually a functional layer with higher carrier mobility in the luminescent material layer 52, which is likely to cause lateral electrical crosstalk between sub-pixels, for example, when the blue sub-pixel is turned on, the red sub-pixel and the green sub-pixel will also have The light color is exposed, causing color mixing, reducing the color gamut of the display device, thereby affecting the display effect of the display substrate.

At least one embodiment of the present disclosure provides a display substrate, the display substrate has a plurality of sub-pixels arranged in an array, and includes a driving circuit substrate, a plurality of first electrodes, a pixel defining layer and a luminescent material layer. The driving circuit substrate includes a plurality of pixel driving circuits for a plurality of sub-pixels and a protective insulating layer covering the plurality of pixel driving circuits. An electrode is arranged on the driving circuit substrate, and is electrically connected to the output terminals of the plurality of pixel driving circuits respectively through a plurality of first via holes. The pixel defining layer is at least disposed on a side of the plurality of first electrodes away from the driving circuit substrate, and includes a plurality of sub-pixel openings respectively exposing the plurality of first electrodes and at least one isolation structure disposed on the pixel defining layer. The luminescent material layer is arranged on the side of the pixel defining layer away from the driving circuit substrate and at least located in a plurality of sub-pixel openings. The pixel defining layer includes a first pixel defining sublayer and a second pixel defining sublayer arranged in layers. The second pixel The defining sublayer is disposed on a side of the first pixel defining sublayer away from the driving circuit substrate, and the width of the second pixel defining sublayer is greater than that of the first pixel defining sublayer.

In the above display substrate provided by at least one embodiment of the present disclosure, the light-emitting material layers of the light-emitting devices of adjacent sub-pixels are disconnected at the position of the isolation structure, so the problem of lateral electrical crosstalk does not occur between adjacent sub-pixels, Therefore, the phenomenon of color mixing between adjacent sub-pixels is avoided, and the display effect of the display substrate can be improved.

In the following, the display substrate provided by the embodiments of the present disclosure will be described in detail through several specific embodiments.

At least one embodiment of the present disclosure provides a display substrate. FIG. 2 shows a schematic plan view of the display substrate, and FIG. 3 shows a schematic cross-sectional view of the display substrate in FIG. 2 along line M-M.

For example, as shown in FIGS. 2 and 3, the display substrate has a display area AA and a peripheral area NA surrounding the display area AA. The display substrate also has a plurality of sub-pixels P arranged in an array, and the plurality of sub-pixels P are arranged in the display area AA. middle. Each sub-pixel P includes a pixel driving circuit and a light emitting device, and the pixel driving circuit is configured to drive the light emitting device to realize display. For example, the light emitting device may be an all fluorescent light emitting device, an all phosphorescent light emitting device or a hybrid light emitting device combining fluorescent light emitting and phosphorescent light emitting, which is not limited in the embodiments of the present disclosure.

For example, as shown in FIG. 3 , the display substrate includes structures such as a driving circuit substrate 110 , a plurality of first electrodes 130 , a pixel defining layer 140 , and a luminescent material layer. The driving circuit substrate 110 includes a plurality of pixel driving circuits 120 for a plurality of sub-pixels P and a protective insulating layer 112 covering the plurality of pixel driving circuits 120. A plurality of first via holes 112A, a plurality of first electrodes 130 are disposed on the driving circuit substrate 110, and are respectively electrically connected to the output terminals 121 of the plurality of pixel driving circuits 120 through the plurality of first via holes 112A.

For example, as shown in FIG. 3 , the pixel driving circuit 120 may include structures such as driving transistors and connection electrodes. For details, refer to FIG. 1B and its related descriptions, which will not be repeated here. The light emitting device includes an anode, a cathode and a layer of light emitting material between the anode and the cathode, and the first electrode 130 is implemented as an anode of the light emitting device, for example. For example, a connection electrode 122 is formed in the first via hole 112A, and the first electrode 130 is connected to the pixel driving circuit 120 through the connection electrode 122 . For example, the connecting electrodes 122 may be made of metal materials or alloy materials such as tungsten, copper, titanium, aluminum or molybdenum.

For example, as shown in FIG. 3 , the pixel defining layer 140 is at least disposed on one side of the plurality of first electrodes 130 away from the driving circuit substrate, and includes a plurality of sub-pixel openings 141 respectively exposing the plurality of first electrodes 130 to define sub-pixels. The light emitting area of P, for example, the pixel defining layer 140 further includes at least one isolation structure 142 disposed on the pixel defining layer 140 .

For example, in some examples, the isolation structure 142 may be located on the first electrode 130, in some examples, the isolation structure 142 may be located between adjacent first electrodes 130, in some examples, at least one isolation structure 142 includes multiple Partial isolation structures 142 are located on the first electrodes 130, and part of the isolation structures 142 are located between adjacent first electrodes 130. For example, in the example shown in FIG. 3 , the isolation structure 142 is located between adjacent first electrodes 130 .

For example, as shown in FIG. 3 , the luminescent material layer 150 is disposed on the side of the pixel defining layer 140 away from the driving circuit substrate 110 and at least in the plurality of sub-pixel openings 141 , for example, at least part of the luminescent material layer 150 is in the isolation structure 142 position is disconnected.

For example, in some examples, all of the luminescent material layer 150 is disconnected at the position of the isolation structure 142, or, in some examples, at least the functional layer with higher carrier mobility (such as hole injection) in the luminescent material layer 150 layer or charge generation layer, etc., which will be described in detail later) are disconnected at the position of the isolation structure 142 . Therefore, the problem of lateral electrical crosstalk will not occur between adjacent sub-pixels in the display substrate, so that the display brightness and display contrast of the display substrate can be improved, and the display effect of the display substrate can be further improved.

For example, in the embodiments of the present disclosure, the partition structure 142 may have various forms, so as to achieve the above-mentioned effect of disconnecting at least part of the luminescent material layer 150 . For example, FIG. 4A-FIG. 24 exemplarily show schematic diagrams of various structures of the isolation structure 142 , and these structures may be used to isolate the luminescent material layer 150 with different functional layers, for example.

For example, as shown in FIGS. 4A-24 , the sidewall of each partition structure 142 has a first notch 142A, thereby facilitating at least part of the luminescent material layer 150 to be disconnected at the location of the partition structure 142 .

For example, in some embodiments, as shown in FIG. 4A and FIG. 4B , the pixel defining layer 140 includes a first pixel defining sublayer 1401 and a second pixel defining sublayer 1402 that are stacked, and the second pixel defining sublayer 1402 is set On the side of the first pixel defining sublayer 1401 away from the driving circuit substrate 110, for example, the width 1402D of the second pixel defining sublayer 1402 is larger than the width 1401D of the first pixel defining sublayer 1401, thereby forming Similar to the structure of half "工" shape.

For example, the thickness of the luminescent material layer 150 is greater than the thickness of the first pixel defining sublayer 1401 and greater than the thickness of the second pixel defining sublayer 1402 .

For example, in some examples, as shown in FIG. 4A and FIG. 4B , at the position of the partition structure 142 , the first pixel defining sublayer 1401 is retracted relative to the second pixel defining sublayer 1402 to form a first notch 142A.

For example, in some embodiments, the protective insulating layer 112 has a planar structure at the location of the isolation structure 142 except for the first via hole 112A, so as to facilitate the formation and structural stability of the isolation structure 142 .

For example, in some embodiments, the width 1402D of the second pixel defining sublayer 1402 is smaller than the width between the adjacent first electrodes 130, for example, the edge of the second pixel defining sublayer 1402 covers the adjacent first electrodes 130 the edge of.

For example, as shown in FIG. 4A , the pixel defining layer 140 may further include a pixel defining sublayer 1405 , and the first pixel defining sublayer 1401 is disposed on a side of the pixel defining sublayer 1405 away from the driving circuit substrate 110 . For example, the first pixel defining sublayer 1401 is also retracted relative to the pixel defining sublayer 1405, thereby forming the first notch 142A.

For example, in some embodiments, the luminescent material layer 150 includes a stack of multiple functional layers, such as a luminescent layer and a plurality of auxiliary luminescent layers that assist the luminescent layer to emit light, and the thickness can be 50nm-500nm, such as 200nm, 300nm or 400nm. wait.

For example, in some examples, as shown in FIG. 26 , the light-emitting material layer 150 includes a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a first light-emitting layer EML1, an exciton control layer and When the ECL, the second light-emitting layer EML2, the third light-emitting layer EML3, the hole blocking layer HBL, the electron transport layer ETL, and the electron injection layer EIL, or the light-emitting material layer 150 includes at least part of the above-mentioned multiple functional layers, the isolation structure 142 can be With the structure shown in FIG. 4A , for convenience of description, the above-mentioned luminescent material layer 150 is called the first luminescent material layer.

For example, in some embodiments, the first pixel defining sublayer 1401 may include inorganic insulating materials, such as silicon oxide, silicon nitride, or silicon oxynitride, and the second pixel defining sublayer 1402 may include inorganic insulating materials or metal oxides. Materials, inorganic insulating materials include silicon oxide, silicon nitride or silicon oxynitride, etc., metal oxide materials include titanium oxide or aluminum oxide, etc. The pixel defining sublayer 1405 may include an inorganic insulating material or a metal oxide material, the inorganic insulating material includes silicon oxide, silicon nitride, or silicon oxynitride, and the metal oxide material includes titanium oxide or aluminum oxide. For example, in some embodiments, the thickness of the pixel defining sublayer 1405 may be 5 nm to 50 nm, the thickness of the first pixel defining sublayer 1401 may be 3 nm to 500 nm, and the thickness of the second pixel defining sublayer 1402 may be 0.5 nm to 5 nm. 100nm.

In the embodiment of the present disclosure, when the second pixel defining sublayer 1402 is made of a metal oxide material, since the metal oxide can have higher etching accuracy, for example, the etching rate and the etching rate of the metal oxide during the preparation process The degree is easy to control, so it is easy to form the desired structure.

For example, in the example of FIG. 4A, when the isolation structure 142 is used to isolate the first luminescent material layer, the second pixel defining sublayer 1402, the first pixel defining sublayer 1401, and the pixel defining sublayer 1405 can respectively use silicon oxide, Silicon nitride and silicon oxide or aluminum oxide, silicon nitride and silicon oxide are used respectively. For example, the sum of the thicknesses of the second pixel defining sublayer 1402 and the first pixel defining sublayer 1401 is greater than or equal to 10 nm and less than or equal to 30 nm. For example, in some examples, the thicknesses H2, H1, and H3 of the second pixel defining sublayer 1402, the first pixel defining sublayer 1401, and the pixel defining sublayer 1405 are 10 nm, 10 nm, and 2 nm, or 10 nm, 10 nm, and 5 nm, respectively. . The setback distance L1 of the first pixel defining sublayer 1401 relative to the second pixel defining sublayer 1402 is 10 nm-100 nm, such as 50 nm.

For example, in some other embodiments, the thickness H1 of the first pixel defining sublayer 1401 may be greater than the thickness H2 of the second pixel defining sublayer 1402 , so as to facilitate isolation of the thicker light-emitting material layer 150 .

For example, in some examples, as shown in FIG. 27 , the luminescent material layer 150 may include a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a first luminescent layer EML1, a second luminescent Layer EML2, electron transport layer ETL, N-type charge generation layer N-CGL, P-type charge generation layer P-CGL, hole transport layer HTL, electron blocking layer EBL, third light-emitting layer EML3, electron transport layer ETL, and electron injection layer EIL, or include at least part of the above-mentioned multiple functional layers (for example, including an N-type charge generation layer and a P-type charge generation layer). At this time, the isolation structure 142 can also adopt the structure shown in FIG. 4A. For convenience of description, The above-mentioned luminescent material layer 150 is called the second luminescent material layer.

For example, in the example of FIG. 4A , when the isolation structure 142 is used to isolate the second luminescent material layer, the second pixel defining sublayer 1402 , the first pixel defining sublayer 1401 and the pixel defining sublayer 1405 can respectively use silicon oxide, Silicon nitride and silicon oxide or aluminum oxide, silicon nitride and silicon oxide are used respectively. For example, the sum of the thicknesses of the second pixel defining sublayer 1402 and the first pixel defining sublayer 1401 is greater than or equal to 10 nm and less than or equal to 100 nm. For example, the thicknesses H2 , H1 and H3 of the second pixel defining sublayer 1402 , the first pixel defining sublayer 1401 and the pixel defining sublayer 1405 are 20 nm, 60 nm and 20 nm, respectively. The setback distance L1 of the first pixel defining sublayer 1401 relative to the second pixel defining sublayer 1402 is 50nm-200nm, such as 100nm or 150nm.

For example, in some embodiments, as shown in FIG. 4A, at least one isolation structure 142 includes a plurality of first isolation structures 143, the plurality of first isolation structures 143 respectively surround the plurality of sub-pixel openings 141, and the plurality of first isolation structures The first notches 142A of 143 respectively face the plurality of sub-pixel openings 141 .

For example, FIG. 5 shows another schematic diagram of the first isolation structure 143. As shown in FIG. The distance H1 is greater than the distance H2 between the surfaces of the plurality of first electrodes 130 away from the driving circuit substrate 110 and the driving circuit substrate 110 . For example, in this example, the pixel defining sublayer 1405 has a relatively large thickness, and the area between adjacent first electrodes 130 can be planarized to increase the distance between the first isolation structure 143 and the driving circuit substrate 110 .

For example, as shown in FIG. 5 , the pixel defining sublayer 1405 has a height D1, and D1 may be 80nm-150nm, such as 100nm, so as to planarize the area between adjacent first electrodes 130 .

For example, the partition structure 142 shown in FIG. 5 can also be used to partition the first luminescent material layer and the second luminescent material layer, and the thickness and retraction distance of the first pixel defining sublayer 1401 and the second pixel defining sublayer 1402 etc. can also refer to the above-mentioned embodiments, which will not be repeated here.

For example, FIG. 6 shows another schematic diagram of partition structures 142. As shown in FIG. 6, in some embodiments, at least one partition structure 142 further includes a plurality of second partition structures 144, and the plurality of second partition structures 144 are It is arranged between two adjacent first partition structures 143 among the plurality of first partition structures 143 . For example, the second partition structure 144 is a chamfered structure. For example, in the second isolation structure 144, the indentation distance of the first pixel defining sublayer 1401 relative to the second pixel defining sublayer 1402 may be equal to, greater than or smaller than that of the first pixel defining sublayer 1401 in the first isolation structure 143. The inset distance of the sub-layer 1402 is defined at the second pixel. The second isolation structure 144 can enhance the isolation effect of the isolation structure 142 .

For example, in some embodiments, as shown in FIG. 6, the distance between the plurality of first isolation structures 143 and the driving circuit substrate 110 is equal to the distance between the plurality of second isolation structures 144 and the driving circuit substrate 110, that is, the first isolation structure 143 and the second isolation structure 144 are at substantially the same height; or, in some other embodiments, as shown in FIG. The distance from the drive circuit substrate 110. For example, the second isolation structure 144 is located between adjacent first electrodes 130, and the first isolation structure 143 is located on the side of the first electrode 130 away from the driving circuit substrate 110, and is shown as being between the first electrodes 130 in the figure. superior.

For example, in some embodiments, as shown in FIG. 7, the second pixel defining layer 1402 has a first slope angle a on the sidewalls of the plurality of first isolation structures 143, and the first slope angle a may be 30°-75° , such as 40°, 50° or 60°, etc.; the second pixel defining layer 1402 has a second slope angle b on the sidewalls of the plurality of second isolation structures 144, and the second slope angle b may be 30°-80°, for example 45°, 55° or 65° etc.

For example, in some embodiments, as shown in FIG. 7 , the slope angle c of the sidewalls of the first pixel defining sublayer 1401 in the plurality of first partition structures 143 is greater than that of the second pixel defining sublayer 1402 in the plurality of first partitions. The slope angle a of the sidewall of the structure 143 .

For example, referring to FIG. 3 , the luminescent material layer 150 is disconnected at the first notch 142A, the luminescent material layer 150 includes a first part 1501 for emitting light and a second part 1502 not used for emitting light, and the luminescent material layer 150 is in the second notch 1502. The position of the portion 1502 is disconnected and the slope angle d of the first portion 1501 is greater than the slope angle e of the second portion 1502 at the disconnected position.

For example, referring to FIG. 4A , the depth L1 of the first notch 142A in a direction parallel to the plate surface of the base substrate 110 is greater than that of the first pixel defining sublayer 1401 and the second pixel defining sublayer 1402 perpendicular to the base substrate 110. Thicknesses H1 and H2 in the direction of the board surface. Thus, the isolation structure 142 can fully realize the isolation function at the first notch 142A.

For example, in some embodiments, FIG. 30 shows a scanning electron microscope image of the display substrate in this example. As shown in FIG. The first part that emits light has a first slope PO1 at the disconnected position, and the slope angle of the first slope PO1 is d, and the second part of the luminescent material layer 150 that is not used for emitting light has a second slope PO2 at the disconnected position , the slope angle of the second slope portion PO2 is e.

For example, the light emitting material layer 150 includes a charge generation layer CGL, which is disconnected at the first notch 142A. For example, the luminescent material layer 150 further includes a third slope portion PO3 (marked at the charge generation layer CGL for clarity of illustration) away from the disconnection position, and the slope angle f of the third slope portion PO3 is smaller than that of the first portion close to the disconnection position. The slope angle d at the position is smaller than the slope angle e at the position where the second part is close to the disconnection.

For example, at a position corresponding to the third slope PO3 , the pixel defining layer includes a fourth slope PO4 , and the slope angle g of the fourth slope PO4 is larger than the slope angle f of the third slope PO3 . For example, the slope angle g of the fourth slope portion PO4 is smaller than the slope angle d of the first portion near the disconnection position. For example, the slope angle g of the slope angle PO4 of the fourth slope portion is smaller than the slope angle e of the second portion at the disconnection position.

For example, in some embodiments, as shown in FIG. 8 and FIG. 9 , the display substrate may further include a pixel disposed on the side of the first pixel defining sublayer 1401 close to the driving circuit substrate 110 and exposed by a plurality of second isolation structures 144 . The first auxiliary electrode layer 201 . The first auxiliary electrode layer 201 can shield the electric field interference that may be generated between the adjacent first electrodes 130 or between the first electrodes 130 and other circuits in the display substrate, thereby improving the display effect of the display substrate, for example, during the preparation of the display substrate During the process, the first auxiliary electrode layer 201 can also serve as an etching stopper layer for preventing the etchant from etching to the functional layer below the first auxiliary electrode layer 201 when the isolation structure 142 is formed by etching.

For example, the first pixel defining sublayer 1401 covers the edge of the first auxiliary electrode layer 201 . For example, the width W3 (refer to FIG. 16 ) of the first auxiliary electrode layer 201 is greater than the depth L1 of the first notch 142A in a direction parallel to the plate surface of the base substrate 110 . Thus, the first auxiliary electrode layer 201 can fully realize the functions of preventing electric field interference and blocking etching.

For example, the isolation structure 142 shown in FIGS. 6-9 can also be used to isolate the first luminescent material layer and the second luminescent material layer, and the thickness of the first pixel defining sublayer 1401 and the second pixel defining sublayer 1402 and For the retraction distance, etc., reference may also be made to the above-mentioned embodiments, which will not be repeated here.

For example, in some embodiments, as shown in FIG. 10 , the partition structure 142 may only include the second partition structure 144, for example, include a plurality of second partition structures 144, and the plurality of second partition structures 144 are respectively arranged on the plurality of second partition structures. between one electrode 130 .

For example, as shown in FIG. 10 , the distance D3 between the surface of the first pixel defining sublayer 1401 away from the driving circuit substrate 110 and the driving circuit substrate 110 is smaller than the distance D3 between the surface of the plurality of first electrodes 130 away from the driving circuit substrate 110 and the driving circuit. The distance D2 of the substrate 110 . For example, in some examples, the thicknesses H2, H1, and H3 of the second pixel defining sublayer 1402, the first pixel defining sublayer 1401, and the pixel defining sublayer 1405 are 20 nm, 70 nm, and 10 nm, respectively, or 20 nm, 60 nm, and 20 nm, respectively. .

For example, as shown in FIG. 10 , the retraction distance L1 of the first pixel defining sublayer 1401 relative to the second pixel defining sublayer 1402 may be 10nm-200nm, such as 50nm-200nm, such as 150nm.

For example, in some embodiments, as shown in FIG. 11 , the display substrate may further include a first auxiliary layer disposed on the side of the first pixel defining sublayer 1401 close to the driving circuit substrate 110 and exposed by a plurality of second isolation structures 144 . Electrode layer 201.

For example, in some embodiments, as shown in FIG. 12 , the display substrate may further include a second auxiliary electrode layer 202 disposed on a side of the second pixel defining sublayer 1402 away from the driving circuit substrate 110 .

For example, in some embodiments, the display substrate may have the first auxiliary electrode layer 201 disposed on the side of the first pixel defining sublayer 1401 close to the driving circuit substrate 110 and exposed by the plurality of second isolation structures 144 and disposed on the The second pixel defines the second auxiliary electrode layer 202 on the side of the sub-layer 1402 away from the driving circuit substrate 110 .

In the embodiment of the present disclosure, at least one auxiliary electrode layer can be arranged at different positions of the isolation structure 142 to shield the electric field that may be generated between the adjacent first electrodes 130 or between the first electrodes 130 and other circuits in the display substrate. interference, thereby improving the display effect of the display substrate.

For example, the isolation structure 142 shown in FIGS. 10-12 can also be used to isolate the first luminescent material layer and the second luminescent material layer, and the thickness of the first pixel defining sublayer 1401 and the second pixel defining sublayer 1402 and The retraction distance and the like can also refer to the above description of FIG. 10 , which will not be repeated here.

For example, in some embodiments, the isolation structure 142/second isolation structure 144 may have a structure as shown in FIG. 13, for example, in the example of FIG. 13, the second pixel defining sublayer 1402 and the first pixel defining sublayer 1401 has a corresponding raised portion at the position of the first auxiliary electrode layer 201, in this example, the thicknesses H2, H1 and H3 of the second pixel defining sublayer 1402, the first pixel defining sublayer 1401 and the pixel defining sublayer 1405 Can be 20nm, 60nm and 20nm respectively. For example, the retraction distance of the first pixel defining sublayer 1401 relative to the second pixel defining sublayer 1402 may be 10nm-200nm, such as 50nm-200nm, such as 150nm. The thickness of the first auxiliary electrode layer 201 may be 20 nm.

For example, in some other embodiments, as shown in FIG. 14 , in addition to the above-mentioned first notch 142A, the sidewall of each second partition structure 144 may also have a second notch 142B, and the second notch 142B is arranged on A side of the first notch 142A away from the driving circuit substrate 110 . The second partition structure 144 having the second notch 142B can partition the thicker luminescent material layer 150 having more functional layers.

For example, as shown in FIG. 14 , the pixel defining layer 140 further includes a third pixel defining sublayer 1403 and a fourth pixel defining sublayer 1404 arranged in layers, and the third pixel defining sublayer 1403 is arranged on the second pixel defining sublayer 1402 On the side away from the driving circuit substrate 110, the fourth pixel defining sublayer 1404 is disposed on the side of the third pixel defining sublayer 1403 away from the driving circuit substrate 110. At the positions of the plurality of second isolation structures 144, the third pixel defining sublayer Layer 1403 is set back relative to fourth pixel-defining sub-layer 1404 to form second recess 142B.

For example, the partition structure having the first notch 142A and the second notch 142B may be used to partition the luminescent material layer 150 having more functional layers, and at this time, the luminescent material layer 150 may include at least one CGL (CGL).

For example, in some embodiments, as shown in FIG. 28 , the light-emitting material layer 150 may include a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a first light-emitting layer EML1, an electron transport Layer ETL, N-type charge generation layer N-CGL, P-type charge generation layer P-CGL, hole transport layer HTL, electron blocking layer EBL, second light-emitting layer EML2, electron transport layer ETL, N-type charge generation layer N- CGL, P-type charge generation layer P-CGL, hole transport layer HTL, electron blocking layer EBL third light emitting layer EML3, electron transport layer ETL and electron injection layer EIL, or include at least part of the above-mentioned multiple functional layers (for example When including two layers of N-type charge generation layer and P-type charge generation layer), the isolation structure 142 can adopt a structure with a first notch 142A and a second notch 142B as shown in FIG. 14 , for convenience of description, The above-mentioned luminescent material layer 150 is called the third luminescent material layer.

For example, in some embodiments, the third pixel defining sublayer 1403 may include an inorganic insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride, and the fourth pixel defining sublayer 1404 may include an inorganic insulating material or a metal oxide material. , the inorganic insulating material includes silicon oxide, silicon nitride or silicon oxynitride, etc., and the metal oxide material includes titanium oxide or aluminum oxide.

For example, in the example of FIG. 14, the sum of the thicknesses of the fourth pixel defining sublayer 1404 and the third pixel defining sublayer 1403 is greater than or equal to 10 nm and less than or equal to 100 nm, the fourth pixel defining sublayer 1404, the third pixel defining sublayer 1403 1403. The sum of the thicknesses of the second pixel defining sublayer 1402 and the first pixel defining sublayer 1401 is greater than or equal to 150 nm and less than or equal to 300 nm.

For example, in some examples, the fourth pixel defining sublayer 1404, the third pixel defining sublayer 1403, the second pixel defining sublayer 1402, the first pixel defining sublayer 1401, and the pixel defining sublayer 1405 can respectively adopt silicon oxide, Silicon nitride, silicon oxide, silicon nitride, and silicon oxide, or aluminum oxide, silicon nitride, aluminum oxide, silicon nitride, and silicon oxide, respectively. For example, the thicknesses of the fourth pixel defining sublayer 1404, the third pixel defining sublayer 1403, the second pixel defining sublayer 1402, the first pixel defining sublayer 1401 and the pixel defining sublayer 1405 can be 20nm, 60nm, 20nm, 80nm and 20nm or 20nm, 70nm, 20nm, 50nm and 20nm respectively. For example, the retraction distance L2 of the third pixel defining sublayer 1403 relative to the fourth pixel defining sublayer 1404 can be 50nm-200nm, such as 150nm, and the inner distance L2 of the first pixel defining sublayer 1401 relative to the second pixel defining sublayer 1402 The shrinkage distance L3 can also be 50nm-200nm, for example, 150nm.

For example, in some embodiments, the second isolation structure 144 may also have a structure as shown in FIG. 15. Compared with the structure shown in FIG. 14, in FIG. 15, the pixel defining sublayer 1405 has a smaller width, The fourth pixel defining sublayer 1404 , the third pixel defining sublayer 1403 , the second pixel defining sublayer 1402 , and the first pixel defining sublayer 1401 have corresponding protrusions at the pixel defining sublayer 1405 . At this time, the thicknesses of the fourth pixel defining sublayer 1404, the third pixel defining sublayer 1403, the second pixel defining sublayer 1402, the first pixel defining sublayer 1401 and the pixel defining sublayer 1405 can be 20nm, 60nm, 20nm respectively . The setback distance L3 of 1402 may also be 50nm-200nm, such as 150nm.

For example, in some embodiments, as shown in FIG. 16 , the display substrate may further include a first auxiliary layer disposed on the side of the first pixel defining sublayer 1401 close to the driving circuit substrate 110 and exposed by a plurality of second isolation structures 144 . Electrode layer 201.

For example, as shown in FIGS. 17 and 18 , the display substrate may further include a second auxiliary electrode layer 202 disposed on a side of the second pixel defining sublayer 1402 away from the driving circuit substrate 110 .

For example, as shown in FIG. 19 and FIG. 20 , the display substrate may further include a third auxiliary electrode layer 203 disposed on a side of the fourth pixel defining sublayer 1404 away from the driving circuit substrate 110 . For example, in the embodiment of FIG. 20 , the fourth pixel defining sublayer 1404 has a recessed portion 1404A, the third auxiliary electrode layer 203 can be disposed in the recessed portion 1404A, and its surface is flush with the surface of the fourth pixel defining sublayer 1404 The overall thickness of the third auxiliary electrode layer 203 and the second isolation structure 144 can be reduced.

For example, in some embodiments, the display substrate may also include two or three of the first auxiliary electrode layer 201, the second auxiliary electrode layer 202 and the third auxiliary electrode layer 203. For example, FIG. 21 shows a display substrate An example of having the first auxiliary electrode layer 201 and the third auxiliary electrode layer 203 at the same time, FIG. 22 shows an example of the display substrate having the first auxiliary electrode layer 201 and the second auxiliary electrode layer 202 at the same time, and FIG. 23 shows the display substrate An example of having the second auxiliary electrode layer 202 and the third auxiliary electrode layer 203 at the same time, FIG. 24 shows an example of the display substrate having the first auxiliary electrode layer 201 , the second auxiliary electrode layer 202 and the third auxiliary electrode layer 203 at the same time.

For example, the material of the first auxiliary electrode layer 201 and/or the second auxiliary electrode layer 202 and/or the third auxiliary electrode layer 203 may include at least one of Al, Ti, TiN, Ag, Mo, ITO and IZO. The materials of the first auxiliary electrode layer 201 , the second auxiliary electrode layer 202 and the third auxiliary electrode layer 203 may be the same or different. For example, the thickness of the first auxiliary electrode layer 201 and/or the second auxiliary electrode layer 202 and/or the third auxiliary electrode layer 203 may be 5nm-100nm, such as 20nm, 30nm, 40nm or 50nm. The auxiliary electrode layer adopting the above arrangement can have a better effect of preventing electric field interference.

For example, in some embodiments, as shown in FIGS. 14-24, in an embodiment having a first notch 142A and a second notch 142B, referring to FIG. The position of the opening 142A is separated by the first distance W1, the fourth pixel defining sublayer 1404 is separated by the second distance W2 at the position of the second notch 142B, the second distance W2 is greater than the first distance W1, and the second distance W2 is the same as the first distance W2. The difference of the distance W1 is 100nm-500nm, such as 150nm, 250nm or 350nm. This helps the first notch 142A to disconnect a part of the luminescent material layer, and the second notch 142B to disconnect another part of the luminescent material layer.

For example, in the embodiment of the present disclosure, when the display substrate further includes the first auxiliary electrode layer 201 disposed on the side of the first pixel defining sublayer 1401 close to the driving circuit substrate 110 and exposed by the plurality of second isolation structures 144 Next, referring to FIG. 16 , the width W3 of the first auxiliary electrode layer 201 is greater than the first distance W1 , so as to fully realize the effect of preventing electric field interference.

In the embodiment of the present disclosure, since the functional layers such as the hole injection layer HIL and the charge generation layer N-CGL and P-CGL in the luminescent material layer have relatively high carrier mobility, when the luminescent material layer 150 includes When using the structure shown or a similar structure, since there are fewer functional layers with higher carrier mobility and the overall thickness is smaller, the isolation structure 142 with only the first notch 142A as shown in Figure 4A-Figure 13 is used The effect of disconnecting the functional layer with higher carrier mobility and avoiding crosstalk between adjacent sub-pixels can be realized.

For example, when the luminescent material layer 150 includes the structure shown in FIG. 27 or a similar structure, since there are relatively many functional layers with high carrier mobility and the overall thickness is relatively thick, at this time, the following can be used: 4A-FIG. 11 only have the partition structure 142 of the first notch 142A, and it is necessary to select an appropriate thickness of the first pixel defining sublayer 1401 and the second first pixel defining sublayer 1402 constituting the first notch 142A, Alternatively, the isolation structure 142 with the first notch 142A and the second notch 142B as shown in Fig. 14-Fig. The effect of crosstalk is generated between adjacent sub-pixels.

For example, when the luminescent material layer 150 includes the structure shown in FIG. 28 or a similar structure, since there are more functional layers with higher carrier mobility and the overall thickness is thicker, at this time, the structure shown in FIG. 14 can be used. - the isolation structure 142 with the first notch 142A and the second notch 142B in FIG. 25 , which can fully realize the disconnection of the functional layer with high carrier mobility and avoid the generation of gaps between adjacent sub-pixels. The effect of crosstalk.

Certainly, in some embodiments, the isolation structure 142 shown in FIGS. 4A-11 having only the first notch 142A can also be used to isolate the luminescent material layer shown in FIG. The partition structure 142 of the first notch 142A and the second notch 142B can also be used to partition the luminescent material layer shown in FIG. 26 , as long as the corresponding partition function can be realized.

For example, the display substrate shown in FIG. 3 includes the isolation structure shown in FIG. 24 . At this time, the luminescent material layer 150 includes, for example, the structure shown in FIG. 28 or a similar structure. For example, as shown in FIG. 3, the luminescent material layer 150 includes a plurality of portions 151-155, and the portion 151 may include a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a first light emitting layer EML1, and an electron transport layer. ETL, part 152 includes N-type charge generation layer N-CGL and P-type charge generation layer P-CGL, part 153 may include hole transport layer HTL, electron blocking layer EBL, second light emitting layer EML2 and electron transport layer ETL, part 154 may include an N-type charge generation layer N-CGL and a P-type charge generation layer P-CGL, and the portion 155 may include a hole transport layer HTL, an electron blocking layer EBL, a third light emitting layer EML3, an electron transport layer ETL, and an electron injection layer EIL . At this time, the first notch 142A is used to isolate the portion 151 and the portion 152, and the second notch 142B is used to isolate the portion 153 and the portion 154. Since there is no functional layer with a higher carrier mobility in the portion 155, the It may not be disconnected, as shown in FIG. 3 , or, in some other examples, the part 155 may also be disconnected by the partition structure 142 , which is not limited in this embodiment of the present disclosure.

For example, FIG. 29 shows a schematic plan view of a plurality of sub-pixels in a display substrate. As shown in FIG. 29 , in some embodiments, the sub-pixel openings 141 may be polygonal, such as hexagonal, and the partition structures 142 are arranged around the sub-pixel openings 141 . For example, the notch of the first partition structure 143 faces the sub-pixel opening 141, and the notch of the second partition structure 144 faces away from the sub-pixel opening 141. Both the first partition structure 143 and the second partition structure 144 can realize the disconnection of the luminescent material layer. 150 effects.

For example, in some embodiments, as shown in FIG. 25 , the first auxiliary electrode layer 201 and at least part of the plurality of first electrodes 130 may be arranged in the same layer and at intervals.

In the embodiments of the present disclosure, "set in the same layer" means that two functional layers or structural layers are formed of the same layer and material in the hierarchical structure of the display substrate, that is, in the manufacturing process, the two functional layers or structural layers can be formed by The same material layer is formed, and the required pattern and structure can be formed through the same patterning process. In this way, the manufacturing method of the display substrate can be simplified.

Partition Structure For example, as shown in FIG. 25 , in some embodiments, the first electrode 130 may include a first sub-electrode layer 131 and a second sub-electrode layer 132 that are stacked. The first sub-electrode layer 131 can be used as a reflective electrode for reflecting the light emitted by the light-emitting material layer formed thereon, so as to improve the light extraction rate of the light-emitting device. For example, the material of the first sub-electrode layer 131 may include titanium, molybdenum, aluminum or silver and other metal materials or alloy materials with high reflectivity, and the thickness may be 10nm-300nm, such as 50nm, 75nm or 100nm. For example, the second sub-electrode layer 132 has a higher work function and light transmittance, and the material of the second sub-electrode layer 132 may include transparent metal oxides, such as indium tin oxide (ITO), indium zinc oxide (IZO), Gallium zinc oxide (GZO), etc., the thickness may be 10nm-300nm, such as 20nm, 50nm or 100nm. Thus, the light reflected by the first sub-electrode layer 131 can pass through the second sub-electrode layer 132 almost without loss, so as to improve the light extraction efficiency and light output brightness of the light emitting device.

For example, in some examples, the first electrode 130 may also include more sub-electrode layers, for example, further include an adhesive sub-electrode layer between the first sub-electrode layer 131 and the second sub-electrode layer 132 and the first sub-electrode layer The connecting sub-electrode layer and the like (not shown in the figure) between the layer 131 and the driving circuit substrate 110, the bonding sub-electrode layer can use TiN etc., which can enhance the connection between the first sub-electrode layer 131 and the second sub-electrode layer 132. The bonding material, the connecting sub-electrode layer and the like may include titanium and other materials with low contact resistance. Embodiments of the present disclosure do not limit the specific structure of the first electrode 130 .

For example, in some examples, the first auxiliary electrode layer 201 and the second sub-electrode layer 132 may be disposed on the same layer, so as to simplify the manufacturing process of the display substrate.

In the embodiment of the present disclosure, the first auxiliary electrode layer 201 can play the role of etching cut-off when preparing the second isolation structure 144, so as to avoid the phenomenon of over-etching when the second isolation structure 144 is formed by etching; in addition In addition, the first auxiliary electrode layer 201 can also be electrically connected with other circuits to achieve the effect of draining current and preventing signal interference.

For example, as shown in FIG. 3 , the display substrate may further include a second electrode layer 160, the second electrode layer 160 is disposed on the side of the luminescent material layer 150 away from the driving circuit substrate 110 and at least located in the plurality of sub-pixel openings 141, for example , the second electrode layer 160 may serve as a cathode of the light emitting device.

For example, in some examples, the second electrode layer 160 may be continuously disposed, so that the light emitting devices of a plurality of sub-pixels on the display substrate may obtain substantially the same voltage from the second electrode layer 160 . Alternatively, in some other examples, the second electrode layer 160 may also be disconnected at the position of the isolation structure 142 . For example, the material of the second electrode layer 160 may be metal materials or alloy materials such as lithium, aluminum, magnesium, silver, or metal oxide materials such as IZO. For example, in one example, the second electrode layer 160 may include a stack of a MgAg alloy layer and an IZO layer.

For example, as shown in FIG. 30 , the second electrode layer 160 corresponding to the first part includes a fifth slope PO5 and a sixth slope PO6 at the disconnected position and the third slope PO3 respectively, and the fifth slope PO5 The slope angle i is smaller than the slope angle d of the first portion at the break position, and the slope angle h of the sixth slope PO6 is smaller than the slope angle f of the third slope PO3.

For example, the first part of the luminescent material layer 150 is a flat structure between the disconnected position (that is, the position of the first slope PO1) and the third slope PO3, and the second electrode layer 160 is between the fifth slope PO5 and the sixth slope PO5. Between the slopes PO6 is a flat structure, for example, within the range shown by the two dashed lines in FIG. 30 .

For example, in some embodiments, as shown in FIG. 3 , the display substrate may further include a light extraction layer 170, the light extraction layer 170 is disposed on the side of the second electrode layer 160 away from the driving circuit substrate 110, and the light extraction layer 170 The refractive index is 1.3-1.7, such as 1.5 or the like. The light extraction layer 170 can improve the light extraction efficiency of the light emitting device, thereby increasing the display brightness of the display substrate, or have lower power consumption when the display substrate has the same display brightness.

For example, in some embodiments, the material of the light extraction layer 170 includes at least one of LiF, SiOx and Al ₂ O ₃ , and the thickness may be 10nm-200nm, such as 30nm, 50nm or 100nm.

For example, in some embodiments, as shown in FIG. 3 , an encapsulation layer 180 may also be formed on the second electrode layer. For example, the encapsulation layer 180 can be a composite encapsulation layer laminated with an organic encapsulation layer 181 and an inorganic encapsulation layer 182, the organic encapsulation layer 181 can be made of organic materials such as polyimide and resin, and the inorganic encapsulation layer 182 can be made of silicon oxide, nitride Inorganic materials such as silicon or silicon oxynitride. For example, in some examples, the encapsulation layer 180 may also include a stack of more organic encapsulation layers and inorganic encapsulation layers 182, FIG. 3 shows only one organic encapsulation layer 181 and one inorganic encapsulation layer 182 as an example, Embodiments of the present disclosure do not limit the specific form of the encapsulation layer 180 .

For example, in some embodiments, as shown in FIG. 3 , a color filter layer 190 may also be provided on the encapsulation layer 180, and the color filter layer 190 includes a plurality of color filters, two color filters are shown in the figure. Filters 191 and 192 are taken as examples. For example, each color filter is set corresponding to the light-emitting area of the light-emitting device of the sub-pixel. For example, a plurality of color filters can respectively transmit light of different colors. For example, in some examples, the light-emitting device of each sub-pixel can emit white light. At this time, the colors of the color filters set on the light-emitting device of each sub-pixel can be red, green, blue, etc., so as to realize full-color display; or, the light-emitting device of each sub-pixel can emit light of different colors, such as red, green and blue, etc., at this time, the color of the color filter arranged on the light-emitting device of each sub-pixel is consistent with the light emitted by the light-emitting device The colors of the light are the same, so that the color purity of the light emitted by the light emitting device can be improved.

For example, the color filter may be at least one of a resin material filter, a fluorescent dye filter and a quantum dot filter, which is not limited in the embodiments of the present disclosure.

For example, in some embodiments, as shown in FIG. 3 , a lens layer 210 can also be provided on the color filter layer 190, and the lens layer 210 can be a continuous structure formed on the entire surface, or include multiple pixels corresponding to different sub-pixels. A lens 211 (the situation shown in the figure) is used to refract the light emitted by each sub-pixel, so that the luminous effect of the entire display substrate is better and uniform. For example, in some examples, lens 211 may be a convex lens. For example, the lens 211 may adopt a single-layer or multi-layer structure. When a multi-layer structure is adopted, the refractive index of each layer increases sequentially from inside to outside in the lens 211 . The shape of the lens 211 may be spherical, cylindrical or prismatic. Embodiments of the present disclosure do not limit the specific form of the lens layer 210 .

For example, in the embodiment of the present disclosure, as shown in FIG. 3 , the driving circuit substrate 10 can be formed by using a silicon-based substrate 111 and using semiconductor manufacturing technology to form various functional layers on the silicon-based substrate 111 , for example, the driving circuit substrate 10 The above-mentioned preparation process can be completed in a wafer factory. Therefore, the display substrate provided by the embodiment of the present disclosure can directly form the first electrode 130, the pixel defining layer 140, the light-emitting material layer 150, and the second electrode layer on the driving circuit substrate 10. 160 and other structures, and the preparation process is simple. Moreover, since the manufacturing process of the silicon-based driving circuit substrate is mature and its performance is stable, it is suitable for manufacturing highly integrated micro-display devices. Therefore, the display substrate provided by the embodiments of the present disclosure may be a silicon-based micro-organic light-emitting diode display substrate, for example, it may be used in display devices such as virtual reality (VR) display devices, augmented reality (AR) display devices, mobile phones, and televisions. When , the display device may have a relatively high resolution, such as a resolution greater than 500PPI, such as a resolution greater than 3000PPI. Alternatively, in some embodiments, the driving circuit substrate 10 may also be a glass substrate, which is used in glass-based high-resolution display products of different sizes such as TVs and mobile phones.

There are a few more things to note:

(1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to common designs.

(2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thicknesses of layers or regions are exaggerated or reduced, that is, the drawings are not drawn in actual scale. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element, or Intermediate elements may be present.

(3) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims (41)

1. A display substrate has a plurality of sub-pixels arranged in an array, and includes:

   A driving circuit substrate comprising a plurality of pixel driving circuits for the plurality of sub-pixels and a protective insulating layer covering the plurality of pixel driving circuits, wherein the protective insulating layer includes an output layer exposing the plurality of pixel driving circuits multiple first vias at the end,

   a plurality of first electrodes, disposed on the driving circuit substrate, and electrically connected to the output ends of the plurality of pixel driving circuits through the plurality of first via holes; and

   A pixel defining layer, disposed at least on a side of the plurality of first electrodes away from the driving circuit substrate, including a plurality of sub-pixel openings respectively exposing the plurality of first electrodes and a pixel defining layer disposed on the pixel defining layer at least one partition structure; and

   A luminescent material layer disposed on a side of the pixel defining layer away from the driving circuit substrate and at least located in the plurality of sub-pixel openings, wherein the pixel defining layer includes a first pixel defining sublayer and a second pixel Defining a sublayer, the second pixel defining sublayer is disposed on a side of the first pixel defining sublayer away from the drive circuit substrate, and the width of the second pixel defining sublayer is larger than that of the first pixel defining sublayer width.
2. The display substrate according to claim 1, wherein the protective insulating layer is a planar structure at the position of the at least one isolation structure except for the first via hole.
3. The display substrate according to claim 1 or 2, wherein a sidewall of each of the at least one partition structure has a first notch.
4. The display substrate according to claim 3, wherein, at the position of the at least one partition structure, the first pixel defining sublayer is retracted relative to the second pixel defining sublayer to form the first concave mouth.
5. The display substrate according to claim 4, wherein a width of the second pixel defining sublayer is smaller than a width between adjacent first electrodes.
6. The display substrate according to claim 4, wherein the first pixel defining sublayer comprises an inorganic insulating material, and the second pixel defining sublayer comprises an inorganic insulating material or a metal oxide material.
7. The display substrate according to any one of claims 4-6, wherein the thickness of the first pixel defining sublayer is greater than the thickness of the second pixel defining sublayer.
8. The display substrate according to any one of claims 4-7, wherein the at least one isolation structure comprises a plurality of first isolation structures, the plurality of first isolation structures respectively surround the plurality of sub-pixel openings, and the The first notches of the plurality of first isolation structures respectively open toward the plurality of sub-pixels.
9. The display substrate according to any one of claims 4-8, wherein the distance between the surface of the first pixel defining sublayer close to the driving circuit substrate and the driving circuit substrate is greater than that of the plurality of first electrodes The distance between the surface away from the driving circuit substrate and the driving circuit substrate.
10. The display substrate according to claim 8, wherein the at least one partition structure further includes a plurality of second partition structures, and the plurality of second partition structures are respectively arranged on adjacent ones of the plurality of first partition structures. Between the two first partition structures.
11. The display substrate according to claim 10, wherein the distance between the plurality of first isolation structures and the driving circuit substrate is equal to the distance between the plurality of second isolation structures and the driving circuit substrate; or

    The distance between the plurality of first isolation structures and the driving circuit substrate is greater than the distance between the plurality of second isolation structures and the driving circuit substrate.
12. The display substrate according to claim 10 or 11, wherein the second pixel defining sublayer has a first slope angle on the sidewalls of the plurality of first isolation structures, and the first slope angle is 30°- 75°;

    The second pixel defining sublayer has a second slope angle on sidewalls of the plurality of second isolation structures, and the second slope angle is 30°-80°.
13. The display substrate according to claim 12, wherein the slope angle of the first pixel defining sublayer on the sidewalls of the plurality of first isolation structures is larger than that of the second pixel defining sublayer on the plurality of second isolation structures. The slope angle of the side walls of a partition structure.
14. The display substrate according to claim 12 or 13, wherein the luminescent material layer is broken at the first notch, and the luminescent material layer includes a first part for emitting light and a second part not for emitting light. part, the luminescent material layer is disconnected at the position of the second part, and the slope angle of the first part is larger than the slope angle of the second part at the disconnected position.
15. The display substrate according to any one of claims 4-14, wherein the depth of the first notch in a direction parallel to the board surface of the base substrate is greater than that of the first pixel defining sublayer and the first pixel defining sublayer. Two pixels define the thickness of the sublayer in a direction perpendicular to the plane of the base substrate.
16. The display substrate according to any one of claims 1-15, wherein the thickness of the luminescent material layer is greater than the thickness of the first pixel defining sublayer and greater than the thickness of the second pixel defining sublayer.
17. The display substrate according to claim 14, wherein the luminescent material layer further includes a third slope portion away from the disconnection position, and the slope angle of the third slope portion is smaller than that of the first portion near the disconnection. The slope angle at the open position is smaller than the slope angle at the position where the second portion is close to the disconnected position.
18. The display substrate according to claim 17, wherein, at a position corresponding to the third slope, the pixel defining layer includes a fourth slope, and the slope angle of the fourth slope is larger than that of the third slope. The slope angle of the section.
19. The display substrate according to claim 18, wherein a slope angle of the fourth slope portion is smaller than a slope angle of the first portion near the disconnection position.
20. The display substrate according to claim 18 or 19, wherein a slope angle of the fourth slope portion is smaller than a slope angle of the second slope angle near the disconnection position.
21. The display substrate according to any one of claims 10-15, further comprising a first auxiliary layer disposed on the side of the first pixel defining sublayer close to the driving circuit substrate and exposed by the plurality of second isolation structures. electrode layer.
22. The display substrate according to claim 21, wherein the first pixel defining sublayer covers an edge of the first auxiliary electrode layer.
23. The display substrate according to claim 21, wherein the width of the first auxiliary electrode layer is greater than the depth of the first recess in a direction parallel to the plate surface of the base substrate.
24. The display substrate according to any one of claims 4-7, wherein the at least one isolation structure comprises a plurality of second isolation structures, and the plurality of second isolation structures are respectively arranged between the plurality of first electrodes .
25. The display substrate according to claim 24 , wherein the distance between the surface of the first pixel defining sublayer that is far away from the driving circuit substrate and the driving circuit substrate is smaller than the distance between the surface of the first pixel defining sublayer and the plurality of first electrodes. The distance between the surface of the driving circuit substrate and the driving circuit substrate.
26. The display substrate according to claim 24 or 25, further comprising:

    A first auxiliary electrode layer disposed on a side of the first pixel defining sublayer close to the driving circuit substrate and exposed by the plurality of second isolation structures; and/or

    A second auxiliary electrode layer disposed on a side of the second pixel defining sublayer away from the driving circuit substrate.
27. The display substrate according to any one of claims 24-26, wherein the first pixel defining sublayer is set back by 10nm-200nm relative to the second pixel defining sublayer.
28. The display substrate according to any one of claims 24-27, wherein the sidewall of each of the plurality of second partition structures further has a second notch, and the second notch is arranged on the first notch. The side of the port away from the drive circuit substrate.
29. The display substrate according to claim 28, wherein the pixel defining layer further comprises a third pixel defining sublayer and a fourth pixel defining sublayer arranged in layers, wherein the third pixel defining sublayer is arranged on the The second pixel defining sublayer is located on a side away from the driving circuit substrate, the fourth pixel defining sublayer is disposed on a side of the third pixel defining sublayer away from the driving circuit substrate,

    At the positions of the plurality of second isolation structures, the third pixel defining sublayer is retracted relative to the fourth pixel defining sublayer to form the second notch.
30. The display substrate according to claim 29, wherein the luminescent material layer comprises at least one charge generation layer or hole injection layer.
31. The display substrate according to claim 29 or 30, further comprising:

    a first auxiliary electrode layer disposed on a side of the first pixel defining sublayer close to the driving circuit substrate and exposed by the plurality of second isolation structures; and/or

    a second auxiliary electrode layer disposed on a side of the second pixel defining sublayer away from the driving circuit substrate; and/or

    A third auxiliary electrode layer disposed on a side of the fourth pixel defining sublayer away from the driving circuit substrate.
32. The display substrate according to claim 31, wherein the material of the first auxiliary electrode layer and/or the second auxiliary electrode layer and/or the third auxiliary electrode layer comprises Al, Ti, TiN, Ag, At least one of Mo, ITO and IZO.
33. The display substrate according to claim 29 or 30, wherein the second pixel defining sublayer is separated by a first distance at the position of the first notch, and the fourth pixel defining sublayer is separated at the second the position of the notch is separated by the second distance;

    The second distance is greater than the first distance by 100nm-500nm.
34. The display substrate according to claim 33, further comprising:

    a first auxiliary electrode layer disposed on a side of the first pixel defining sublayer close to the driving circuit substrate and exposed by the plurality of second isolation structures,

    Wherein, the width of the first auxiliary electrode layer is greater than the first distance.
35. The display substrate according to any one of claims 29-34, wherein the first pixel defining sublayer is set back by 50nm-200nm relative to the second pixel defining sublayer;

    The third pixel defining sublayer is set back by 50nm-200nm relative to the fourth pixel defining sublayer.
36. The display substrate according to any one of claims 21, 31 and 34, wherein the first auxiliary electrode and at least part of the plurality of first electrodes are arranged in the same layer and at intervals.
37. The display substrate according to claim 17, further comprising:

    The second electrode layer is disposed on a side of the luminescent material layer away from the driving circuit substrate and at least located in the plurality of sub-pixel openings,

    Wherein, the second electrode layer is arranged continuously.
38. The display substrate according to claim 37, wherein the second electrode layer includes a fifth slope and a sixth slope at the position of the disconnection and the position of the third slope corresponding to the first portion, respectively. The slope angle of the fifth slope portion is smaller than the slope angle of the first portion at the disconnection position, and the slope angle of the sixth slope portion is smaller than the slope angle of the third slope portion.
39. The display substrate according to claim 38, wherein the luminescent material layer is a flat structure between the disconnected position of the first portion and the third slope portion, and the second electrode layer is formed at the third slope portion. There is a flat structure between the fifth slope and the sixth slope.
40. The display substrate according to claim 37, further comprising:

    a light extraction layer disposed on a side of the second electrode layer away from the drive circuit substrate,

    Wherein, the refractive index of the light extraction layer is 1.3-1.7.
41. The display substrate according to claim 40, wherein the material of the light extraction layer comprises at least one of LiF, SiOx and Al ₂ O ₃ .

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