WO2023092408A1 - 一种通信方法、装置及系统 - Google Patents

一种通信方法、装置及系统 Download PDF

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Publication number
WO2023092408A1
WO2023092408A1 PCT/CN2021/133256 CN2021133256W WO2023092408A1 WO 2023092408 A1 WO2023092408 A1 WO 2023092408A1 CN 2021133256 W CN2021133256 W CN 2021133256W WO 2023092408 A1 WO2023092408 A1 WO 2023092408A1
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sequence
bits
ber
subsequence
fec code
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PCT/CN2021/133256
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English (en)
French (fr)
Inventor
张兴新
鲍鹏鑫
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华为技术有限公司
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Priority to PCT/CN2021/133256 priority Critical patent/WO2023092408A1/zh
Publication of WO2023092408A1 publication Critical patent/WO2023092408A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector

Definitions

  • the embodiments of the present application relate to the field of communication technologies, and in particular, to a communication method, device, and system.
  • the performance of the transmission chip is very important to the transmission rate of the data. For this reason, it is often necessary to test the performance of the transmission chip.
  • the bit error rate (BER) is an important indicator of the transmission chip, which can be obtained by testing the transmission chip. Conduct BER test to verify whether the transmission chip reaches the set BER index.
  • the uplink rate of the transmission chip in a vehicle-mounted high-definition camera often reaches 1-10Gbps, while the downlink rate is generally only 1Gbps. ⁇ 100Mbps.
  • the present application provides a communication method, device and system for performing BER test on a transmission chip in an asymmetric transmission scenario.
  • the communication method provided in this application may be executed by a second device, where the second device may serve as a test equipment (Test Equipment, TE).
  • the second device can be abstracted as a computer system.
  • the second device may be a whole machine, or part of devices in the whole machine, such as a system chip or a processing chip.
  • the system chip may also include a system on chip (system on chip, SOC), or a SoC chip.
  • the second device may be a separate device for performing BER test on the device under test, or the second device may be a device in the whole machine for performing BER test on the device under test.
  • the second device may be an on-board computer with a BER test function, a terminal device such as a vehicle machine, or an on-board device, or it may be a system chip with a BER test function that can be installed in a computer system of a vehicle or an on-board device. Decision processing chips or other types of chips, etc.
  • the embodiment of the present application provides a communication method, including:
  • Sending a first sequence to the first device the first sequence is used by the first device to count a first bit error rate BER, the first sequence includes P subsequences A, and the subsequences A constitute one or more Forward error correction FEC code block; send a second sequence to the first device, the second sequence is used for the first device to count the second BER, the second sequence includes Q sub-sequences B, the sub-sequence Sequence B constitutes one or more FEC code blocks; wherein, the length of the second sequence is greater than or equal to the length of the first sequence, and P and Q are positive integers.
  • the first sequence and the second sequence may be sent respectively.
  • the second device may first send the first sequence to the first device, and then send the second sequence to the first device.
  • the first sequence and the second sequence may be sent simultaneously.
  • the second device sends first information to the first device, and the first information includes the first sequence and the second sequence.
  • this method since the BER test performed by this application effectively utilizes the FEC code block used in equipment transmission as the minimum repeating unit of the first sequence and the second sequence, the complexity of constructing the test sequence for the equipment is reduced, and the robustness of the test process is improved. . Further, when the length of the second sequence is greater than the length of the first sequence, the time of the function test based on the first sequence can be effectively shortened and the test speed can be improved. For asymmetric transmission scenarios, this method can be used to perform a one-way BER test, which can simplify the test process and time, and improve test efficiency. It can be understood that this test method can also be applied to symmetric transmission scenarios.
  • the second sequence is sent to the first device.
  • the first preset BER may be a specific value. Wherein, when the first preset BER is a specific value, the first BER is equal to the first preset BER, then it is determined that the first BER satisfies the first preset BER; or, when the first preset BER is a specific value, If the first BER is within a floating range based on the first preset BER, it is determined that the first BER satisfies the first preset BER.
  • the left boundary of the floating range based on the first preset BER can be obtained by subtracting the first value from the first preset BER
  • the right boundary of the floating range based on the first preset BER can be obtained by subtracting the first value from the first preset BER.
  • the first value and the second value may be equal or different, and both are positive numbers.
  • the left boundary of the floating range based on the first preset BER may be obtained by multiplying the first preset BER by the first ratio
  • the right boundary of the floating range based on the first preset BER may be obtained by multiplying the first It is obtained by multiplying the preset BER by the second ratio, where the second ratio is greater than the first ratio and both are positive numbers.
  • the first preset BER may also be a value range. Wherein, when the first preset BER is in a value range, and the first BER is within the value range of the first preset BER, it is determined that the first BER satisfies the first preset BER.
  • this method provides a situation in which the second device is triggered to send the second sequence to the first device in an asymmetric transmission scenario, for example, when it is determined that the first device calculates the first sequence based on the received first sequence
  • the first device has accurate error detection and statistical capabilities, which can better ensure that the subsequent performance test results of the first device based on the second sequence are accurate and reliable, so the first device can be triggered.
  • the second device sends the second sequence to the first device.
  • the tester may manually judge whether the first BER calculated by the first device based on the received first sequence satisfies the first preset BER.
  • the second device is artificially triggered to send the second sequence to the first device; or, the present application determines that the first device is based on
  • the first device may return the first BER to the first BER Two devices, so that the second device judges whether the received first BER satisfies the first preset BER, and when the second device determines that the first BER satisfies the first preset BER, it triggers sending the second sequence to the first device.
  • the subsequence A includes N bits; the subsequence A includes M abnormal bits; the ratio of M or M to N corresponds to the first preset BER; wherein, N and M are positive integers, and N is greater than or equal to M. Therefore, the present application provides a method for constructing the subsequence A.
  • the M in the embodiment of the present application corresponds to the first preset BER, which means that when the test device needs to meet different first preset BERs, it can flexibly set the first Default BER.
  • the corresponding first preset BER is BER1
  • the M value in subsequence A is M2
  • the corresponding first preset BER is BER2
  • the ratio of M to N in the embodiment of the present application corresponds to the first preset BER, which means that when the test device needs to meet different first preset BERs, it can be flexibly adjusted by adjusting the ratio of M to N in the subsequence A.
  • Set the first preset BER For example, when the ratio of M to N in subsequence A is the first ratio, the corresponding first preset BER is BER3; when the ratio of M to N in subsequence A is the second ratio, the corresponding first The preset BER is BER4, and when the test device wants to set the first preset BER to BER3, the ratio of M and N in the subsequence A can be adjusted to the first ratio.
  • the second device when the application performs BER testing in an asymmetric transmission scenario, for example, in the scenario of performing BER testing on the transmission chip in the vehicle-mounted high-definition camera, the second device does not need additional circuits to encode and generate the first sequence.
  • the first sequence can be generated based on one or more stored FEC units, which can better adapt to the case of using FEC code block transmission in an asymmetric transmission scenario.
  • the first preset BER needs to be adjusted, one way can be to flexibly construct a function test matching the first preset BER by adjusting the value of the abnormal bit M in the subsequence A.
  • the first sequence or in this application, when a new first sequence needs to be set, a new first sequence can be obtained by adjusting the value of the abnormal bit M in subsequence A; in this application, when it is necessary to adjust the first preset For BER, another way is to flexibly construct the first sequence for functional testing that matches the first preset BER by adjusting the ratio of M to N in subsequence A, or to set a new first sequence in this application A new first sequence can be obtained by adjusting the ratio of M and N in the subsequence A.
  • the N bits are the number of bits included in the effective sequence in the subsequence A; the M bits are the number of abnormal bits included in the effective sequence in the subsequence A; or the The N bits are the number of bits included in the effective sequence and the redundant sequence in the subsequence A; the M bits are the number of abnormal bits included in the effective sequence and the redundant sequence in the subsequence A; wherein,
  • Each FEC code block in the one or more FEC code blocks includes a data symbol sequence and a redundant symbol sequence, and the effective sequence in the subsequence A includes the data code of the one or more FEC code blocks An element sequence, wherein the redundant sequence in the subsequence A includes the redundant symbol sequence of the one or more FEC code blocks.
  • the number of bits included in the effective sequence in the subsequence A in this application refers to the number of bits included in the data symbol sequences of all the FEC code blocks constituting the subsequence A.
  • the number of bits included in the redundant sequence in the subsequence A in this application refers to the number of bits included in the redundant symbol sequences used to form all the FEC code blocks of the subsequence A.
  • the first device when the first device counts the first BER based on the first sequence, it may only count the data symbol sequences in the FEC code blocks that constitute the first sequence. Therefore, in the design When the BER is first preset, only the data symbol sequences in the FEC code blocks constituting the first sequence may be considered.
  • the N bits corresponding to the first preset BER at this time are the number of bits included in the effective sequence in the subsequence A; the M bits are the number of abnormal bits included in the effective sequence in the subsequence A.
  • the first device when the first device calculates the first BER based on the first sequence, it may also consider all the symbols in the FEC code blocks that constitute the first sequence, that is, the data symbols sequence and redundant symbol sequence, therefore, when designing the first preset BER, all symbols in the FEC code blocks constituting the first sequence can be considered.
  • the N bits corresponding to the first preset BER are the number of bits included in the effective sequence and redundant sequence in subsequence A; the M bits are the abnormalities included in the effective sequence and redundant sequence in subsequence A number of bits.
  • the subsequence A includes X first FEC code blocks and Y second FEC code blocks; the bits included in the data symbol sequence of the first FEC code block are all normal bits;
  • the data symbol sequence of the second FEC code block includes a fixed number of abnormal bits or a fixed proportion of abnormal bits; the ratio of Y or Y to (X+Y) corresponds to the first preset BER; wherein, X and Y are positive integers. Therefore, the present application provides another composition method of the subsequence A.
  • the correspondence between Y and the first preset BER in the embodiment of the present application means that the test device can flexibly set the first preset BER by adjusting the value of Y in subsequence A when it needs to meet different first preset BERs.
  • Default BER For example, when the Y value in subsequence A is Y1, the corresponding first preset BER is BER1; when the Y value in subsequence A is Y2, the corresponding first preset BER is BER2, then when the test device When you want to set the first preset BER to BER1, you can adjust the Y value in subsequence A to Y1.
  • the ratio of Y to (X+Y) corresponds to the first preset BER, which means that when the test device needs to meet different first preset BERs, it can adjust the Y and (X+Y) ratio, flexible setting of the first preset BER.
  • the corresponding first preset BER is BER3
  • the ratio of Y to (X+Y) in subsequence A is the first
  • the corresponding first preset BER is BER4
  • the test device wants to set the first preset BER to BER3
  • the ratio of Y and (X+Y) in subsequence A can be adjusted to the first ratio.
  • the second device when the application performs BER testing in an asymmetric transmission scenario, for example, in the scenario of performing BER testing on the transmission chip in the vehicle-mounted high-definition camera, the second device does not need additional circuits to encode and generate the first sequence.
  • the first sequence can be generated based on one or more stored FEC units, which can better adapt to the case of using FEC code block transmission in an asymmetric transmission scenario.
  • the first preset BER when the first preset BER needs to be adjusted, one way can be to flexibly construct the first sequence for functional testing that matches the first preset BER by adjusting the Y value in subsequence A, Or in this application, when it is necessary to set a new first sequence, a new first sequence can be obtained by adjusting the different Y value in subsequence A; in this application, when it is necessary to adjust the first preset BER, another way By adjusting the ratio of Y and (X+Y) in subsequence A, flexibly construct the first sequence for functional testing that matches the first preset BER, or when a new first sequence needs to be set in this application , a new first sequence can be obtained by adjusting the ratio of Y in subsequence A to (X+Y).
  • the present application provides another composition method of the subsequence A.
  • all the bits included in the redundant symbol sequence of the first FEC code block are normal bits; all the bits included in the redundant symbol sequence of the second FEC code block are also abnormal bits.
  • the first device when the first device counts the first BER based on the first sequence, it can only count the effective sequences in the FEC code blocks that constitute the first sequence. Therefore, when designing the first When presetting the BER, only the data symbol sequences in the FEC code blocks constituting the first sequence may be considered. For example, at this time, the bits included in the data symbol sequence of the first FEC code block corresponding to the first preset BER are all normal bits; the bits included in the data symbol sequence of the second FEC code block are all abnormal bits.
  • the first device when the first device calculates the first BER based on the first sequence, it may also consider all the symbols in the FEC code blocks that constitute the first sequence, that is, the data symbols sequence and redundant symbol sequence, therefore, when designing the first preset BER, all symbols in the FEC code blocks constituting the first sequence can be considered.
  • all the bits included in the data symbol sequence and redundant symbol sequence of the first FEC code block corresponding to the first preset BER are normal bits; the data symbol sequence and redundant code element sequence of the second FEC code block All the bits included in the meta-sequence are abnormal bits.
  • the length of the subsequence A is equal to the length of the subsequence B.
  • the normal bits in this embodiment of the application can be understood as bits that match the expected value. For example, if the sequence sent by the test device to the device under test is 10111, the expected bit received by the device under test should be 10111 . If the sequence received by the device under test is 11011, the bits corresponding to the first, fourth, and fifth bits of the sequence received by the device under test are in line with the expected value, which is a normal bit, and the sequence received by the device under test The bit corresponding to the second and third bit does not match the expected value, which is an abnormal bit.
  • the application sets the abnormal bit value to 1 by setting the value of the normally received bit to 0; or, by setting the value of the normally received bit to 1, the abnormal bit value is set to 0, so that the tested device
  • BER statistics can be performed by recording the number of bits with a value of 1 or 0. The statistical method is more simplified and helps to determine the first BER more quickly and efficiently.
  • the bits included in the first FEC code block may all be 0, and the bits included in the second FEC code block may all be 1; when the normal bit value is When 1, the bits included in the first FEC code block may all be 1, and the bits included in the second FEC code block may all be 0.
  • the present application sets all the bits included in the second FEC code block to 1 by setting all the bits included in the first FEC code block to 1 when the normal bit value is 0; or, when the normal bit value is When 1, set all the bits included in the first FEC code block to 1, and set all the bits included in the second FEC code block to 0, so that in an asymmetric transmission scenario, the device under test is based on the first sequence or the second sequence.
  • BER statistics can be performed by recording the number of the first FEC code block and/or the number of the second FEC code block. The statistical method is more simplified and helps to determine the first BER more quickly and efficiently.
  • the second device before the second device sends the first sequence to the first device, the second device performs link training with the first device.
  • link training is performed before the actual test, so that the receiving parameters of the second device (that is, the device under test) can be effectively converged, the actual test process is more stable, and the obtained test results are more accurate.
  • the communication method provided in this application can be executed by the first device, where the first device can be used as a device under test (Device Under Test, DUT).
  • the first device can be abstracted as a computer system.
  • the first device may be a whole machine, or part of devices in the whole machine, such as a system chip or a processing chip.
  • the system chip may also include a system on chip (system on chip, SOC), or a SoC chip.
  • the first device may be a separate device for performing BER test, or the first device may be a device for performing BER test in the whole machine.
  • the first device may be a terminal device or a vehicle-mounted device such as a vehicle camera or a vehicle display that needs to perform a BER test, or may be a device used in the camera or display that needs to perform a BER test.
  • Data Controller, MDC MDC
  • decision processing chip or other types of chips for data transmission.
  • the embodiment of the present application provides a communication method, including:
  • the first sequence includes P subsequences A, the subsequences A constitute one or more forward error correction FEC code blocks; count the first bit errors of the received first sequence rate BER; receive the second sequence sent by the second device, the second sequence includes Q subsequences B, and the subsequences B constitute one or more forward error correction FEC code blocks; count the received second sequence The second BER; wherein, the length of the second sequence is greater than or equal to the length of the first sequence, and P and Q are positive integers.
  • the first device can receive the first sequence and the second sequence respectively. For example, the first device receives the first sequence sent by the second device first, and then receives the second sequence. The second sequence sent after the device.
  • the first device may receive the first sequence and the second sequence at the same time, for example, the first device may receive the first information sent by the second device, in the first information Including the first sequence and the second sequence.
  • this method since the BER test performed by this application effectively utilizes the FEC code block used in equipment transmission as the minimum repeating unit of the first sequence and the second sequence, the complexity of constructing the test sequence for the equipment is reduced, and the robustness of the test process is improved. . Further, when the length of the second sequence is greater than the length of the first sequence, the time of the function test based on the first sequence can be effectively shortened and the test speed can be improved. For asymmetric transmission scenarios, this method can be used to perform a one-way BER test, which can simplify the test process and time, and improve test efficiency. It can be understood that this test method can also be applied to symmetric transmission scenarios.
  • count the number of abnormal bits in the received first sequence or count the ratio of the number of abnormal bits in the received first sequence to the total number of bits in the received first sequence.
  • a manner of determining the first BER is provided, for example, determining the first BER by recording the number of abnormal bits in the first sequence.
  • the first device determines the first BER of the first sequence, it can directly count the abnormal bits without comparing them one by one, which can effectively increase the speed of the first device to count the first BER.
  • count the number of abnormal bits in the received second sequence or count the ratio of the number of abnormal bits in the received second sequence to the total number of bits in the received second sequence.
  • a manner of determining the second BER is provided, for example, determining the second BER by recording the number of abnormal bits in the second sequence.
  • the first device determines the second BER of the second sequence, it can directly count the abnormal bits without comparing them one by one, which can effectively increase the speed of the first device to count the second BER.
  • the received second BER of the second sequence is counted.
  • the first preset BER may be a specific value. Wherein, when the first preset BER is a specific value, the first BER is equal to the first preset BER, then it is determined that the first BER satisfies the first preset BER; or, when the first preset BER is a specific value, If the first BER is within a floating range based on the first preset BER, it is determined that the first BER satisfies the first preset BER.
  • the left boundary of the floating range based on the first preset BER can be obtained by subtracting the first value from the first preset BER
  • the right boundary of the floating range based on the first preset BER can be obtained by subtracting the first value from the first preset BER.
  • the first value and the second value may be equal or different, and both are positive numbers.
  • the left boundary of the floating range based on the first preset BER may be obtained by multiplying the first preset BER by the first ratio
  • the right boundary of the floating range based on the first preset BER may be obtained by multiplying the first It is obtained by multiplying the preset BER by the second ratio, where the second ratio is greater than the first ratio and both are positive numbers.
  • the first preset BER may also be a value range. Wherein, when the first preset BER is in a value range, and the first BER is within the value range of the first preset BER, it is determined that the first BER satisfies the first preset BER.
  • this method provides a situation in which the first device is triggered to count the second BER of the second sequence in an asymmetric transmission scenario, for example, when the first BER calculated by the first device based on the first sequence meets the first BER
  • BER is preset, it is considered that the first device has accurate error detection and statistical capabilities, which can better ensure that the results of subsequent performance tests of the first device are ready and reliable, so the BER of the first device based on the second sequence can be triggered test.
  • the tester may manually judge whether the first BER calculated by the first device based on the received first sequence satisfies the first preset BER.
  • the tester when the tester determines that the first BER satisfies the first preset BER, the tester artificially triggers the first device to count the second BER of the second sequence; or, the present application determines that the first device is based on receiving
  • the first BER calculated by the first sequence obtained meets the first preset BER the first BER can also be sent back to the second device through the first device, so that the second device can judge whether the received first BER is The first preset BER is satisfied, and if satisfied, the second sequence is sent to the first device, so that the first device triggers to count the second BER of the second sequence after receiving the second sequence.
  • the subsequence A includes N bits; the subsequence A sequence includes M abnormal bits; the ratio of M or M to N corresponds to the first preset BER; wherein , N and M are positive integers, and N is greater than or equal to M. Therefore, the present application provides a method for constructing the subsequence A.
  • the M in the embodiment of the present application corresponds to the first preset BER, which means that when the test device needs to meet different first preset BERs, it can flexibly set the first Default BER.
  • the corresponding first preset BER is BER1
  • the M value in subsequence A is M2
  • the corresponding first preset BER is BER2
  • the ratio of M to N in the embodiment of the present application corresponds to the first preset BER, which means that when the test device needs to meet different first preset BERs, it can be flexibly adjusted by adjusting the ratio of M to N in the subsequence A.
  • Set the first preset BER For example, when the ratio of M to N in subsequence A is the first ratio, the corresponding first preset BER is BER3; when the ratio of M to N in subsequence A is the second ratio, the corresponding first The preset BER is BER4, and when the test device wants to set the first preset BER to BER3, the ratio of M and N in the subsequence A can be adjusted to the first ratio.
  • the first device is the transmission chip in the vehicle-mounted high-definition camera
  • the second device performs the BER test on the transmission chip in the vehicle-mounted high-definition camera
  • the second device No additional circuits are needed to encode and generate the first sequence, and the first sequence can be generated based on one or more stored FEC units, which can better adapt to the situation of using FEC code block transmission in asymmetric transmission scenarios.
  • the first preset BER needs to be adjusted, one way can be to flexibly construct a function test matching the first preset BER by adjusting the value of the abnormal bit M in the subsequence A.
  • the first sequence or in this application, when a new first sequence needs to be set, a new first sequence can be obtained by adjusting the value of the abnormal bit M in subsequence A; in this application, when it is necessary to adjust the first preset For BER, another way is to flexibly construct the first sequence for functional testing that matches the first preset BER by adjusting the ratio of M to N in subsequence A, or to set a new first sequence in this application A new first sequence can be obtained by adjusting the ratio of M and N in the subsequence A.
  • the N bits are the number of bits included in the effective sequence in the subsequence A; the M bits are the number of abnormal bits included in the effective sequence in the subsequence A; or the The N bits are the number of bits included in the effective sequence and the redundant sequence in the subsequence A; the M bits are the number of abnormal bits included in the effective sequence and the redundant sequence in the subsequence A; wherein,
  • Each FEC code block in the one or more FEC code blocks includes a data symbol sequence and a redundant symbol sequence, and the effective sequence in the subsequence A includes the data code of the one or more FEC code blocks An element sequence, wherein the redundant sequence in the subsequence A includes the redundant symbol sequence of the one or more FEC code blocks.
  • the number of bits included in the effective sequence in the subsequence A in this application refers to the number of bits included in the data symbol sequences of all the FEC code blocks constituting the subsequence A.
  • the number of bits included in the redundant sequence in the subsequence A of the present application refers to the number of bits included in the redundant symbol sequence used to form all FEC code blocks of the subsequence A.
  • the first device when the first device counts the first BER based on the first sequence, it may only count the data symbol sequences in the FEC code blocks that constitute the first sequence. Therefore, in the design When the BER is first preset, only the data symbol sequences in the FEC code blocks constituting the first sequence may be considered.
  • the N bits corresponding to the first preset BER at this time are the number of bits included in the effective sequence in the subsequence A; the M bits are the number of abnormal bits included in the effective sequence in the subsequence A.
  • the first device when the first device calculates the first BER based on the first sequence, it may also consider all the symbols in the FEC code blocks that constitute the first sequence, that is, the data symbols sequence and redundant symbol sequence, therefore, when designing the first preset BER, all symbols in the FEC code blocks constituting the first sequence can be considered.
  • the N bits corresponding to the first preset BER are the number of bits included in the effective sequence and redundant sequence in subsequence A; the M bits are the abnormalities included in the effective sequence and redundant sequence in subsequence A number of bits.
  • the subsequence A includes X first FEC code blocks and Y second FEC code blocks; the bits included in the data symbol sequence of the first FEC code block are all normal bits;
  • the data symbol sequence of the second FEC code block includes a fixed number of abnormal bits or a fixed proportion of abnormal bits; the ratio of Y or Y to (X+Y) corresponds to the first preset BER; wherein, X and Y are positive integers. Therefore, the present application provides another composition method of the subsequence A.
  • the correspondence between Y and the first preset BER in the embodiment of the present application means that the test device can flexibly set the first preset BER by adjusting the value of Y in subsequence A when it needs to meet different first preset BERs.
  • Default BER For example, when the Y value in subsequence A is Y1, the corresponding first preset BER is BER1; when the Y value in subsequence A is Y2, the corresponding first preset BER is BER2, then when the test device When you want to set the first preset BER to BER1, you can adjust the Y value in subsequence A to Y1.
  • the ratio of Y to (X+Y) corresponds to the first preset BER, which means that when the test device needs to meet different first preset BERs, it can adjust the Y and (X+Y) ratio, flexible setting of the first preset BER.
  • the corresponding first preset BER is BER3
  • the ratio of Y to (X+Y) in subsequence A is the first
  • the corresponding first preset BER is BER4
  • the test device wants to set the first preset BER to BER3
  • the ratio of Y and (X+Y) in subsequence A can be adjusted to the first ratio.
  • the second device when the application performs BER testing in an asymmetric transmission scenario, for example, in the scenario of performing BER testing on the transmission chip in the vehicle-mounted high-definition camera, the second device does not need additional circuits to encode and generate the first sequence.
  • the first sequence can be generated based on one or more stored FEC units, which can better adapt to the case of using FEC code block transmission in an asymmetric transmission scenario.
  • the first preset BER when the first preset BER needs to be adjusted, one way can be to flexibly construct the first sequence for functional testing that matches the first preset BER by adjusting the Y value in subsequence A, Or in this application, when it is necessary to set a new first sequence, a new first sequence can be obtained by adjusting the Y value in subsequence A; in this application, when it is necessary to adjust the first preset BER, another way is to pass Adjust the ratio of Y to (X+Y) in subsequence A, flexibly construct the first sequence for functional testing that matches the first preset BER, or when a new first sequence needs to be set in this application, A new first sequence can be obtained by adjusting the ratio of Y to (X+Y) in subsequence A.
  • the present application provides another composition method of the subsequence A.
  • all the bits included in the redundant symbol sequence of the first FEC code block are normal bits; all the bits included in the redundant symbol sequence of the second FEC code block are also abnormal bits.
  • the first device when the first device counts the first BER based on the first sequence, it can only count the effective sequences in the FEC code blocks that constitute the first sequence. Therefore, when designing the first When presetting the BER, only the data symbol sequences in the FEC code blocks constituting the first sequence may be considered. For example, at this time, the bits included in the data symbol sequence of the first FEC code block corresponding to the first preset BER are all normal bits; the bits included in the data symbol sequence of the second FEC code block are all abnormal bits.
  • the first device when the first device calculates the first BER based on the first sequence, it may also consider all the symbols in the FEC code blocks that constitute the first sequence, that is, the data symbols sequence and redundant symbol sequence, therefore, when designing the first preset BER, all symbols in the FEC code blocks constituting the first sequence can be considered.
  • all the bits included in the data symbol sequence and redundant symbol sequence of the first FEC code block corresponding to the first preset BER are normal bits; the data symbol sequence and redundant code element sequence of the second FEC code block All the bits included in the meta-sequence are abnormal bits.
  • the length of the subsequence A is equal to the length of the subsequence B.
  • the normal bits in this embodiment of the application can be understood as bits that match the expected value. For example, if the sequence sent by the test device to the device under test is 10111, the expected bit received by the device under test should be 10111 . If the sequence received by the device under test is 11011, the bits corresponding to the first, fourth, and fifth bits of the sequence received by the device under test are in line with the expected value, which is a normal bit, and the sequence received by the device under test The bit corresponding to the second and third bit does not match the expected value, which is an abnormal bit.
  • the present application sets the value of the abnormal bit to 1 by setting the value of the normally received bit to 0; or, by setting the value of the normally received bit to 1, the abnormal bit value is set to 0, so that in asymmetric
  • BER statistics can be performed by recording the number of bits with a value of 1 or 0. The statistical method is more simplified, which is helpful for faster and more efficient Determine the first BER.
  • the bits included in the first FEC code block may all be 0, and the bits included in the second FEC code block may all be 1; when the normal bit value is When 1, the bits included in the first FEC code block may all be 1, and the bits included in the second FEC code block may all be 0.
  • the bits included in the data symbol sequences of all FEC code blocks in the subsequence B are all 0; or, when the normal bit value is 1, the subsequence B All the bits included in the data symbol sequence of all FEC code blocks in sequence B are 1.
  • the present application sets all the bits included in the second FEC code block to 1 by setting all the bits included in the first FEC code block to 1 when the normal bit value is 0; or, when the normal bit value is When 1, set all the bits included in the first FEC code block to 1, and set all the bits included in the second FEC code block to 0, so that in an asymmetric transmission scenario, the device under test is based on the first sequence or the second sequence.
  • BER statistics can be performed by recording the number of the first FEC code block and/or the number of the second FEC code block. The statistical method is more simplified and helps to determine the first BER more quickly and efficiently.
  • the first device before the first device receives the first sequence sent by the second device, it further includes performing link training with the second device.
  • link training is carried out before the actual test, so that the receiving parameters of the first device (ie, the device under test) can be effectively converged, the actual test process is more stable, and the obtained test results are more accurate.
  • the embodiment of the present application provides a communication device, which is used to implement the first aspect or any one of the methods in the first aspect, including corresponding functional modules or units, respectively used to implement the first aspect steps in the method.
  • Functions can be realized by hardware, or by executing corresponding software by hardware, and the hardware or software includes one or more modules or units corresponding to the above-mentioned functions.
  • the embodiment of the present application provides a communication device, which is used to implement any one of the methods in the second aspect or the second aspect above, including corresponding functional modules or units, respectively used to implement the second aspect above steps in the method.
  • Functions can be realized by hardware, or by executing corresponding software by hardware, and the hardware or software includes one or more modules or units corresponding to the above-mentioned functions.
  • a communication device includes a processor and a memory.
  • the memory is used to store calculation programs or instructions
  • the processor is coupled to the memory; when the processor executes the computer programs or instructions, the device is made to execute the first aspect or any one of the methods in the first aspect.
  • the communication device may be the second device, or a device capable of supporting the second device to implement the functions required by the method provided by the first aspect above, such as a chip system.
  • the communication device may be a terminal device or a part of components (such as a chip) in the terminal device.
  • the terminal device may be, for example, a smart mobile terminal, a smart home device, a smart car, a smart wearable device, and the like.
  • the smart mobile terminal includes a mobile phone, a tablet computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a personal digital assistant (PDA) and the like.
  • Smart home devices such as smart refrigerators, smart washing machines, smart TVs, speakers, etc.
  • Smart car wearable devices such as smart headphones, smart glasses, smart clothing or shoes, etc.
  • a communication device includes a processor and a memory.
  • the memory is used to store calculation programs or instructions
  • the processor is coupled to the memory; when the processor executes the computer programs or instructions, the device is made to execute any method in the second aspect or the second aspect.
  • the communication device may be the first device or a device capable of supporting the first device to implement the functions required by the method provided by the second aspect above, such as a chip system.
  • the communication device may be a terminal device or a part of components (such as a chip) in the terminal device.
  • the terminal device may be, for example, a smart mobile terminal, a smart home device, a smart car, a smart wearable device, and the like.
  • the smart mobile terminal includes a mobile phone, a tablet computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a personal digital assistant (PDA) and the like.
  • Smart home devices such as smart refrigerators, smart washing machines, smart TVs, speakers, etc.
  • Smart car wearable devices such as smart headphones, smart glasses, smart clothing or shoes, etc.
  • a terminal is provided, and the terminal may include the device described in any one of the third aspect to the sixth aspect.
  • the device may be smart home equipment, smart manufacturing equipment, smart transportation equipment, etc., such as vehicles, drones, unmanned transport vehicles, cars and vehicles, or robots.
  • the present application provides a chip, which is connected to a memory and used to read and execute computer programs or instructions stored in the memory, so as to realize the above-mentioned first aspect or any possible implementation of the first aspect method; or to achieve the second aspect or a method in any possible implementation manner of the second aspect.
  • a computer-readable storage medium is provided.
  • Computer programs or instructions are stored in the computer-readable storage medium.
  • the device executes the above-mentioned first aspect or the first aspect.
  • the method in any possible implementation manner of the device, or causing the device to execute the method in the second aspect or any possible implementation manner of the second aspect.
  • the present application provides a computer program product, the computer program product includes a computer program or an instruction, and when the computer program or instruction is executed by the above-mentioned communication device, the device executes any of the above-mentioned first aspect or the first aspect.
  • the present application provides a communication system, where the system includes a first device and a second device;
  • the second device is configured to send a first sequence to the first device; send a second sequence to the first device;
  • the first device is configured to receive the first sequence sent by the second device, and count the first bit error rate BER of the received first sequence; it is also used to receive the second sequence sent by the second device, and count a second BER of the second sequence received;
  • the first sequence includes P subsequences A, and the subsequences A constitute one or more forward error correction FEC code blocks;
  • the second sequence includes Q subsequences B, and the subsequences B constitute one or more A plurality of FEC code blocks;
  • the length of the second sequence is greater than or equal to the length of the first sequence, and P and Q are positive integers.
  • Fig. 1 is an exemplary structural diagram of a test system provided by the present application
  • Fig. 2 is a connection example diagram of a test device provided by the present application and the device under test;
  • FIG. 3 is a schematic flow chart of the first communication method provided by the present application.
  • FIG. 4 is a schematic diagram of a FEC code block provided by the present application.
  • FIG. 5 is an exemplary structural diagram of the first sequence provided by the present application.
  • FIG. 6 is an exemplary structural diagram of the second first sequence provided by the present application.
  • FIG. 7 is an exemplary structural diagram of the second first sequence provided by the present application.
  • FIG. 8 is a schematic flowchart of a second communication method provided by the present application.
  • FIG. 9 is a schematic flowchart of a third communication method provided by the present application.
  • Fig. 10 is a schematic structural diagram of the first device provided by the present application.
  • Fig. 11 is a schematic structural diagram of the second device provided by the present application.
  • the present application provides a communication method, device and system for improving the flexibility of BER testing and effectively shortening the testing time.
  • the communication method and the communication device described in the embodiment of the present application are based on the same technical concept. Since the communication method and the communication device described in the embodiment of the present application have similar problem-solving principles, the communication method described in the embodiment of the present application The implementation of the device and the communication method can be referred to each other, and repeated descriptions will not be repeated.
  • the communication system involved in the embodiment of the present application may include a first device 101 and a second device 102 .
  • the communication system involved in the embodiment of the present application may be applicable to an asymmetric transmission scenario, and may also be applicable to a symmetric transmission scenario.
  • the communication system involved in the embodiments of the present application may be applicable to wired transmission scenarios and wireless transmission scenarios.
  • the first device 101 in the embodiment of the present application may be an electronic device or a device in an electronic device with sending and receiving functions.
  • the first device 101 may include a transmitter (Transmitter, TX) and a receiver (Receiver, RX) electronic equipment.
  • the second device 102 in the embodiment of the present application may be an electronic device or a device in the electronic device with sending and receiving functions, for example, the second device 102 may be an electronic device including TX and RX.
  • the first device may be a vehicle-mounted display screen that needs to be tested for BER, or a chip in a vehicle-mounted display screen that needs to be tested for BER; the second device may be a An external terminal device for performing a BER test on the first device.
  • the first device can also be a vehicle-mounted camera that needs to be tested for BER, or a chip in a vehicle-mounted camera that needs to be tested for BER; the second device can be used to test the first device External terminal device for BER testing.
  • the first device 101 and the second device 102 in this embodiment of the present application may be connected through a cable.
  • the first sequence and the second sequence are mainly sent to the first device through the second device, and then according to the first BER output by the first device based on the first sequence, and based on The output of the second sequence, the second BER, determines whether the first device passed the test.
  • the first device 101 shown in FIG. 1 above can be understood as a device that needs to be tested, that is, the device under test, and has a BER statistical function;
  • the second device 102 shown in FIG. 1 above can be understood as testing the device under test.
  • the equipment, that is, the test equipment, has the function of serial transmission.
  • test device in the embodiment of the present application may also have a function of sequence generation or sequence adjustment.
  • the first device 101 can also have a display function, for example, the first device 101 can include a display screen for displaying the BER obtained when performing BER tests based on different sequences; or, the first device 101 can also have a voice broadcast Functions, for example, the first device 101 may include voice broadcasting means for broadcasting the BER obtained when testing based on different sequences.
  • the number of cables connected between the first device 101 and the second device 102 is not limited in this embodiment of the present application.
  • the first device and the second device are connected through a cable, wherein the cable connected between the first device and the second device is used for The second device performs one-way communication to the first device; or, as shown in (b) in Figure 2, a cable connected between the first device and the second device is used between the second device and the first device For two-way communication.
  • the first device and the second device are connected through two cables, wherein the cable 1 connected between the first device and the second device uses One-way communication is performed from the second device to the first device; the cable 2 connected between the first device and the second device is used for one-way communication from the first device to the second device.
  • FIG. 3 it is an exemplary flow chart of a communication method provided by this application. It should be understood that the processes shown in FIG. 3 may be executed in various orders and/or concurrently, and are not limited to the execution order shown in FIG. 3 .
  • the second device sends a first sequence to the first device.
  • the first sequence is used for the first device to count the first BER.
  • the first sequence sent by the second device to the first device can be understood as a functional test sequence, wherein the functional test sequence is used to perform a functional test on the first device, and is generally sent before performing a performance test on the first device.
  • the amount of data sent by the functional test sequence is small, mainly to determine whether the first device has accurate error detection and statistical capabilities, so as to better ensure that the performance test results of the first device are accurate and reliable, and save the cost of the first device.
  • the testing time of the equipment is very longitude and statistical capabilities.
  • the first sequence includes P subsequences A, and the subsequences A constitute one or more forward error correction (Forward Error Correction, FEC) code blocks, and P is a positive integer.
  • FEC Forward Error Correction
  • the first sequence can be expressed as ⁇ A, A, ..., A ⁇ , and P is the repetition number of A in the first sequence.
  • the embodiment of the present application does not limit the types of FEC code blocks used to form the subsequence A, and the specific structure of each FEC code block. Any FEC code block applicable to the embodiments of the present application belongs to the protection of the embodiments of the present application. scope.
  • FIG. 4 it is a schematic diagram of an FEC code block provided by the embodiment of the present application.
  • the FEC code block may be composed of two parts, wherein the first part is a data symbol sequence, that is, through at least one A sequence composed of data symbols, the second part is a redundant symbol sequence, that is, a sequence composed of at least one redundant symbol, wherein each symbol is composed of a bit sequence with the same length.
  • subsequence A constitutes a plurality of FEC code blocks
  • subsequence A constitutes L FEC code blocks (a positive integer greater than 1)
  • (data symbol sequence i, redundant symbol sequence i) constitutes an RS-FEC code block
  • the effective sequence of subsequence A includes data symbol sequence i
  • the first device receives a first sequence sent by the second device.
  • the first device may obtain the first sequence sent by the testing device through a communication cable connected to the second device.
  • the first device counts the received first BER of the first sequence.
  • the specific content may be as follows:
  • a first sequence (also referred to as a functional test sequence) for performing a functional test and a first preset BER corresponding to the first sequence are determined.
  • the first sequence for functional testing can be designed first, so as to determine the first preset BER based on the first sequence; in the embodiment of the present application, the first preset BER can also be determined first. value, so that the design of the first sequence is performed based on the first preset BER.
  • the second device sends the first sequence to the first device, and asks the first device to count the BER of the received first sequence to obtain the first BER.
  • the first device can perform effective performance testing according to the first BER and the first preset BER. If the first BER obtained by the first device based on the received first sequence satisfies the first preset BER, it can be considered that the first device can perform an effective performance test; otherwise, it can be considered that the first device cannot perform an effective performance test.
  • the second device may send the first sequence to the first device multiple times for functional testing.
  • the first device when the ratio of the number of passing functional tests to the total number of functional tests (i.e. the pass rate) satisfies the first threshold ratio, it can be considered that the first device can perform an effective performance test; otherwise, it can be considered that the first device is not Enables effective performance testing.
  • the first preset BER in the embodiment of the present application may be a specific value or a value range.
  • the first preset BER is a specific value
  • the first BER is equal to the first preset BER
  • the first preset BER is a specific value and the first BER is within a floating range based on the first preset BER, it is determined that the first BER satisfies the first preset BER.
  • the left boundary of the floating range based on the first preset BER may be obtained by subtracting the first value from the first preset BER
  • the right boundary of the floating range based on the first preset BER may be obtained by
  • the first preset BER is obtained by adding the second value.
  • the first value and the second value may be equal or different, and both of them are positive numbers.
  • the range obtained based on the first preset BER is 5.2% ⁇ 15.2%.
  • the left boundary of the floating range based on the first preset BER can be obtained by multiplying the first preset BER by the first ratio
  • the right boundary of the floating range based on the first preset BER can be obtained by It is obtained by multiplying the first preset BER by the second ratio, wherein the second ratio is greater than the first ratio, and both are positive numbers.
  • the range obtained based on the first preset BER is 9.69% ⁇ 10.71%.
  • the first preset BER is in a value range, and the first BER is within the value range of the first preset BER, it is determined that the first BER satisfies the first preset BER.
  • the second device sends the second sequence to the first device.
  • the second sequence is used for the first device to count the second bit error rate BER.
  • the second sequence sent by the second device to the first device can be understood as a performance test sequence.
  • the performance test sequence is used to perform a performance test on the first device, and is generally sent after the first device passes the functional test, and the performance test sequence is The amount of data sent by the test sequence is large, mainly to determine whether the performance of the first device is qualified.
  • the second device can determine whether the chip is a qualified chip based on the BER results calculated by the chip for the received performance test sequence by sending the performance test sequence to the chip.
  • the second sequence includes Q subsequences B, the subsequences B constitute one or more FEC code blocks, and Q is a positive integer.
  • the second sequence can be expressed as ⁇ B, B,...,B ⁇ , and Q is the number of repetitions of B in the second sequence.
  • the embodiment of the present application does not limit the types of FEC code blocks used to form the subsequence B, and the specific structure of each FEC code block. Any FEC code block applicable to the embodiments of the present application belongs to the protection of the embodiments of the present application. scope.
  • the length of the second sequence in the embodiment of the present application is greater than or equal to the length of the first sequence.
  • Case 1 The length of the second sequence is equal to the length of the first sequence.
  • the length of the second sequence in the embodiment of the present application is equal to the length of the first sequence
  • the length of the subsequence B in the second sequence may be equal to the length of the subsequence A in the first sequence
  • the second The number of subsequences B in the sequence may be equal to the number of subsequences A in the first sequence, so that the length of the second sequence is equal to the length of the first sequence.
  • the length of subsequence B is 50 bits
  • the length of subsequence A is 50 bits
  • the number of subsequence B in the second sequence is 20, and the number of subsequence A in the first sequence is also 20, then at this time
  • the length of the subsequence B in the second sequence may be less than the length of the subsequence A in the first sequence, and the second The number of subsequence B in the sequence may be greater than the number of subsequence A in the first sequence, so that the length of the second sequence is equal to the length of the first sequence.
  • the length of subsequence B is 40 bits
  • the length of subsequence A is 50 bits
  • the number of subsequence B in the second sequence is 20, and the number of subsequence A in the first sequence is also 16, then at this time
  • Case 2 The length of the second sequence is greater than the length of the first sequence.
  • the length of the subsequence B in the second sequence may be equal to the length of the subsequence A in the first sequence, and the second The number of subsequence B in the sequence may be greater than the number of subsequence A in the first sequence, so that the length of the second sequence is greater than the length of the first sequence.
  • the length of subsequence B is 50 bits
  • the length of subsequence A is 50 bits
  • the number of subsequence B in the second sequence is 30, and the number of subsequence A in the first sequence is also 20, then at this time
  • the length of the subsequence B in the second sequence may be greater than the length of the subsequence A in the first sequence
  • the second The number of subsequences B in the sequence may be equal to the number of subsequences A in the first sequence, so that the length of the second sequence is greater than the length of the first sequence.
  • the length of subsequence B is 50 bits
  • the length of subsequence A is 40 bits
  • the number of subsequence B in the second sequence is 30, and the number of subsequence A in the first sequence is also 30, then at this time
  • the length of the second sequence in the embodiment of the present application when the length of the second sequence in the embodiment of the present application is greater than the length of the first sequence, the length of the subsequence B in the second sequence may be greater than the length of the subsequence A in the first sequence, and the second The number of subsequence B in the sequence may be greater than the number of subsequence A in the first sequence, so that the length of the second sequence is greater than the length of the first sequence.
  • the length of subsequence B is 50 bits
  • the length of subsequence A is 40 bits
  • the number of subsequence B in the second sequence is 30, and the number of subsequence A in the first sequence is also 20, then at this time
  • the second device may send the first sequence and the second sequence to the first device together, that is, in the embodiment of the present application, S303 and the above S300 may be combined into one step.
  • the second device may send first information to the first device, and the first information may include the first sequence and the second sequence.
  • the first device receives the second sequence sent by the second device.
  • the first device counts the received second BER of the second sequence.
  • the specific content may be as follows:
  • a second sequence (also referred to as a performance test sequence) for performance testing and a second preset BER corresponding to the second sequence are determined.
  • the second sequence for performance testing can be designed first, so as to determine the second preset BER based on the second sequence; in the embodiment of the present application, the second preset BER can also be determined first. value, so that the second sequence is designed based on the second preset BER.
  • the second device sends the second sequence to the first device, so that the first device counts the BER of the received second sequence to obtain the second BER.
  • the first device may be determined whether the first device passes the performance test according to the second BER and the second preset BER. If the second BER obtained by the first device based on the received second sequence satisfies the second preset BER, it can be considered that the first device has passed the performance test; otherwise, it can be considered that the first device has not passed the performance test.
  • the second device may send the second sequence to the first device multiple times to perform the performance test.
  • the first device when the ratio of the number of passing performance tests to the total number of performance tests (ie pass rate) meets the second threshold ratio, the first device can be considered qualified; otherwise, the first device can be considered unqualified.
  • the second preset BER threshold in the embodiment of the present application may be a specific value or a value range.
  • the second preset BER is a specific value
  • the second BER is smaller than the second preset BER
  • the second preset BER is 10 ⁇ -12
  • the second BER is smaller than 10 ⁇ -12
  • the second preset BER is within a value range
  • the second BER is within the value range of the second preset BER
  • the first sequence and the second sequence of the BER test in the asymmetric transmission scenario of the present application are composed of at least one FEC code block
  • the design method of the minimum repetition unit can better adapt to the case of using FEC code block transmission in an asymmetric transmission scenario, and better facilitate the first device and/or the second device to perform BER statistics.
  • the first sequence in this application is composed of P subsequences A
  • the second sequence is composed of Q subsequences B.
  • the length of the second sequence is greater than or equal to the length of the first sequence.
  • the value of the abnormal bit can be set to 1 by setting the value of the normally received bit to 0; or, by setting the value of the normally received bit to 1, the value of the abnormal bit can be set to 0, so that This makes it possible to perform statistics by recording the number of bits whose value is 1 or 0 when performing a BER test.
  • the second sequence is set to all 0s
  • the abnormal bit set in the first sequence takes a value of 1
  • the normal bit in the first sequence takes a value of 0.
  • BER statistics can be performed by recording the number of special values 1 or 0 corresponding to the abnormal bits, and the statistical method is more simplified and effective. Helps to determine BER more quickly and efficiently.
  • Construction mode 1 As shown in (a) in FIG. 5 , the first sequence includes P subsequences A, and each subsequence A includes N bits, wherein the N bits include M abnormal bits.
  • P is a positive integer, representing the number of subsequences A in the first sequence.
  • each subsequence A in the first sequence may also be represented by 1 ⁇ P.
  • the subsequence A corresponding to 1 shown in (a) in FIG. 5 may represent the subsequence A in the first position in the first sequence
  • the 2 shown in (a) in FIG. 5 corresponds to
  • the subsequence A may represent the subsequence A in the second position in the first sequence
  • the subsequence A corresponding to (P-1) shown in (a) in FIG. 5 may represent the subsequence A in the first sequence (P -1) subsequence A of the bit, the subsequence A corresponding to P shown in (a) in Fig.
  • N is a positive integer, representing a subsequence The total number of bits included in sequence A; M is a positive integer, indicating the number of abnormal bits included in a subsequence A. It can be understood that N is greater than or equal to M in this embodiment of the application.
  • the first sequence can also be expressed as shown in (b) in FIG. 5 .
  • the subsequence A (1) shown in (b) in Fig. 5 can represent the subsequence A in the first position in the first sequence, and the subsequence A shown in (b) in Fig.
  • the subsequence A(P-1) shown in (b) in Figure 5 can represent the (P-1th) in the first sequence ) bit subsequence A
  • the subsequence A(P) shown in (b) in FIG. 5 is to represent the subsequence A at the Pth position in the first sequence.
  • the first sequence includes P subsequences A, the total number of bits of each subsequence A is N, and the number of abnormal bits is M, it can be understood that the total number of bits included in the first sequence is all subsequences in the first sequence
  • the sum of the total number of bits included in A, that is, P*N; the number of abnormal bits included in the first sequence is the sum of the number of abnormal bits included in all subsequences A in the first sequence, that is, P*M.
  • the number of normal bits included in the first sequence is the sum of the numbers of normal bits included in all subsequences A in the first sequence, ie (P*N-P*M). Therefore, the first sequence can also be simplified as shown in (c) in FIG. 5 , the first sequence includes P*N bits, and there are P*M abnormal bits among the P*N bits.
  • the number of abnormal bits in the first sequence can also be adjusted to correspond to different first preset BERs.
  • the ratio of M or M to N in the first sequence may be adjusted to correspond to different first preset BERs.
  • the M value in subsequence A is M1
  • the corresponding first preset BER is BER1
  • the M value in subsequence A is M2
  • the corresponding first preset BER is BER2
  • the corresponding first preset BER is BER3; when the ratio of M to N in subsequence A is the second ratio, the corresponding first default BER is BER3.
  • a preset BER is BER4, and when the test device wants to set the first preset BER to BER3, the ratio of M and N in the subsequence A can be adjusted to the first ratio.
  • the first preset BER corresponding to the first sequence can be determined according to the following formula 1:
  • P represents the number of subsequence A included in the first sequence
  • N represents the total number of bits included in one subsequence A
  • M represents the number of abnormal bits included in one subsequence A.
  • the N bits in this embodiment of the present application may be the number of bits included in the effective sequence in subsequence A
  • the M bits in the embodiment of the present application may be the number of abnormal bits included in the effective sequence in subsequence A.
  • the subsequence A in the first sequence is a bit sequence composed of an RS-FEC (384, 354, 9) code block, wherein "9" in the RS-FEC (384, 354, 9) indicates that the RS -The length of each symbol in the FEC code block is 9 bits, "354" in RS-FEC (384, 354, 9) indicates that the number of data symbols included in the RS-FEC code block is 354, and RS- "384" in FEC(384, 354, 9) indicates that the total number of symbols included in the RS-FEC code block is 384.
  • the redundant code can be obtained according to the number 384 of the total symbols and the number 354 of data symbols
  • the M value is 354
  • the N value is 3186 into the above formula 1
  • the N bits in the embodiment of the present application may be the number of bits included in the effective sequence and the redundant sequence in the subsequence A
  • the M bits in the embodiment of the present application may be the effective sequence and the redundant sequence in the subsequence A.
  • the number of abnormal bits included in the redundant sequence may be the number of bits included in the redundant sequence.
  • the first sequence includes P subsequences A, each subsequence A includes X first FEC code blocks and Y second FEC code blocks, and the data symbol sequence of the first FEC code block All are normal bits; all the data symbol sequences of the second FEC code block are abnormal bits.
  • P is a positive integer, representing the number of subsequences A in the first sequence.
  • 1 ⁇ P can also be used to represent the position of each subsequence A in the first sequence.
  • a number of FEC code blocks A number of FEC code blocks; Y is a positive integer, indicating the number of second FEC code blocks included in a subsequence A.
  • the above Figure 6 can be expressed as that the first sequence includes 5 subsequences A, and each subsequence A includes 3 first FEC code blocks and 2 first FEC code blocks Two FEC code blocks.
  • the arrangement position of the first sequence and the second sequence shown in FIG. 6 above is only an example, and the embodiment of the present application does not limit the first FEC code block and the second FEC code block in the subsequence A.
  • the positions of the code blocks, the first FEC code block and the second FEC code block may be randomly arranged.
  • the subsequence A includes X first FEC code blocks and Y second FEC code blocks, it can be understood that one first FEC code block and one second FEC code block are in the first sequence
  • the smallest repetition unit, that is, the length of the first FEC code block and the length of the second FEC code block in this embodiment of the present application may be the same.
  • the first FEC code block and the second FEC code block are both composed of the above-mentioned RS-FEC (384,354,9) code block with a length of 3456 bits, wherein 0 represents an abnormal bit, 1 represents a normal bit, Then the data symbol sequences of the first FEC code block are all 1s, and the data symbol sequences of the second FEC code block are all 0s.
  • the subsequence A when it is assumed that the subsequence A includes 3 first FEC code blocks (for convenience of description, referred to as a1) and 1 second FEC code block (for convenience of description, referred to as a2), the subsequence A can be expressed as a1, a1, a2, a1.
  • the first sequence when the first sequence includes two subsequences A, the first sequence can be expressed as a1, a1, a2, a1, a1, a1, a2, a1.
  • subsequence A includes 3 first FEC code blocks and 1 second FEC code block
  • the number of second FEC code blocks in the first sequence can also be adjusted to correspond to different first preset BERs.
  • the value of Y in the first sequence or the ratio of Y to (X+Y) may be adjusted to correspond to different first preset BERs.
  • the corresponding first preset BER is BER1; when the Y value in subsequence A is Y2, the corresponding first preset BER is BER2, then when the test device When you want to set the first preset BER to BER1, you can adjust the Y value in subsequence A to Y1.
  • the corresponding first preset BER is BER3
  • the ratio of Y in subsequence A to (X+Y) is For the second ratio
  • the corresponding first preset BER is BER4
  • the test device wants to set the first preset BER to BER3
  • the ratio of Y and (X+Y) in subsequence A can be adjusted to the first A ratio.
  • the first preset BER corresponding to the first sequence can be determined according to the following formula 2:
  • X represents the number of first FEC code blocks included in a subsequence A
  • Y represents the number of second FEC code blocks included in a subsequence A.
  • all the bits included in the data symbol sequence of the first FEC code block can be set as normal bits, and all the bits included in the data symbol sequence of the second FEC code block can be set as abnormal bits .
  • subsequence A in the first sequence includes 963 first FEC code blocks, that is, the X value is 963, and the data symbol sequences in the first FEC code block are all normal bits; subsequence A includes 37 The second FEC code block, that is, the Y value is 37, and the data symbol sequences in the second FEC code block are all abnormal bits.
  • the data symbol sequence lengths of the first FEC code block and the second FEC code block are the same.
  • all the bits included in the data symbol sequence and the redundant symbol sequence of the first FEC code block can be set as normal bits, and the data symbol sequence and the redundant symbol sequence of the second FEC code block can be set to All the bits included in the redundant symbol sequence are set as abnormal bits.
  • subsequence A in the first sequence includes 963 first FEC code blocks, that is, the value of X is 963, and the data symbol sequence and redundant symbol sequence in the first FEC code block are all normal bits;
  • the subsequence A includes 37 second FEC code blocks, that is, the Y value is 37, and the data symbol sequence and redundant symbol sequence in the second FEC code block are all abnormal bits.
  • the first sequence includes P subsequences A, and each subsequence A includes X first FEC code blocks and Y second FEC code blocks.
  • the data symbol sequences of the first FEC code block are all normal bits; the data symbol sequences of the second FEC code block have a fixed number of abnormal bits, or the data symbol sequences of the second FEC code block have a fixed proportion of abnormal bits bit.
  • both the first FEC code block and the second FEC code block are composed of the above-mentioned RS-FEC (384, 354, 9) code blocks with a length of 3456 bits, and the first The data symbol sequence of the FEC code block is all 1, and there is a fixed number of 5 abnormal bits in the data symbol sequence of the second FEC code block, then the second FEC code block can be 111...1000001, or 111...1010000 , or 111...0001001, etc., that is, to ensure that the number of abnormal bits in the data symbol sequence of the second FEC code block is 5.
  • the subsequence A when it is assumed that the subsequence A includes 3 first FEC code blocks (for convenience of description, a1 for short), and 1 second FEC code block (for convenience of description, a3 for short), the subsequence A can be expressed as a1, a3, a1, a1.
  • the first sequence when the first sequence includes two subsequences A, the first sequence can be expressed as a1, a3, a1, a1, a1, a3, a1, a1.
  • the length of the first FEC code block and the second FEC code block is 3456 bits
  • the number of second FEC code blocks in the first sequence can also be adjusted to correspond to different first preset BERs.
  • the value of Y in the first sequence or the ratio of Y to (X+Y) may be adjusted to correspond to different first preset BERs.
  • the corresponding first preset BER is BER1; when the Y value in subsequence A is Y2, the corresponding first preset BER is BER2, then when the test device When you want to set the first preset BER to BER1, you can adjust the Y value in subsequence A to Y1.
  • the corresponding first preset BER is BER3
  • the ratio of Y in subsequence A to (X+Y) is For the second ratio
  • the corresponding first preset BER is BER4
  • the test device wants to set the first preset BER to BER3
  • the ratio of Y and (X+Y) in subsequence A can be adjusted to the first A ratio.
  • the first preset BER corresponding to the first sequence can be determined according to the following formula 3:
  • the first preset BER T*Y/(X+Y) Formula 3
  • X represents the number of first FEC code blocks included in a subsequence A
  • T represents the proportion of abnormal bits in the first FEC code block
  • Y represents the number of second FEC code blocks included in a subsequence A.
  • all the bits included in the data symbol sequence of the first FEC code block can be set as normal bits, and the fixed number of bits or fixed ratio of the data symbol sequence included in the second FEC code block bit is set as an exception bit.
  • subsequence A in the first sequence includes 963 first FEC code blocks, that is, the X value is 963, and the data symbol sequences in the first FEC code block are all normal bits; subsequence A includes 74 The second FEC code block, that is, the Y value is 74, and 50% of the data symbol sequences in the second FEC code block are abnormal bits.
  • the data symbol sequence lengths of the first FEC code block and the second FEC code block are the same.
  • all the bits included in the data symbol sequence and the redundant symbol sequence of the first FEC code block can be set as normal bits, and the data symbol sequence and the redundant symbol sequence of the second FEC code block can be set to A fixed number of bits or a fixed ratio of bits included in the redundant symbol sequence are set as abnormal bits.
  • subsequence A in the first sequence includes 963 first FEC code blocks, that is, the value of X is 963, and the data symbol sequence and redundant symbol sequence in the first FEC code block are all normal bits;
  • the subsequence A includes 74 second FEC code blocks, that is, the Y value is 74, and the number of abnormal bits in the second FEC code block accounts for 50% of the total number of bits in the data symbol sequence and the redundant symbol sequence.
  • the first preset BER when the first preset BER needs to be adjusted in this application, one way can be to flexibly construct a function test matching the first preset BER by adjusting the Y value in subsequence A.
  • the first sequence or in this application, when a new first sequence needs to be set, a new first sequence can be obtained by adjusting the different Y value in subsequence A; in this application, when the first preset BER needs to be adjusted, Another way is to flexibly construct the first sequence for functional testing that matches the first preset BER by adjusting the ratio of Y to (X+Y) in subsequence A, or to set a new For the first sequence, a new first sequence can be obtained by adjusting the ratio of Y and (X+Y) in subsequence A.
  • the second FEC code block in the above construction method 3 can also be referred to as an uncorrectable FEC code block, which refers to a sequence with the same length as the first FEC code block, and the wrong code in the second FEC code block The number of elements exceeds the upper limit of error-correctable symbols of the FEC code block.
  • Scenario 1 The second device sends both the first sequence and the second sequence to the first device.
  • the communication method corresponding to one scenario may perform the following steps.
  • the second device sends the first sequence and the second sequence to the first device.
  • the first device receives a first sequence and a second sequence from a second device.
  • the first device counts the received first BER of the first sequence.
  • the first device determines whether the first BER satisfies the first preset BER. If yes, execute S804. If not, execute S805.
  • the tester may determine whether the first BER obtained by the first device satisfies the first preset BER based on the first BER output by the first device; The BER is sent back to the second device, and the second device determines whether the first BER satisfies the first preset BER, and then notifies the first device or the tester of the determination result.
  • the first device counts the received second BER of the second sequence.
  • the first device may output the second BER, so that the tester determines whether the first device passes the performance test according to the second BER.
  • the tester determines that the second BER does not meet the second preset BER, it is determined that the first device performance test fails; if the tester determines that the second BER meets the second preset BER, it is determined that the first device performance test is qualified.
  • the first device terminates subsequent testing of the received second sequence.
  • the first device may prompt the tester to fail the function test by voice.
  • Scenario 2 When the first BER satisfies the first preset BER, the second device is triggered to send the second sequence to the first device.
  • the communication method corresponding to the second scenario may perform the following steps.
  • the second device sends the first sequence to the first device.
  • the first device receives a first sequence from the second device.
  • the first device counts the received first BER of the first sequence.
  • the first device sends back the first BER to the second device.
  • the second device determines whether the first BER satisfies the first preset BER. If yes, execute S905. If not, execute S906.
  • the tester may also determine whether the first BER obtained by the first device satisfies the first preset BER based on the first BER output by the first device.
  • the tester may determine whether the first BER obtained by the first device is based on the first BER output by the first device. If the first preset BER is satisfied, steps S903 and S904 can be omitted at this time.
  • the second device sends the second sequence to the first device, and continues to execute S907.
  • the tester may trigger the second device to send the second sequence to the first device.
  • the tester may determine whether the first BER obtained by the first device is based on the first BER output by the first device. The first preset BER is met, and when it is determined that the first BER satisfies the first preset BER, the second device is triggered to send the second sequence to the first device.
  • the second device may also trigger itself to send the second sequence to the first device.
  • the first device sends back the first BER to the second device, and the second device determines whether the first BER satisfies the first preset BER, and when the second device determines that the first BER satisfies the first preset BER, triggers The second device sends the second sequence to the first device.
  • the second device when the second device determines that the first BER satisfies the first preset BER, it may prompt the tester to pass the function test of the test device (that is, the first device) by voice.
  • the second device determines to terminate subsequent testing of the second sequence.
  • the tester may trigger the second device to terminate subsequent testing of the second sequence.
  • the tester may determine whether the first BER obtained by the first device is based on the first BER output by the first device. The first preset BER is met, and when it is determined that the first BER does not satisfy the first preset BER, the second device is triggered to terminate subsequent tests on the second sequence.
  • the second device may also trigger and terminate subsequent testing of the second sequence by itself.
  • the first device sends back the first BER to the second device, and the second device determines whether the first BER satisfies the first preset BER, and when the second device determines that the first BER does not meet the first preset BER, The trigger terminates subsequent testing of the second sequence.
  • the second device when the second device determines that the first BER does not meet the first preset BER, it may prompt the tester to fail the function test of the device under test (that is, the first device) by voice.
  • the first device counts the received second BER of the second sequence.
  • the first device may output the second BER, so that the tester determines whether the first device passes the performance test according to the second BER.
  • the tester determines that the second BER does not meet the second preset BER, it is determined that the first device performance test fails; if the tester determines that the second BER meets the second preset BER, it is determined that the first device performance test is qualified.
  • the first sequence may be sent to the first device multiple times for testing, that is, multiple times for the first device A functional test is performed each time, and the first sequence sent each time may be the same or different, which is not limited in this embodiment of the present application.
  • the second sequence of tests is performed on the first device, That is, a performance test is performed on the first device.
  • the threshold ratio is 80%
  • the total number of functional tests performed on the first device is 10 times.
  • the number of times the first device has passed the functional test is 9 times, and the pass rate is 90%, which is greater than the threshold ratio of 80%.
  • the test results obtained by the first device are accurate and reliable, and subsequent performance tests can be carried out. test.
  • the second device may also send at least one training sequence to the first device, and perform receiving link training with the first device through the training sequence, The receiving parameters of the first device are converged. Therefore, in the subsequent testing process, the testing process is smoother and more stable.
  • the method and the device are conceived based on the same or similar technology, and since the method and the device have similar problem-solving principles, the implementation of the device and the method can be referred to each other, and the repetition will not be repeated.
  • Appatus and equipment in the embodiments of the present application may be used interchangeably.
  • "and/or” describes the association relationship of associated objects, indicating that there may be three types of relationships, for example, A and/or B, which may mean: A exists alone, A and B exist simultaneously, and There are three cases of B.
  • the character "/” generally indicates that the contextual objects are an "or” relationship.
  • the at least one involved in this application refers to one or more; a plurality refers to two or more than two.
  • Fig. 10 is a schematic block diagram of an apparatus 1000 provided by an embodiment of the present application, which is used to realize the functions of the first device or the second device in the above method embodiments.
  • the device may be a software module or a system on a chip.
  • the chip may consist of chips, or may include chips and other discrete devices.
  • the apparatus 1000 includes a processing unit 1001 and a communication unit 1002 .
  • the communication unit 1002 is used to communicate with other devices, and can also be called a communication interface, a transceiver unit, or an input/output interface, etc.
  • the above-mentioned apparatus 1000 may be a first device, or a chip or a circuit configured in the first device.
  • the processing unit 1001 can be used to perform processing related operations of the first device in the above method embodiments
  • the communication unit 1002 can be used to instruct the sending and receiving related operations of the first device in the above method embodiments, for example, the communication unit in the embodiment of the present application 1002 may be a receiving unit.
  • the communication unit 1002 is configured to receive the first sequence sent by the second device, the first sequence includes P subsequences A, and the subsequences A constitute one or more forward error correction FEC code blocks; the processing unit 1001 , used to count the first BER of the received first sequence; the communication unit 1002, configured to receive the second sequence sent by the second device, the second sequence includes Q subsequences B, and the subsequences B constitute a or a plurality of forward error correction FEC code blocks; the processing unit 1001 is used to count the second BER of the second sequence received; wherein, the length of the second sequence is greater than or equal to the length of the first sequence, and P and Q is a positive integer.
  • the processing unit 1001 is further configured to, when the first BER satisfies a first preset BER, count the received second BER of the second sequence.
  • processing unit 1001 is specifically configured to:
  • processing unit 1001 is specifically configured to:
  • the subsequence A includes N bits; the subsequence A sequence includes M abnormal bits; the ratio of M or M to N corresponds to the first preset BER; wherein , N and M are positive integers, and N is greater than or equal to M.
  • the N bits are the number of bits included in the effective sequence in the subsequence A; the M bits are the number of abnormal bits included in the effective sequence in the subsequence A; or the The N bits are the number of bits included in the effective sequence and the redundant sequence in the subsequence A; the M bits are the number of abnormal bits included in the effective sequence and the redundant sequence in the subsequence A; wherein,
  • Each FEC code block in the one or more FEC code blocks includes a data symbol sequence and a redundant symbol sequence, and the effective sequence in the subsequence A includes the data code of the one or more FEC code blocks An element sequence, wherein the redundant sequence in the subsequence A includes the redundant symbol sequence of the one or more FEC code blocks.
  • the subsequence A includes X first FEC code blocks and Y second FEC code blocks; the bits included in the data symbol sequence of the first FEC code block are all normal bits;
  • the data symbol sequence of the second FEC code block includes a fixed number of abnormal bits or a fixed proportion of abnormal bits; the ratio of Y or Y to (X+Y) corresponds to the first preset BER; wherein, X and Y are positive integers.
  • all the bits included in the data symbol sequence of the second FEC code block are abnormal bits.
  • all the bits included in the redundant symbol sequence of the first FEC code block are normal bits; all the bits included in the redundant symbol sequence of the second FEC code block are also abnormal bits.
  • the length of the subsequence A is equal to the length of the subsequence B.
  • all bits included in the first FEC code block may be 0, a fixed number or a fixed proportion of abnormal bits in the second FEC code block may all be 1, and all remaining bits may be 0.
  • the bits included in the data symbol sequence of all FEC code blocks in the subsequence B are all 0; or when the normal bit value is 1, the subsequence The bits included in the data symbol sequence of all FEC code blocks in B are all 1.
  • the processing unit 1001 before sending the first sequence to the first device, the processing unit 1001 is further configured to perform link training with the first device.
  • the above apparatus 1000 may be a second device, or a chip or a circuit configured in the second device.
  • the processing unit 1001 can be used to perform the processing-related operations of the second device in the above method embodiments
  • the communication unit 1002 can be used to perform the sending and receiving related operations of the second device in the above method embodiments, for example, the communication unit in the embodiments of the present application 1002 may be a sending unit.
  • the communication unit 1002 is configured to send a first sequence to the first device, the first sequence is used by the first device to count a first bit error rate BER, the first sequence includes P subsequences A, the Subsequence A constitutes one or more forward error correction FEC code blocks; sending a second sequence to the first device, the second sequence is used by the first device to count a second BER, and the second sequence includes Q subsequences B, the subsequences B constitute one or more forward error correction FEC code blocks; wherein, the length of the second sequence is greater than or equal to the length of the first sequence, and P and Q are positive integers.
  • the first BER is obtained by recording the number of abnormal bits in the first sequence; the second BER is obtained by recording the number of abnormal bits in the second sequence.
  • the communication unit 1002 is specifically configured to send the second sequence to the first device when the first BER satisfies a first preset BER.
  • the subsequence A includes N bits; the subsequence A sequence includes M abnormal bits; the ratio of M or M to N corresponds to the first preset BER; wherein , N and M are positive integers, and N is greater than or equal to M.
  • the N bits are the number of bits included in the effective sequence in the subsequence A; the M bits are the number of abnormal bits included in the effective sequence in the subsequence A; or the The N bits are the number of bits included in the effective sequence and the redundant sequence in the subsequence A; the M bits are the number of abnormal bits included in the effective sequence and the redundant sequence in the subsequence A; wherein,
  • Each FEC code block in the one or more FEC code blocks includes a data symbol sequence and a redundant symbol sequence, and the effective sequence in the subsequence A includes the data code of the one or more FEC code blocks An element sequence, wherein the redundant sequence in the subsequence A includes the redundant symbol sequence of the one or more FEC code blocks.
  • the subsequence A includes X first FEC code blocks and Y second FEC code blocks; the bits included in the data symbol sequence of the first FEC code block are all normal bits;
  • the data symbol sequence of the second FEC code block includes a fixed number of abnormal bits or a fixed proportion of abnormal bits; the ratio of Y or Y to (X+Y) corresponds to the first preset BER; wherein, X and Y are positive integers.
  • all the bits included in the data symbol sequence of the second FEC code block are abnormal bits.
  • all the bits included in the redundant symbol sequence of the first FEC code block are normal bits; all the bits included in the redundant symbol sequence of the second FEC code block are also abnormal bits.
  • the length of the subsequence A is equal to the length of the subsequence B.
  • all bits included in the first FEC code block may be 0, a fixed number or a fixed proportion of abnormal bits in the second FEC code block may all be 1, and all remaining bits may be 0.
  • the bits included in all FEC code blocks in the subsequence B are all 0; or when the normal bit value is 1, all FEC code blocks in the subsequence B
  • the data symbol sequence of a block includes all 1 bits.
  • the processing unit 1001 before sending the first sequence to the first device, the processing unit 1001 is further configured to perform link training with the first device.
  • each functional unit may be integrated into one processor, or physically exist separately, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.
  • FIG. 11 is a schematic diagram of a device 1100 provided by an embodiment of the present application.
  • the device 1100 may be an electronic device, or a component of an electronic device, such as a chip or an integrated circuit.
  • the apparatus 1100 can include at least one processor 1102 and a communication interface 1104 . Further, optionally, the device may further include at least one memory 1101 . Further, optionally, a bus 1103 may also be included. Wherein, the memory 1101 , the processor 1102 and the communication interface 1104 are connected through a bus 1103 .
  • the memory 1101 is used to provide a storage space, in which data such as operating systems and computer programs can be stored.
  • the memory 1101 mentioned in the embodiment of the present application may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memories.
  • the non-volatile memory can be read-only memory (read-only memory, ROM), programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically programmable Erases programmable read-only memory (electrically EPROM, EEPROM) or flash memory.
  • Volatile memory can be random access memory (RAM), which acts as external cache memory.
  • RAM random access memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • DRAM synchronous dynamic random access memory
  • SDRAM double data rate synchronous dynamic random access memory
  • double data rate SDRAM double data rate SDRAM
  • DDR SDRAM enhanced synchronous dynamic random access memory
  • ESDRAM enhanced synchronous dynamic random access memory
  • serial link DRAM SLDRAM
  • direct memory bus random access memory direct rambus RAM, DR RAM
  • the processor 1102 is a module for performing arithmetic operations and/or logical operations, specifically, a central processing unit (central processing unit, CPU), a picture processing unit (graphics processing unit, GPU), a microprocessor (microprocessor unit, MPU), Application specific integrated circuit (ASIC), field programmable logic gate array (field programmable gate array, FPGA), complex programmable logic device (complex programmable logic device, CPLD), coprocessor (to assist the central processing unit to complete Corresponding processing and application), microcontroller unit (microcontroller unit, MCU) and other processing modules or a combination of more.
  • central processing unit central processing unit
  • CPU central processing unit
  • MPU picture processing unit
  • ASIC application specific integrated circuit
  • FPGA field programmable logic gate array
  • FPGA field programmable gate array
  • CPLD complex programmable logic device
  • coprocessor to assist the central processing unit to complete Corresponding processing and application
  • microcontroller unit microcontroller unit, MCU
  • the processor is a general-purpose processor, ASIC, FPGA or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components
  • the memory storage module may be integrated in the processor.
  • Communication interface 1104 may be used to provide information input or output to the at least one processor. And/or the communication interface can be used to receive data sent from the outside and/or send data to the outside, which can be a wired link interface such as an Ethernet cable, or a wireless link (Wi-Fi, Bluetooth, General wireless transmission, vehicle short-distance communication technology, etc.) interface.
  • the communication interface 1104 may further include a transmitter (such as a radio frequency transmitter, an antenna, etc.) or a receiver coupled with the interface.
  • the foregoing apparatus 1100 may be the first device or a component in the first device in the foregoing method embodiments, such as a chip or an integrated circuit.
  • the processor 1102 in the apparatus 1100 is configured to read the computer program stored in the memory 1101, and control the first device to perform the following operations:
  • Sending a first sequence to the first device the first sequence is used by the first device to count a first BER, the first sequence includes P subsequences A, and the subsequences A constitute one or more forward corrections Wrong FEC code block; send a second sequence to the first device, the second sequence is used for the first device to count the second BER, the second sequence includes Q subsequences B, and the subsequences B constitute One or more FEC code blocks; wherein, the length of the second sequence is greater than or equal to the length of the first sequence, and P and Q are positive integers.
  • the processor 1102 in the first device can also be used to read the program in the memory 1101 and execute the method flow executed by the test device in S300-S305 as shown in FIG. 3; or, it can also be used to Read the program in the memory 1101 and execute the method flow performed by the test device in S800-S805 as shown in Figure 8; or, it can also be used to read the program in the memory 1101 and execute S900-S907 as shown in Figure 9 The method flow performed by the test device.
  • the foregoing apparatus 1100 may be the second device or a component in the second device in the foregoing method embodiments, such as a chip or an integrated circuit.
  • the processor 1102 in the apparatus 1100 is configured to read the computer program stored in the memory 1101, and control the second device to perform the following operations:
  • the first sequence includes P subsequences A, the subsequences A constitute one or more forward error correction FEC code blocks; count the first bit errors of the received first sequence rate BER; receive the second sequence sent by the second device, the second sequence includes Q subsequences B, and the subsequences B constitute one or more forward error correction FEC code blocks; count the received second sequence The second BER; wherein, the length of the second sequence is greater than or equal to the length of the first sequence, and P and Q are positive integers.
  • the processor 1102 in the second device can also be used to read the program in the memory 1101 and execute the method flow performed by the device under test in S300-S305 shown in FIG. 3; or, it can also It is used to read the program in the memory 1101 and execute the method flow executed by the device under test in S800-S805 shown in FIG. 8; or, it can also be used to read the program in the memory 1101 and execute the method shown in FIG. 9 The flow of the method executed by the testing device in S900-S907.
  • the embodiment of the present application also provides a computer-readable storage medium (including but not limited to disk storage, CD-ROM, optical storage, etc.), including instructions, which, when run on a computer, cause the computer to perform the operations described in the above-mentioned embodiments. Methods.
  • a computer-readable storage medium including but not limited to disk storage, CD-ROM, optical storage, etc.
  • An embodiment of the present application further provides a system on chip, where the system on chip includes at least one processor and an interface circuit. Further optionally, the chip system may further include a memory or an external memory. The processor is configured to perform instruction and/or data interaction through the interface circuit, so as to implement the methods in the above method embodiments.
  • the system-on-a-chip may consist of chips, or may include chips and other discrete devices.
  • the embodiments of the present application also provide a computer program product, including instructions, which, when run on a computer, cause the computer to execute the method described in the above embodiments.
  • the methods provided in the embodiments of the present application may be implemented in whole or in part by software, hardware, firmware or any combination thereof.
  • software When implemented using software, it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions according to the embodiments of the present application will be generated in whole or in part.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

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Abstract

本申请公开了一种通信方法、装置及系统，可以用于自动驾驶、辅助驾驶或者智能驾驶。该方法包括：向第一设备发送包括P个子序列A的第一序列，所述第一序列用于第一设备统计第一误比特率BER，子序列A构成一个或多个前向纠错FEC码块；向第一设备发送包括Q个子序列B的第二序列，第二序列用于第一设备统计第二BER，子序列B构成一个或多个FEC码块；其中，第二序列的长度大于或等于第一序列的长度，P与Q为正整数。该方法以FEC码块作为最小重复单元，灵活构造功能测试和性能测试序列，简化了BER测试的复杂度。进一步，该方法可以应用于车联网，如车辆外联V2X、车间通信长期演进技术LTE-V、车辆-车辆V2V等。

Description

一种通信方法、装置及系统 技术领域
本申请实施例涉及通信技术领域，尤其涉及一种通信方法、装置及系统。
背景技术
传输芯片的性能对于数据的传输速率至关重要，为此经常需要对传输芯片的性能进行测试，其中，误比特率(bit error rate，BER)是传输芯片的一个重要指标，可以通过对传输芯片进行BER测试，以验证传输芯片是否达到设定的BER指标。
在实际应用中，经常存在上行速率和下行速率不相等的非对称传输场景，例如车载高清摄像头中的传输芯片上行速率(摄像头图像数据输出方向)往往会达到1～10Gbps，而下行速率一般只有1～100Mbps。
因此，如何设计针对传输芯片在非对称传输场景下的BER测试方法是亟待解决的问题。
发明内容
本申请提供一种通信方法、装置和系统，用以在非对称传输场景下对传输芯片进行BER测试。
本申请提供的通信方法可以由第二设备执行，其中，该第二设备可以作为测试装置(Test Equipment，TE)。该第二设备可以被抽象为计算机系统。该第二设备可以是整机，也可以是整机中的部分器件，例如：系统芯片或处理芯片。其中，系统芯片也可以包括片上系统(system on chip，SOC)，或SoC芯片。具体地，该第二设备可以是一个单独的用于对被测试装置进行BER测试的装置，或者，该第二设备可以是整机中的用于对被测试装置进行BER测试的器件。例如，第二设备可以是具有BER测试功能的车载电脑、车机等这样的终端装置或车载设备，也可以是能够被设置在车辆或车载设备的计算机系统中的具有BER测试功能的系统芯片、决策处理芯片或其他类型的芯片等。
第一方面，本申请实施例提供一种通信方法，包括：
向第一设备发送第一序列，所述第一序列用于所述第一设备统计第一误比特率BER，所述第一序列包括P个子序列A，所述子序列A构成一个或多个前向纠错FEC码块；向所述第一设备发送第二序列，所述第二序列用于所述第一设备统计第二BER，所述第二序列包括Q个子序列B，所述子序列B构成一个或多个前向纠错FEC码块；其中，所述第二序列的长度大于或等于所述第一序列的长度，P与Q为正整数。
作为一种示例，在非对称传输场景下，当上述方法是由第二设备执行时，可以分别发送第一序列和第二序列。例如第二设备可以先向第一设备发送第一序列，然后，再向第一设备发送第二序列。
作为另一种示例，在非对称传输场景下，当上述方法是由第二设备执行时，可以同时发送第一序列和第二序列。例如第二设备向第一设备发送第一信息，第一信息中包括第一序列以及第二序列。
采用该方法，由于本申请进行BER测试有效利用了设备传输所采用的FEC码块作为 第一序列与第二序列的最小重复单元，减少设备构造测试序列的复杂度，提升测试过程的鲁棒性。进一步，当第二序列的长度大于第一序列的长度时，能够有效缩短基于第一序列的功能测试的时间，提高测试速度。对于非对称传输场景，可以采用该方法进行单向的BER测试，可以简化测试过程和时间，提高测试效率。可以理解的是，这一测试方法也可以适用于对称传输场景。
一种可能的设计中，当所述第一BER满足第一预设BER时，向所述第一设备发送所述第二序列。
作为一种示例，第一预设BER，可以为一个具体值。其中，当第一预设BER为一个具体值时，第一BER等于第一预设BER，则确定第一BER满足第一预设BER；或者，当第一预设BER为一个具体值时，第一BER在基于第一预设BER的浮动范围内，则确定第一BER满足第一预设BER。例如，基于第一预设BER的浮动范围的左边界可以是通过对第一预设BER减去第一数值得到的，基于第一预设BER的浮动范围的右边界可以是通过对第一预设BER加上第二数值得到的，第一数值与该第二数值可以相等，也可以不等，且都为正数。再例如，基于第一预设BER的浮动范围的左边界可以是通过对第一预设BER乘以第一比例得到的，基于第一预设BER的浮动范围的右边界可以是通过对第一预设BER乘以第二比例得到的，其中，第二比例大于第一比例，且都为正数。
作为一种示例，第一预设BER，还可以为一个取值范围。其中，当第一预设BER为一个取值范围时，第一BER在第一预设BER的取值范围内，则确定第一BER满足第一预设BER。
可以理解的，该方法中提供了一种在非对称传输场景下，触发第二设备向第一设备发送第二序列的情况，例如当确定第一设备基于接收到的第一序列统计出的第一BER满足第一预设BER时，认为第一设备具有准确的错误检测和统计能力，能够更好的保证第一设备后续基于第二序列进行性能测试的结果是准确可靠的，故可以触发第二设备向第一设备发送第二序列。
其中，本申请在确定第一设备基于接收到的第一序列统计出的第一BER是否满足第一预设BER时，可以由测试人员人为判断第一设备基于接收到的第一序列统计出的第一BER是否满足第一预设BER，当测试人员判断第一BER满足第一预设BER时，人为触发第二设备向第一设备发送第二序列；或者，本申请在确定第一设备基于接收到的第一序列统计出的第一BER是否满足第一预设BER时，第一设备基于接收到的第一序列统计出第一BER后，第一设备可以将第一BER回传给第二设备，从而通过第二设备判断接收到的第一BER是否满足第一预设BER，当第二设备确定第一BER满足第一预设BER时，则触发向第一设备发送第二序列。一种可能的设计中，所述子序列A包括N个比特；所述子序列A中包括M个异常比特；所述M或M与N的比值与所述第一预设BER对应；其中，N与M为正整数，且N大于或等于M。因此，本申请提供了一种子序列A的构成方式。
可以理解的，本申请实施例中的M与第一预设BER对应是指测试装置在需要满足不同的第一预设BER时，可以通过调整子序列A中的M值，灵活的设置第一预设BER。例如，当子序列A中的M值为M1时，对应的第一预设BER为BER1，当子序列A中的M值为M2时，对应的第一预设BER为BER2，则当测试装置想将第一预设BER设置成BER1时，可以将子序列A中的M值调整为M1。
本申请实施例中的M与N的比值与第一预设BER对应是指测试装置在需要满足不同 的第一预设BER时，可以通过调整子序列A中的M与N的比值，灵活的设置第一预设BER。例如，当子序列A中的M与N的比值为第一比值时，对应的第一预设BER为BER3，当子序列A中的M与N的比值为第二比值时，对应的第一预设BER为BER4，则当测试装置想将第一预设BER设置成BER3时，可以将子序列A中的M与N的比值调整为第一比值。
采用该方法，本申请在非对称传输场景下进行BER测试时，例如在对车载高清摄像头中的传输芯片进行BER测试的场景中，第二设备不需要额外的电路去做编码生成第一序列，可以基于存储的一个或多个FEC单元去生成第一序列，能够更好的适配非对称传输场景中使用FEC码块传输的情况。其中，本申请中在需要调整第一预设BER时，一种方式可以通过调整子序列A中的异常比特M的取值，灵活构造与第一预设BER相匹配的用于进行功能测试的第一序列，或者本申请中在需要设置新的第一序列时，可以通过调整子序列A中的异常比特M的取值，得到新的第一序列；本申请中在需要调整第一预设BER时，另一种方式通过调整子序列A中M与N的比值，灵活构造与第一预设BER相匹配的用于进行功能测试的第一序列，或者本申请中在需要设置新的第一序列时，可以通过调整子序列A中的M与N的比值，得到新的第一序列。
一种可能的设计中，所述N个比特为所述子序列A中的有效序列包括的比特数量；所述M个比特为所述子序列A中的有效序列包括的异常比特数量；或所述N个比特为所述子序列A中的有效序列与冗余序列包括的比特数量；所述M个比特为所述子序列A中的有效序列与冗余序列包括的异常比特数量；其中，所述一个或多个FEC码块中的每一个FEC码块包括数据码元序列和冗余码元序列，所述子序列A中的有效序列包括所述一个或多个FEC码块的数据码元序列，所述子序列A中的冗余序列包括所述一个或多个FEC码块的冗余码元序列。
可以理解的，本申请子序列A中的有效序列包括的比特数量，是指用于构成子序列A的所有FEC码块的数据码元序列包括的比特数量。本申请子序列A中的冗余序列包括的比特数量，是指用于构成子序列A的所有FEC码块的冗余码元序列包括的比特数量。
作为一种示例，本申请在非对称传输场景下，第一设备在基于第一序列统计第一BER时，可以仅统计构成第一序列的FEC码块中的数据码元序列，因此，在设计第一预设BER时，可以仅考虑构成第一序列的FEC码块中的数据码元序列。例如，此时与第一预设BER对应的N个比特为子序列A中有效序列包括的比特数量；M个比特为子序列A中的有效序列包括的异常比特数量。
作为另一种示例，本申请在非对称传输场景下，第一设备在基于第一序列统计第一BER时，还可以考虑构成第一序列的FEC码块中的所有码元，即数据码元序列与冗余码元序列，因此，在设计第一预设BER时，可以考虑构成第一序列的FEC码块中的所有码元。例如，此时与第一预设BER对应的N个比特为子序列A中的有效序列与冗余序列包括的比特数量；M个比特为子序列A中的有效序列与冗余序列包括的异常比特数量。
一种可能的设计中，所述子序列A包括X个第一FEC码块和Y个第二FEC码块；所述第一FEC码块的数据码元序列包括的比特全部为正常比特；所述第二FEC码块的数据码元序列包括固定数量的异常比特或固定比例的异常比特；所述Y或Y与(X+Y)的比值与所述第一预设BER对应；其中，X与Y为正整数。因此，本申请提供了另一种子序列A的构成方式。
可以理解的，本申请实施例中的Y与第一预设BER对应是指测试装置在需要满足不同的第一预设BER时，可以通过调整子序列A中的Y值，灵活的设置第一预设BER。例如，当子序列A中的Y值为Y1时，对应的第一预设BER为BER1，当子序列A中的Y值为Y2时，对应的第一预设BER为BER2，则当测试装置想将第一预设BER设置成BER1时，可以将子序列A中的Y值调整为Y1。
本申请实施例中的Y与(X+Y)的比值与所述第一预设BER对应是指测试装置在需要满足不同的第一预设BER时，可以通过调整子序列A中的Y与(X+Y)的比值，灵活的设置第一预设BER。例如，当子序列A中的Y与(X+Y)的比值为第一比值时，对应的第一预设BER为BER3，当子序列A中的Y与(X+Y)的比值为第二比值时，对应的第一预设BER为BER4，则当测试装置想将第一预设BER设置成BER3时，可以将子序列A中的Y与(X+Y)的比值调整为第一比值。
采用该方法，本申请在非对称传输场景下进行BER测试时，例如在对车载高清摄像头中的传输芯片进行BER测试的场景中，第二设备不需要额外的电路去做编码生成第一序列，可以基于存储的一个或多个FEC单元去生成第一序列，能够更好的适配非对称传输场景中使用FEC码块传输的情况。其中，本申请中在需要调整第一预设BER时，一种方式可以通过调整子序列A中的Y值，灵活构造与第一预设BER相匹配的用于进行功能测试的第一序列，或者本申请中在需要设置新的第一序列时，可以通过调整子序列A中的异Y值，得到新的第一序列；本申请中在需要调整第一预设BER时，另一种方式通过调整子序列A中Y与(X+Y)的比值，灵活构造与第一预设BER相匹配的用于进行功能测试的第一序列，或者本申请中在需要设置新的第一序列时，可以通过调整子序列A中Y与(X+Y)的比值，得到新的第一序列。
一种可能的设计中，所述第二FEC码块的数据码元序列包括的比特全部为异常比特。因此，本申请提供了另一种子序列A的构成方式。
采用该方法，本申请中通过将第二FEC码块包括的比特全部设置成异常比特，能够更便于调整第一预设BER，简化了在非对称传输场景下进行BER测试时，确定第一预设BER的计算过程。
一种可能的设计中，所述第一FEC码块的冗余码元序列包括的比特全部为正常比特；所述第二FEC码块的冗余码元序列包括的比特也全部为异常比特。
作为一种示例，本申请在非对称传输场景下，第一设备在基于第一序列统计第一BER时，可以仅统计构成第一序列的FEC码块中的有效序列，因此，在设计第一预设BER时，可以仅考虑构成第一序列的FEC码块中的数据码元序列。例如，此时与第一预设BER对应的第一FEC码块的数据码元序列包括的比特全部为正常比特；第二FEC码块的数据码元序列包括的比特全部为异常比特。
作为另一种示例，本申请在非对称传输场景下，第一设备在基于第一序列统计第一BER时，还可以考虑构成第一序列的FEC码块中的所有码元，即数据码元序列与冗余码元序列，因此，在设计第一预设BER时，可以考虑构成第一序列的FEC码块中的所有码元。例如，此时与第一预设BER对应的第一FEC码块的数据码元序列与冗余码元序列包括的比特全部为正常比特；第二FEC码块的数据码元序列与冗余码元序列包括的比特全部为异常比特。
一种可能的设计中，所述子序列A的长度与所述子序列B的长度相等。
一种可能的设计中，当正常比特值为0时，1为异常比特值；或当正常比特值为1时，0为异常比特值。
作为一种示例，本申请实施例中的正常比特可以理解为与预期值相符的比特，例如假设测试装置向被测试装置发送的序列为10111，则被测试装置接收到的预期的比特应该为10111。若被测试装置接收到的序列为11011，则被测试装置接收到的序列的第一位，第四位，第五位对应的比特与预期值相符，为正常比特，被测试装置接收到的序列的第二位，第三位对应的比特与预期值不相符，为异常比特。
采用该方法，本申请通过将正常接收比特的值设置为0，将异常比特值设置为1；或者，通过将正常接收比特的值设置为1，将异常比特值设置为0，使得被测试装置在基于第一序列或第二序列进行BER测试时，可以通过记录取值为1或0的比特个数进行BER统计，统计方式更加简化，有助于更加快速高效的确定第一BER。
一种可能的设计中，当正常比特值为0时，所述第一FEC码块包括的比特可以全部为0，所述第二FEC码块包括的比特可以全部为1；当正常比特值为1时，所述第一FEC码块包括的比特可以全部为1，所述第二FEC码块包括的比特可以全部为0。
采用该方法，本申请在正常比特值为0时，通过将第一FEC码块包括的比特全部设置为0，将第二FEC码块包括的比特全部设置为1；或者，在正常比特值为1时，通过将第一FEC码块包括的比特全部设置为1，将第二FEC码块包括的比特全部设置为0，使得在非对称传输场景下，被测试装置在基于第一序列或第二序列进行BER测试时，可以通过记录第一FEC码块的个数和/或第二FEC码块的个数进行BER统计，统计方式更加简化，有助于更加快速高效的确定第一BER。
一种可能的设计中，所述第二设备向第一设备发送第一序列之前，第二设备与第一设备进行链路训练。
采用该方法，在进行实际的测试之前，先进行链路训练，从而能够使第二设备(即被测试设备)的接收参数有效收敛，使得实际的测试过程更加稳定，得到的测试结果更加准确。
本申请提供的通信方法可以由第一设备执行，其中，该第一设备可以作为被测试装置(Device Under Test，DUT)。该第一设备可以被抽象为计算机系统。该第一设备可以是整机，也可以是整机中的部分器件，例如：系统芯片或处理芯片。其中，系统芯片也可以包括片上系统(system on chip，SOC)，或SoC芯片。具体地，该第一设备可以是一个单独的用于进行BER测试的装置，或者，第一设备可以是整机中的用于进行BER测试的器件。例如，第一设备可以是需要进行BER测试的车载摄像头、车载显示屏等这样的终端装置或车载设备，也可以是需要进行BER测试的摄像头或显示屏中的用于与元数据控制器(Meta Data Controller，MDC)进行数据传输的系统芯片、决策处理芯片或其他类型的芯片等。
第二方面，本申请实施例提供一种通信方法，包括：
接收第二设备发送的第一序列，所述第一序列包括P个子序列A，所述子序列A构成一个或多个前向纠错FEC码块；统计接收的第一序列的第一误比特率BER；接收所述第二设备发送的第二序列，所述第二序列包括Q个子序列B，所述子序列B构成一个或多个前向纠错FEC码块；统计接收的第二序列的第二BER；其中，所述第二序列的长度大于或等于所述第一序列的长度，P与Q为正整数。
作为一种示例，在非对称传输场景下进行BER测试时，第一设备可以分别接收第一序列和第二序列，例如第一设备接收第二设备先发送的第一序列，然后再接收第二设备后发送的第二序列。
作为另一种示例，在非对称传输场景下进行BER测试时，第一设备可以同时接收第一序列和第二序列，例如第一设备可以接收第二设备发送的第一信息，第一信息中包括第一序列以及第二序列。
采用该方法，由于本申请进行BER测试有效利用了设备传输所采用的FEC码块作为第一序列与第二序列的最小重复单元，减少设备构造测试序列的复杂度，提升测试过程的鲁棒性。进一步，当第二序列的长度大于第一序列的长度时，能够有效缩短基于第一序列的功能测试的时间，提高测试速度。对于非对称传输场景，可以采用该方法进行单向的BER测试，可以简化测试过程和时间，提高测试效率。可以理解的是，这一测试方法也可以适用于对称传输场景。
一种可能的设计中，统计接收的第一序列中异常比特的数量；或统计接收的第一序列中异常比特的数量与接收的第一序列中总比特数量的比值。
采用该方法，提供了一种确定第一BER的方式，例如通过记录第一序列中异常比特的数量确定第一BER。此外，通过该种方式，第一设备在确定第一序列的第一BER时，可以直接统计异常比特，不需要挨个比较，能够有效增加第一设备统计第一BER的速度。
一种可能的设计中，统计接收的第二序列中异常比特的数量；或统计接收的第二序列中异常比特的数量与接收的第二序列中总比特数量的比值。
采用该方法，提供了一种确定第二BER的方式，例如通过记录第二序列中异常比特的数量确定第二BER。此外，通过该种方式，第一设备在确定第二序列的第二BER时，可以直接统计异常比特，不需要挨个比较，能够有效增加第一设备统计第二BER的速度。一种可能的设计中，当所述第一BER满足第一预设BER时，统计接收到的所述第二序列的第二BER。
作为一种示例，第一预设BER，可以为一个具体值。其中，当第一预设BER为一个具体值时，第一BER等于第一预设BER，则确定第一BER满足第一预设BER；或者，当第一预设BER为一个具体值时，第一BER在基于第一预设BER的浮动范围内，则确定第一BER满足第一预设BER。例如，基于第一预设BER的浮动范围的左边界可以是通过对第一预设BER减去第一数值得到的，基于第一预设BER的浮动范围的右边界可以是通过对第一预设BER加上第二数值得到的，第一数值与该第二数值可以相等，也可以不等，且都为正数。再例如，基于第一预设BER的浮动范围的左边界可以是通过对第一预设BER乘以第一比例得到的，基于第一预设BER的浮动范围的右边界可以是通过对第一预设BER乘以第二比例得到的，其中，第二比例大于第一比例，且都为正数。
作为一种示例，第一预设BER，还可以为一个取值范围。其中，当第一预设BER为一个取值范围时，第一BER在第一预设BER的取值范围内，则确定第一BER满足第一预设BER。
可以理解的，该方法中提供了一种在非对称传输场景下，触发第一设备统计第二序列的第二BER的情况，例如当第一设备基于第一序列统计出的第一BER满足第一预设BER时，认为第一设备具有准确的错误检测和统计能力，能够更好的保证第一设备后续进行性能测试的结果是准备可靠的，故可以触发第一设备基于第二序列的BER测试。
其中，本申请在确定第一设备基于接收到的第一序列统计出的第一BER是否满足第一预设BER时，可以由测试人员人为判断第一设备基于接收到的第一序列统计出的第一BER是否满足第一预设BER，测试人员确定第一BER满足第一预设BER时，人为触发第一设备统计第二序列的第二BER；或者，本申请在确定第一设备基于接收到的第一序列统计出的第一BER是否满足第一预设BER时，还可以通过第一设备将第一BER回传给第二设备，从而通过第二设备判断接收到的第一BER是否满足第一预设BER，若满足，则向第一设备发送该第二序列，使得第一设备在接收到第二序列后触发统计第二序列的第二BER。
一种可能的设计中，所述子序列A包括N个比特；所述子序列A序列中包括M个异常比特；所述M或M与N的比值与所述第一预设BER对应；其中，N与M为正整数，且N大于或等于M。因此，本申请提供了一种子序列A的构成方式。
可以理解的，本申请实施例中的M与第一预设BER对应是指测试装置在需要满足不同的第一预设BER时，可以通过调整子序列A中的M值，灵活的设置第一预设BER。例如，当子序列A中的M值为M1时，对应的第一预设BER为BER1，当子序列A中的M值为M2时，对应的第一预设BER为BER2，则当测试装置想将第一预设BER设置成BER1时，可以将子序列A中的M值调整为M1。
本申请实施例中的M与N的比值与第一预设BER对应是指测试装置在需要满足不同的第一预设BER时，可以通过调整子序列A中的M与N的比值，灵活的设置第一预设BER。例如，当子序列A中的M与N的比值为第一比值时，对应的第一预设BER为BER3，当子序列A中的M与N的比值为第二比值时，对应的第一预设BER为BER4，则当测试装置想将第一预设BER设置成BER3时，可以将子序列A中的M与N的比值调整为第一比值。
采用该方法，本申请在非对称传输场景下进行BER测试时，例如第一设备为车载高清摄像头中的传输芯片，第二设备在对车载高清摄像头中的传输芯片进行BER测试时，第二设备不需要额外的电路去做编码生成第一序列，可以基于存储的一个或多个FEC单元去生成第一序列，能够更好的适配非对称传输场景中使用FEC码块传输的情况。其中，本申请中在需要调整第一预设BER时，一种方式可以通过调整子序列A中的异常比特M的取值，灵活构造与第一预设BER相匹配的用于进行功能测试的第一序列，或者本申请中在需要设置新的第一序列时，可以通过调整子序列A中的异常比特M的取值，得到新的第一序列；本申请中在需要调整第一预设BER时，另一种方式通过调整子序列A中M与N的比值，灵活构造与第一预设BER相匹配的用于进行功能测试的第一序列，或者本申请中在需要设置新的第一序列时，可以通过调整子序列A中的M与N的比值，得到新的第一序列。
一种可能的设计中，所述N个比特为所述子序列A中的有效序列包括的比特数量；所述M个比特为所述子序列A中的有效序列包括的异常比特数量；或所述N个比特为所述子序列A中的有效序列与冗余序列包括的比特数量；所述M个比特为所述子序列A中的有效序列与冗余序列包括的异常比特数量；其中，所述一个或多个FEC码块中的每一个FEC码块包括数据码元序列和冗余码元序列，所述子序列A中的有效序列包括所述一个或多个FEC码块的数据码元序列，所述子序列A中的冗余序列包括所述一个或多个FEC码块的冗余码元序列。
可以理解的，本申请子序列A中的有效序列包括的比特数量，是指用于构成子序列A的所有FEC码块的数据码元序列包括的比特数量。本申请子序列A中的冗余序列包括的 比特数量，是指用于构成子序列A的所有FEC码块的冗余码元序列包括的比特数量。
作为一种示例，本申请在非对称传输场景下，第一设备在基于第一序列统计第一BER时，可以仅统计构成第一序列的FEC码块中的数据码元序列，因此，在设计第一预设BER时，可以仅考虑构成第一序列的FEC码块中的数据码元序列。例如，此时与第一预设BER对应的N个比特为子序列A中有效序列包括的比特数量；M个比特为子序列A中的有效序列包括的异常比特数量。
作为另一种示例，本申请在非对称传输场景下，第一设备在基于第一序列统计第一BER时，还可以考虑构成第一序列的FEC码块中的所有码元，即数据码元序列与冗余码元序列，因此，在设计第一预设BER时，可以考虑构成第一序列的FEC码块中的所有码元。例如，此时与第一预设BER对应的N个比特为子序列A中的有效序列与冗余序列包括的比特数量；M个比特为子序列A中的有效序列与冗余序列包括的异常比特数量。
一种可能的设计中，所述子序列A包括X个第一FEC码块和Y个第二FEC码块；所述第一FEC码块的数据码元序列包括的比特全部为正常比特；所述第二FEC码块的数据码元序列包括固定数量的异常比特或固定比例的异常比特；所述Y或Y与(X+Y)的比值与所述第一预设BER对应；其中，X与Y为正整数。因此，本申请提供了另一种子序列A的构成方式。
可以理解的，本申请实施例中的Y与第一预设BER对应是指测试装置在需要满足不同的第一预设BER时，可以通过调整子序列A中的Y值，灵活的设置第一预设BER。例如，当子序列A中的Y值为Y1时，对应的第一预设BER为BER1，当子序列A中的Y值为Y2时，对应的第一预设BER为BER2，则当测试装置想将第一预设BER设置成BER1时，可以将子序列A中的Y值调整为Y1。
本申请实施例中的Y与(X+Y)的比值与所述第一预设BER对应是指测试装置在需要满足不同的第一预设BER时，可以通过调整子序列A中的Y与(X+Y)的比值，灵活的设置第一预设BER。例如，当子序列A中的Y与(X+Y)的比值为第一比值时，对应的第一预设BER为BER3，当子序列A中的Y与(X+Y)的比值为第二比值时，对应的第一预设BER为BER4，则当测试装置想将第一预设BER设置成BER3时，可以将子序列A中的Y与(X+Y)的比值调整为第一比值。
采用该方法，本申请在非对称传输场景下进行BER测试时，例如在对车载高清摄像头中的传输芯片进行BER测试的场景中，第二设备不需要额外的电路去做编码生成第一序列，可以基于存储的一个或多个FEC单元去生成第一序列，能够更好的适配非对称传输场景中使用FEC码块传输的情况。其中，本申请中在需要调整第一预设BER时，一种方式可以通过调整子序列A中的Y值，灵活构造与第一预设BER相匹配的用于进行功能测试的第一序列，或者本申请中在需要设置新的第一序列时，可以通过调整子序列A中的Y值，得到新的第一序列；本申请中在需要调整第一预设BER时，另一种方式通过调整子序列A中Y与(X+Y)的比值，灵活构造与第一预设BER相匹配的用于进行功能测试的第一序列，或者本申请中在需要设置新的第一序列时，可以通过调整子序列A中Y与(X+Y)的比值，得到新的第一序列。
一种可能的设计中，所述第二FEC码块的数据码元序列包括的比特全部为异常比特。因此，本申请提供了另一种子序列A的构成方式。
采用该方法，本申请中通过将第二FEC码块包括的比特全部设置成异常比特，能够更 便于调整第一预设BER，简化了在非对称传输场景下进行BER测试时，确定第一预设BER的计算过程。
一种可能的设计中，所述第一FEC码块的冗余码元序列包括的比特全部为正常比特；所述第二FEC码块的冗余码元序列包括的比特也全部为异常比特。
作为一种示例，本申请在非对称传输场景下，第一设备在基于第一序列统计第一BER时，可以仅统计构成第一序列的FEC码块中的有效序列，因此，在设计第一预设BER时，可以仅考虑构成第一序列的FEC码块中的数据码元序列。例如，此时与第一预设BER对应的第一FEC码块的数据码元序列包括的比特全部为正常比特；第二FEC码块的数据码元序列包括的比特全部为异常比特。
作为另一种示例，本申请在非对称传输场景下，第一设备在基于第一序列统计第一BER时，还可以考虑构成第一序列的FEC码块中的所有码元，即数据码元序列与冗余码元序列，因此，在设计第一预设BER时，可以考虑构成第一序列的FEC码块中的所有码元。例如，此时与第一预设BER对应的第一FEC码块的数据码元序列与冗余码元序列包括的比特全部为正常比特；第二FEC码块的数据码元序列与冗余码元序列包括的比特全部为异常比特。
一种可能的设计中，所述子序列A的长度与所述子序列B的长度相等。
一种可能的设计中，当正常比特值为0时，1为异常比特值；或当正常比特值为1时，0为异常比特值。
作为一种示例，本申请实施例中的正常比特可以理解为与预期值相符的比特，例如假设测试装置向被测试装置发送的序列为10111，则被测试装置接收到的预期的比特应该为10111。若被测试装置接收到的序列为11011，则被测试装置接收到的序列的第一位，第四位，第五位对应的比特与预期值相符，为正常比特，被测试装置接收到的序列的第二位，第三位对应的比特与预期值不相符，为异常比特。
采用该方法，本申请通过将正常接收比特的值设置为0，将异常比特值设置为1；或者，通过将正常接收比特的值设置为1，将异常比特值设置为0，使得在非对称传输场景下，被测试装置在基于第一序列或第二序列进行BER测试时，可以通过记录取值为1或0的比特个数进行BER统计，统计方式更加简化，有助于更加快速高效的确定第一BER。
一种可能的设计中，当正常比特值为0时，所述第一FEC码块包括的比特可以全部为0，所述第二FEC码块包括的比特可以全部为1；当正常比特值为1时，所述第一FEC码块包括的比特可以全部为1，所述第二FEC码块包括的比特可以全部为0。
一种可能的设计中，当正常比特值为0时，所述子序列B中所有FEC码块的数据码元序列包括的比特全部为0；或者，当正常比特值为1时，所述子序列B中所有FEC码块的数据码元序列包括的比特全部为1。
采用该方法，本申请在正常比特值为0时，通过将第一FEC码块包括的比特全部设置为0，将第二FEC码块包括的比特全部设置为1；或者，在正常比特值为1时，通过将第一FEC码块包括的比特全部设置为1，将第二FEC码块包括的比特全部设置为0，使得在非对称传输场景下，被测试装置在基于第一序列或第二序列进行BER测试时，可以通过记录第一FEC码块的个数和/或第二FEC码块的个数进行BER统计，统计方式更加简化，有助于更加快速高效的确定第一BER。
一种可能的设计中，所述第一设备接收第二设备发送的第一序列之前，还包括与第二 设备进行链路训练。
采用该方法，在进行实际的测试之前，先进行链路训练，从而能够使第一设备(即被测试设备)的接收参数有效收敛，使得实际的测试过程更加稳定，得到的测试结果更加准确。
第三方面，本申请实施例提供了一种通信装置，该装置用于实现上述第一方面或第一方面中任意一种方法，包括相应的功能模块或单元，分别用于实现上述第一方面方法中的步骤。功能可以通过硬件实现，也可以通过硬件执行相应的软件实现，硬件或软件包括一个或多个与上述功能相应的模块或单元。
第四方面，本申请实施例提供了一种通信装置，该装置用于实现上述第二方面或第二方面中任意一种方法，包括相应的功能模块或单元，分别用于实现上述第二方面方法中的步骤。功能可以通过硬件实现，也可以通过硬件执行相应的软件实现，硬件或软件包括一个或多个与上述功能相应的模块或单元。
第五方面，提供一种通信装置，该装置包括处理器和存储器。其中，存储器用于存储计算程序或指令，处理器与存储器耦合；当处理器执行计算机程序或指令时，使得该装置执行上述第一方面或第一方面中的任意一种方法。通信装置可以是第二设备，或能够支持第二设备实现上述第一方面提供的方法所需的功能的装置，例如芯片系统。例如，所述通信装置可以是终端设备或终端设备内的部分组件(比如芯片)。所述终端设备例如可以是智能移动终端、智能家居设备、智能汽车、智能穿戴设备等等。其中，智能移动终端比如手机、平板电脑、笔记本电脑、超级移动个人计算机(ultra-mobile personal computer，UMPC)、上网本、个人数字助理(personal digital assistant，PDA)等。智能家居设备比如智能冰箱、智能洗衣机、智能电视机、音箱等。智能汽车穿戴设备比如智能耳机、智能眼镜、智能服饰或鞋子等。
第六方面，提供一种通信装置，该装置包括处理器和存储器。其中，存储器用于存储计算程序或指令，处理器与存储器耦合；当处理器执行计算机程序或指令时，使得该装置执行上述第二方面或第二方面中的任意一种方法。通信装置可以是第一设备或能够支持第一设备实现上述第二方面提供的方法所需的功能的装置，例如芯片系统。例如，所述通信装置可以是终端设备或终端设备内的部分组件(比如芯片)。所述终端设备例如可以是智能移动终端、智能家居设备、智能汽车、智能穿戴设备等等。其中，智能移动终端比如手机、平板电脑、笔记本电脑、超级移动个人计算机(ultra-mobile personal computer，UMPC)、上网本、个人数字助理(personal digital assistant，PDA)等。智能家居设备比如智能冰箱、智能洗衣机、智能电视机、音箱等。智能汽车穿戴设备比如智能耳机、智能眼镜、智能服饰或鞋子等。
第七方面，提供一种终端，该终端可包括上述第三方面至第六方面中任一方面所述的装置。可选的，该装置可以为智能家居设备、智能制造设备、智能运输设备等，例如车辆、无人机、无人运输车、汽车和车辆等，或机器人等。
第八方面，本申请提供一种芯片，芯片与存储器相连，用于读取并执行存储器中存储的计算机程序或指令，以实现上述第一方面或第一方面的任一种可能的实现方式中的方法；或以实现上述第二方面或第二方面的任一种可能的实现方式中的方法。
第九方面，提供一种计算机可读存储介质，计算机可读存储介质中存储有计算机程序或指令，当计算机程序或指令被上述通信装置执行时，使得该装置执行上述第一方面或第一方面的任意可能的实现方式中的方法，或使得该装置执行上述第二方面或第二方面的任意可能的实现方式中的方法。
第十方面，提供本申请提供一种计算机程序产品，该计算机程序产品包括计算机程序或指令，当计算机程序或指令被上述通信装置执行时，使得该装置执行上述第一方面或第一方面的任意可能的实现方式中的方法，或使得该装置执行上述第二方面或第二方面的任意可能的实现方式中的方法。
第十一方面，本申请提供一种通信系统，该系统包括第一设备和第二设备；
所述第二设备，用于向所述第一设备发送第一序列；向所述第一设备发送第二序列；
所述第一设备，用于接收所述第二设备发送的第一序列，统计接收的第一序列的第一误比特率BER；还用于接收所述第二设备发送的第二序列，统计接收的第二序列的第二BER；
其中，所述第一序列包括P个子序列A，所述子序列A构成一个或多个前向纠错FEC码块；所述第二序列包括Q个子序列B，所述子序列B构成一个或多个前向纠错FEC码块；所述第二序列的长度大于或等于所述第一序列的长度，P与Q为正整数。
应理解，基于本申请所提供的技术方案，能够更加灵活高效的实现非对称传输场景下的BER测试，可应用量产芯片的BER测试，或者应用芯片产品的BER测试。
附图说明
图1为本申请提供的一种测试系统的示例性的结构图；
图2为本申请提供的一种测试设备与被测试设备的连接示例图；
图3为本申请提供的第一种通信方法的流程示意图；
图4为本申请提供的一种FEC码块示意图；
图5为本申请提供的第一种第一序列的示例性的结构图；
图6为本申请提供的第二种第一序列的示例性的结构图；
图7为本申请提供的第二种第一序列的示例性的结构图；
图8为本申请提供的第二种通信方法的流程示意图；
图9为本申请提供的第三种通信方法的流程示意图；
图10为本申请提供的第一种装置结构示意图；
图11为本申请提供的第二种装置结构示意图。
具体实施方式
本申请提供一种通信方法、装置和系统，用以提高BER测试的灵活性，有效缩短测试时间。其中，本申请实施例中所述的通信方法和通信装置是基于同一技术构思的，由于本申请实施例所述的通信方法及通信装置解决问题的原理相似，因此本申请实施例所述的通信装置与通信方法的实施可以相互参见，重复之处不再赘述。
下面将结合附图对本申请实施例作进一步地详细描述。
首先介绍本申请实施例所涉及的通信系统，如图1中的(a)所示，本申请实施例中的通信系统可以包括第一设备101和第二设备102。其中，本申请实施例所涉及的通信系统可以适用于非对称传输场景，也可以适用于对称传输场景。此外，本申请实施例所涉及的通信系统可以适用于有线传输场景和无线传输场景。
其中，本申请实施例中的第一设备101可以是具备发送和接收功能的电子设备或者电子设备中的器件，例如第一设备101可以是包括发送器(Transmitter，TX)和接收器(Receiver，RX)的电子设备。
本申请实施例中的第二设备102可以是具备发送和接收功能的电子设备或者电子设备中的器件，例如第二设备102可以是包括TX和RX的电子设备。
示例性的，如图1中的(b)所示，第一设备可以是需要进行BER测试的车载显示屏，也可以是需要进行BER测试的车载显示屏中的芯片；第二设备可以是用于对第一设备进行BER测试的外连终端装置。如图1中的(c)所示，第一设备还可以是需要进行BER测试的车载摄像头，也可以是需要进行BER测试的车载摄像头中的芯片；第二设备可以是用于对第一设备进行BER测试的外连终端装置。
可选的，本申请实施例中的第一设备101与第二设备102之间可以通过线缆连接。
其中，本申请实施例基于上述通信系统执行通信方法时，主要通过第二设备向第一设备发送第一序列和第二序列，然后根据第一设备基于第一序列输出的第一BER，以及基于第二序列的输出第二BER判断第一设备是否通过测试。
其中，上述图1所示的第一设备101可以理解为需要进行测试的设备，即被测试设备，具备BER统计功能；上述图1所示的第二设备102可以理解为对被测试设备进行测试的设备，即测试设备，具备序列发送功能。
此外，本申请实施例中测试设备还可以具备序列生成或者序列调整的功能等。
可选的，第一设备101还可以具有显示功能，例如，第一设备101可以包括显示屏幕，用于显示基于不同序列进行BER测试时得到的BER；或者，第一设备101还可以具有语音播报功能，例如，第一设备101可以包括语音播报装置，用于播报基于不同序列进行测试时得到的BER。
可选的，第一设备101与第二设备102之间连接的线缆数量本申请实施例中并不进行限定。
作为一种示例，如图2中的(a)所示，第一设备与第二设备之间通过一条线缆进行连接，其中，第一设备与第二设备之间连接的一条线缆用于第二设备向第一设备进行单向通信；或者，如图2中的(b)所示，第一设备与第二设备之间连接的一条线缆用于第二设备与第一设备之间进行双向通信。
作为一种示例，如图2中的(c)所示，第一设备与第二设备之间通过两条线缆进行连接，其中，第一设备与第二设备之间连接的线缆1用于第二设备向第一设备进行单向通信； 第一设备与第二设备之间连接的线缆2用于第一设备向第二设备进行单向通信。
进一步的，为了更好的理解本申请所述的通信方法，如图3所示，为本申请提供的一种通信方法的一个示例性的流程图。应当理解的是，图3所示的过程可以以各种顺序执行和/或同时发生，不限于图3所示的执行顺序。
S300，第二设备向第一设备发送第一序列。
其中，本申请实施例中第一序列用于第一设备统计第一BER。
本申请实施例中第二设备向第一设备发送的第一序列可以理解为功能测试序列，其中，功能测试序列用于对第一设备进行功能测试，一般在对第一设备进行性能测试前发送，且功能测试序列发送的数据量较少，主要确定第一设备是否具备准确的错误检测和统计能力，从而更好的保证第一设备进行性能测试的结果是准确可靠的，以及节省对第一设备的测试时间。
具体地，本申请实施例中第一序列包括P个子序列A，子序列A构成一个或多个前向纠错(Forward Error Correction，FEC)码块，P为正整数。
例如，第一序列可以表示为{A，A，……，A}，P为第一序列中A的重复次数。其中，本申请实施例中并不限定用于构成子序列A的FEC码块的种类，以及每种FEC码块的具体结构，任何适用本申请实施例的FEC码块都属于本申请实施例保护范围。
作为一种示例，如图4所示，为本申请实施例提供的一种FEC码块的示意图，该FEC码块可以由2部分组成，其中，第一部分为数据码元序列，即通过至少一个数据码元组成的序列，第二部分为冗余码元序列，即通过至少一个冗余码元组成的序列，其中，每个码元由长度一致的比特序列构成。
例如，以里德所罗门(Reed-Solomon)RS-FEC(384，354，9)为例，该RS-FEC(384，354，9)表示总码元的数量为384个，数据码元的数量为354个，每个码元的长度为9比特，整个RS-FEC码块的长度为384*9＝3456比特，其中，由数据码元通过RS编码产生的冗余码元的数量为30个(384-354＝30)。
一种情况下，子序列A构成一个FEC码块时，子序列A可以表示成A＝[数据码元序列，冗余码元序列]，数据码元序列构成子序列A的有效序列，冗余码元序列构成子序列A的冗余序列。
另一种情况下，子序列A构成多个FEC码块时，比如子序列A构成L个FEC码块(大于1的正整数)，子序列A可以表示成A＝[(数据码元序列1，冗余码元序列1)，(数据码元序列2，冗余码元序列2)，…，(数据码元序列L，冗余码元序列L)]。其中，(数据码元序列i，冗余码元序列i)构成一个RS-FEC码块，子序列A的有效序列包括数据码元序列i，子序列A的冗余序列包括冗余码元序列i，i为整数，i＝1…L。
S301，第一设备接收第二设备发送的第一序列。
其中，本申请实施例中第一设备可以通过与第二设备之间连接的用于通信的线缆获取该测试装置发送的第一序列。
S302，第一设备统计接收的第一序列的第一BER。
其中，本申请提供一种验证方案，具体内容可以如下：
首先，确定用于进行功能测试的第一序列(也可以称为功能测试序列)，以及第一序列对应的第一预设BER。
需要说明的是，本申请实施例中可以先设计用于进行功能测试的第一序列，从而基于第一序列确定第一预设BER；本申请实施例中还可以先确定第一预设BER的值，从而基于第一预设BER进行第一序列的设计。
然后，第二设备将第一序列发送给第一设备，让第一设备统计接收到的第一序列的BER，得到第一BER。
最后，可以根据第一BER，以及第一预设BER，确定第一设备是否能进行有效的性能测试。若第一设备基于接收的第一序列得到的第一BER满足第一预设BER，则可以认为第一设备能够进行有效的性能测试，反之，则认为第一设备不能够进行有效的性能测试。
此外，本申请实施例中为了更好的保证第一设备能够有效的进行性能测试，第二设备可以向第一设备多次发送第一序列进行功能测试，当第一设备在进行所述多次功能测试中，通过功能测试的次数占功能测试的总次数的比例(即通过率)满足第一阈值比例时，则可以认为第一设备能够进行有效的性能测试，反之，则认为第一设备不能够进行有效的性能测试。
其中，本申请实施例中的第一预设BER，可以为一个具体值，也可以为一个取值范围。
可选的，当第一预设BER为一个具体值时，第一BER等于第一预设BER，则确定第一BER满足第一预设BER。
可选的，当第一预设BER为一个具体值时，第一BER在基于第一预设BER的浮动范围内，则确定第一BER满足第一预设BER。
一种情况下，基于第一预设BER的浮动范围的左边界可以是通过对第一预设BER减去第一数值得到的，基于第一预设BER的浮动范围的右边界可以是通过对第一预设BER加上第二数值得到的，第一数值与第二数值可以相等，也可以不等，且都为正数。
例如，假设第一数值和第二数值都为0.05，第一预设BER为10.2％，则基于第一预设BER得到的范围为5.2％～15.2％。
另一种情况下，基于第一预设BER的浮动范围的左边界可以是通过对第一预设BER乘以第一比例得到的，基于第一预设BER的浮动范围的右边界可以是通过对第一预设BER乘以第二比例得到的，其中，第二比例大于第一比例，且都为正数。
例如，假设第一比例为0.95，第二比例为1.05，第一预设BER为10.2％，则基于第一预设BER得到的范围为9.69％～10.71％。
可选的，当第一预设BER为一个取值范围时，第一BER在第一预设BER的取值范围内，则确定第一BER满足第一预设BER。
S303，第二设备向第一设备发送第二序列。
其中，本申请实施例中第二序列用于第一设备统计第二误比特率BER。
本申请实施例中第二设备向第一设备发送的第二序列可以理解为性能测试序列，性能测试序列用于对第一设备进行性能测试，一般在第一设备通过功能测试后发送，且性能测试序列发送的数据量较多，主要确定第一设备的性能是否合格。
例如，假设第一设备为芯片时，第二设备通过向该芯片发送性能测试序列，从而可以基于该芯片针对接收到的性能测试序列统计的BER结果，来判断该芯片是否是合格的芯片等。
具体地，本申请实施例中第二序列包括Q个子序列B，所述子序列B构成一个或多个FEC码块，Q为正整数。
例如，第二序列可以表示为{B，B,……,B}，Q为第二序列中B的重复次数。其中，本申请实施例中并不限定用于构成子序列B的FEC码块的种类，以及每种FEC码块的具体结构，任何适用本申请实施例的FEC码块都属于本申请实施例保护范围。
其中，本申请实施例中的第二序列的长度大于或等于第一序列的长度。
下面基于第二序列的长度与第一序列的长度的不同情况分别进行介绍：
情况1：第二序列的长度等于第一序列的长度。
作为一种示例，当本申请实施例中的第二序列的长度等于第一序列的长度时，第二序列中的子序列B的长度可以等于第一序列中的子序列A的长度，第二序列中子序列B的数量可以等于第一序列中子序列A的数量，从而实现该第二序列的长度等于第一序列的长度。
例如，子序列B的长度为50比特，子序列A的长度为50比特，以及第二序列中子序列B的数量为20个，第一序列中子序列A的数量也为20，则此时第二序列的长度等于第一序列的长度，都为50*20＝1000比特。
作为一种示例，当本申请实施例中的第二序列的长度等于第一序列的长度时，第二序列中的子序列B的长度可以小于第一序列中的子序列A的长度，第二序列中子序列B的数量可以大于第一序列中子序列A的数量，从而实现第二序列的长度等于第一序列的长度。
例如，子序列B的长度为40比特，子序列A的长度为50比特，以及第二序列中子序列B的数量为20个，第一序列中子序列A的数量也为16，则此时第二序列的长度为800比特(20*40＝800)，等于第一序列的长度800比特(50*16＝800)。
情况2：第二序列的长度大于第一序列的长度。
作为一种示例，当本申请实施例中的第二序列的长度大于第一序列的长度时，第二序列中的子序列B的长度可以等于第一序列中的子序列A的长度，第二序列中子序列B的数量可以大于第一序列中子序列A的数量，从而实现第二序列的长度大于第一序列的长度。
例如，子序列B的长度为50比特，子序列A的长度为50比特，以及第二序列中子序列B的数量为30个，第一序列中子序列A的数量也为20，则此时第二序列的长度为1500比特(30*50＝1500)，大于第一序列的长度1000比特(50*20＝1000)。
作为一种示例，当本申请实施例中的第二序列的长度大于第一序列的长度时，第二序列中的子序列B的长度可以大于第一序列中的子序列A的长度，第二序列中子序列B的数量可以等于第一序列中子序列A的数量，从而实现第二序列的长度大于第一序列的长度。
例如，子序列B的长度为50比特，子序列A的长度为40比特，以及第二序列中子序列B的数量为30个，第一序列中子序列A的数量也为30，则此时第二序列的长度为1500比特(30*50＝1500)，大于第一序列的长度1200比特(40*30＝1200)。
作为一种示例，当本申请实施例中的第二序列的长度大于第一序列的长度时，第二序列中的子序列B的长度可以大于第一序列中的子序列A的长度，第二序列中子序列B的数量可以大于第一序列中子序列A的数量，从而实现第二序列的长度大于第一序列的长度。
例如，子序列B的长度为50比特，子序列A的长度为40比特，以及第二序列中子序列B的数量为30个，第一序列中子序列A的数量也为20，则此时第二序列的长度为1500比特(30*50＝1500)，大于第一序列的长度800比特(40*20＝800)。
此外，本申请实施例中第二设备可以将第一序列以及第二序列一起发送给第一设备，即本申请实施例中可以将S303与上述S300可以合并为一个步骤。
例如，在S300中，第二设备可以向第一设备发送第一信息，第一信息中可以包括第一序列以及第二序列。
S304，第一设备接收第二设备发送的第二序列。
S305，第一设备统计接收的第二序列的第二BER。
其中，本申请提供一种验证方案，具体内容可以如下：
首先，确定用于进行性能测试的第二序列(也可以称为性能测试序列)，以及第二序列对应的第二预设BER。
需要说明的是，本申请实施例中可以先设计用于进行性能测试的第二序列，从而基于第二序列确定第二预设BER；本申请实施例中还可以先确定第二预设BER的值，从而基于第二预设BER进行第二序列的设计。
然后，第二设备将第二序列发送给第一设备，让第一设备统计接收到的第二序列的BER，得到第二BER。
最后，可以根据第二BER，以及第二预设BER，确定第一设备是否通过性能测试。若第一设备基于接收的第二序列得到的第二BER满足第二预设BER，则可以认为第一设备通过性能测试，反之，则认为第一设备没有通过性能测试。
此外，本申请实施例中为了更好的保证第一设备进行性能测试结果的准确性，第二设备可以向第一设备多次发送第二序列进行性能测试，当第一设备在进行所述多次性能测试中，通过性能测试的次数占性能测试的总次数的比例(即通过率)满足第二阈值比例时，则可以认为第一设备合格，反之，则认为第一设备不合格。
其中，本申请实施例中的第二预设BER阈值，可以为一个具体值，也可以为一个取值范围。
可选的，当第二预设BER为一个具体值时，第二BER小于第二预设BER，则确定第二BER满足第二预设BER。
例如，当第二预设BER为10 ^-12时，若第二BER小于10 ^-12，则确定第二BER满足第二预设BER。
可选的，当第二预设BER为一个取值范围时，第二BER在第二预设BER的取值范围内，则确定第二BER满足第二预设BER。
通过上述方法，由于本申请在非对称传输场景下进行BER测试的第一序列以及第二序列都是由至少一个FEC码块构成的，通过将FEC码块序列作为第一序列与第二序列的最小重复单元的设计方式，能够更好的适配非对称传输场景中使用FEC码块传输的情况，以及更好的便于第一设备和/或第二设备进行BER统计。此外，本申请中的第一序列是由P个子序列A构成的，第二序列是由Q个子序列B构成的，可以看出，本申请中第一序列与第二序列之间不存在耦合关系，使得在非对称传输场景下进行BER测试的序列的灵活性更强，以及由于目前功能测试序列一般是通过改变性能测试序列中的预设比特位的取值得到的，而本申请中的第二序列的长度大于或等于所述第一序列的长度，当第二序列的长度大于第一序列的长度时，能够有效缩短基于第一序列的功能测试的时间，提高测试速度。
进一步的，本申请实施例中可以通过将正常接收比特的值设置为0，将异常比特值设置为1；或者，通过将正常接收比特的值设置为1，将异常比特值设置为0，从而使得在进行BER测试时，可以通过记录取值为1或0的比特个数进行统计。例如，将第二序列设置 为全0，第一序列中设置的异常比特取值为1，第一序列中的正常比特取值为0。
通过该种设计方式，使得被测试装置在基于第一序列或第二序列进行BER测试时，可以通过记录异常比特对应的特殊取值1或0的个数进行BER统计，统计方式更加简化，有助于更加快速高效的确定BER。
进一步的，本申请实施例中第一序列的构造方式有多种，包括但不限于下述几种：
构造方式1：如图5中的(a)所示，第一序列包括P个子序列A，每个子序列A包括N个比特，其中，N个比特中包括M个异常比特。其中，P为正整数，表示第一序列中子序列A的数量。
此外，还可以通过1～P，来表示每个子序列A在第一序列中的位置。例如，所述图5中的(a)所示的1对应的子序列A可以表示处于第一序列中第一位的子序列A，所述图5中的(a)所示的2对应的子序列A可以表示处于第一序列中第二位的子序列A，所述图5中的(a)所示的(P-1)对应的子序列A可以表示处于第一序列中第(P-1)位的子序列A，所述图5中的(a)所示的P对应的子序列A可以表示处于第一序列中第P位的子序列A；N为正整数，表示一个子序列A中包括的总比特数量；M为正整数，表示一个子序列A中包括的异常比特数量，可以理解的，本申请实施例中N大于或等于M。
例如，假设P为5，N为7，M为2，则上述图5中的(a)可以表示为第一序列中包括5个子序列A，每个子序列A中包括的总比特数量为7，其中，每个子序列A包括的7个比特中存在2个异常比特。
再例如，假设子序列A为0110111011，其中，0表示异常比特，1表示正常比特，则子序列A包括的总比特数量为10个比特，即N＝10，子序列A包括的异常比特数量为3个比特，即M＝3。基于此，第一序列还可以表示成如图5中的(b)所示。其中，所述图5中的(b)所示的子序列A(1)可以表示处于第一序列中第一位的子序列A，所述图5中的(b)所示的子序列A(2)可以表示处于第一序列中第二位的子序列A，所述图5中的(b)所示的子序列A(P-1)可以表示处于第一序列中第(P-1)位的子序列A，所述图5中的(b)所示的子序列A(P)以表示处于第一序列中第P位的子序列A。
此外，由于第一序列包括P个子序列A，每个子序列A的总比特数量为N，异常比特数量为M，可以理解的，第一序列中包括的总比特数量为第一序列中所有子序列A包括的总比特数量之和，即P*N；第一序列中包括的异常比特数量为第一序列中所有子序列A包括的异常比特数量之和，即P*M。第一序列中包括的正常比特数量为第一序列中所有子序列A包括的正常比特数量之和，即(P*N-P*M)。因此，第一序列还可以简化成如图5中的(c)所示，第一序列包括P*N个比特，该P*N个比特中存在P*M个异常比特。
基于该构造方式1，本申请实施例中还可以通过调整第一序列中的异常比特的数量，来对应不同第一预设BER。
可选的，本申请实施例可以通过调整第一序列中M或者M与N的比值，来对应不同的第一预设BER。例如，当子序列A中的M值为M1时，对应的第一预设BER为BER1，当子序列A中的M值为M2时，对应的第一预设BER为BER2，则当测试装置想将第一预设BER设置成BER1时，可以将子序列A中的M值调整为M1。
再例如，当子序列A中的M与N的比值为第一比值时，对应的第一预设BER为BER3，当子序列A中的M与N的比值为第二比值时，对应的第一预设BER为BER4，则当测试装置想将第一预设BER设置成BER3时，可以将子序列A中的M与N的比值调整为第一比值。
可选的，本申请实施例中可以根据下述公式1确定第一序列对应的第一预设BER：
第一预设BER＝P*M/P*N＝M/N   公式1
其中，P表示第一序列中包括的子序列A的数量，N表示一个子序列A中包括的总比特数量，M表示一个子序列A中包括的异常比特数量。
一种情况下，本申请实施例中N个比特可以为子序列A中的有效序列包括的比特数量，本申请实施例中M个比特可以为子序列A中的有效序列包括的异常比特数量。
示例性的，假设第一序列中子序列A为一个RS-FEC(384，354，9)码块构成的比特序列，其中，RS-FEC(384，354，9)中的“9”表示RS-FEC码块中的每个码元的长度为9比特，RS-FEC(384，354，9)中的“354”表示RS-FEC码块包括的数据码元的数量为354个，RS-FEC(384，354，9)中的“384”表示RS-FEC码块包括的总码元的数量为384个。由于RS-FEC码块中的总码元的数量为数据码元的数量与冗余码元的数量之和，因此根据总码元的数量384以及数据码元的数量354可以得出冗余码元的数量为30个。由于每个码元的长度为9比特，因此整个RS-FEC码块的长度为384*9＝3456比特，冗余码元序列的总长度为30*9＝270比特，数据码元序列的总长度为354*9＝3186比特，则此时N值为3186，即子序列A中的有效序列包括的比特数量。
当子序列A中设置的异常比特数量为118时，即M值为118，此时，将M值为118，N值为3186代入上述公式1，可以得到第一序列对应的第一预设BER为3.7％(M/N＝118/3186＝3.7％)。
当子序列A中设置的异常比特数量为236时，即M值为236，此时，将M值为236，N值为3186代入上述公式1，可以得到第一序列对应的第一预设BER为7.4％(M/N＝236/3186＝7.4％)。
当该子序列A设置的异常比特数量为354时，即M值为354，此时，将M值为354，N值为3186代入上述公式1，可以得到第一序列对应的第一预设BER为11.1％(M/N＝354/3186＝11.1％)。
另一种情况下，本申请实施例中N个比特可以为子序列A中的有效序列与冗余序列包括的比特数量，本申请实施例中M个比特可以为子序列A中的有效序列与冗余序列包括的异常比特数量。
示例性的，假设第一序列中子序列A同样是由上述一个RS-FEC(384，354，9)码块构成的比特序列，由于整个RS-FEC码块的长度为384*9＝3456比特，冗余码元序列的总长度为30*9＝270比特，数据码元序列的总长度为354*9＝3186比特，则此时N值为3456，即子序列A中的有效序列与冗余序列包括的比特数量。
当子序列A中设置的异常比特数量为118时，即M值为118。此时，将M值为118，N值为3456代入上述公式1，可以得到第一序列对应的第一预设BER为3.4％(M/N＝118/3456＝3.4％)。
当该子序列A设置的异常比特数量为236时，即M值为236，此时，将M值为236，N值为3456代入上述公式1，可以得到第一序列对应的第一预设BER为6.8％ (M/N＝236/3456＝6.8％)。
当该子序列A设置的异常比特数量为354时，即M值为354，此时，将M值为354，N值为3456代入上述公式1，可以得到第一序列对应的第一预设BER为10.2％(M/N＝354/3456＝10.2％)。
基于该构造方式1，本申请实施例在根据M或M与N的比值确定对应的第一预设BER时，可以仅考虑构成序列的FEC码块中的数据码元序列部分；或者，还可以考虑构成序列的FEC码块中的所有比特，即数据码元序列和冗余码元序列。
通过上述构造方式1，本申请中在需要调整第一预设BER时，一种方式可以通过调整子序列A中的异常比特M的取值，灵活构造与第一预设BER相匹配的用于进行功能测试的第一序列，或者本申请中在需要设置新的第一序列时，可以通过调整子序列A中的异常比特M的取值，得到新的第一序列；本申请中在需要调整第一预设BER时，另一种方式通过调整子序列A中M与N的比值，灵活构造与第一预设BER相匹配的用于进行功能测试的第一序列，或者本申请中在需要设置新的第一序列时，可以通过调整子序列A中的M与N的比值，得到新的第一序列。
构造方式2：如图6所示，第一序列包括P个子序列A，每个子序列A包括X个第一FEC码块和Y个第二FEC码块，第一FEC码块的数据码元序列全部为正常比特；第二FEC码块的数据码元序列全部为异常比特。其中，P为正整数，表示第一序列中子序列A的数量。
此外，还可以通过1～P，来表示每个子序列A在第一序列中的位置，为简洁描述，请参考上述构造方式1的内容；X为正整数，表示一个子序列A中包括的第一FEC码块数量；Y为正整数，表示一个子序列A中包括的第二FEC码块数量。
例如，假设P为5，X为3，Y为2，则上述图6可以表示为第一序列中包括5个子序列A，每个子序列A中包括的3个第一FEC码块和2个第二FEC码块。
需要说明的是，上述图6所示的第一序列与第二序列的排列位置情况仅是一种示例，本申请实施例中并不限定子序列A中的第一FEC码块与第二FEC码块的位置，第一FEC码块与第二FEC码块可以随机排列。
其中，本申请实施例中由于子序列A包括X个第一FEC码块以及Y个第二FEC码块，可以理解的，一个第一FEC码块与一个第二FEC码块是第一序列中的最小重复单元，即本申请实施例中的第一FEC码块的长度与第二FEC码块的长度可以相同。
例如，假设第一FEC码块和第二FEC码块均是由上述长度为3456比特的RS-FEC(384，354，9)码块构成的，其中，0表示异常比特，1表示正常比特，则第一FEC码块的数据码元序列全为1，第二FEC码块的数据码元序列全为0。
其中，假设子序列A包括3个第一FEC码块(为方便描述，简称a1)，1个第二FEC码块(为方便描述，简称a2)时，子序列A可以表示为a1，a1，a2，a1。当第一序列包括2个子序列A时，第一序列可以表示为a1，a1，a2，a1，a1，a1，a2，a1。其中，由于第一FEC码块和第二FEC码块的长度为3456比特，子序列A包括3个第一FEC码块以及1个第二FEC码块，则子序列A包括的总比特数量为3456*4＝13824，子序列A包括的异常比特数量为3456。由于第一序列包括2个子序列A，则第一序列包括的总比特数量为13824*2＝27648，第一序列包括的异常比特数量为6912。
基于该构造方式2，本申请实施例中还可以通过调整第一序列中的第二FEC码块的数量，来对应不同第一预设BER。
可选的，本申请实施例可以通过调整第一序列中Y值或者Y与(X+Y)的比值，来对应不同的第一预设BER。
例如，当子序列A中的Y值为Y1时，对应的第一预设BER为BER1，当子序列A中的Y值为Y2时，对应的第一预设BER为BER2，则当测试装置想将第一预设BER设置成BER1时，可以将子序列A中的Y值调整为Y1。
再例如，当子序列A中的Y与(X+Y)的比值为第一比值时，对应的第一预设BER为BER3，当子序列A中的Y与(X+Y)的比值为第二比值时，对应的第一预设BER为BER4，则当测试装置想将第一预设BER设置成BER3时，可以将子序列A中的Y与(X+Y)的比值调整为第一比值。
可选的，本申请实施例中可以根据下述公式2确定第一序列对应的第一预设BER：
第一预设BER＝Y/(X+Y)   公式2
其中，X表示一个子序列A中包括的第一FEC码块的数量，Y表示一个子序列A中包括的第二FEC码块的数量。
一种情况下，本申请实施例可以将第一FEC码块的数据码元序列包括的比特全部设置为正常比特，以及将第二FEC码块的数据码元序列包括的比特全部设置为异常比特。
示例性的，假设第一序列中子序列A中包括963个第一FEC码块，即X值为963，第一FEC码块中的数据码元序列全部为正常比特；子序列A中包括37个第二FEC码块，即Y值为37，第二FEC码块中的数据码元序列全部为异常比特。第一FEC码块与第二FEC码块的数据码元序列长度一致。
此时，将X值为963，Y值为37代入上述公式2，可以得到第一序列对应的第一预设BER为3.7％(Y/(X+Y)＝37/(37+963)＝3.7％)。
另一种情况下，本申请实施例可以将第一FEC码块的数据码元序列与冗余码元序列包括的比特全部设置为正常比特，以及将第二FEC码块的数据码元序列与冗余码元序列包括的比特全部设置为异常比特。
示例性的，假设第一序列中子序列A中包括963个第一FEC码块，即X值为963，第一FEC码块中的数据码元序列与冗余码元序列全部为正常比特；子序列A中包括37个第二FEC码块，即Y值为37，第二FEC码块中的数据码元序列与冗余码元序列全部为异常比特。
此时，将X值为963，Y值为37代入上述公式2，可以得到第一序列对应的第一预设BER为3.7％(Y/(X+Y)＝37/(37+963)＝3.7％)。
通过上述构造方式2，本申请中通过将第二FEC码块包括的比特全部设置成异常比特，能够更便于调整第一预设BER，简化确定第一预设BER的计算过程。
构造方式3：如图7所示，第一序列包括P个子序列A，每个子序列A包括X个第一FEC码块和Y个第二FEC码块。其中，第一FEC码块的数据码元序列全部为正常比特；第二FEC码块的数据码元序列存在固定数量的异常比特，或者第二FEC码块的数据码元序列存在固定比例的异常比特。
例如，假设0表示异常比特，1表示正常比特，第一FEC码块与第二FEC码块均是由上述长度为3456比特的RS-FEC(384，354，9)码块构成的，第一FEC码块的数据码元序列为全1，第二FEC码块的数据码元序列中存在固定数量为5的异常比特，则第二FEC码块可以为111……1000001，或者111……1010000，再或者111……0001001等，即保证第二FEC码块的数据码元序列中异常比特的数量为5。
其中，假设子序列A包括3个第一FEC码块(为方便描述，简称a1)，1个第二FEC码块(为方便描述，简称a3)时，子序列A可以表示为a1，a3，a1，a1。当第一序列包括2个子序列A时，第一序列可以表示为a1，a3，a1，a1，a1，a3，a1，a1。其中，由于第一FEC码块和第二FEC码块的长度为3456比特，子序列A包括3个第一FEC码块以及1个第二FEC码块，则子序列A包括的总比特数量为3456*4＝13824。由于第一FEC码块的数据码元序列为全1，第二FEC码块的数据码元序列中存在固定数量为5的异常比特，则子序列A包括的异常比特数量为5。由于第一序列包括2个子序列A，则第一序列包括的总比特数量为13824*2＝27648，第一序列包括的异常比特数量为10。
基于该构造方式3，本申请实施例中还可以通过调整第一序列中的第二FEC码块的数量，来对应不同第一预设BER。
可选的，本申请实施例可以通过调整第一序列中Y值或者Y与(X+Y)的比值，来对应不同的第一预设BER。
例如，当子序列A中的Y值为Y1时，对应的第一预设BER为BER1，当子序列A中的Y值为Y2时，对应的第一预设BER为BER2，则当测试装置想将第一预设BER设置成BER1时，可以将子序列A中的Y值调整为Y1。
再例如，当子序列A中的Y与(X+Y)的比值为第一比值时，对应的第一预设BER为BER3，当子序列A中的Y与(X+Y)的比值为第二比值时，对应的第一预设BER为BER4，则当测试装置想将第一预设BER设置成BER3时，可以将子序列A中的Y与(X+Y)的比值调整为第一比值。
可选的，本申请实施例中可以根据下述公式3确定第一序列对应的第一预设BER：
第一预设BER＝T*Y/(X+Y)    公式3
其中，X表示一个子序列A中包括的第一FEC码块的数量，T表示第一FEC码块中异常比特的比例，Y表示一个子序列A中包括的第二FEC码块的数量。
一种情况下，本申请实施例可以将第一FEC码块的数据码元序列包括的比特全部设置为正常比特，以及将第二FEC码块的数据码元序列包括的固定数量比特或固定比例比特设置为异常比特。
示例性的，假设第一序列中子序列A中包括963个第一FEC码块，即X值为963，第一FEC码块中的数据码元序列全部为正常比特；子序列A中包括74个第二FEC码块，即Y值为74，第二FEC码块中50％的数据码元序列为异常比特。第一FEC码块与第二FEC码块的数据码元序列长度一致。
此时，将X值为963，Y值为74，T值为50％代入上述公式3，可以得到第一序列对应的第一预设BER为3.5％(T*Y/(X+Y)＝74*50％/(74+963)＝3.5％)。
另一种情况下，本申请实施例可以将第一FEC码块的数据码元序列与冗余码元序列包括的比特全部设置为正常比特，以及将第二FEC码块的数据码元序列与冗余码元序列包括 的固定数量比特或固定比例比特设置为异常比特。
示例性的，假设第一序列中子序列A中包括963个第一FEC码块，即X值为963，第一FEC码块中的数据码元序列与冗余码元序列全部为正常比特；子序列A中包括74个第二FEC码块，即Y值为74，第二FEC码块中的异常比特数量占数据码元序列与冗余码元序列总比特数量的50％。
此时，将X值为963，Y值为74，T值为50％代入上述公式3，可以得到第一序列对应的第一预设BER为3.5％(T*Y/(X+Y)＝74*50％/(74+963)＝3.5％)。
通过上述构造方式3，本申请中在需要调整第一预设BER时，一种方式可以通过调整子序列A中的Y值，灵活构造与第一预设BER相匹配的用于进行功能测试的第一序列，或者本申请中在需要设置新的第一序列时，可以通过调整子序列A中的异Y值，得到新的第一序列；本申请中在需要调整第一预设BER时，另一种方式通过调整子序列A中Y与(X+Y)的比值，灵活构造与第一预设BER相匹配的用于进行功能测试的第一序列，或者本申请中在需要设置新的第一序列时，可以通过调整子序列A中Y与(X+Y)的比值，得到新的第一序列。
进一步的，上述构造方式3中的第二FEC码块还可以称为不可纠错的FEC码块，是指一个与第一FEC码块等长度的序列，在第二FEC码块中错误的码元数量超过了FEC码块可纠错的码元上限。
示例性的，假设以上述RS-FEC(384，354，9)作为一个FEC码块为例，正常情况下，一个RS-FEC码块包括354个数据码元，按照编码规则，会产生对应的30个冗余码元。其中，可以在RS-FEC码块的354个数据码元中挑选15个数量以上的码元，即正常编码规则产生的冗余码元的一半((384-354)/2＝15)，用错误码元代替(即异常比特)，得到新的RS-FEC码块。
此时，无法通过RS-FEC的解码纠错恢复得到354个正确的有效数据码元。例如，将RS-FEC码块中的所有比特都用错误码元代替，其中，通过1表示错误码元，则新的RS-FEC码块为长度为3456(即384*9＝3456)的全1序列，这样就构成一个无法通过解码纠错的错误RS-FEC码块。
需要说明的是，理论上还有很多其他满足上述条件的非全1的序列，本申请实施例在此不进行限定。
其中，为了更好的对本申请提供的通信方法进行介绍，基于图3所示的内容，结合下述两种场景，进一步详细介绍。
其中，下文所涉及的场景中的部分步骤可以是可选的，步骤顺序也不代表实际的执行顺序，因此本申请不限定完全按照下文的步骤和顺序执行。
场景一、第二设备将第一序列以及第二序列一起发送给第一设备。
参阅图8所示，场景一对应的通信方法的可以执行下述步骤。
S800、第二设备向第一设备发送第一序列以及第二序列。
S801、第一设备接收来自第二设备的第一序列以及第二序列。
S802、第一设备统计接收到的第一序列的第一BER。
S803、第一设备确定第一BER是否满足第一预设BER，若是，执行S804，若否，执 行S805。
需要说明的是，本申请实施例中可以是测试人员基于第一设备输出的第一BER，确定第一设备得到的第一BER是否满足第一预设BER；还可以是第一设备将第一BER回传给第二设备，由第二设备确定第一BER是否满足第一预设BER，然后将确定结果通知给第一设备或测试人员的。
本申请实施例中S803中所述的内容，仅作为示例说明，并不构成对本申请实施例的限定。
S804、第一设备统计接收到的第二序列的第二BER。
进一步的，第一设备可以将第二BER进行输出，从而使测试人员根据第二BER确定第一设备是否通过性能测试。
例如，若测试人员确定第二BER不满足第二预设BER，则确定第一设备性能测试不合格；若测试人员确定第二BER满足第二预设BER，则确定第一设备性能测试合格。
S805、第一设备终止后续对接收到的第二序列的测试。
可选的，第一设备在确定第一BER不满足第一预设BER时，可以通过语音提示测试人员自身功能测试不通过。
场景二、当第一BER满足第一预设BER后，触发第二设备向第一设备发送第二序列。
参阅图9所示，场景二对应的通信方法的可以执行下述步骤。
S900、第二设备向第一设备发送第一序列。
S901、第一设备接收来自第二设备的第一序列。
S902、第一设备统计接收到的第一序列的第一BER。
S903、第一设备将第一BER回传给第二设备。
S904、第二设备确定第一BER是否满足第一预设BER，若是，执行S905，若否，执行S906。
需要说明的是，本申请实施例中还可以是测试人员基于第一设备输出的第一BER，确定第一设备得到的第一BER是否满足第一预设BER。
本申请实施例中S903和S904中所述的内容，仅作为示例说明，可以作为可选步骤，并不构成对本申请实施例的限定。例如，当第一设备基于接收到的第一序列统计得出第一BER后，本申请实施例中可以是测试人员基于第一设备输出的第一BER，确定第一设备得到的第一BER是否满足第一预设BER，则此时步骤S903和S904可以省略。
S905、第二设备向第一设备发送第二序列，继续执行S907。
可选的，本申请实施例中可以是测试人员触发第二设备向第一设备发送第二序列。例如，当第一设备基于接收到的第一序列统计得出第一BER后，本申请实施例中可以是测试人员基于第一设备输出的第一BER，确定第一设备得到的第一BER是否满足第一预设BER，以及在确定第一BER满足第一预设BER时，触发第二设备向第一设备发送第二序列。
可选的，本申请实施例中还可以是第二设备自行触发向第一设备发送第二序列。例如，第一设备将第一BER回传给第二设备，由第二设备确定第一BER是否满足第一预设BER，以及第二设备在确定第一BER满足第一预设BER时，触发第二设备向第一设备发送第二序列。此外，本申请实施例中第二设备在确定第一BER满足第一预设BER时，可以通过语音提示测试人员被测试装置(即第一设备)功能测试通过。
S906、第二设备确定终止后续对第二序列的测试。
可选的，本申请实施例中可以是测试人员触发第二设备终止后续对第二序列的测试。例如，当第一设备基于接收到的第一序列统计得出第一BER后，本申请实施例中可以是测试人员基于第一设备输出的第一BER，确定第一设备得到的第一BER是否满足第一预设BER，以及在确定第一BER不满足第一预设BER时，触发第二设备终止后续对第二序列的测试。
可选的，本申请实施例中还可以是第二设备自行触发终止后续对第二序列的测试。例如，第一设备将第一BER回传给第二设备，由第二设备确定第一BER是否满足第一预设BER，以及第二设备在确定第一BER不满足第一预设BER时，触发终止后续对第二序列的测试。
此外，本申请实施例中第二设备在确定第一BER不满足第一预设BER时，可以通过语音提示测试人员被测试装置(即第一设备)功能测试不通过。
S907、第一设备统计接收到的第二序列的第二BER。
进一步的，第一设备可以将第二BER进行输出，从而使测试人员根据第二BER确定第一设备是否通过性能测试。
例如，若测试人员确定第二BER不满足第二预设BER，则确定第一设备性能测试不合格；若测试人员确定第二BER满足第二预设BER，则确定第一设备性能测试合格。
此外，本申请实施例中为了有效保证第一设备得到的测试结果是准确可靠的，在进行第二序列测试之前，可以向第一设备多次发送第一序列进行测试，即对第一设备多次进行功能性测试，其中每次发送的第一序列可以相同也可以不同，具体本申请实施例并不进行限定。
当第一设备在进行所述多次功能测试中，通过功能性测试的次数占功能性测试的总次数的比例(即通过率)满足阈值比例时，则针对第一设备进行第二序列测试，即对第一设备进行性能测试。
例如，假设阈值比例为80％，以及对第一设备进行功能性测试的总次数为10次。其中，第一设备通过功能性测试的次数为9次，通过率为90％，大于该阈值比例80％，此时，可以确认第一设备得到的测试结果是准确可靠的，可以进行后续的性能测试。
进一步的，本申请实施例中在执行上述场景一或者场景二的内容之前，第二设备还可以通过向第一设备发送至少一个训练序列，通过训练序列，与第一设备进行接收链路训练，使第一设备的接收参数收敛。从而使得在后续的测试过程中，测试流程更加顺利，稳定。
其中，方法和装置是基于相同或相似技术构思的，由于方法及装置解决问题的原理相似，因此装置与方法的实施可以相互参见，重复之处不再赘述。
本申请实施例中的术语“装置”和“设备”可被互换使用。本申请实施例的描述中，“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。本申请中所涉及的至少一个是指一个或多个；多个，是指两个或两个以上。
另外，需要理解的是，在本申请的描述中，“第一”、“第二”、“第三”等词汇，仅用于 区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。在本说明书中描述的参考“一个实施例”或“一些实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在一些实施例中”、“在其他一些实施例中”、“在另外一些实施例中”等不是必然都参考相同的实施例，而是意味着“一个或多个但不是所有的实施例”，除非是以其他方式另外特别强调。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
以下结合图10和图11详细说明本申请实施例提供的装置。应理解，装置实施例的描述与方法实施例的描述相互对应。因此，未详细描述的内容可相互参见。
图10是本申请实施例提供的装置1000的示意性框图，用于实现上文方法实施例中第一设备或第二设备的功能。例如，该装置可以为软件模块或芯片系统。所述芯片可以由芯片构成，也可以包括芯片和其他分立器件。该装置1000包括处理单元1001和通信单元1002。通信单元1002用于与其它设备进行通信，还可以称为通信接口、收发单元或输入\输出接口等。
在一些实施例中，上述装置1000可以是第一设备，或者配置于第一设备中的芯片或电路等。处理单元1001可用于执行上文方法实施例中第一设备的处理相关操作，通信单元1002用于指示上文方法实施例中第一设备的收发相关操作，例如，本申请实施例中的通信单元1002可以为接收单元。
例如，通信单元1002，用于接收第二设备发送的第一序列，所述第一序列包括P个子序列A，所述子序列A构成一个或多个前向纠错FEC码块；处理单元1001，用于统计接收的第一序列的第一BER；通信单元1002，用于接收所述第二设备发送的第二序列，所述第二序列包括Q个子序列B，所述子序列B构成一个或多个前向纠错FEC码块；处理单元1001，用于统计接收的第二序列的第二BER；其中，所述第二序列的长度大于或等于所述第一序列的长度，P与Q为正整数。
一种可选的方式，所述处理单元1001，还用于当所述第一BER满足第一预设BER时，统计接收到的所述第二序列的第二BER。
一种可选的方式，所述处理单元1001，具体用于：
统计接收的第一序列中异常比特的数量；或统计接收的第一序列中异常比特的数量与接收的第一序列中总比特数量的比值。
一种可选的方式，所述处理单元1001，具体用于：
统计接收的第二序列中异常比特的数量；或统计接收的第二序列中异常比特的数量与接收的第二序列中总比特数量的比值。
一种可选的方式，所述子序列A包括N个比特；所述子序列A序列中包括M个异常比特；所述M或M与N的比值与所述第一预设BER对应；其中，N与M为正整数，且N大于或等于M。
一种可选的方式，所述N个比特为所述子序列A中的有效序列包括的比特数量；所述M个比特为所述子序列A中的有效序列包括的异常比特数量；或所述N个比特为所述子序列A中的有效序列与冗余序列包括的比特数量；所述M个比特为所述子序列A中的有效序列与冗余序列包括的异常比特数量；其中，所述一个或多个FEC码块中的每一个FEC 码块包括数据码元序列和冗余码元序列，所述子序列A中的有效序列包括所述一个或多个FEC码块的数据码元序列，所述子序列A中的冗余序列包括所述一个或多个FEC码块的冗余码元序列。
一种可选的方式，所述子序列A包括X个第一FEC码块和Y个第二FEC码块；所述第一FEC码块的数据码元序列包括的比特全部为正常比特；所述第二FEC码块的数据码元序列包括固定数量的异常比特或固定比例的异常比特；所述Y或Y与(X+Y)的比值与所述第一预设BER对应；其中，X与Y为正整数。
一种可选的方式，所述第二FEC码块的数据码元序列包括的比特全部为异常比特。
一种可选的方式，所述第一FEC码块的冗余码元序列包括的比特全部为正常比特；所述第二FEC码块的冗余码元序列包括的比特也全部为异常比特。
一种可选的方式，所述子序列A的长度与所述子序列B的长度相等。
一种可选的方式，当正常比特值为0时，1为异常比特值；或当正常比特值为1时，0为异常比特值。
一种可选的方式，所述第一FEC码块包括的比特可以全部为0，所述第二FEC码块中固定数量或固定比例的异常比特全部为1，剩余比特全部为0。
一种可选的方式，当正常比特值为0时，所述子序列B中所有FEC码块的数据码元序列包括的比特全部为0；或当正常比特值为1时，所述子序列B中所有FEC码块的数据码元序列包括的比特全部为1。
一种可选的方式，所述向第一设备发送第一序列之前，所述处理单元1001还用于与第一设备进行链路训练。
在另一些实施例中，上述装置1000可以是第二设备，或者配置于第二设备中的芯片或电路等。处理单元1001可用于执行上文方法实施例中第二设备的处理相关操作，通信单元1002可用于执行上文方法实施例中第二设备的收发相关操作，例如，本申请实施例中的通信单元1002可以为发送单元。
例如，通信单元1002，用于向第一设备发送第一序列，所述第一序列用于所述第一设备统计第一误比特率BER，所述第一序列包括P个子序列A，所述子序列A构成一个或多个前向纠错FEC码块；向所述第一设备发送第二序列，所述第二序列用于所述第一设备统计第二BER，所述第二序列包括Q个子序列B，所述子序列B构成一个或多个前向纠错FEC码块；其中，所述第二序列的长度大于或等于所述第一序列的长度，P与Q为正整数。
一种可选的方式，所述第一BER是通过记录所述第一序列中异常比特的数量得到的；所述第二BER是通过记录所述第二序列中异常比特的数量得到的。
一种可选的方式，所述通信单元1002，具体用于当所述第一BER满足第一预设BER时，向所述第一设备发送第二序列。
一种可选的方式，所述子序列A包括N个比特；所述子序列A序列中包括M个异常比特；所述M或M与N的比值与所述第一预设BER对应；其中，N与M为正整数，且N大于或等于M。
一种可选的方式，所述N个比特为所述子序列A中的有效序列包括的比特数量；所述M个比特为所述子序列A中的有效序列包括的异常比特数量；或所述N个比特为所述子序列A中的有效序列与冗余序列包括的比特数量；所述M个比特为所述子序列A中的有 效序列与冗余序列包括的异常比特数量；其中，所述一个或多个FEC码块中的每一个FEC码块包括数据码元序列和冗余码元序列，所述子序列A中的有效序列包括所述一个或多个FEC码块的数据码元序列，所述子序列A中的冗余序列包括所述一个或多个FEC码块的冗余码元序列。
一种可选的方式，所述子序列A包括X个第一FEC码块和Y个第二FEC码块；所述第一FEC码块的数据码元序列包括的比特全部为正常比特；所述第二FEC码块的数据码元序列包括固定数量的异常比特或固定比例的异常比特；所述Y或Y与(X+Y)的比值与所述第一预设BER对应；其中，X与Y为正整数。
一种可选的方式所述第二FEC码块的数据码元序列包括的比特全部为异常比特。
一种可选的方式，所述第一FEC码块的冗余码元序列包括的比特全部为正常比特；所述第二FEC码块的冗余码元序列包括的比特也全部为异常比特。
一种可选的方式，所述子序列A的长度与所述子序列B的长度相等。
一种可选的方式，当正常比特值为0时，1为异常比特值；或当正常比特值为1时，0为异常比特值。
一种可选的方式，所述第一FEC码块包括的比特可以全部为0，所述第二FEC码块中固定数量或固定比例的异常比特全部为1，剩余比特全部为0。
一种可选的方式，当正常比特值为0时，所述子序列B中所有FEC码块包括的比特全部为0；或当正常比特值为1时，所述子序列B中所有FEC码块的数据码元序列包括的比特全部为1。
一种可选的方式，所述向第一设备发送第一序列之前，所述处理单元1001还用于与第一设备进行链路训练。
本申请实施例中对单元的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。另外，在本申请实施例中各功能单元可以集成在一个处理器中，也可以是单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
请参见图11，图11为本申请实施例提供的装置1100的示意图，该装置1100可以为电子装置，或者电子装置中的一部件，例如芯片或集成电路等。该装置1100可包括至少一个处理器1102和通信接口1104。进一步，可选的，所述装置还可以包括至少一个存储器1101。更进一步，可选的，还可以包含总线1103。其中，存储器1101、处理器1102和通信接口1104通过总线1103相连。
其中，存储器1101用于提供存储空间，存储空间中可以存储操作系统和计算机程序等数据。本申请实施例中提及的存储器1101可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(dynamic RAM，DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存 取存储器(double data rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM，DR RAM)。
应注意，本文描述的存储器旨在包括但不限于这些和任意其它适合类型的存储器。处理器1102是进行算术运算和/或逻辑运算的模块，具体可以是中央处理器(central processing unit，CPU)、图片处理器(graphics processing unit，GPU)、微处理器(microprocessor unit，MPU)、专用集成电路(application specific integrated circuit，ASIC)、现场可编程逻辑门阵列(field programmable gate array，FPGA)、复杂可编程逻辑器件(complex programmable logic device，CPLD)、协处理器(协助中央处理器完成相应处理和应用)、微控制单元(microcontroller unit，MCU)等处理模块中的一种或者多种的组合。
需要说明的是，当处理器为通用处理器、ASIC、FPGA或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件时，存储器(存储模块)可以集成在处理器中。
通信接口1104可以用于为所述至少一个处理器提供信息输入或者输出。和/或所述通信接口可以用于接收外部发送的数据和/或向外部发送数据，可以为包括诸如以太网电缆等的有线链路接口，也可以是无线链路(Wi-Fi、蓝牙、通用无线传输、车载短距通信技术等)接口。可选的，通信接口1104还可以包括与接口耦合的发射器(如射频发射器、天线等)，或者接收器等。
在一些实施例中，上述装置1100可以为上文方法实施例中的第一设备或者第一设备中的部件，例如芯片或者集成电路。该装置1100中的处理器1102用于读取所述存储器1101中存储的计算机程序，控制所述第一设备执行以下操作：
向第一设备发送第一序列，所述第一序列用于所述第一设备统计第一BER，所述第一序列包括P个子序列A，所述子序列A构成一个或多个前向纠错FEC码块；向所述第一设备发送第二序列，所述第二序列用于所述第一设备统计第二BER，所述第二序列包括Q个子序列B，所述子序列B构成一个或多个前向纠错FEC码块；其中，所述第二序列的长度大于或等于所述第一序列的长度，P与Q为正整数。
可选的，该第一设备中的处理器1102，还可以用于读取存储器1101中的程序并执行如图3所示的S300～S305中测试装置执行的方法流程；或者，还可以用于读取存储器1101中的程序并执行如图8所示的S800～S805中测试装置执行的方法流程；或者，还可以用于读取存储器1101中的程序并执行如图9所示的S900～S907中测试装置执行的方法流程。
关于具体细节，可参见上文方法实施例中的记载，在此不再赘述。
在另一些实施例中，上述装置1100可以为上文方法实施例中的第二设备或者第二设备中的部件，例如芯片或者集成电路。该装置1100中的处理器1102用于读取所述存储器1101中存储的计算机程序，控制所述第二设备执行以下操作：
接收第二设备发送的第一序列，所述第一序列包括P个子序列A，所述子序列A构成一个或多个前向纠错FEC码块；统计接收的第一序列的第一误比特率BER；接收所述第二设备发送的第二序列，所述第二序列包括Q个子序列B，所述子序列B构成一个或多个前向纠错FEC码块；统计接收的第二序列的第二BER；其中，所述第二序列的长度大于或等于所述第一序列的长度，P与Q为正整数。
可选的，该第二设备中的处理器1102，还可以用于读取存储器1101中的程序并执行 如图3所示的S300～S305中该被测试装置执行的方法流程；或者，还可以用于读取存储器1101中的程序并执行如图8所示的S800～S805中被测试装置执行的方法流程；或者，还可以用于读取存储器1101中的程序并执行如图9所示的S900～S907中被测试装置执行的方法流程。
关于具体细节，可参见上文方法实施例中的记载，在此不再赘述。
本申请实施例还提供一种计算机可读存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)，包括指令，当其在计算机上运行时，使得计算机执行上文实施例所描述的方法。
本申请实施例还提供一种芯片系统，该芯片系统包括至少一个处理器和接口电路。进一步可选的，所述芯片系统还可以包括存储器或者外接存储器。所述处理器用于通过所述接口电路执行指令和/或数据的交互，以实现上文方法实施例中的方法。该芯片系统可以由芯片构成，也可以包含芯片和其他分立器件。
本申请实施例还提供一种计算机程序产品，包括指令，当其在计算机上运行时，使得计算机执行上文实施例所描述的方法。
本申请实施例提供的方法中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (31)

  1. 一种通信方法，其特征在于，包括：
    向第一设备发送第一序列，所述第一序列用于所述第一设备统计第一误比特率BER，所述第一序列包括P个子序列A，所述子序列A构成一个或多个前向纠错FEC码块；
    向所述第一设备发送第二序列，所述第二序列用于所述第一设备统计第二BER，所述第二序列包括Q个子序列B，所述子序列B构成一个或多个前向纠错FEC码块；
    其中，所述第二序列的长度大于或等于所述第一序列的长度，P与Q为正整数。
  2. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    当所述第一BER满足第一预设BER时，向所述第一设备发送所述第二序列。
  3. 根据权利要求1或2所述的方法，其特征在于，
    所述子序列A包括N个比特；
    所述子序列A中包括M个异常比特；
    所述M或M与N的比值与所述第一预设BER对应；
    其中，N与M为正整数，且N大于或等于M。
  4. 根据权利要求3所述的方法，其特征在于，所述N个比特为所述子序列A中的有效序列包括的比特数量；所述M个比特为所述子序列A中的有效序列包括的异常比特数量；或
    所述N个比特为所述子序列A中的有效序列与冗余序列包括的比特数量；所述M个比特为所述子序列A中的有效序列与冗余序列包括的异常比特数量；
    其中，所述一个或多个FEC码块中的每一个FEC码块包括数据码元序列和冗余码元序列，所述子序列A中的有效序列包括所述一个或多个FEC码块的数据码元序列，所述子序列A中的冗余序列包括所述一个或多个FEC码块的冗余码元序列。
  5. 根据权利要求1或2所述的方法，其特征在于，所述子序列A包括X个第一FEC码块和Y个第二FEC码块；
    所述第一FEC码块的数据码元序列包括的比特全部为正常比特；
    所述第二FEC码块的数据码元序列包括固定数量的异常比特或固定比例的异常比特；
    所述Y或Y与(X+Y)的比值与所述第一预设BER对应；
    其中，X与Y为正整数。
  6. 根据权利要求5所述的方法，其特征在于，所述第二FEC码块的数据码元序列包括的比特全部为异常比特。
  7. 根据权利要求6所述的方法，其特征在于，所述第一FEC码块的冗余码元序列包括的比特全部为正常比特；所述第二FEC码块的冗余码元序列包括的比特全部为异常比特。
  8. 根据权利要求1～7任一项所述的方法，其特征在于，所述子序列A的长度与所述子序列B的长度相等。
  9. 根据权利要求1～8任一项所述的方法，其特征在于，所述方法还包括：
    当正常比特值为0时，1为异常比特值；或
    当正常比特值为1时，0为异常比特值。
  10. 根据权利要求9所述的方法，其特征在于，当正常比特值为0时，所述方法还包括：
    所述第一FEC码块包括的比特全部为0，所述第二FEC码块中固定数量或固定比例的 异常比特全部为1，剩余比特全部为0。
  11. 根据权利要求9所述的方法，其特征在于，当正常比特值为0时，所述子序列B中所有FEC码块的数据码元序列包括的比特全部为0；或
    当正常比特值为1时，所述子序列B中所有FEC码块的数据码元序列包括的比特全部为1。
  12. 根据权利要求1～11任一项所述的方法，其特征在于，所述向第一设备发送第一序列之前，还包括：
    与所述第一设备进行链路训练。
  13. 一种通信方法，其特征在于，包括：
    接收第二设备发送的第一序列，所述第一序列包括P个子序列A，所述子序列A构成一个或多个前向纠错FEC码块；
    统计接收的第一序列的第一误比特率BER；
    接收所述第二设备发送的第二序列，所述第二序列包括Q个子序列B，所述子序列B构成一个或多个前向纠错FEC码块；
    统计接收的第二序列的第二BER；
    其中，所述第二序列的长度大于或等于所述第一序列的长度，P与Q为正整数。
  14. 根据权利要求13所述的方法，其特征在于，所述方法还包括：
    当所述第一BER满足第一预设BER时，统计接收的第二序列的第二BER。
  15. 根据权利要求13或14所述的方法，其特征在于，
    所述子序列A包括N个比特；
    所述子序列A序列中包括M个异常比特；
    所述M或M/N与所述第一预设BER对应；
    其中，N与M为正整数，且N大于或等于M。
  16. 根据权利要求15所述的方法，其特征在于，所述N个比特为所述子序列A中的有效序列包括的比特数量；所述M个比特为所述子序列A中的有效序列包括的异常比特数量；或
    所述N个比特为所述子序列A中的有效序列与冗余序列包括的比特数量；所述M个比特为所述子序列A中的有效序列与冗余序列包括的异常比特数量；
    其中，所述一个或多个FEC码块中的每一个FEC码块包括数据码元序列和冗余码元序列，所述子序列A中的有效序列包括所述一个或多个FEC码块的数据码元序列，所述子序列A中的冗余序列包括所述一个或多个FEC码块的冗余码元序列。
  17. 根据权利要求13或14所述的方法，其特征在于，所述子序列A包括X个第一FEC码块和Y个第二FEC码块；
    所述第一FEC码块的数据码元序列包括的比特全部为正常比特；
    所述第二FEC码块的数据码元序列包括固定数量的异常比特或固定比例的异常比特；
    所述Y或Y与(X+Y)的比值与所述第一预设BER对应；
    其中，X与Y为正整数。
  18. 根据权利要求17所述的方法，其特征在于，所述第二FEC码块的数据码元序列包括的比特全部为异常比特。
  19. 根据权利要求18所述的方法，其特征在于，所述第一FEC码块的冗余码元序列包括的比特全部为正常比特；所述第二FEC码块的冗余码元序列包括的比特全部为异常比特。
  20. 根据权利要求13～19任一项所述的方法，其特征在于，所述子序列A的长度与所述子序列B的长度相等。
  21. 根据权利要求13～20任一项所述的方法，其特征在于，所述方法还包括：
    当正常比特值为0时，1为异常比特值；或
    当正常比特值为1时，0为异常比特值。
  22. 根据权利要求21所述的方法，其特征在于，当正常比特值为0时，所述方法还包括：
    所述第一FEC码块包括的比特全部为0，所述第二FEC码块中固定数量或固定比例的异常比特全部为1，剩余比特全部为0。
  23. 根据权利要求21所述的方法，其特征在于，当正常比特值为0时，所述子序列B中所有FEC码块包括的比特全部为0；或
    当正常比特值为1时，所述子序列B中所有FEC码块的数据码元序列包括的比特全部为1。
  24. 根据权利要求13-23任一项所述的方法，其特征在于，所述统计接收的第一序列的第一误比特率BER，包括：
    统计接收的第一序列中异常比特的数量；或
    统计接收的第一序列中异常比特的数量与接收的第一序列中总比特数量的比值；
    所述统计接收的第二序列的第二BER，包括：
    统计接收的第二序列中异常比特的数量；或
    统计接收的第二序列中异常比特的数量与接收的第二序列中总比特数量的比值。
  25. 根据权利要求13～24任一项所述的方法，其特征在于，所述接收第二设备发送的第一序列之前，还包括：
    与所述第二设备进行链路训练。
  26. 一种测试装置，其特征在于，包括：
    收发模块，用于向第一设备发送第一序列，所述第一序列用于所述第一设备统计第一误比特率BER，所述第一序列包括P个子序列A，所述子序列A构成一个或多个前向纠错FEC码块；向所述第一设备发送第二序列，所述第二序列用于所述第一设备统计第二BER，所述第二序列包括Q个子序列B，所述子序列B构成一个或多个前向纠错FEC码块；其中，所述第二序列的长度大于或等于所述第一序列的长度，P与Q为正整数。
  27. 一种测试装置，其特征在于，包括：
    收发模块，用于接收第二设备发送的第一序列，统计所述第一序列的第一误比特率BER，所述第一序列包括P个子序列A，所述子序列A构成一个或多个前向纠错FEC码块；接收所述第二设备发送的第二序列，统计所述第二序列的第二BER，所述第二序列包括Q个子序列B，所述子序列B构成一个或多个前向纠错FEC码块；其中，所述第二序列的长度大于或等于所述第一序列的长度，P与Q为正整数。
  28. 一种测试装置，其特征在于，包括：
    一个或多个处理器；
    存储器，用于存储一个或多个程序；
    当所述一个或多个程序被所述一个或多个处理器执行时，实现如权利要求1～12中任一项所述的方法。
  29. 一种测试装置，其特征在于，包括：
    一个或多个处理器；
    存储器，用于存储一个或多个程序；
    当所述一个或多个程序被所述一个或多个处理器执行时，实现如权利要求13～25中任一项所述的方法。
  30. 一种测试芯片，其特征在于，包括：处理器和通信接口，所述处理器用于从所述通信接口调用并运行指令，当所述处理器执行所述指令时，
    实现如权利要求1～12中任一项所述的方法；或实现如权利要求13～25中任一项所述的方法。
  31. 一种计算机可读存储介质，其特征在于，其上存有计算机程序，所述计算机程序被执行时，实现如权利要求1～12中任一项所述的方法；或实现如权利要求13～25中任一项所述的方法。
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