WO2023087200A1 - 一种信号处理装置及通信设备 - Google Patents

一种信号处理装置及通信设备 Download PDF

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Publication number
WO2023087200A1
WO2023087200A1 PCT/CN2021/131414 CN2021131414W WO2023087200A1 WO 2023087200 A1 WO2023087200 A1 WO 2023087200A1 CN 2021131414 W CN2021131414 W CN 2021131414W WO 2023087200 A1 WO2023087200 A1 WO 2023087200A1
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Prior art keywords
circuit
signal
coupled
filter
output
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PCT/CN2021/131414
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English (en)
French (fr)
Inventor
罗宇平
魏宏亮
李晶
唐海正
肖宇翔
鲁哨廷
王光伟
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华为技术有限公司
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Priority to PCT/CN2021/131414 priority Critical patent/WO2023087200A1/zh
Publication of WO2023087200A1 publication Critical patent/WO2023087200A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion

Definitions

  • the present application relates to the technical field of communication, and in particular to a signal processing device and communication equipment.
  • a useful signal ie, a service signal
  • a useful signal passes through a nonlinear system
  • nonlinear distortion will occur.
  • the useful signal is amplified by a power amplifier (power amplifier, PA)
  • PA power amplifier
  • feed-forward cancellation technology is usually used to cancel the nonlinear distortion components in the output signal of the nonlinear system.
  • the processing accuracy of the existing feedforward cancellation technology is low, resulting in poor cancellation effect of nonlinear distortion components, which further leads to poor performance of the communication system.
  • the present application provides a signal processing device and communication equipment, which are used to improve the cancellation accuracy of nonlinear distortion signals.
  • a signal processing device including: a first branching module, a time delay, a first combining module, and a filter circuit.
  • the first branching module can be a coupler, a splitter and other devices, and the following will introduce the first branching module as the first coupler as an example;
  • the first combining module can be a coupler, a combiner and other devices , the following takes the first combining module as the second coupler as an example for introduction.
  • the signal processing device includes: a first coupler, a second coupler, a time delay and a filter circuit; the first coupler is coupled with the signal source of the signal processing device, and the output terminals of the first coupler are respectively connected to the time
  • the input end of the delayer is coupled to the input end of the filter circuit; the output end of the delayer is coupled to the first input end of the second coupler; the output end of the filter circuit is coupled to the second input end of the second coupler;
  • the filter circuit It includes a plurality of filtering subcircuits and an accumulation circuit, and the output terminals of the plurality of filtering subcircuits are coupled with the input terminals of the accumulation circuit.
  • the first coupler is used to output the first sub-signal and the second sub-signal according to the input signal of the first coupler, and the power of the first sub-signal can be greater than the power of the second sub-signal;
  • the time delayer is used to delay the second sub-signal
  • a sub-signal is used to output a delayed signal;
  • the filter circuit includes a plurality of filter sub-circuits and an accumulation circuit; wherein, the plurality of filter sub-circuits are respectively used to sample the second sub-signal at different sampling times, and sample the obtained samples
  • the signal is filtered to output a sample filter signal, that is, multiple filter sub-circuits can be used to adjust the amplitude of the second sub-signal at different phases;
  • the accumulation circuit is used to accumulate the samples output by the multiple filter sub-circuits Filter the signal to obtain the intermodulation cancellation signal;
  • the second coupler is used to output the target signal according to the intermodulation cancellation signal and the delay signal, such as subtracting the
  • the device realizes the equalization processing of the second sub-signal through a filter circuit
  • the filter circuit includes a plurality of filter sub-circuits and an accumulation circuit
  • the plurality of filter sub-circuits and accumulation circuits can analyze the second sub-signal in the analog signal domain.
  • High-precision amplitude adjustment is performed on different phases, so that the equalization processing of the intermodulation signal can be realized under the condition that the time delay device provides a very small amount of delay, thereby reducing the processing time delay and improving the processing accuracy.
  • the device further includes: a second combining module, and the following description is made by taking the second combining module as a third coupler as an example.
  • the first input end of the third coupler is coupled to the output end of the first coupler, the second input end of the third coupler is coupled to the signal source, and the output end of the third coupler is coupled to the input end of the filter circuit.
  • the third coupler is used to couple the first intermodulation signal from the second sub-signal.
  • the third coupler can be replaced by an equalizer, and outputs the first intermodulation signal.
  • the above-mentioned plurality of filtering sub-circuits are respectively used to sample the first intermodulation signal in the second sub-signal at different sampling times, and filter the sampled signal to output the sampled filtered signal, that is, a plurality of The filtering sub-circuits can be used to adjust the amplitudes of the first intermodulation signal at different phases respectively.
  • the first intermodulation signal in the second sub-signal can be extracted, so that the filter circuit can perform high-precision filtering on the first intermodulation signal
  • the amplitude and phase adjustment can reduce the component of the service signal in the intermodulation cancellation signal output by the filter circuit, reduce the adverse effect of the intermodulation cancellation signal on the useful signal component in the delayed signal, and further improve the cancellation performance of the intermodulation signal.
  • the filter circuit and the first intermodulation signal processed by the filter sub-circuit are replaced by the second sub-signal.
  • each of the plurality of filtering subcircuits includes: a sampling and holding circuit and an amplitude adjustment circuit, and the output terminal of the sampling and holding circuit is connected to the first An input terminal is coupled; a sample-and-hold circuit is used to sample and hold the first intermodulation signal at the sampling moment to output a sample signal; an amplitude adjustment circuit is used to filter the sample signal to output a sample-filtered signal Signal.
  • the above possible implementation manner can enable the plurality of filtering sub-circuits to adjust the amplitudes of the first intermodulation signal at different phases respectively, so as to ensure high processing precision in the equalization processing of the intermodulation signal.
  • the sample-and-hold circuit includes a switch, a capacitor, and a buffer
  • the amplitude adjustment circuit includes a multiplier; wherein, the first end of the switch is an input end of the filtering subcircuit , the second end of the switch, the first end of the capacitor and the first end of the buffer are coupled, the second end of the capacitor is grounded, the second end of the buffer is coupled to the first input end of the multiplier, The second input end of the multiplier is used to receive filter coefficients, and the output end of the multiplier is used to output the sampling filter signal.
  • the sample-hold circuit and the amplitude adjustment circuit are simple, effective, and low in cost, and the first intermodulation signal is sampled and held and filtered by the sample-hold circuit and the amplitude adjustment circuit During the processing, the high-precision amplitude and phase adjustment of the first intermodulation signal of the intermodulation signal can be realized with a very small amount of delay, thereby reducing the processing time delay and improving the processing accuracy.
  • the amplitude adjustment circuit further includes: a transconductance amplifier coupled to the output terminal of the multiplier; the transconductance amplifier is configured to amplify the sampled filtered signal.
  • the filter circuit further includes: a variable gain amplifier coupled to the output terminal of the accumulation circuit.
  • the device further includes: an attenuator, the attenuator is coupled between the first coupler and the third coupler, and the attenuator is used to attenuate the second sub-signal, so that the amplitude of the second sub-signal matches the amplitude of the service signal input to the third coupler.
  • the first input end of the third coupler is coupled to the output end of the filter circuit
  • the second input end of the third coupler is coupled to the signal source
  • the third coupler's The output terminal is coupled with the second coupler.
  • the device further includes an amplifier coupled between the signal source and the third coupler.
  • the device further includes: a post-distortion circuit coupled to the third coupler and the signal source; the post-distortion circuit is used for the signal output by the signal source (which can be understood as the first Injecting the second intermodulation signal into a service signal) to obtain the second service signal, the second service signal and the second sub-signal are used to couple the first intermodulation signal, and the frequency point of the second intermodulation signal is the same as that of the first intermodulation signal The frequency points of the signals are different.
  • the difference between the frequency point of the second intermodulation signal and the frequency point of the first service signal is greater than a preset threshold.
  • the post-distortion circuit injects the second intermodulation signal into the first service signal to obtain the second service signal, so that the third coupler uses the second service signal to couple the first Intermodulation signals, so as to ensure that the coupled first intermodulation signal is an intermodulation signal within a certain frequency range, thereby reducing the complexity of the filter circuit for processing the first intermodulation signal, and at the same time reducing costs.
  • the device further includes: a predistortion circuit, configured to inject a third intermodulation signal into the first service signal, the frequency point of the third intermodulation signal is the same as that of the first service signal The difference between the frequency points is smaller than the first threshold, the third intermodulation signal may be called a near-end intermodulation signal, and the third intermodulation signal is used to reduce the first intermodulation signal in the input signal of the first coupler.
  • a predistortion circuit configured to inject a third intermodulation signal into the first service signal, the frequency point of the third intermodulation signal is the same as that of the first service signal The difference between the frequency points is smaller than the first threshold, the third intermodulation signal may be called a near-end intermodulation signal, and the third intermodulation signal is used to reduce the first intermodulation signal in the input signal of the first coupler.
  • the device further includes: a filter coefficient calculation circuit, the output terminal of the filter coefficient calculation circuit is coupled to the second input terminal of the amplitude adjustment circuit; the filter coefficient calculation circuit, It is used for outputting a plurality of filter coefficients according to the first intermodulation signal and the target signal, and the plurality of filter coefficients are filter coefficients of the plurality of filter subcircuits.
  • the filter coefficient calculation circuit includes: a second branching module and a calculation circuit.
  • the filter calculation circuit includes: a fourth coupler and a calculation circuit; the input end of the fourth coupler is coupled to the output end of the second coupler, and the fourth coupler The first output terminal is coupled to the first input terminal of the calculation circuit, and the second input terminal of the calculation circuit is used for receiving the first intermodulation signal.
  • the filter coefficient calculation circuit is used to output multiple filter coefficients of the multiple filter sub-circuits according to the first intermodulation signal and the target signal, so as to filter the first intermodulation signal according to the multiple filter coefficients During processing, the processing precision of the filter circuit can be improved.
  • the filter coefficient calculation circuit further includes: a first switch circuit and a second switch circuit coupled between the fourth coupler and the calculation circuit, and the first switch circuit and the second switch circuit are coupled between the fourth coupler and the calculation circuit.
  • the second switch circuit is used to turn off or turn on the connection between the fourth coupler and the calculation circuit.
  • the hardware link between the first switch circuit and the second switch circuit can realize time division multiplexing, that is, multiple fourth The couplers share a calculation circuit to improve the utilization rate of the hardware link and reduce the cost.
  • the device further includes: a parameter calibration circuit coupled to the filter circuit; the parameter calibration circuit is configured to determine the A mismatch parameter of the filter circuit, where the mismatch parameter is used to calibrate the filter circuit.
  • the mismatch parameter includes at least one of the following: a sampling moment mismatch value, a gain mismatch value, and a DC mismatch value.
  • the parameter calibration circuit is used to calibrate the filter circuit according to the mismatch parameters output by the first intermodulation signal and the intermodulation cancellation signal, which can avoid multiple filter sub-circuits in the filter circuit due to manufacturing differences of the device itself. The resulting difference in filtering efficiency improves the processing accuracy of the filtering circuit.
  • the filter circuit and at least one of the following items are integrated into one chip: the filter coefficient calculation circuit, the parameter calibration circuit, and the post-distortion circuit.
  • the filter coefficient calculation circuit the parameter calibration circuit
  • the post-distortion circuit the post-distortion circuit
  • the device further includes: a power amplifier coupled between the input terminal of the first coupler and the signal source, and a duplexer coupled to the output terminal of the second coupler ; the power amplifier is used to output the input signal of the first coupler; the duplexer is used to receive the target signal and perform transmit filter processing on the target signal.
  • the impact of the target signal on the signal received in the duplexer when passing through the duplexer can be avoided.
  • a chip in a second aspect, includes: a filter circuit; the filter circuit includes: a plurality of filter sub-circuits and an accumulation circuit; The modulated signal is sampled, and the sampled signal is filtered to output a sampled filter signal; the accumulation circuit is used to accumulate the sampled filter signal output by the plurality of filter sub-circuits to obtain an intermodulation cancellation signal.
  • each of the plurality of filtering subcircuits includes: a sample and hold circuit, configured to sample and hold the first intermodulation signal at the sampling moment, to Outputting the sampling signal; the amplitude adjustment circuit is used for filtering the sampling signal to output the sampling filtered signal.
  • the sample-and-hold circuit includes a switch, a capacitor, and a buffer
  • the amplitude adjustment circuit includes a multiplier; wherein, the first end of the switch is an input end of the filtering subcircuit , the second end of the switch, the first end of the capacitor and the first end of the buffer are coupled, the second end of the capacitor is grounded, the second end of the buffer is coupled to the first input end of the multiplier, The second input end of the multiplier is used to receive filter coefficients, and the output end of the multiplier is used to output the sampling filter signal.
  • the amplitude adjustment circuit further includes: a transconductance amplifier coupled to the output terminal of the multiplier; the transconductance amplifier is configured to amplify the sampled filtered signal.
  • the filter circuit further includes: a gain amplifier coupled to the output end of the accumulation circuit.
  • the chip further includes: a post-distortion circuit; the post-distortion circuit is configured to inject a second intermodulation signal into the first service signal to obtain a second service signal, and the second The service signal and the second transmission sub-signal are used to output the first intermodulation signal, and the frequency point of the second intermodulation signal is different from that of the first intermodulation signal.
  • the difference between the frequency point of the second intermodulation signal and the frequency point of the first service signal is greater than a preset threshold.
  • the chip further includes: a filter coefficient calculation circuit; the filter coefficient calculation circuit is configured to output a plurality of filter coefficients according to the first intermodulation signal and the target signal, and the plurality of filter coefficients The coefficients are filter coefficients of the plurality of filter subcircuits.
  • the chip further includes: a parameter calibration circuit coupled to the filter circuit; the parameter calibration circuit is configured to determine the A mismatch parameter of the filter circuit, where the mismatch parameter is used to calibrate the filter circuit.
  • the mismatch parameter includes at least one of the following: a sampling time mismatch value, a gain mismatch value, and a DC mismatch value.
  • a filter coefficient calculation circuit is provided, which is applied to the signal processing device provided in the first aspect; wherein, the first input end of the filter coefficient calculation circuit is coupled to the output end of the second coupler, and the filter coefficient
  • the second input terminal of the calculation circuit is used to receive the first intermodulation signal, which is the input signal of the filter circuit, and the output terminal of the filter coefficient calculation circuit is used to output the filter coefficient of the filter circuit.
  • the filter coefficient calculation circuit includes: a third coupler and a calculation circuit; wherein, the input terminal of the third coupler is coupled to the output terminal of the second coupler, and the third coupling The first output end of the filter is coupled to the first input end of the calculation circuit, the second input end of the calculation circuit is used to receive the first intermodulation signal, and the output end of the calculation circuit is used to output the filter coefficient of the filter circuit.
  • the filter coefficient calculation circuit further includes: a first switch circuit and a second switch circuit coupled between the third coupler and the calculation circuit, the first switch circuit and the second switch circuit The second switch circuit is used to turn off or turn on the connection between the third coupler and the calculation circuit.
  • the hardware link between the first switch circuit and the second switch circuit can realize time division multiplexing, that is, the hardware link is realized by turning off and on the first switch circuit and the second switch circuit switching to improve the utilization of the hardware link and reduce costs.
  • a communication device in a fourth aspect, includes a baseband circuit, and the signal processing apparatus provided in the first aspect or any possible implementation manner of the first aspect.
  • any chip, filter coefficient calculation circuit and communication device provided above all include at least part of the content of the signal processing device provided above. Therefore, the beneficial effects that it can achieve can refer to the above provided The beneficial effects in the signal processing device are not repeated here.
  • FIG. 1 is a schematic structural diagram of a wireless communication device provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a feed-forward cancellation system provided in an embodiment of the present application
  • 3a-3d are schematic structural diagrams of a signal processing device provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a filter circuit provided in an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another filter circuit provided in an embodiment of the present application.
  • FIG. 6 is a working timing diagram of a filtering circuit provided in an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of another signal processing device provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another signal processing device provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of another signal processing device provided by an embodiment of the present application.
  • At least one means one or more, and “multiple” means two or more.
  • “And/or” describes the association relationship of associated objects, indicating that there may be three types of relationships, for example, A and/or B, which can mean: A exists alone, A and B exist at the same time, and B exists alone, where A, B can be singular or plural.
  • the character “/” generally indicates that the contextual objects are an “or” relationship.
  • “At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items.
  • At least one (unit) of a, b or c can represent: a, b, c, a and b, a and c, b and c or a, b and c, wherein a, b and c can be It can be single or multiple.
  • Coupled is used to indicate an electrical connection, including direct connection through wires or terminals or indirect connection through other devices. "Coupling” should therefore be viewed as an electronic communication connection in a broad sense.
  • FIG. 1 is a schematic structural diagram of a wireless communication device provided by an embodiment of the present application.
  • the wireless communication device can be deployed on land, including indoors or outdoors, hand-held or vehicle-mounted.
  • the wireless communication device can also be deployed on water (such as ships, etc.).
  • the wireless communication device can also be deployed in the air (eg, on aircraft, balloons, satellites, etc.).
  • the wireless communication device may be a terminal or a base station.
  • the terminal includes but is not limited to: mobile phone (mobile phone), tablet computer, notebook computer, palmtop computer, mobile internet device (mobile internet device, MID), wearable device (such as smart watch, smart bracelet, pedometer etc.), vehicle-mounted equipment (such as automobiles, bicycles, electric vehicles, airplanes, ships, trains, high-speed rail, etc.), virtual reality (virtual reality, VR) equipment, augmented reality (augmented reality, AR) equipment, industrial control (industrial control ), wireless terminals in smart home equipment (such as refrigerators, TVs, air conditioners, electric meters, etc.), intelligent robots, workshop equipment, wireless terminals in self-driving (self-driving), and remote medical surgery (remote medical surgery) Wireless terminals, wireless terminals in smart grid, wireless terminals in transportation safety, wireless terminals in smart city, or wireless terminals in smart home, flight equipment (eg, intelligent robots, hot air balloons, drones, airplanes), etc.
  • the structure of the wireless communication device will be described in detail below with reference to FIG. 1 .
  • the wireless communication device shown in FIG. 1 includes: a baseband circuit, a radio frequency (radio frequency, RF) circuit, and an antenna (antenna) coupled in sequence.
  • a baseband circuit a radio frequency (radio frequency, RF) circuit
  • an antenna antenna
  • the baseband circuit has a baseband processing function and can be used for processing baseband signals.
  • the radio frequency circuit can be used to provide functions such as power amplification or filtering.
  • the radio frequency circuit can be used to perform power amplification or filtering on the baseband signal to convert the baseband signal into a radio frequency signal.
  • Antennas can be used to receive or send radio frequency signals, that is, to realize energy conversion between radio frequency signals and electromagnetic waves.
  • the foregoing radio frequency circuit may include one or more transmit (transmit, Tx) channels and one or more receive (receive, Rx) channels.
  • Each transmit channel includes a power amplifier (power amplifier, PA).
  • the transmit channel may also include a transmit filter (Tx filter), which may be an isolator.
  • Each receive channel includes a low noise amplifier (LNA).
  • the receiving channel may further include a receiving filter (Rx filter), and the receiver may be a surface acoustic wave filter (surface acoustic wave filter, SAW filter).
  • the radio frequency circuit can also be used to realize the modulation or demodulation between the baseband signal and the radio frequency signal.
  • the radio frequency circuit can also include a modulation circuit corresponding to the above-mentioned transmitting channel, and a demodulation circuit corresponding to the above-mentioned receiving channel. circuit.
  • the modulation circuit corresponding to the transmission channel may include a digital to analog converter (DAC), a low pass filter (low pass filter, LPF) and an up converter (up converter), and a driver amplifier (driver amplifier, DA) .
  • the demodulation circuit corresponding to the receiving channel may include an analog to digital converter (analog to digital converter, ADC), a low pass filter (low pass filter, LPF), and a down converter (down converter).
  • the communication device shown in FIG. 1 supports frequency division duplexing (FDD), in order to isolate the transmission signal from the reception signal and ensure that the reception and transmission can work simultaneously, the communication device also includes a duplexer.
  • a duplexer can be placed between the RF circuit and the antenna.
  • the duplexer is a special two-way three-terminal filter, including a transmit filter and a receive filter, which can filter and suppress the transmit signal and the receive signal separately, so as to isolate the transmit signal from the receive signal and ensure that the receive and transmit can work at the same time.
  • Multiple transmit channels and multiple receive channels in the radio frequency circuit can share a duplexer.
  • the transmit filter in the duplexer There are two requirements for the transmit filter in the duplexer: one is to ensure that the interference signal that falls into the receiving frequency band after being suppressed by the transmit filter does not affect the receiving sensitivity of the receiver; the other is to ensure that the interference signal that is suppressed by the transmit filter is located Interference signals outside the receiving frequency band meet the agreed emission spurious index.
  • the above requirements can be achieved by increasing the rejection of the transmit filter in the duplexer. However, this results in a larger and more expensive transmit filter.
  • the nonlinear distortion signal in the transmit signal input to the duplexer can be canceled by a feed-forward cancellation system to reduce the impact of the nonlinear distortion signal on the above-mentioned receiving sensitivity and transmitting Effect of spurious indicators.
  • the nonlinear distorted signal is generated due to the nonlinear operation of the devices in the transmitting channel, mainly due to the nonlinear operation of the PA in the transmitting channel.
  • the nonlinear distortion signal mainly includes an intermodulation signal, and the intermodulation signal refers to a signal generated by mutual modulation of an interference signal or a noise signal and a useful signal (also called a service signal).
  • Non-linear distortion signals may also include harmonic signals.
  • intermodulation signals are used below to represent nonlinear distortion signals.
  • the feed-forward cancellation system is introduced below.
  • FIG. 2 provides a schematic structural diagram of a feedforward cancellation system, which may be located between a PA and a duplexer in a transmit channel.
  • the feedforward cancellation system includes: a first coupler, a time delay, an equalizer, an amplifier and a second coupler, the input of the first coupler is coupled to the PA, and the output of the second coupler The terminal is coupled to the transmit filter in the duplexer.
  • the first coupler is used to output two transmit sub-signals according to the transmit signal output by the PA; the equalizer is used to adjust the amplitude and phase of the intermodulation signal in one of the transmit sub-signals to output a cancellation signal; the amplifier is used to amplify the The cancellation signal is used to match the power of the intermodulation signal in another transmission sub-signal; the delayer is used to delay another transmission sub-signal to output a transmission delay signal, which is used to match the processing delay of the equalizer and amplifier; the second coupling The detector is used to cancel the intermodulation signal in the transmission delay signal according to the amplified cancellation signal.
  • the equalizer can be implemented by sequentially coupling a limiter, a band-stop filter, and a phase shifter.
  • the limiter can be used to adjust the amplitude of the input signal
  • the band rejection filter can be used to extract the intermodulation signal
  • the phase shifter is used to adjust the phase of the intermodulation signal.
  • the equalizer can also be implemented by sequentially coupling an ADC, a digital filter, a digital equalizer, and a DAC. Wherein the digital filter is used for extracting the intermodulation signal, and the digital filter is used for equalizing the amplitude and phase of the intermodulation signal.
  • the equalizer may also be implemented in other ways.
  • the processing accuracy of the existing feedforward cancellation technology is low, resulting in poor cancellation effect of nonlinear distortion components, which further leads to poor performance of the communication system.
  • the embodiment of the present application provides a signal processing device as shown in Figure 3a to Figure 3d (the signal processing device can also be called a feedforward cancellation system), by using multiple filter sub-circuits at different sampling time Sampling and filtering the intermodulation signal, and accumulating the sampling and filtering signals output by the multiple filter sub-circuits through the accumulation circuit to obtain the intermodulation cancellation signal, thereby realizing high-precision amplitude and phase adjustment of the intermodulation signal in the analog signal domain , thereby reducing the processing delay and improving the processing accuracy.
  • the signal processing device can also be called a feedforward cancellation system
  • the signal processing device can be applied not only to the above-mentioned communication equipment supporting FDD, but also to communication equipment supporting other duplex communication, or to communication equipment that does not support or use duplex communication, so as to reduce Effects of nonlinear distorted signals on communication equipment.
  • the aforementioned other duplex communication may include time division duplex (tine division duplexing, TDD) and FDD+TDD communication scenarios.
  • the signal processing device may be arranged between the PA of the transmission channel and the transmission filter of the duplexer, or between the PA of the transmission channel and the transmission filter of the transmission channel.
  • a device with nonlinear distortion in the communication device can be directly or indirectly connected to the input end of the signal processing device, so that the signal processing device can cancel the nonlinear distortion introduced by the device.
  • the signal processing device will be described below.
  • the signal processing device includes a branching module #11, a time delayer 20, a combining module #21 and a filter circuit 30.
  • the branching module #11 can be a coupler, a splitter and other devices, and the following will introduce the branching module #1 as the first coupler 10 as an example;
  • the combining module #21 can be a coupler, a combiner, etc. devices, the following will introduce the combination module #21 as the second coupler 40 as an example.
  • the branching module #11 and the combining module #21 can also be implemented in other ways, which is not limited in this application.
  • the signal processing device shown in FIG. 3 a includes: a first coupler 10 , a delayer 20 , a second coupler 40 and a filter circuit 30 .
  • the input end of the first coupler 10 is coupled with the signal source of the signal processing device; the output end of the first coupler 10 is respectively coupled with the input end of the delayer 20 and the input end of the filter circuit 30; the output of the delayer 20 end and the first input end coupling of the second coupler 40; the output end of the filter circuit 30 is coupled with the second input end of the second coupler 40; the filter circuit 30 includes a plurality of filter sub-circuits 31 and accumulation circuits 32, a plurality An output of the filter subcircuit 31 is coupled to an input of an accumulation circuit 32 .
  • the above-mentioned signal source may be a baseband circuit, and the output of the signal source may be a baseband signal.
  • the first coupler 10 is configured to output the first sub-signal and the second sub-signal according to the input signal.
  • the first sub-signal is output to the delayer 20
  • the second sub-signal is output to the filter circuit 30 .
  • the first coupler 10 can be used to separate the input signal into a first sub-signal and a second sub-signal.
  • the input signal is an analog signal.
  • the input signal is specifically a signal after nonlinear distortion is introduced into the signal output by the signal source, for example, it may be a signal directly output by a device introducing nonlinear distortion, or it may be a signal after the directly output signal passes through other devices.
  • the input signal is the output signal of the PA in the transmit channel.
  • Input signals include useful signals (hereinafter referred to as service signals) and intermodulation signals.
  • Both the first sub-signal and the second sub-signal include an intermodulation signal and a service signal.
  • the signal processing device is used for filtering intermodulation signals to obtain service signals.
  • the power of the first sub-signal and the second sub-signal may be different, for example, the power of the first sub-signal is greater than the power of the second sub-signal.
  • the delayer 20 is configured to delay the first sub-signal to output the delayed signal to the second coupler 40 .
  • the delay amount of the delayer 20 can be set in advance, and the delay amount can be used for the processing delay of the matched filter circuit 30 .
  • the filter circuit 30 includes a plurality of filter sub-circuits 31 and an accumulation circuit 32; the plurality of filter sub-circuits 31 are respectively used to sample the second sub-signal at different sampling times, and filter the sampled signal obtained by sampling to output the sample filter Signal; the accumulating circuit 32 is used for accumulating the sampling and filtering signals output by the plurality of filtering sub-circuits 31 to obtain an intermodulation cancellation signal. That is, the plurality of filtering sub-circuits 31 can be used to adjust the amplitude and phase of the second sub-signal respectively, and the accumulating circuit 32 is used to obtain the intermodulation cancellation signal obtained after adjusting the second sub-signal.
  • the second coupler 40 is configured to cancel the delayed signal according to the intermodulation cancellation signal, and output the target signal.
  • the second coupler 40 can subtract the intermodulation cancellation signal from the delayed signal to cancel the intermodulation signal in the delayed signal, so as to obtain the target signal.
  • the signal processing device may further include an amplifier 50 a coupled between the filter circuit 30 and the second coupler 40 .
  • the amplifier 50a is used to amplify the intermodulation cancellation signal output by the filter circuit 30, so that the amplitude of the intermodulation cancellation signal can match the amplitude of the intermodulation signal in the delayed signal.
  • the signal processing device further includes a combining module #22.
  • a combining module #22 The following description will be made by taking the combining module #22 as the third coupler 60 as an example.
  • the first input end of the third coupler 60 is coupled to the output end of the first coupler 10 to obtain the second sub-signal; the second input end of the third coupler 60 is coupled to the signal source, The output terminal of the third coupler 60 is coupled to the input terminal of the filter circuit 30 .
  • the third coupler 60 is configured to extract the first intermodulation signal from the second sub-signal.
  • the signal output by the signal source and the second sub-signal are input to the third coupler 60 respectively, and the third coupler 60 outputs the first intermodulation signal after cancellation. That is to say, among the signals input to the third coupler 60 , one path is the second sub-signal, and the other path is a signal homologous to the second sub-signal, which is used to extract the first intermodulation signal.
  • the third coupler 60 may be replaced by the above-mentioned equalizer.
  • the signal output by the equalizer is the first intermodulation signal. That is to say, the above-mentioned combining module #2 can be replaced by the above-mentioned equalizer.
  • the third coupler 60 can also be coupled between the filter circuit 30 and the second coupler 40; or, as shown in FIG. 3c, the third coupler 60 can be coupled between the filter circuit 30 and the amplifier 50a or, as shown in FIG. 3d, the third coupler 60 may be coupled between the amplifier 50a and the second coupler 40. That is to say, the first input end of the third coupler 60 can also be coupled with the output end of the filter circuit 30 or the output end of the amplifier 50a; the output end of the third coupler 60 can also be coupled with the input end of the second coupler 40 Alternatively, the input of amplifier 50a is coupled. It can be understood that, in Fig.
  • the second input end of the third coupler 60 can also be coupled with the amplifier 50b, and the input end of the amplifier 50b is coupled with the signal source.
  • the signal source signal input to the third coupler 60 can match the power of the second sub-signal or the service signal in the second sub-signal.
  • the service signal can be reduced to a certain extent before the signal enters the second coupler 40, so that when the intermodulation cancellation signal is used to cancel the intermodulation signal in the delayed signal, the delay signal can be reduced. Detrimental effects of the business signal component.
  • the device includes a third coupler 60 and the third coupler 60 is coupled between the first coupler 10 and the filter circuit 30 as an example for introduction, as shown in FIG. 3 b . It can be understood that when the filter circuit 30 is directly coupled to the first coupler 10 , the first intermodulation signal in the filter circuit 30 hereinafter may be replaced with the second sub-signal.
  • the signal processing device may also include an attenuator.
  • the attenuator is coupled between the first coupler 10 and the third coupler 60 .
  • the attenuator is used to attenuate the second sub-signal, so that the amplitude of the second sub-signal matches the amplitude of the service signal input to the third coupler 60 .
  • each filter sub-circuit 31 in the plurality of filter sub-circuits 31 includes: a sample-and-hold circuit 311 and an amplitude adjustment circuit 312 .
  • the sample-and-hold circuit 311 is configured to sample and hold the first intermodulation signal at the sampling time corresponding to the filter sub-circuit 31, so as to output the sampled signal.
  • the amplitude adjustment circuit 312 is used to filter the sampled signal to adjust the amplitude and phase of the sampled signal, and output the sampled filtered signal.
  • Sample and hold can be understood as holding a sampled value for a period of time after obtaining a sampled value at the sampling moment for subsequent processes. And, after the new sampling value is obtained at the next sampling moment, the new sampling value is kept for a subsequent process in the next period of time. Maintain can also be understood as maintaining, retaining, or preserving.
  • the filter circuit 30 may be a switched capacitor analog filter, and the switched capacitor analog filter may be in the form of multiple phases, and each of the multiple phases may correspond to a filter sub-circuit 31 .
  • the sample-and-hold circuit 311 may include a switch SW, a capacitor C, and a buffer BF; the amplitude adjustment circuit 312 includes a multiplier MUL.
  • the amplitude adjustment circuit 312 may also include a transconductance amplifier GM.
  • the first end of the switch SW is the input end of the filter sub-circuit 31, the second end of the switch SW, the first end of the capacitor C and the first end of the buffer BF are coupled, the second end of the capacitor C is grounded, and the buffer
  • the second end of the device BF is coupled with the first input end of the multiplier MUL, the second input end of the multiplier MUL is used to receive the filter coefficient c, the output end of the multiplier MUL is coupled with the input end of the transconductance amplifier GM, and the transconductance
  • the output terminal of the amplifier GM is the output terminal of the filtering subcircuit 31 .
  • a plurality of filter sub-circuits 31 including 9 filter sub-circuits 31 are used as an example for illustration, and the switches and capacitors in the i-th filter sub-circuit 31 of the 9 filter sub-circuits 31 are , buffer, multiplier, and transconductance amplifier, and the filter coefficients corresponding to the multiplier are denoted as SWi, Ci, BFi, MULi, GMi, and ci, respectively, and the value of i ranges from 0 to 8.
  • the switch SWi and the capacitor Ci can be used to sample the first intermodulation signal at the sampling moment corresponding to the filter sub-circuit 31, the buffer BFi can be used to hold the sampled signal, and the multiplier MULi can be used to adjust the amplitude of the sampled signal according to the filter coefficient ci, and the transconductance amplifier GMi can be used to amplify the power of the adjusted sampled signal.
  • the filter coefficient c corresponding to the multiplier MUL in different filter sub-circuits 31 may be different.
  • the amplification factors of the transconductance amplifiers GM in different filter sub-circuits 31 may also be different.
  • the buffers BF in different filter sub-circuits 31 hold the same time length of the sampled signal.
  • turning off or turning on the switch SW may be controlled by a controller.
  • the filter coefficient c of the multiplier MUL in the different filter sub-circuits 31 can be set by the controller.
  • the amplification factor of the transconductance amplifier GM in different filtering sub-circuits 31 can be set by the controller.
  • the foregoing controller may be a controller of a device to which the signal processing apparatus is applied, for example, the controller may be a processor or a system on chip (system of chip, SoC).
  • the amplifier 50 amplifies the intermodulation
  • the signal output after adjusting and canceling the signal Y is expressed as Gain ⁇ Y
  • the target signal output by the second coupler 40 is Error
  • the sequence formed by the plurality of filter coefficients is expressed as Cn
  • the formula middle represents a convolution operation.
  • FIG. 6 is a working timing diagram of the filter circuit 30 corresponding to FIG. 5 .
  • the working principle of the filter circuit 30 will be described in detail below in conjunction with FIG. 6 .
  • X represents the first intermodulation signal
  • x1 to x17 represent the data flow of the first intermodulation signal X at different times
  • p0 to p8 represent the driving signals of the sampling and holding circuit 311 in the nine filter sub-circuits 31 respectively.
  • the sample-and-hold circuit 311 performs sampling and holding when the rising edge of the corresponding driving signal comes, and performs sampling and holding again when the next rising edge of the driving signal comes.
  • the nine filter sub-circuits 31 respectively sample and hold the sampled signals as d0 to d8 respectively according to the above process, that is, d0 to d8 are the sample signals output by the sample-hold circuit 311 in the nine filter sub-circuits 31 respectively.
  • d0 to d8 are the sample signals output by the sample-hold circuit 311 in the nine filter sub-circuits 31 respectively.
  • the filter coefficients corresponding to each filter sub-circuit 31 can be directly configured or input by the above-mentioned controller, or the filter coefficient corresponding to each filter sub-circuit 31 can be calculated by the calculation circuit 82 and input to each filter sub-circuit.
  • the filter coefficients corresponding to each filter sub-circuit 31 may have different values at different times. The value of the filter coefficient, and the change of the filter coefficient can be controlled by the above-mentioned controller.
  • the filter coefficient corresponding to the first filter sub-circuit is c0, and the filter coefficient corresponding to the second filter sub-circuit is c1; and at the time corresponding to x9, the filter coefficient corresponding to the first filter sub-circuit can be changed is c0', and the filter coefficient corresponding to the second filtering sub-circuit is changed to c1'.
  • the filter circuit 30 may further include: a variable-gain amplifier (variable-gain amplifier, VGA) 33 coupled to the output terminal of the accumulation circuit 32 .
  • VGA variable-gain amplifier
  • the VGA 33 can be used to amplify the gain of the intermodulation cancellation signal output by the filter circuit 30, so that the gain of the intermodulation cancellation signal can match the gain of the intermodulation signal in the transmission delay signal.
  • the device further includes: a post-distortion circuit 70 a coupled to the third coupler 60 .
  • the input end of the post-distortion circuit 70a is used to receive the first service signal, which is the signal output by the signal source of the signal processing device.
  • the first service signal may be a signal for inputting a nonlinear distortion device.
  • the first service signal may be a baseband signal generated by a baseband circuit, and a power-amplified signal of the first service signal is the above-mentioned input signal of the signal processing device.
  • the post-distortion circuit 70a includes a main carrier cancellation circuit, configured to provide the above-mentioned first service signal.
  • the main carrier cancellation circuit can be implemented by a digital adaptive filter to compensate the amplitude and phase flatness of the hardware link.
  • the post-distortion circuit 70a further includes a nonlinear post-distortion circuit and an addition circuit.
  • the nonlinear post-distortion circuit is used for injecting the second intermodulation signal into the first service signal.
  • the adding circuit is used to add the first service signal and the second intermodulation signal to obtain the second service signal, and output the second service signal to the third coupler 60 .
  • the third coupler 60 may subtract the second service signal from the second sub-signal to obtain the first intermodulation signal.
  • the second intermodulation signal may be called a remote intermodulation signal; the frequency point of the first intermodulation signal and The difference between the frequency points of the first service signal is smaller than the first threshold, and the first intermodulation signal may be called a near-end intermodulation signal.
  • the third coupler 60 can further filter out intermodulation signals not in the receiving frequency band from the first sub-signal, so that the processing of the filtering circuit 30 can focus on receiving
  • the intermodulation signal in the frequency band helps to improve the cancellation effect of the intermodulation signal in the receiving frequency band.
  • Intermodulation signals that are not in the receiving frequency band can be filtered out by filters in the subsequent link of the communication equipment.
  • the third coupler 60 can also be coupled at the position shown in FIG. 3 c or FIG. 3 d , at this time, the post-distortion circuit 70 a can also be coupled with the third coupler 60 .
  • the above-mentioned amplifier 50 b can be coupled between the post-distortion circuit 70 a and the third coupler 60 .
  • the device further includes: a pre-distortion circuit 70b.
  • the predistortion circuit 70b is located before the nonlinear distortion device.
  • the predistortion circuit is coupled to the input of the PA.
  • the pre-distortion circuit 70b may also be called a nonlinear pre-distortion circuit, and is configured to inject a third intermodulation signal into the first service signal to obtain a pre-distortion signal.
  • the distortion caused by the nonlinear device can be offset to a certain extent, thereby reducing the intermodulation signal in the output signal of the nonlinear device.
  • the third intermodulation signal is a near-end intermodulation signal.
  • the predistortion circuit 70b can be realized by a digital adaptive filter.
  • the device further includes: a filter coefficient calculation circuit 80 .
  • the filter coefficient calculation circuit 80 has two input terminals, which are respectively used to receive the first intermodulation signal and the target signal.
  • the filter coefficient calculation circuit 80 is configured to output a plurality of filter coefficients according to the first intermodulation signal and the target signal, and the plurality of filter coefficients are filter coefficients of the plurality of filter sub-circuits 31 .
  • the filter coefficient calculation circuit 80 may output the multiple filter coefficients to the above-mentioned controller, and the controller distributes the multiple filter coefficients to different filter sub-circuits 31 among the multiple filter sub-circuits 31 .
  • the filter coefficient calculation circuit 80 includes: a branching module #12 and a calculation circuit 82 .
  • the branching module can be a coupler, a splitter and other devices, and the following will introduce that the branching module #12 is the fourth coupler 81 as an example.
  • the input end of the fourth coupler 81 is coupled to the output end of the second coupler 40, the first output end of the fourth coupler 81 is coupled to the first input end of the calculation circuit 82, and the second input end of the calculation circuit 82 is used for A first intermodulation signal is received.
  • the fourth coupler 81 is used to couple the target sub-signal from the target signal.
  • the fourth coupler 81 may be a splitter, configured to split the target sub-signal from the target signal.
  • the power of the target sub-signal may be smaller than the target signal.
  • the calculation circuit 82 is configured to output a plurality of filter coefficients according to the first intermodulation signal and the target sub-signal.
  • the target transmission sub-signal is represented as Error
  • the first intermodulation signal is represented as X
  • the plurality of filter coefficients are represented as C(n) (n represents the number of iterations)
  • the solution formula of the plurality of filter coefficients can be Expressed as the following formula (3).
  • mu represents the iteration step size of each iteration
  • conj represents the conjugate operation.
  • the device further includes: a parameter calibration circuit 90 coupled to the filter circuit 30 .
  • the parameter calibration circuit 90 has two input terminals, which are respectively used to receive the first intermodulation signal and the intermodulation cancellation signal.
  • the parameter calibration circuit 90 is used for determining the mismatch parameter of the filter circuit 30 according to the first intermodulation signal and the intermodulation cancellation signal.
  • the mismatch parameter is used to calibrate the filter circuit 30 so as to align the performance of each filter sub-circuit.
  • the mismatch parameter includes at least one of the following: a sampling moment mismatch value, a gain mismatch value, and a DC mismatch value.
  • the above-mentioned filter circuit 30 is essentially a filter with a multi-phase structure. Since the filter circuit 30 is implemented by an analog circuit, there will be parameter mismatch between the multi-phases in the actual application process, such as the sampling time mismatch value, Gain mismatch value and DC mismatch value, etc. Assuming that the filter circuit 30 includes M filter sub-circuits 31 (ie, M phases), the parameter adaptation will cause the output signal of the filter circuit 30 to have spurs of f s /M ⁇ f in in the frequency spectrum. fin represents the frequency of the first intermodulation signal. The stray energy caused by the mismatch of these parameters satisfies the following formula (4), X represents the first intermodulation signal, Y represents the intermodulation cancellation signal, C represents the filter coefficient, Represents a convolution operation.
  • mismatch parameter Assume that the above mismatch parameter is denoted as S.
  • the value of the mismatch parameter can be determined by injecting a known dither signal into X. If the known jitter signal is denoted as ⁇ , two corresponding stray energies P ⁇ 1 and P ⁇ 2 can be obtained after injecting two known jitter signals ( ⁇ 1 and ⁇ 2), and the mismatch value of the mismatch parameter (or called is the correction value) satisfies the following formula (5).
  • mu is the step size of each iteration correction.
  • the parameter calibration circuit 90 may also send the determined mismatch parameters to the above-mentioned controller, so that the controller corrects the filter circuit 30 according to the corresponding mismatch parameters, thereby ensuring that the cancellation performance of the device is not affected by stray energy Impact.
  • the device further includes: a power amplifier PA and a duplexer DUX.
  • the power amplifier PA is coupled before the input end of the first coupler 10 , and the power amplifier PA is used to amplify the output signal of the predistortion circuit 70 b, or to amplify the first service signal, and output the signal to the first coupler 10 .
  • the duplexer DUX is coupled between the second output terminal of the fourth coupler 81 or the output terminal of the second coupler 40 and the antenna. The duplexer DUX is used to receive the target signal, and perform transmit filter processing on the target signal, and the processed signal is transmitted through the antenna.
  • the signal processing device may not include the power amplifier PA and the duplexer DUX, for example, the power amplifier PA and the duplexer DUX may be set independently of the device, and the signal processing device may also be called a feedforward pair
  • the elimination system which is not specifically limited in this embodiment of the present application.
  • the signal processing apparatus provided in the embodiment of the present application may be applied in a multi-antenna scenario, and in this case, the number of the signal processing apparatus may be the same as the number of power amplifiers PA. There may not be a binding relationship between the number of the signal processing apparatus and the number of antennas, that is, one or more antennas may correspond to one signal processing apparatus.
  • the filter circuit 30 may also be integrated with one or more of the post-distortion circuit 70a, the filter coefficient calculation circuit 80 and the parameter calibration circuit 90 into one chip.
  • the filter circuit 30 , the calculation circuit 81 and the parameter calibration circuit 90 in the filter coefficient calculation circuit 80 are integrated into one chip.
  • the filter circuit 30 , the post-distortion circuit 70 a , the calculation circuit 81 in the filter coefficient calculation circuit 80 , and the parameter calibration circuit 90 are integrated into one chip.
  • the filter coefficient calculation circuit 80 may also include a first switch circuit 83 and a second switch coupled between the fourth coupler 82 and the calculation circuit 81 circuit 84, the first switch circuit 83 can be set outside the chip, and the second switch circuit 84 can be integrated in the chip, so that the hardware link between the first switch circuit 83 and the second switch circuit 84 can also realize time division Multiplexing, that is, by turning off and turning on the first switch circuit 83 and the second switch circuit 84, multiple fourth couplers 81 can share one calculation circuit 82, so as to improve the utilization rate of the hardware link and reduce the the cost of.
  • the first coupler 10 is used to output the first sub-signal and the second sub-signal according to the input signal
  • the delayer 20 is used to delay the first sub-signal to output the delayed signal
  • the third coupler 60 is used to To extract the first intermodulation signal in the second word signal
  • the filter circuit 30 includes a plurality of filter subcircuits 31 and an accumulation circuit 32, and the plurality of filter subcircuits 31 are respectively used to simulate the first intermodulation signal at different sampling times Sampling and filtering processing in the domain
  • the accumulation circuit 32 is used for accumulating the sampling filter signals output by the plurality of filtering sub-circuits 31 to obtain the intermodulation cancellation signal
  • the second coupler 40 is used for intermodulation cancellation signal and delay signal, Output target signal.
  • the filter circuit 30 includes a plurality of filter sub-circuits 31 and accumulation circuits 32 that can realize high-precision analog domain sampling and amplitude of the first intermodulation signal through multi-phase sample-and-hold circuits and amplitude-phase adjustment in the analog signal domain. phase adjustment. It can be understood that the more the number of multiphase phases, that is, the more the number of filtering sub-circuits 31, the more sampling data of the first intermodulation signal at a time, and the higher the fineness of amplitude and phase adjustment. Moreover, since the filtering circuit 30 performs processing in the analog domain, no additional analog-to-digital conversion is required, and time delay can be effectively reduced.
  • the equalization processing of the intermodulation signal can be realized when the time delay device 20 provides a very small amount of delay, thereby reducing the processing time delay and improving the processing accuracy.
  • the intermodulation signal cancellation effect in the receiving frequency band can be further improved, and the system cost can be reduced.
  • the high performance of the filter circuit 30 can also be ensured by the filter coefficient calculation circuit 80 and the parameter calibration circuit 90 .
  • an embodiment of the present application further provides a chip, and the chip includes a filter circuit 30 .
  • the filter circuit For a specific description of the filter circuit, reference may be made to the description of the filter circuit 30 above, which will not be repeated in this embodiment of the present application.
  • the embodiment of the present application also provides a communication device, which may be a base station or a terminal, and the communication device includes a baseband circuit and the signal processing apparatus provided in any one of the above-mentioned figures 3a-9.
  • the signal processing apparatus For a specific description of the signal processing apparatus, reference may be made to the foregoing description, and details are not repeated here in this embodiment of the present application.
  • the disclosed devices may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components can be Incorporation or may be integrated into another device, or some features may be omitted, or not implemented.
  • the unit described as a separate component may or may not be physically separated, and the component displayed as a unit may be one physical unit or multiple physical units, that is, it may be located in one place, or may be distributed to multiple different places . Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

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Abstract

本申请提供一种信号处理装置及通信设备，涉及通信技术领域，用于提高非线性失真信号的对消精度。该装置包括：第一分路模块、第一合路模块、时延器和滤波电路；第一分路模块与该信号处理装置的信号源耦合，第一分路模块的输出端分别与时延器的输入端和滤波电路的输入端耦合；时延器的输出端和第一合路模块的第一输入端耦合；滤波电路的输出端和第一合路模块的第二输入端耦合；滤波电路包括多个滤波子电路和累加电路，该多个滤波子电路的输出端与累加电路的输入端耦合。

Description

一种信号处理装置及通信设备 技术领域
本申请涉及通信技术领域，尤其涉及一种信号处理装置及通信设备。
背景技术
有用信号(即业务信号)通过非线性系统时会产生非线性失真。例如有用信号通过功率放大器(power amplify，PA)进行功率放大后，输出信号包含有用信号和非线性失真信号。
目前，通常采用前馈对消技术对非线性系统输出信号中的非线性失真成分进行对消。然而现有前馈对消技术的处理精度低，导致非线性失真成分的对消效果不佳，进一步导致通信系统的性能不佳。
发明内容
本申请提供一种信号处理装置及通信设备，用于提高非线性失真信号的对消精度。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，提供一种信号处理装置，包括：第一分路模块、时延器、第一合路模块和滤波电路。其中，第一分路模块可以是耦合器、分路器等器件，下文以第一分路模块为第一耦合器为例进行介绍；第一合路模块可以是耦合器、合路器等器件，下文以第一合路模块为第二耦合器为例进行介绍。也就是说，该信号处理装置包括：第一耦合器、第二耦合器、时延器和滤波电路；第一耦合器与信号处理装置的信号源耦合，第一耦合器的输出端分别与时延器的输入端和滤波电路的输入端耦合；时延器的输出端和第二耦合器的第一输入端耦合；滤波电路的输出端和第二耦合器的第二输入端耦合；滤波电路包括多个滤波子电路和累加电路，多个滤波子电路的输出端与累加电路的输入端耦合。
第一耦合器，用于根据第一耦合器的输入信号输出第一子信号和第二子信号，第一子信号的功率可以大于第二子信号的功率；该时延器，用于延迟第一子信号以输出延迟信号；该滤波电路包括多个滤波子电路和累加电路；其中，该多个滤波子电路分别用于在不同采样时刻对第二子信号进行采样，并对采样得到的采样信号进行滤波处理以输出采样滤波信号，即多个滤波子电路可分别用于对第二子信号在不同相位上进行幅值调整；该累加电路用于累加该多个滤波子电路输出的该采样滤波信号以得到互调对消信号；第二耦合器，用于根据该互调对消信号和该延迟信号输出目标信号，比如利用延迟信号减去互调对消信号以对消掉延迟信号中的互调信号。
上述技术方案中，该装置通过滤波电路实现第二子信号的均衡处理，滤波电路包括多个滤波子电路和累加电路，该多个滤波子电路和累加电路能够在模拟信号域对第二子信号在不同相位上进行高精度的幅值调整，从而能够在时延器提供极小延迟量的情况下实现互调信号的均衡处理，进而降低了处理时延、提高了处理精度。
在第一方面的一种可能的实现方式中，该装置还包括：第二合路模块，下文以第二合路模块为第三耦合器为例进行介绍。第三耦合器的第一输入端与第一耦合器的输出端耦合，第三耦合器的第二输入端与信号源耦合，第三耦合器的输出端与滤波电路的输入端耦 合。第三耦合器，用于从第二子信号中耦合出第一互调信号。该第三耦合器可以替换为均衡器，并输出第一互调信号。此时，上述多个滤波子电路分别用于在不同采样时刻对第二子信号中的第一互调信号进行采样，并对采样得到的采样信号进行滤波处理以输出采样滤波信号，即多个滤波子电路可分别用于对第一互调信号在不同相位上进行幅值调整。通过引入第三耦合器(第二合路模块)或者均衡器，可以提取出第二子信号中的第一互调信号，从而使滤波电路能够针对性的对第一互调信号进行高精度的幅相调整，且能够减少滤波电路输出的互调对消信号中业务信号的分量，减小互调对消信号对延迟信号中有用信号成分的不利影响，进一步提高互调信号的对消性能。
可以理解的是，当该装置不包括合路模块时，滤波电路，以及滤波子电路所处理的第一互调信号替换为第二子信号。
在第一方面的一种可能的实现方式中，该多个滤波子电路中的每个滤波子电路包括：采样保持电路和幅值调节电路，采样保持电路的输出端与幅值调节电路的第一输入端耦合；采样保持电路，用于在该采样时刻对第一互调信号进行采样并保持，以输出采样信号；幅值调节电路，用于对该采样信号进行滤波处理，以输出采样滤波信号。上述可能的实现方式，能够使得该多个滤波子电路分别对第一互调信号在不同相位上进行幅值调整，保证互调信号的均衡处理具有较高的处理精度。
在第一方面的一种可能的实现方式中，该采样保持电路包括开关、电容和缓冲器，该幅值调节电路包括乘法器；其中，该开关的第一端为该滤波子电路的输入端，该开关的第二端、该电容的第一端和该缓冲器的第一端耦合，该电容的第二端接地，该缓冲器的第二端与该乘法器的第一输入端耦合，该乘法器的第二输入端用于接收滤波系数，该乘法器的输出端用于输出该采样滤波信号。上述可能的实现方式中，提供了的采样保持电路和幅值调节电路简单有效、成本较低，且在通过该采样保持电路和幅值调节电路对第一互调信号进行采样并保持、以及滤波处理时能够在极小延迟量下实现互调信号的第一互调信号的高精度的幅相调整，从而降低了处理时延、提高了处理精度。
在第一方面的一种可能的实现方式中，该幅值调节电路还包括：与该乘法器的输出端耦合的跨导放大器；该跨导放大器，用于放大该采样滤波信号。和/或，该滤波电路还包括：与该累加电路的输出端耦合的可变增益放大器。上述可能的实现方式中，能够保证互调对消信号的幅值与延迟信号中的互调信号的幅值相匹配，从而提高延迟信号中的互调信号对消的效果。
在第一方面的一种可能的实现方式中，该装置还包括：衰减器，该衰减器耦合在第一耦合器和第三耦合器之间，该衰减器用于对第二子信号进行衰减，以使第二子信号的幅值与输入到第三耦合器的业务信号的幅值相匹配。
在第一方面的一种可能的实现方式中，该第三耦合器的第一输入端与滤波电路的输出端耦合，第三耦合器的第二输入端与信号源耦合，第三耦合器的输出端与第二耦合器耦合。可选的，该装置还包括耦合在信号源和第三耦合器之间的放大器。
在第一方面的一种可能的实现方式中，该装置还包括：与第三耦合器和信号源耦合的后失真电路；该后失真电路，用于在信号源输出的信号(可以理解为第一业务信号)中注入第二互调信号以得到第二业务信号，第二业务信号和第二子信号用于耦合出第一互调信号，第二互调信号的频点与第一互调信号的频点不同。可选的，第二互调信号的频点与第 一业务信号的频点之差大于预设阈值。上述可能的实现方式中，后失真电路通过在第一业务信号中注入第二互调信号以得到第二业务信号，从而使得第三耦合器利用第二业务信号从第二子信号耦合出第一互调信号，从而保证耦合出的第一互调信号是一定频段范围内的互调信号，进而降低滤波电路处理第一互调信号的复杂度，同时降低成本。
在第一方面的一种可能的实现方式中，该装置还包括：预失真电路，用于在第一业务信号中注入第三互调信号，第三互调信号的频点与第一业务信号的频点之差小于第一阈值，第三互调信号可以称为近端互调信号，第三互调信号用于减小第一耦合器输入信号中的第一互调信号。上述可能的实现方式中，通过在第一业务信号中注入第三互调信号，并利用第三互调信号减小第一耦合器输入信号中的第一互调信号，能够降低滤波电路处理第一互调信号的处理难度，同时降低成本。
在第一方面的一种可能的实现方式中，该装置还包括：滤波系数计算电路，该滤波系数计算电路的输出端与该幅值调节电路的第二输入端耦合；该滤波系数计算电路，用于根据第一互调信号和该目标信号输出多个滤波系数，该多个滤波系数为该多个滤波子电路的滤波系数。可选的，该滤波系数计算电路包括：第二分路模块和计算电路。以第二分路模块为第四耦合器为例，该滤波计算电路包括：第四耦合器和计算电路；第四耦合器的输入端与第二耦合器的输出端耦合，第四耦合器的第一输出端与该计算电路的第一输入端耦合，该计算电路的第二输入端用于接收第一互调信号。上述可能的实现方式中，使用滤波系数计算电路根据第一互调信号和该目标信号输出该多个滤波子电路的多个滤波系数，从而根据该多个滤波系数对第一互调信号进行滤波处理时，能够提高该滤波电路的处理精度。
在第一方面的一种可能的实现方式中，该滤波系数计算电路还包括：耦合在第四耦合器和该计算电路之间的第一开关电路和第二开关电路，第一开关电路和第二开关电路用于关断或导通第四耦合器与该计算电路之间的连接。上述可能的实现方式中，第一开关电路与第二开关电路之间的硬件链路可以实现时分复用，即通过第一开关电路与第二开关电路的关断和导通实现多个第四耦合器共用一个计算电路，以提高该硬件链路的利用率，降低成本。
在第一方面的一种可能的实现方式中，该装置还包括：与该滤波电路耦合的参数校准电路；该参数校准电路，用于根据第一互调信号和该互调对消信号确定该滤波电路的失配参数，该失配参数用于校准该滤波电路。可选的，该失配参数包括以下至少一项：采样时刻失配值，增益失配值，直流失配值。上述可能的实现方式中，使用参数校准电路根据第一互调信号和该互调对消信号输出的失配参数校准该滤波电路，能够避免滤波电路中多个滤波子电路因为器件本身的制造差异而导致的滤波效率的差异，从而提高该滤波电路的处理精度。
在第一方面的一种可能的实现方式中，该滤波电路与以下至少一项集成在一个芯片中：该滤波系数计算电路、该参数校准电路、该后失真电路。上述可能的实现方式中，通过将上述电路集成在芯片中，可以降低系统的体积和成本。
在第一方面的一种可能的实现方式中，该装置还包括：耦合在第一耦合器的输入端和信号源之间的功率放大器，和与第二耦合器的输出端耦合的双工器；该功率放大器，用于输出上述第一耦合器的输入信号；该双工器，用于接收该目标信号，并对该目标信号进行 发射滤波处理。上述可能的实现方式中，能够避免目标信号在经过双工器时对该双工器中接收信号的影响。
第二方面，提供一种芯片，该芯片包括：滤波电路；该滤波电路，包括：多个滤波子电路和累加电路；其中，该多个滤波子电路分别用于在不同采样时刻对第一互调信号进行采样，并对采样得到的采样信号进行滤波处理以输出采样滤波信号；该累加电路用于累加该多个滤波子电路输出的该采样滤波信号以得到互调对消信号。
在第二方面的一种可能的实现方式中，该多个滤波子电路中的每个滤波子电路包括：采样保持电路，用于在该采样时刻对第一互调信号进行采样并保持，以输出采样信号；幅值调节电路，用于对该采样信号进行滤波处理，以输出采样滤波信号。
在第二方面的一种可能的实现方式中，该采样保持电路包括开关、电容和缓冲器，该幅值调节电路包括乘法器；其中，该开关的第一端为该滤波子电路的输入端，该开关的第二端、该电容的第一端和该缓冲器的第一端耦合，该电容的第二端接地，该缓冲器的第二端与该乘法器的第一输入端耦合，该乘法器的第二输入端用于接收滤波系数，该乘法器的输出端用于输出该采样滤波信号。
在第二方面的一种可能的实现方式中，该幅值调节电路还包括：与该乘法器的输出端耦合的跨导放大器；该跨导放大器，用于放大该采样滤波信号。
在第二方面的一种可能的实现方式中，该滤波电路还包括：与该累加电路的输出端耦合的增益放大器。
在第二方面的一种可能的实现方式中，该芯片还包括：后失真电路；该后失真电路，用于在第一业务信号中注入第二互调信号以得到第二业务信号，第二业务信号和第二发射子信号用于输出第一互调信号，第二互调信号的频点与第一互调信号的频点不同。
在第二方面的一种可能的实现方式中，第二互调信号的频点与第一业务信号的频点之差大于预设阈值。
在第二方面的一种可能的实现方式中，该芯片还包括：滤波系数计算电路；该滤波系数计算电路，用于根据第一互调信号和目标信号输出多个滤波系数，该多个滤波系数为该多个滤波子电路的滤波系数。
在第二方面的一种可能的实现方式中，该芯片还包括：与该滤波电路耦合的参数校准电路；该参数校准电路，用于根据第一互调信号和该互调对消信号确定该滤波电路的失配参数，该失配参数用于校准该滤波电路。
在第二方面的一种可能的实现方式中，该失配参数包括以下至少一项：采样时刻失配值，增益失配值，直流失配值。
第三方面，提供一种滤波系数计算电路，应用于第一方面所提供的信号处理装置中；其中，该滤波系数计算电路的第一输入端与第二耦合器的输出端耦合，该滤波系数计算电路的第二输入端用于接收第一互调信号，第一互调信号为该滤波电路的输入信号，该滤波系数计算电路的输出端用于输出该滤波电路的滤波系数。
在第三方面的一种可能的实现方式中，该滤波系数计算电路包括：第三耦合器和计算电路；其中，第三耦合器的输入端与第二耦合器的输出端耦合，第三耦合器的第一输出端与该计算电路的第一输入端耦合，该计算电路的第二输入端用于接收第一互调信号，该计算电路的输出端用于输出该滤波电路的滤波系数。
在第三方面的一种可能的实现方式中，该滤波系数计算电路还包括：耦合在第三耦合器和该计算电路之间的第一开关电路和第二开关电路，第一开关电路和第二开关电路用于关断或导通第三耦合器与该计算电路之间的连接。上述可能的实现方式中，第一开关电路与第二开关电路之间的硬件链路可以实现时分复用，即通过第一开关电路与第二开关电路的关断和导通实现该硬件链路的切换，以提高该硬件链路的利用率，降低成本。
第四方面，提供一种通信设备，该通信设备包括基带电路、以及如第一方面或者第一方面的任一种可能的实现方式所提供的信号处理装置。
可以理解地，上述提供的任一种芯片、滤波系数计算电路和通信设备均包含了上文所提供的信号处理装置的至少一部分内容，因此，其所能达到的有益效果可参考上文所提供的信号处理装置中的有益效果，此处不再赘述。
附图说明
图1为本申请实施例提供的一种无线通信设备的结构示意图；
图2为本申请实施例提供的一种前馈对消系统的结构示意图；
图3a-图3d为本申请实施例提供的一种信号处理装置的结构示意图；
图4为本申请实施例提供的一种滤波电路的结构示意图；
图5为本申请实施例提供的另一种滤波电路的结构示意图；
图6为本申请实施例提供的一种滤波电路的工作时序图；
图7为本申请实施例提供的另一种信号处理装置的结构示意图；
图8为本申请实施例提供的又一种信号处理装置的结构示意图；
图9为本申请实施例提供的另一种信号处理装置的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。
在本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a和b，a和c，b和c或a、b和c，其中a、b和c可以是单个，也可以是多个。
在本申请的实施例中，“第一”、“第二”等字样并不对数量和次序进行限定。“耦合”一词用于表示电性连接，包括通过导线或连接端直接相连或通过其他器件间接相连。因此“耦合”应被视为是一种广义上的电子通信连接。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
图1为本申请实施例提供的一种无线通信设备的结构示意图。该无线通信设备可以部署在陆地上，包括室内或室外、手持或车载。该无线通信设备也可以部署在水面上(如轮船等)。该无线通信设备还可以部署在空中(例如飞机、气球和卫星上等)。比如，该无 线通信设备可以为终端或者基站。比如，该终端包括但不限于：手机(mobile phone)、平板电脑、笔记本电脑、掌上电脑、移动互联网设备(mobile internet device，MID)、可穿戴设备(例如智能手表、智能手环、计步器等)、车载设备(例如，汽车、自行车、电动车、飞机、船舶、火车、高铁等)、虚拟现实(virtual reality，VR)设备、增强现实(augmented reality，AR)设备、工业控制(industrial control)中的无线终端、智能家居设备(例如，冰箱、电视、空调、电表等)、智能机器人、车间设备、无人驾驶(self-driving)中的无线终端、远程手术(remote medical surgery)中的无线终端、智能电网(smart grid)中的无线终端、运输安全(transportation safety)中的无线终端、智慧城市(smart city)中的无线终端，或智慧家庭(smart home)中的无线终端、飞行设备(例如，智能机器人、热气球、无人机、飞机)等。下面结合图1对该无线通信设备的结构进行详细介绍。
图1所示的无线通信设备包括：依次耦合的基带电路、射频(radio frequency，RF)电路和天线(antenna)。
其中，基带电路具有基带处理功能，可用于处理基带信号。射频电路可用于提供功率放大或滤波等功能，比如，射频电路可用于对基带信号进行功率放大或滤波，以将基带信号转换为射频信号。天线可用于实现射频信号的接收或发送，即实现射频信号与电磁波之间的能量转换。
上述射频电路中可以包括一个或者多个发射(transmit，Tx)通道、以及一个或者多个接收(receive，Rx)通道。每个发射通道包括功率放大器(power amplifier，PA)。发射通道还可以包括发射滤波器(Tx filter)，该发射滤波器可以为隔离器。每个接收通道包括低噪声放大器(low noise amplifier，LNA)。接收通道还可以包括接收滤波器(Rx filter)，该接收器可以为声表面波滤波器(surface acoustic wave filter，SAW filter)。
进一步的，该射频电路还可以用于实现基带信号与射频信号之间的调制或解调，比如，该射频电路还可以包括与上述发射通道对应的调制电路、以及与上述接收通道对应的解调电路。发射通道对应的调制电路可以包括数模转换器(digital to analog converter，DAC)、低通滤波器(low pass filter，LPF)和上转换器(up converter)、以及驱动放大器(driver amplifier，DA)。接收通道对应的解调电路可以包括模数转换器(analog to digital converter，ADC)、低通滤波器(low pass filter，LPF)和下转换器(down converter)等。
当图1所示的通信设备支持频分双工(frequency division duplexing，FDD)，为了将发射信号和接收信号相隔离，保证接收和发射能够同时工作，该通信设备还包括双工器。如图1所示，双工器可以位于射频电路和天线之间。双工器是一种特殊的双向三端滤波器，包括发射滤波器和接收滤波器，可以分别对发射信号和接收信号进行滤波抑制，以将发射信号和接收信号相隔离，保证接收和发射能够同时工作。射频电路中的多个发射通道和多个接收通道可以共用一个双工器。
对于双工器中的发射滤波器有以下两个需求：一是保证经过发射滤波器抑制后的落入接收频段的干扰信号不影响接收端的接收灵敏度；二是保证经过发射滤波器抑制后的位于接收频段之外的干扰信号满足约定的发射杂散指标。上述需求可以通过提高双工器中发射滤波器的抑制度来实现。然而这将导致发射滤波器的体积更大，成本更高。
为了降低双工器中发射滤波器的抑制度，可以通过前馈对消系统对输入双工器的发射信号中的非线性失真信号进行对消，以减少非线性失真信号对于上述接收灵敏度和发射杂 散指标的影响。该非线性失真信号是由于上述发射通道中各器件的非线性工作而产生的，主要是由于发射通道中PA的非线性工作而产生的。非线性失真信号主要包括互调信号，互调信号是指干扰信号或者噪声信号与有用信号(也可以称为业务信号)互相调制而产生的信号。非线性失真信号还可以包括谐波信号。为了便于描述，下文以互调信号代表非线性失真信号。
下面对前馈对消系统展开介绍。
图2提供了一种前馈对消系统的结构示意图，该系统可以位于发射通道的PA和双工器之间。如图2所示，该前馈对消系统包括：第一耦合器、时延器、均衡器、放大器和第二耦合器，第一耦合器的输入端与PA耦合，第二耦合器的输出端与双工器中的发射滤波器耦合。具体的，第一耦合器用于根据PA输出的发射信号输出两个发射子信号；均衡器用于调整其中一个发射子信号中互调信号的幅值和相位以输出对消信号；放大器用于放大该对消信号以匹配另一个发射子信号中互调信号的功率；时延器用于延迟另一个发射子信号以输出发射延迟信号，该延迟用于匹配均衡器和放大器的处理时延；第二耦合器用于根据放大后的对消信号对消该发射延迟信号中的互调信号。均衡器可以通过依次耦合的限幅器、带阻滤波器、移相器来实现。其中该限幅器可以用于调整输入信号的幅值，带阻滤波器可以用于提取互调信号，移相器用于调整互调信号的相位。均衡器还可以通过依次耦合的ADC、数字滤波器、数字均衡器、DAC来实现。其中该数字滤波器用于提取互调信号，数字滤波器用于对互调信号进行幅相均衡处理。均衡器具体还可以通过其他方式实现。然而现有前馈对消技术的处理精度低，导致非线性失真成分的对消效果不佳，进一步导致通信系统的性能不佳。
基于此，本申请实施例提供一种如图3a至图3d所示的信号处理装置(该信号处理装置也可以称为前馈对消系统)，通过利用多个滤波子电路分别在不同采样时刻对互调信号进行采样和滤波处理，并通过累加电路累加该多个滤波子电路输出的采样滤波信号得到互调对消信号，从而在模拟信号域实现了互调信号的高精度的幅相调整，进而降低了处理时延，提高了处理精度。
该信号处理装置不仅可以应用于上述支持FDD的通信设备中，还可以应用于支持其他双工通信的通信设备中，也可以应用于不支持或者不使用双工通信的通信设备中，以减小非线性失真信号对于通信设备的影响。上述其他双工通信可以包括时分双工(tine division duplexing，TDD)、以及FDD+TDD的通信场景。
可以理解的是，该信号处理装置可以设置在发射通道的PA和双工器的发射滤波器之间，也可以设置在发射通道的PA和发射通道的发射滤波器之间。进一步的，通信设备中存在非线性失真的器件可以直接或者间接的连接到该信号处理装置的输入端，从而通过该信号处理装置对消该器件所引入的非线性失真。
下面对该信号处理装置进行介绍说明。
图3a至图3d为本申请实施例提供的一种信号处理装置的结构示意图，该信号处理装置包括分路模块#11、时延器20、合路模块#21和滤波电路30。其中，分路模块#11可以是耦合器、分路器等器件，下文以分路模块#1为第一耦合器10为例进行介绍；合路模块#21可以是耦合器、合路器等器件，下文以合路模块#21为第二耦合器40为例进行介绍。可以理解的是，分路模块#11与合路模块#21还可以通过其他方式实现，本申请对此不作 限定。
基于上述说明，图3a所示的信号处理装置包括：第一耦合器10、时延器20、第二耦合器40和滤波电路30。
第一耦合器10的输入端与该信号处理装置的信号源耦合；第一耦合器10的输出端分别与时延器20的输入端和滤波电路30的输入端耦合；时延器20的输出端和第二耦合器40的第一输入端耦合；滤波电路30的输出端和第二耦合器40的第二输入端耦合；滤波电路30包括多个滤波子电路31和累加电路32，多个滤波子电路31的输出端与累加电路32的输入端耦合。上述信号源可以是基带电路，信号源输出的可以是基带信号。
第一耦合器10，用于根据输入信号输出第一子信号和第二子信号。第一子信号输出至时延器20，第二子信号输出至滤波电路30。其中，第一耦合器10可用于将输入信号分离为第一子信号和第二子信号。该输入信号为模拟信号。该输入信号具体为信号源输出的信号引入非线性失真后的信号，例如可以为引入非线性失真的器件直接输出的信号，或者可以为该直接输出的信号经过其他器件后的信号。例如该输入信号为发射通道中PA的输出信号。输入信号包括有用信号(下文称为业务信号)和互调信号。第一子信号和第二子信号中均包括互调信号和业务信号。该信号处理装置用于滤除互调信号，得到业务信号。第一子信号和第二子信号的功率可以不同，比如，第一子信号的功率大于第二子信号的功率。
时延器20，用于延迟第一子信号，以输出延迟信号至第二耦合器40。其中，时延器20的延迟量可以是事先设置的，该延迟量可用于匹配滤波电路30的处理时延。
滤波电路30包括多个滤波子电路31和累加电路32；多个滤波子电路31分别用于在不同采样时刻对第二子信号进行采样，并对采样得到的采样信号进行滤波处理以输出采样滤波信号；累加电路32用于累加多个滤波子电路31输出的采样滤波信号以得到互调对消信号。也即是，多个滤波子电路31可分别用于对第二子信号进行幅相调整，累加电路32用于获取调整第二子信号后得到的互调对消信号。
第二耦合器40，用于根据互调对消信号对延迟信号进行对消，输出目标信号。第二耦合器40可利用延迟信号减去互调对消信号以对消掉延迟信号中的互调信号，从而得到目标信号。
进一步的，该信号处理装置还可以包括放大器50a，放大器50a耦合在滤波电路30与第二耦合器40之间。放大器50a用于放大滤波电路30输出的互调对消信号，以使互调对消信号的幅值能够与延迟信号中的互调信号的幅值相匹配。
可选的，该信号处理装置还包括合路模块#22。下文以该合路模块#22为第三耦合器60为例进行介绍。如图3b所示，该第三耦合器60的第一输入端与第一耦合器10的输出端耦合，以获得第二子信号；第三耦合器60的第二输入端与信号源耦合，第三耦合器60的输出端与滤波电路30的输入端耦合。
该第三耦合器60，用于从第二子信号中提取第一互调信号。可选的，信号源输出的信号和第二子信号分别输入到第三耦合器60，经过对消后第三耦合器60输出第一互调信号。也就是说，输入第三耦合器60的信号中，一路为第二子信号，另一路为与第二子信号同源的信号，该信号用于提取第一互调信号。
可选的，该第三耦合器60可以替换为上述均衡器。此时，均衡器输出的信号为第一互调信号。也就是说，上述合路模块#2可以替换为上述均衡器。
可以理解的是，该第三耦合器60还可以耦合在滤波电路30和第二耦合器40之间；或者，如图3c所示，该第三耦合器60可以耦合在滤波电路30和放大器50a之间；或者，如图3d所示，该第三耦合器60可以耦合在放大器50a和第二耦合器40之间。也就是说，第三耦合器60的第一输入端还可以与滤波电路30的输出端或者放大器50a的输出端耦合；第三耦合器60的输出端还可以与第二耦合器40的输入端或者放大器50a的输入端耦合。可以理解的是，在图3d中，第三耦合器60的第二输入端还可以与放大器50b耦合，该放大器50b的输入端与信号源耦合。通过引入该放大器50b，使得输入第三耦合器60的信号源信号能够与第二子信号或者说与第二子信号中业务信号的功率相匹配。
通过引入第三耦合器60，可以在信号进入第二耦合器40之前一定程度上减少业务信号，从而在利用互调对消信号来对消延迟信号中的互调信号时，能够减少对延迟信号中业务信号成分的不利影响。
下文以该装置包括第三耦合器60，且该第三耦合器60耦合在第一耦合器10与滤波电路30之间为例进行介绍，即如图3b所示。可以理解的是，当滤波电路30直接与第一耦合器10耦合，则下文中滤波电路30中的第一互调信号替换为第二子信号即可。
可选的，该信号处理装置还可以包括衰减器。该衰减器耦合在第一耦合器10和第三耦合器60之间。该衰减器用于对第二子信号进行衰减，以使第二子信号的幅值与输入到第三耦合器60的业务信号的幅值相匹配。
进一步的，如图4所示，多个滤波子电路31中的每个滤波子电路31包括：采样保持电路311和幅值调节电路312。采样保持电路311用于在该滤波子电路31对应的采样时刻对第一互调信号进行采样并保持，以输出采样信号。幅值调节电路312用于对采样信号进行滤波处理，以调节采样信号的幅值和相位，并输出采样滤波信号。采样并保持可以理解为在采样时刻获得一个采样值之后在一段时间内保持该采样值用于后续流程。并且，当在下一个采样时刻获取新的采样值之后，在下一段时间内保持新的采样值用于后续流程。保持还可以理解为维持、保留、或保存。
在一种可能的实施例中，滤波电路30可以为开关电容型模拟滤波器，且该开关电容型模拟滤波器可以为多相形式，该多相中的每相可以对应一个滤波子电路31。如图5所示，对于每个滤波子电路31，采样保持电路311可以包括开关SW、电容C和缓冲器BF；幅值调节电路312包括乘法器MUL。可选的，幅值调节电路312还可以包括跨导放大器GM。其中，开关SW的第一端为该滤波子电路31的输入端，开关SW的第二端、电容C的第一端和缓冲器BF的第一端耦合，电容C的第二端接地，缓冲器BF的第二端与乘法器MUL的第一输入端耦合，乘法器MUL的第二输入端用于接收滤波系数c，乘法器MUL的输出端与跨导放大器GM的输入端耦合，跨导放大器GM的输出端为该滤波子电路31的输出端。
需要说明的是，图5中以多个滤波子电路31包括9个滤波子电路31为例进行说明，且将这9个滤波子电路31中的第i个滤波子电路31中的开关、电容、缓冲器、乘法器和跨导放大器，以及乘法器对应的滤波系数分别表示为SWi、Ci、BFi、MULi、GMi和ci，i的取值范围为0至8。
具体的，在第i个滤波子电路31中，开关SWi和电容Ci可用于在该滤波子电路31对应的采样时刻对第一互调信号进行采样，缓冲器BFi可用于保持采样信号，乘法器MULi 可用于根据滤波系数ci调整采样信号的幅值，跨导放大器GMi可用于对调整后的采样信号进行功率放大。其中，不同的滤波子电路31中的乘法器MUL对应的滤波系数c可以是不同的。不同的滤波子电路31中的跨导放大器GM的放大倍数也可以是不同的。不同的滤波子电路31中的缓冲器BF保持采样信号的时间长度是相同的。
可选的，上述开关SW的关断或导通可以由控制器来控制。不同滤波子电路31中乘法器MUL的滤波系数c可以由控制器来设置。不同的滤波子电路31中的跨导放大器GM的放大倍数可以由控制器来设置。上述控制器可以为应用该信号处理装置的设备的控制器，比如，该控制器可以为处理器或者片上系统(system of chip，SoC)。
示例性的，在该信号处理装置中，假设第一互调信号表示为X、滤波电路30输出的互调对消信号表示为Y，时延器输出的信号表示为Y’，放大器50放大互调对消信号Y后输出的信号表示为Gain×Y，第二耦合器40输出的目标信号为Error，该多个滤波系数构成的序列表示为Cn，则Error需要满足如下公式(1)，式中
Figure PCTCN2021131414-appb-000001
表示卷积运算。
Figure PCTCN2021131414-appb-000002
图6为图5对应的滤波电路30的一种工作时序图，下面结合图6对滤波电路30的工作原理进行详细描述。在图6中，X表示第一互调信号，x1至x17表示第一互调信号X在不同时刻的数据流，p0至p8分别表示这9个滤波子电路31中采样保持电路311的驱动信号。采样保持电路311在对应的驱动信号的上升沿来临时进行采样并保持，直到该驱动信号的下一个上升沿来临时再次进行采样并保持。示例性的，当p0的第一个上升沿到来，SW0、C0和BF0采样获得X在该时刻的值，记为x0；并保持该值直到p0的下一个上升沿到来。可以理解的是，在获得采样值x0和p0的下一个上升沿到来并获得新的采样值x9之前的这段时间里，BF0输出到MUL0的值一直为x0。可以理解的是，p0至p8的上升沿用于触发采样，而下降沿对于滤波子电路可以不产生作用。可以理解的是，在具体实现过程中，驱动信号的上升沿可能不表现为瞬时的跳变。这种情况下，驱动信号的上升沿来临时进行采样并保持可以是驱动信号的变化达到设定阈值的时刻进行采样并保持。
这9个滤波子电路31分别按照上述过程进行采样并保持后的采样信号分别表示为d0至d8，即d0至d8分别为这9个滤波子电路31中的采样保持电路311输出的采样信号。假设x8对应的时刻为滤波电路30的输出时刻，若p0至p8对应的滤波系数分别为c0至c8，则滤波电路30在不同时刻对应输出的信号满足如下公式(2)：
Figure PCTCN2021131414-appb-000003
其中，可以由上述控制器直接配置或者输入各滤波子电路31对应的滤波系数或者输入，也可以由计算电路82计算得到各滤波子电路31对应的滤波系数并输入各滤波子电路。各滤波子电路31对应的滤波系数在不同时刻可以具有不同的值。滤波系数的值，以及滤波系数的改变可以由上述控制器来控制。例如x8对应的时刻，第一路滤波子电路对应的滤波系数为c0，第二路滤波子电路对应的滤波系数为c1；而x9对应的时刻，第一路滤波子电路对应的滤波系数可以改变为c0’，第二路滤波子电路对应的滤波系数改变为c1’。
可选的，如图5所示，滤波电路30还可以包括：与累加电路32的输出端耦合的可变增益放大器(variable-gain amplifier，VGA)33。VGA 33可用于放大滤波电路30输出的互调对消信号的增益，以使互调对消信号的增益能够与发射延迟信号中互调信号的增益匹配。
在一种可能的实施例中，如图7所示，该装置还包括：与第三耦合器60耦合的后失真电路70a。后失真电路70a的输入端用于接收第一业务信号，第一业务信号即该信号处理装置的信号源输出的信号。第一业务信号可以是用于输入非线性失真器件的信号。示例性的，第一业务信号可以是基带电路产生的基带信号，第一业务信号经过功率放大后的信号为该信号处理装置的上述输入信号。可选的，后失真电路70a包括主载波对消电路，用于提供上述第一业务信号。该主载波对消电路可以通过数字自适应滤波器实现，以补偿硬件链路的幅相平坦度。可选的，后失真电路70a还包括非线性后失真电路和加法电路。非线性后失真电路用于在第一业务信号中注入第二互调信号。加法电路用于将第一业务信号和第二互调信号相加，以得到第二业务信号，并将第二业务信号输出至第三耦合器60。第三耦合器60在接收到第二业务信号后，可以从第二子信号中减去第二业务信号，以得到第一互调信号。其中，第二互调信号的频点与第一业务信号的频点之差大于或等于第一阈值，第二互调信号可以称为远端互调信号；第一互调信号的频点与第一业务信号的频点之差小于第一阈值，第一互调信号可以称为近端互调信号。也就是说，进一步引入非线性后失真电路和加法电路，可以使第三耦合器60从第一子信号中进一步滤除不在接收频段中的互调信号，从而使滤波电路30的处理聚焦于接收频段中的互调信号，有助于提高接受频段中互调信号的对消效果。不在接收频段中的互调信号可以通过通信设备后续环节的滤波器滤除。可以理解的是，第三耦合器60还可以耦合在如图3c或图3d所示的位置，此时该后失真电路70a也可以与该第三耦合器60耦合。当第三耦合器60耦合在如图3d所示的位置，上述放大器50b可以耦合在该后失真电路70a与第三耦合器60之间。
在另一种可能的实施例中，如图7所示，该装置还包括：预失真电路70b。该预失真电路70b位于非线性失真器件之前。例如该预失真电路与PA的输入端耦合。预失真电路70b也可以称为非线性预失真电路，用于在第一业务信号中注入第三互调信号，得到预失真信号。该预失真经过非线性失真器件后，可以一定程度抵消非线性器件引起的失真，从而减小非线性器件输出信号中的互调信号。第三互调信号为近端互调信号。该预失真电路70b可以通过数字自适应滤波器实现。
进一步的，如图7所示，该装置还包括：滤波系数计算电路80。滤波系数计算电路80具有两个输入端，这两个输入端分别用于接收第一互调信号和目标信号。滤波系数计算电路80用于根据第一互调信号和目标信号输出多个滤波系数，该多个滤波系数为多个滤波子电路31的滤波系数。可选的，滤波系数计算电路80可以将该多个滤波系数输出至上述控制器，由该控制器将该多个滤波系数分配给多个滤波子电路31中的不同滤波子电路31。
在一种可能的实施例中，滤波系数计算电路80包括：分路模块#12和计算电路82。如前所述，分路模块可以是耦合器、分路器等器件，下文以分路模块#12为第四耦合器81为例进行介绍。第四耦合器81的输入端与第二耦合器40的输出端耦合，第四耦合器81的第一输出端与计算电路82的第一输入端耦合，计算电路82的第二输入端用于接收第一 互调信号。第四耦合器81用于从目标信号中耦合出目标子信号。示例性的，第四耦合器81可以是分路器，用于从目标信号中分出目标子信号。该目标子信号的功率可以小于目标信号。计算电路82用于根据第一互调信号和目标子信号输出多个滤波系数。其中，若该目标发射子信号表示为Error，第一互调信号表示为X，该多个滤波系数表示为C(n)(n表示迭代次数)，则该多个滤波系数的解算公式可以表示为如下公式(3)。式中，mu表示每次迭代的迭代步长，conj表示共轭运算。
Figure PCTCN2021131414-appb-000004
进一步的，如图7所示，该装置还包括：与滤波电路30耦合的参数校准电路90。参数校准电路90具有两个输入端，这两个输入端分别用于接收第一互调信号和互调对消信号。参数校准电路90用于根据第一互调信号和互调对消信号确定滤波电路30的失配参数。该失配参数用于校准滤波电路30，以使各路滤波子电路的性能对齐。可选的，该失配参数包括以下至少一项：采样时刻失配值，增益失配值，直流失配值。
其中，上述滤波电路30在本质上是一种多相架构的滤波器，由于滤波电路30是模拟电路实现，在实际应用过程中多相之间会存在参数失配，比如采样时刻失配值、增益失配值和直流失配值等。假设滤波电路30包括M个滤波子电路31(即M相)，则参数适配会导致滤波电路30的输出信号在频谱上出现f s/M±f in的杂散。f in表示第一互调信号的频率。这些参数失配所导致的杂散能量满足如下公式(4)，X表示第一互调信号，Y表示互调对消信号，C表示滤波系数，
Figure PCTCN2021131414-appb-000005
表示卷积运算。
Figure PCTCN2021131414-appb-000006
假设上述失配参数表示为S。可以通过向X注入已知的抖动信号来确定失配参数的值。若已知的抖动信号表示为Δ，则注入两次已知抖动信号(Δ1和Δ2)后可以得到两个相应的杂散能量P Δ1以及P Δ2，该失配参数的失配值(或者称为校正值)满足如下公式(5)。式中，mu为每次迭代校正的步长。
Figure PCTCN2021131414-appb-000007
通过参数校准电路90来校正上述参数失配，可以减少杂散能量，提高对消性能。可选的，参数校准电路90还可以将确定的失配参数发送给上述控制器，以使控制器根据对应的失配参数矫正滤波电路30，从而保证该装置的对消性能不受杂散能量的影响。
进一步的，如图7所示，该装置还包括：功率放大器PA和双工器DUX。功率放大器PA耦合在第一耦合器10的输入端之前，功率放大器PA用于放大预失真电路70b的输出信号，或者用于放大第一业务信号，并输出信号到第一耦合器10。双工器DUX耦合在第四耦合器81的第二输出端或者第二耦合器40的输出端与天线之间。双工器DUX用于接收目标信号，并对该目标信号进行发射滤波处理，处理后的信号经过天线发射出去。
需要说明的是，该信号处理装置也可以不包括功率放大器PA和双工器DUX，比如，功率放大器PA和双工器DUX可以独立于该装置设置，该信号处理装置也可以称为前馈对消系统，本申请实施例对此不作具体限制。
本申请实施例提供的信号处理装置可以应用于多天线场景中，此时该信号处理装置的数量与功率放大器PA的数量可以是相同的。该信号处理装置的数量与天线的数量之间可以不存在绑定关系，即一个或者多个天线可对应一个该信号处理装置。
可选的，滤波电路30还可以与后失真电路70a、滤波系数计算电路80和参数校准电路90中的一个或多个集成在一个芯片中。
在一种示例中，如图8所示，滤波电路30与滤波系数计算电路80中的计算电路81和参数校准电路90集成在一个芯片中。在另一种示例中，如图9所示，滤波电路30与后失真电路70a、滤波系数计算电路80中的计算电路81和参数校准电路90集成在一个芯片中。
可选的，当计算电路81与滤波电路30集成在一个芯片中时，滤波系数计算电路80还可以包括耦合在第四耦合器82与计算电路81之间的第一开关电路83和第二开关电路84，第一开关电路83可以设置在该芯片之外，第二开关电路84可以集成在该芯片中，这样第一开关电路83与第二开关电路84之间的硬件链路还可以实现时分复用，即通过第一开关电路83与第二开关电路84的关断和导通可以实现多个第四耦合器81共用一个计算电路82，以提高该硬件链路的利用率，降低该装置的成本。
在本申请实施例中，第一耦合器10用于根据输入信号输出第一子信号和第二子信号，时延器20用于延迟第一子信号以输出延迟信号，第三耦合器60用于提取第二字信号中的第一互调信号，滤波电路30包括多个滤波子电路31和累加电路32，多个滤波子电路31分别用于在不同采样时刻对第一互调信号进行模拟域的采样和滤波处理，累加电路32用于累加该多个滤波子电路31输出的采样滤波信号以得到互调对消信号，第二耦合器40用于根据互调对消信号和延迟信号，输出目标信号。也即是，滤波电路30包括的多个滤波子电路31和累加电路32能够在模拟信号域通过多相的采样保持电路和幅相调节实现第一互调信号的高精度的模拟域采样和幅相调整。可以理解的是，多相的相数越多，即滤波子电路31的路数越多，第一互调信号在一个时刻的采样数据越多，幅相调整的精细度越高。并且，由于该滤波电路30在模拟域进行处理，不需要额外的模数转换，能够有效减小时延。因此能够在时延器20提供极小延迟量的情况下实现互调信号的均衡处理，进而在降低处理时延的同时，也提高了处理精度。此外，通过预失真电路70b和后失真电路70a还能够进一步提高接收频段中的互调信号对消效果，降低系统成本。通过滤波系数计算电路80和参数校准电路90还能够保证滤波电路30的高性能。
基于此，本申请实施例还提供一种芯片，该芯片包括滤波电路30。关于该滤波电路的具体描述可以参见上文中滤波电路30的描述，本申请实施例在此不再赘述。
另一方面，本申请实施例还提供一种通信设备，该通信设备可以为基站或者终端，该通信设备包括基带电路、以及上述图3a-图9任一图示所提供的信号处理装置。关于该信号处理装置的具体描述可以参见上文中的描述，本申请实施例在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的不同装置，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个装置，或一些特征可以忽略，或不执行。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是一个物理单元或多个物理单元，即可以位于一个地方，或者也可以分布到多个不同地方。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种信号处理装置，其特征在于，包括：第一分路模块、第一合路模块、时延器和滤波电路；
    所述第一分路模块与所述信号处理装置的信号源耦合，所述第一分路模块的输出端分别与所述时延器的输入端和所述滤波电路的输入端耦合；
    所述时延器的输出端和所述第一合路模块的第一输入端耦合；
    所述滤波电路的输出端和所述第一合路模块的第二输入端耦合；所述滤波电路包括多个滤波子电路和累加电路，所述多个滤波子电路的输出端与所述累加电路的输入端耦合。
  2. 根据权利要求1所述的装置，其特征在于，所述多个滤波子电路中的每个滤波子电路包括：
    采样保持电路和幅值调节电路，所述采样保持电路的输出端与所述幅值调节电路的第一输入端耦合。
  3. 根据权利要求2所述的装置，其特征在于，所述采样保持电路包括开关、电容和缓冲器，所述幅值调节电路包括乘法器；
    其中，所述开关的第一端为所述滤波子电路的输入端，所述开关的第二端、所述电容的第一端和所述缓冲器的第一端耦合，所述电容的第二端接地，所述缓冲器的第二端与所述乘法器的第一输入端耦合。
  4. 根据权利要求3所述的装置，其特征在于，所述幅值调节电路还包括：与所述乘法器的输出端耦合的跨导放大器。
  5. 根据权利要求1-4任一项所述的装置，其特征在于，所述滤波电路还包括：与所述累加电路的输出端耦合的可变增益放大器。
  6. 根据权利要求2-5任一项所述的装置，其特征在于，所述装置还包括：滤波系数计算电路；
    所述滤波系数计算电路的输出端与所述幅值调节电路的第二输入端耦合。
  7. 根据权利要求6所述的装置，其特征在于，所述滤波系数计算电路包括：第二分路模块和计算电路；
    所述第二分路模块的输入端与所述第一合路模块的所述输出端耦合，所述第二分路模块的第一输出端与所述计算电路的第一输入端耦合，所述计算电路的第二输入端与所述第二合路模块的所述输出端耦合。
  8. 根据权利要求1-7任一项所述的装置，其特征在于，所述装置还包括：与所述滤波电路耦合的参数校准电路。
  9. 根据权利要求1-8任一项所述的装置，其特征在于，所述装置还包括：第二合路模块，所述第二合路模块的第一输入端与所述第一分路模块的输出端耦合，所述第二合路模块的第二输入端与所述信号源耦合，所述第二合路模块的输出端和所述滤波电路的输入端耦合。
  10. 根据权利要求9所述的装置，其特征在于，所述装置还包括：衰减器，所述衰减器耦合在所述第一分路模块和所述第二合路模块之间。
  11. 根据权利要求1-8任一项所述的装置，其特征在于，所述装置还包括：第二合路模块，所述第二合路模块的第一输入端与所述滤波电路的所述输出端耦合，所述第二合路 模块的第二输入端与所述信号源耦合，所述第二合路模块的输出端与所述第一合路模块的所述第二输入端耦合。
  12. 根据权利要求11所述的装置，其特征在于，所述装置还包括：与所述第二合路模块的第二输入端耦合的放大器。
  13. 根据权利要求9-12任一项所述的装置，其特征在于，所述装置还包括：后失真电路，所述后失真电路耦合在所述信号源和所述第二合路模块之间。
  14. 根据权利要求13所述的装置，其特征在于，所述后失真电路包括：数字自适应滤波器。
  15. 根据权利要求9-12任一项所述的装置，其特征在于，所述第二合路模块替换为均衡器。
  16. 根据权利要求1-15任一项所述的装置，其特征在于，所述滤波电路集成在一个芯片中。
  17. 根据权利要求16所述的装置，其特征在于，所述滤波电路与以下至少一项集成在所述芯片中：所述滤波系数计算电路、所述参数校准电路、所述后失真电路。
  18. 根据权利要求1-17任一项所述的装置，其特征在于，所述装置还包括：耦合在所述第一分路模块的输入端和所述信号源之间的功率放大器，和与所述第一合路模块的输出端耦合的双工器。
  19. 一种通信设备，其特征在于，所述通信设备包括基带电路、以及如权利要求1-18任一项所述的信号处理装置。
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