WO2023083793A1 - Semiconductor chip and semiconductor component - Google Patents

Semiconductor chip and semiconductor component Download PDF

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Publication number
WO2023083793A1
WO2023083793A1 PCT/EP2022/081095 EP2022081095W WO2023083793A1 WO 2023083793 A1 WO2023083793 A1 WO 2023083793A1 EP 2022081095 W EP2022081095 W EP 2022081095W WO 2023083793 A1 WO2023083793 A1 WO 2023083793A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor chip
carrier
semiconductor
active region
connection structure
Prior art date
Application number
PCT/EP2022/081095
Other languages
German (de)
French (fr)
Inventor
Reith ANDREAS
Original Assignee
Ams-Osram International Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ams-Osram International Gmbh filed Critical Ams-Osram International Gmbh
Publication of WO2023083793A1 publication Critical patent/WO2023083793A1/en

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    • H01L2224/33517—Layer connectors having different functions including layer connectors providing primarily mechanical support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/54—Encapsulations having a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/56—Materials, e.g. epoxy or silicone resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • a semiconductor chip and a semiconductor component are specified.
  • a problem to be solved is to provide an improved semiconductor chip, for example a semiconductor chip for simple hermetic sealing.
  • a further problem to be solved is to provide a semiconductor component with such a semiconductor chip, in particular a semiconductor component with a hermetic seal.
  • the semiconductor chip is specified first.
  • the semiconductor chip has a substrate with a first side.
  • the substrate can be self-supporting.
  • the substrate can be the stabilizing component of the semiconductor chip.
  • the first side is, for example, a main side of the substrate, for example a side parallel to a main plane of extent of the substrate. In plan view, the first side can be rectangular or hexagonal or round or oval.
  • the substrate can Semiconductor substrate or a glass substrate or a plastic substrate be f.
  • the substrate has one or more of the following materials or consists of: silicon, SiC, GaN, sapphire, GaAs, glass, Plexiglas, quartz glass.
  • the semiconductor chip has an active area on the first side.
  • the active region can be arranged on the first side or formed on the first side, for example at least partially integrated into the substrate.
  • the active area can be formed at least partially from semiconductor material.
  • the semiconductor material can be silicon, silicon carbide or a II-IV compound semiconductor material.
  • the semiconductor material is, for example, a nitride compound semiconductor material, such as Al n In]__ nm Ga m N, or a phosphide compound semiconductor material, such as Al n In]__ nm Ga m P, or an arsenide compound semiconductor material, such as Al n In]__ nm Ga m As or Al n In]__ nm Ga m AsP, where 0 ⁇ n ⁇ 1, 0 ⁇ m ⁇ 1 and m + n ⁇ 1 in each case.
  • the semiconductor material can have dopants and additional components.
  • the essential components of the crystal lattice of the semiconductor layer sequence are specified, ie for example Al, As, Ga, In, N or P, even if these can be partially replaced and/or supplemented by small amounts of other substances.
  • the semiconductor chip has a connection structure on the first side.
  • the connection structure can be arranged in particular on the first side.
  • the connection structure forms for example a bump on the first side extending away from the substrate.
  • the connection structure can be designed to be continuous.
  • the interconnect structure includes or is made of a different material than the substrate.
  • an electrical functionality of the semiconductor chip is assigned to the active region.
  • the electrical functionality is performed during operation of the semiconductor chip.
  • the electrical functionality is the conduction of charge carriers and/or the generation of electromagnetic radiation.
  • charge carriers flow through the active area and/or recombine in the active area.
  • a diode or a transistor or a thyristor of the semiconductor chip can be formed with the active region.
  • the active region may have or consist of a pn junction or a single quantum well (SQW) or a multi-quantum well (MQW) structure.
  • connection structure laterally completely surrounds the active region. Viewed in plan view on the first side, the connection structure forms, for example, a track or barrier or frame completely surrounding the active area.
  • a lateral direction is presently a direction parallel to or along the first side.
  • the connection structure runs along the edge(s) of the first side 14 when viewed in plan view of the first side.
  • the width of the connection structure measured in a lateral direction perpendicular to the main direction of extension the connection structure, is for example at least 10 pm or at least 50 pm or at least 100 pm. Alternatively or additionally, the width can be at most 1 mm or at most 500 ⁇ m or at most 300 ⁇ m or at most 200 ⁇ m. For example, the width of the interconnect structure is constant along its path around the active area.
  • connection structure is set up for forming a mechanical connection between the semiconductor chip and a carrier by means of a connection material.
  • the connection by means of the connecting material is in particular such that the connecting material completely laterally surrounds the active region.
  • the connection structure already includes the connection material through which the connection to the carrier is established.
  • the connection structure can also be free of the connection material and, for example, be wettable with the connection material to produce the connection, for example more wettable than the regions of the semiconductor chip laterally next to the connection structure.
  • the connection is, for example, a material connection.
  • the semiconductor chip has a substrate with a first side, an active area on the first side, and an interconnection structure on the first side.
  • An electrical functionality of the semiconductor chip is assigned to the active region and is executed during the operation of the semiconductor chip.
  • the connection structure laterally completely surrounds the active area and is for the formation of a mechanical connection between the semiconductor chip and a carrier set up by means of a connecting material, so that the connecting material laterally completely surrounds the active region.
  • connection structure allows in particular a hermetic sealing of the active area directly at the chip level.
  • a hermetic seal at package level is then no longer necessary. This allows the package to be more compact, less complex and ultimately more cost-effective. Since the hermetic seal is created automatically when the semiconductor chip is connected to the carrier, the process flow is also simplified and more cost-effective.
  • connection structure is a metallic structure for forming a soldered connection between the carrier and the semiconductor chip.
  • the compound structure includes or consists of one or more of the following materials: Au, Ag, Sn, Pt, AuSn, InAuSn, BiSn, SnAgCu, SnPb.
  • connection structure has the connection material.
  • the connecting material can be a solder material.
  • the connection can be a soldered connection.
  • the soldering material can be one or more of the following soldering materials: AuSn, AgSn, InAuSn, BiSn, SnAgCu, SnPb.
  • the bonding structure includes all bonding material needed or used to form the bond to the carrier.
  • the connection structure can have a metallization, for Example of Au that does not melt during the soldering process.
  • the soldering material which is melted on during the soldering process, can be arranged on the metallization.
  • the metallization is then arranged, for example, between the substrate and the connecting material.
  • connection structure can also only have the metallization and/or be free of connection material or solder material.
  • connecting material can be provided separately when the connection is made to the carrier and/or can be arranged on the carrier.
  • connection structure protrudes beyond the active area in the direction away from the substrate, in particular if the connection structure has the connection material.
  • the active area can also protrude beyond the connection structure in the direction away from the substrate, for example if the connection structure only has the metallization and/or is free of the connection material.
  • the semiconductor chip is a surface-mountable chip.
  • several or all of the contact elements required for making electrical contact with the semiconductor chip are arranged on the first side.
  • the semiconductor chip is an optoelectronic semiconductor chip, for example a radiation-emitting semiconductor chip, in particular an LED chip.
  • the active area is an area in which electromagnetic radiation is generated during operation by recombination of charge carriers.
  • the active area is, for example, an active layer or an area of an active layer in which electromagnetic radiation is generated during operation.
  • the active layer is part of a semiconductor layer sequence of the semiconductor chip, which is arranged on the first side of the substrate.
  • the active region When the semiconductor chip is operated as intended, the active region generates, for example, electromagnetic radiation in the UV range or in the visible range or in the IR range.
  • the substrate can be transmissive or transparent for the generated radiation.
  • the electromagnetic radiation is UV-C radiation.
  • hermetic encapsulation using a potting material such as silicone is problematic, since this can become brittle as a result of the UV radiation.
  • Encapsulation can be done at the package level, for example with the help of a frame around the semiconductor chip and a glass lid that is soldered onto the frame.
  • This is space-consuming and relatively expensive.
  • the substrate is a growth substrate on which the active region, in particular the semiconductor layer sequence with the active layer, has grown, for example grown epitaxially.
  • the substrate is based on sapphire, GaN, GaAs, silicon, SiC.
  • the semiconductor chip is a thin-film chip.
  • a growth substrate on which the active region or the semiconductor layer sequence has grown is detached or thinned to such an extent that the rest of the growth substrate is no longer self-supporting, for example.
  • the substrate is then a different substrate from the growth substrate, for example a plastic substrate or a glass substrate.
  • connection structure forms a contact element of the semiconductor chip for making electrical contact with the semiconductor chip.
  • connection structure forms a cathode or an anode of the semiconductor chip.
  • the connection structure can be electrically conductively connected to the active area and/or the semiconductor layer sequence.
  • the connection structure is directly electrically conductively connected to an n-conducting or p-conducting region of the semiconductor layer sequence.
  • the connection structure overlaps with the active region and/or the semiconductor layer sequence in the lateral direction. In a plan view of the first side, the connection structure can therefore cover part of the active region and/or the semiconductor layer sequence.
  • connection structure is electrically isolated from the active area.
  • the connection structure is then spaced apart from the active region and/or the semiconductor layer sequence in the lateral direction.
  • the active region and/or the semiconductor layer sequence are electrically insulated from the connection structure by the substrate.
  • the active region and/or the semiconductor layer sequence can be surrounded by a cohesive, circumferential track made of the substrate.
  • the active region or the semiconductor layer sequence and the peripheral path made of the substrate can in turn be surrounded by the peripheral connection structure, viewed in plan view.
  • connection structure that is electrically insulated from the active region is not used, for example, to supply the semiconductor chip with charge carriers during operation of the semiconductor chip. For example, no charge carriers then flow through the connection structure during operation of the semiconductor chip.
  • the semiconductor chip already includes the connection structure in the unmounted state of the semiconductor chip, ie before the connection to the carrier is established.
  • the connection structure and/or the contact elements of the semiconductor chip can be exposed on the first side in the unmounted state of the semiconductor chip.
  • the semiconductor component comprises a semiconductor chip in accordance with one or more of the embodiments described here. All features disclosed in connection with the semiconductor chip are also disclosed for the semiconductor component and vice versa.
  • the semiconductor component comprises a carrier.
  • the carrier can in particular be a connection carrier with contact areas and/or act contact structures.
  • the carrier is, for example, a ceramic carrier or plastic carrier with integrated contact structures.
  • the carrier can also be a printed circuit board, for example a PCB.
  • the semiconductor chip is connected to the carrier by means of a connecting material.
  • the connection is in particular a material connection between the semiconductor chip and the carrier.
  • the connecting material can be an adhesive or a solder material.
  • the semiconductor chip is mounted on an upper side of the carrier, for example.
  • the active area is arranged between the carrier and the substrate of the semiconductor chip.
  • the connecting material laterally completely surrounds the active region of the semiconductor chip.
  • the connecting material is designed to be continuous, for example, that is to say free of holes and/or interruptions.
  • the active area is hermetically encapsulated by the carrier, the substrate and the connecting material.
  • the substrate, carrier, and interconnect material define a cavity in which the active region is located.
  • the cavity is hermetically sealed at the top and bottom by the carrier and the substrate and in the lateral direction by the connecting material.
  • the cavity is thus sealed off from the outside by the carrier, the substrate and the connecting material, in particular in a gas-tight manner, so that gas exchange between the cavity and the outside world is suppressed or prevented.
  • the active area can be from be spaced from the carrier or the top of the carrier.
  • the carrier has an upper side and an opposite lower side.
  • the upper side is, for example, the side facing the semiconductor chip.
  • the underside faces away from the semiconductor chip, for example.
  • the semiconductor chip is mounted on the carrier in particular in such a way that the active area faces the top side of the semiconductor chip.
  • the carrier has a base body and contact structures.
  • the contact structures can be routed from the top to the bottom of the carrier.
  • the contact structures each have or consist of a metal.
  • the base body can be formed from an electrically insulating material, for example ceramic and/or plastic.
  • the contact structures form contact areas on the upper side, for example.
  • the semiconductor chip is attached to the top side of the carrier.
  • the semiconductor chip is electrically connected to the contact structures on the upper side of the carrier.
  • the semiconductor chip is electrically connected to the contact structures on the upper side of the carrier.
  • the electrical connection between the contact structures of the carrier and the contact elements of the semiconductor chip is established, for example, by a soldering material or an electrically conductive adhesive.
  • the contact structures are at different electrical potentials during operation of the semiconductor component.
  • one contact structure is electrically conductively connected to a cathode of the semiconductor chip and another contact structure is electrically conductively connected to an anode of the semiconductor chip.
  • the contact structures are routed through the base body from the top to the bottom via feedthroughs.
  • the passages are designed in particular as holes in the base body, which can be completely surrounded by the base body in the lateral direction.
  • the feedthroughs of the contact structures overlap in the lateral direction with the active region and/or the semiconductor layer sequence.
  • “Overlapping in the lateral direction” means that the respective feedthrough is arranged below the active region or the semiconductor layer sequence. In a plan view of the top side of the carrier, the respective feedthrough is therefore partially or completely covered by the active region and/or the semiconductor layer sequence.
  • a first feedthrough overlaps a first contact structure laterally Direction with the active area and / or the Haiblei ter layer sequence.
  • a second feedthrough of a second contact structure is offset in the lateral direction with respect to the active region and/or the semiconductor layer sequence. This means that the second feedthrough does not overlap with the active region and/or the semiconductor layer sequence in the lateral direction. In a plan view of the top side, the second feedthrough is therefore not covered by the active region and/or the semiconductor layer sequence.
  • the second contact structure can also be led out laterally beyond the semiconductor chip on the upper side, that is to say project beyond the semiconductor chip in the lateral direction.
  • the semiconductor component described here can be used, for example, for disinfection or in the automotive sector, for example in a headlight.
  • FIGS. 1 and 2 show a first exemplary embodiment of the semiconductor chip in different views
  • FIG. 3 shows a second exemplary embodiment of the semiconductor chip in a cross-sectional view
  • FIGS. 4 and 6 show an exemplary embodiment of the semiconductor component in different views
  • FIG. 5 shows an exemplary embodiment of the carrier in a plan view
  • FIGS. 7 and 8 show another exemplary embodiment of the semiconductor chip in different views
  • FIG. 10 shows a further exemplary embodiment of the carrier in plan view.
  • FIG. 1 shows an exemplary embodiment of the semiconductor chip 100 in a cross-sectional view.
  • the semiconductor chip 100 is, for example, an optoelectronic semiconductor chip for generating electromagnetic radiation, for example for generating UV-C radiation.
  • the semiconductor chip 100 comprises a substrate 1, for example a sapphire substrate.
  • a semiconductor layer sequence 20 is arranged on a first side 10 of the substrate 1, for example grown epitaxially.
  • FIG. 2 shows a top view of the first side 10 of the substrate 1 .
  • the semiconductor layer sequence 20 includes an active layer 2 , which in the present case forms an active region 2 of the semiconductor chip 100 .
  • the semiconductor layer sequence 20 is based on AlGaN, for example.
  • Electromagnetic radiation for example UV-C radiation, is generated in the active layer 2 during the operation of the semiconductor chip 100 by recombination of charge carriers.
  • Contact elements 5 , 6 for electrically contacting the semiconductor layer sequence 20 are applied to the semiconductor layer sequence 20 .
  • the contact element 5 is, for example, a cathode and the contact element 6 is an anode.
  • the contact elements 5 , 6 are metallic, for example.
  • connection structure 3 presently consisting of a metallization 30 , is also applied to the first side 10 of the substrate 1 .
  • the metallization 30 contains or consists of Au, for example.
  • the connection structure 3 is arranged laterally completely and continuously around the semiconductor layer sequence 20 or the active region 2 .
  • the connection structure 3 is set up to form a connection to a carrier by means of a connection material.
  • the connection structure 3 is set up for wetting with the connection material, for example a soldering material, which then forms a material connection to the carrier.
  • connection material for example a soldering material
  • connection structure 3 is laterally spaced apart from the active region 2 or the semiconductor layer sequence 20 and is therefore also electrically insulated from the semiconductor layer sequence 20 or the active region 2 .
  • the connection structure 3 is therefore not set up for making electrical contact with the semiconductor layer sequence 20 .
  • no charge carriers flow through the connection structure 3 during the intended operation of the semiconductor chip 100 .
  • the contact elements 5 , 6 completely overlap with the semiconductor layer sequence 20 .
  • connection structure 3 here includes not only a metallization 30 but also the connection material 300 by means of which the material connection to the carrier is produced.
  • the connection material 300 here is, for example, a solder material such as AuSn.
  • the connection structure 3 protrudes beyond the active area 2 or the semiconductor layer sequence 20 in the direction away from the first side 10 .
  • the contact elements 5 , 6 could already be wetted with solder material.
  • FIGS. 1 to 3 show exemplary embodiments of a semiconductor chip 100 in the unmounted state, that is to say before a mechanical and electrical connection to a carrier.
  • FIG. 4 shows an exemplary embodiment of a semiconductor component 1000 in which the semiconductor chip 100 from FIGS. 1 and 2 or from FIG. In this case, the semiconductor chip 100 is mounted with the first side 10 first on the top side 201 of the carrier 200 .
  • the connecting material 300 wets the metallization 30 and completely surrounds the active region 2 or the semiconductor layer sequence 20 in the lateral direction.
  • the connecting material 300 wets a metallization 230 of the carrier 200 on the upper side 201 .
  • the connection material 300 that completely laterally surrounds the active region 2 , the carrier 200 and the substrate 1 enclose a cavity and hermetically seal it from the outside.
  • the active area 2 is arranged in the cavity and is thus hermetically encapsulated and protected from external influences.
  • the contact elements 5, 6 of the semiconductor chip 1 are electrically conductively connected to contact structures 205, 206 of the carrier 200, in the present case also via a soldered connection.
  • the contact structures 205 , 206 are metallic, for example.
  • the contact structures 205 , 206 extend from the top 201 through bushings 207 , 208 of a base body 204 of the carrier 200 to a bottom 202 of the carrier 200 .
  • the base body 204 is made of ceramic or plastic, for example.
  • the feedthroughs 207 , 208 overlap in the lateral direction with the active region 2 or the semiconductor layer sequence 20 of the semiconductor chip 100 .
  • the contact structures 205 , 206 extend laterally beyond the semiconductor chip 100 .
  • the Metallization 230 of the carrier 200 is led out laterally beyond the semiconductor chip 100 on the upper side 201 .
  • FIG. 6 shows the semiconductor component 1000 from FIG. 4 in a plan view of the top side 201 of the carrier 200 .
  • the substrate 1 is drawn semi-transparent.
  • FIG. 5 shows the carrier 200 from FIGS. 4 and 6 in a plan view of the upper side 201 . It can be seen here that the contact structures 205 , 206 form contact areas on the upper side 201 . The metallization 230 of the carrier 200 runs continuously and completely around the contact areas.
  • Mounting surfaces 209 for at least one protective element, for example for ESD structures, are also formed on the upper side 201 of the carrier 200 .
  • FIG. 7 shows a further exemplary embodiment of a semiconductor chip 100 in a cross-sectional view.
  • FIG. 8 shows the exemplary embodiment in a top view of the first side 10 of the substrate 1 .
  • the connection structure 3 here again realized by a metallization 30 ) is not electrically isolated from the active region 2 or the semiconductor layer sequence 20 . Rather, the connection structure 3 makes contact with the semiconductor layer sequence 20 and forms a contact element 6 for making electrical contact with the semiconductor layer sequence 20 .
  • the connection structure 3 overlaps with the semiconductor layer sequence 20 in the lateral direction. As can be seen in FIG. 8, the connection structure 3 partially covers the semiconductor layer sequence 20 on one side.
  • connection structure 3 is spaced apart from the semiconductor layer sequence 20 in the lateral direction.
  • connection structure 3 could also cover the semiconductor layer sequence 20 on more than just one side, for example on all four sides, and thus make electrical contact with the semiconductor layer sequence 20 on all four sides, for example.
  • FIG. 9 shows a further exemplary embodiment of the semiconductor component 1000.
  • the semiconductor chip 100 of FIGS. 7 and 8 is mounted on a carrier 200 .
  • the connecting material 300 together with the carrier 200 and the substrate 1 hermetically encapsulates the semiconductor layer sequence 20 or the active region 2 .
  • the other feedthrough 208, namely the feedthrough for the contact structure 206, which is electrically conductively connected to the connection structure 3 or the contact element 6, is offset laterally with respect to the active region 2 or the semiconductor layer sequence 20 and therefore does not overlap with the semiconductor layer sequence 20 in the lateral direction or the active area 2 .
  • FIG. 11 again shows the semiconductor component 1000 of FIG. 9 in a plan view of the upper side 201 of the carrier 200 , the substrate 1 of the semiconductor chip 100 being shown as transparent for reasons of better illustration.
  • FIG. 10 shows the carrier 200 of FIGS. 9 and 11 in a plan view of the upper side 201 .
  • the contact area of the contact element 205 is here laterally completely surrounded by the contact area of the contact element 206 .
  • the contact area of the contact structure 206 simultaneously forms the metallization 230 for wetting with the connecting material 300 .
  • the invention is not limited to the description based on the exemplary embodiments. Rather, the invention includes every new feature and every combination of features, which in particular includes every combination of features in the patent claims, even if these features or this combination themselves are not explicitly stated in the patent claims or exemplary embodiments.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Abstract

In at least one embodiment, the semiconductor chip (100) comprises a substrate (1) having a first side (10), an active region (2) on the first side and a connecting structure (3) on the first side. The active region is assigned an electrical functionality of the semiconductor chip, which is executed during operation of the semiconductor chip. The connecting structure laterally completely surrounds the active region and is designed to form a mechanical connection between the semiconductor chip and a carrier (200) by means of a connecting material (300), such that the connecting material laterally completely surrounds the active region.

Description

Beschreibung Description
HALBLEITERCHIP UND HALBLEITERBAUTEIL SEMICONDUCTOR CHIP AND COMPONENT
Es werden ein Halbleiterchip und ein Halbleiterbauteil angegeben . A semiconductor chip and a semiconductor component are specified.
Eine zu lösende Aufgabe besteht darin, einen verbesserten Halbleiterchip, beispielsweise einen Halbleiterchip für eine einfache hermetische Abdichtung, bereitzustellen . Eine weitere zu lösende Aufgabe besteht darin, ein Halbleiterbauteil mit einem solchen Halbleiterchip, insbesondere ein Halbleiterbauteil mit einer hermetischen Abdichtung, bereitzustellen . A problem to be solved is to provide an improved semiconductor chip, for example a semiconductor chip for simple hermetic sealing. A further problem to be solved is to provide a semiconductor component with such a semiconductor chip, in particular a semiconductor component with a hermetic seal.
Diese Aufgaben werden unter anderem durch die Gegenstände des unabhängigen Patentanspruchs 1 und des Patentanspruchs 11 gelöst . Vorteilhafte Ausgestaltungen und Weiterbildungen sind Gegenstand der übrigen abhängigen Patentansprüche und gehen weiterhin aus der nachfolgenden Beschreibung und den Figuren hervor . These objects are achieved, inter alia, by the subject matter of independent patent claim 1 and patent claim 11 . Advantageous refinements and developments are the subject matter of the remaining dependent patent claims and are also evident from the following description and the figures.
Zunächst wird der Halbleiterchip angegeben . The semiconductor chip is specified first.
Gemäß zumindest einer Aus führungs form weist der Halbleiterchip ein Substrat mit einer ersten Seite auf . Das Substrat kann selbsttragend sein . Insbesondere kann das Substrat die stabilisierende Komponente des Halbleiterchips sein . Bei der ersten Seite handelt es sich beispielsweise um eine Hauptseite des Substrats , zum Beispiel eine Seite parallel zu einer Haupterstreckungsebene des Substrats . In Draufsicht kann die erste Seite rechteckig oder sechseckig oder rund oder oval ausgebildet sein . Das Substrat kann ein Halbleitersubstrat oder ein Glassubstrat oder ein Kunststof f substrat sein . Zum Beispiel weist das Substrat eines oder mehrere der folgenden Materialien auf oder besteht daraus : Sili zium, SiC, GaN, Saphir, GaAs , Glas , Plexiglas , Quarzglas . According to at least one embodiment, the semiconductor chip has a substrate with a first side. The substrate can be self-supporting. In particular, the substrate can be the stabilizing component of the semiconductor chip. The first side is, for example, a main side of the substrate, for example a side parallel to a main plane of extent of the substrate. In plan view, the first side can be rectangular or hexagonal or round or oval. The substrate can Semiconductor substrate or a glass substrate or a plastic substrate be f. For example, the substrate has one or more of the following materials or consists of: silicon, SiC, GaN, sapphire, GaAs, glass, Plexiglas, quartz glass.
Gemäß zumindest einer Aus führungs form weist der Halbleiterchip einen aktiven Bereich an der ersten Seite auf . Der aktive Bereich kann auf der ersten Seite angeordnet sein oder an der ersten Seite ausgebildet sein, zum Beispiel zumindest teilweise in das Substrat integriert sein . Der aktive Bereich kann zumindest teilweise aus Halbleitermaterial gebildet sein . Bei dem Halbleitermaterial kann es sich um Sili zium, Sili ziumcarbid oder ein I I I-V- Verbindungshalbleitermaterial handeln . Bei dem Halbleitermaterial handelt es sich zum Beispiel um ein Nitrid-Verbindungshalbleitermaterial , wie AlnIn]__n-mGamN, oder um ein Phosphid-Verbindungshalbleitermaterial , wie AlnIn]__n-mGamP, oder um ein Arsenid- Verbindungshalbleitermaterial , wie AlnIn]__n-mGamAs oder AlnIn]__n-mGamAsP, wobei j eweils 0 < n < 1 , 0 < m < 1 und m + n < 1 ist . Dabei kann das Halbleitermaterial Dotierstof fe sowie zusätzliche Bestandteile aufweisen . Der Einfachheit halber sind j edoch nur die wesentlichen Bestandteile des Kristallgitters der Halbleiterschichtenfolge , also zum Beispiel Al , As , Ga, In, N oder P, angegeben, auch wenn diese teilweise durch geringe Mengen weiterer Stof fe ersetzt und/oder ergänzt sein können . According to at least one embodiment, the semiconductor chip has an active area on the first side. The active region can be arranged on the first side or formed on the first side, for example at least partially integrated into the substrate. The active area can be formed at least partially from semiconductor material. The semiconductor material can be silicon, silicon carbide or a II-IV compound semiconductor material. The semiconductor material is, for example, a nitride compound semiconductor material, such as Al n In]__ nm Ga m N, or a phosphide compound semiconductor material, such as Al n In]__ nm Ga m P, or an arsenide compound semiconductor material, such as Al n In]__ nm Ga m As or Al n In]__ nm Ga m AsP, where 0 < n < 1, 0 < m < 1 and m + n < 1 in each case. In this case, the semiconductor material can have dopants and additional components. For the sake of simplicity, however, only the essential components of the crystal lattice of the semiconductor layer sequence are specified, ie for example Al, As, Ga, In, N or P, even if these can be partially replaced and/or supplemented by small amounts of other substances.
Gemäß zumindest einer Aus führungs form weist der Halbleiterchip eine Verbindungstruktur an der ersten Seite auf . Die Verbindungsstruktur kann insbesondere auf der ersten Seite angeordnet sein . Die Verbindungstruktur bildet beispielsweise eine Erhebung auf der ersten Seite , die sich von dem Substrat weg erstreckt . Die Verbindungstruktur kann zusammenhängend ausgebildet sein . Zum Beispiel umfasst die Verbindungstruktur ein anderes Material als das Substrat oder besteht aus einem anderen Material als das Substrat . According to at least one embodiment, the semiconductor chip has a connection structure on the first side. The connection structure can be arranged in particular on the first side. The connection structure forms for example a bump on the first side extending away from the substrate. The connection structure can be designed to be continuous. For example, the interconnect structure includes or is made of a different material than the substrate.
Gemäß zumindest einer Aus führungs form ist dem aktiven Bereich eine elektrische Funktionalität des Halbleiterchips zugeordnet . Die elektrische Funktionalität wird während des Betriebs des Halbleiterchips ausgeführt . Beispielsweise ist die elektrische Funktionalität die Leitung von Ladungsträger und/oder die Erzeugung elektromagnetischer Strahlung . Zum Beispiel fließen während des Betriebs des Halbleiterchips Ladungsträger durch den aktiven Bereich und/oder rekombinieren im aktiven Bereich . Mit dem aktiven Bereich kann beispielsweise eine Diode oder ein Transistor oder ein Thyristor des Halbleiterchips gebildet sein . Der aktive Bereich kann einen pn-Übergang oder einen einzelnen Quantentopf ( SQW) oder eine Multi-Quantentopfstruktur (MQW) aufweisen oder daraus bestehen . According to at least one embodiment, an electrical functionality of the semiconductor chip is assigned to the active region. The electrical functionality is performed during operation of the semiconductor chip. For example, the electrical functionality is the conduction of charge carriers and/or the generation of electromagnetic radiation. For example, during operation of the semiconductor chip, charge carriers flow through the active area and/or recombine in the active area. For example, a diode or a transistor or a thyristor of the semiconductor chip can be formed with the active region. The active region may have or consist of a pn junction or a single quantum well (SQW) or a multi-quantum well (MQW) structure.
Gemäß zumindest einer Aus führungs form umgibt die Verbindungstruktur den aktiven Bereich lateral vollständig . In Draufsicht auf die erste Seite betrachtet bildet die Verbindungstruktur zum Beispiel eine den aktiven Bereich vollständig umgebende Bahn oder Barriere oder Rahmen . Eine laterale Richtung ist vorliegend eine Richtung parallel zur oder entlang der ersten Seite . Zum Beispiel verläuft die Verbindungstruktur in Draufsicht auf die erste Seite gesehen entlang der Kante (n) der ersten Seite . According to at least one embodiment, the connection structure laterally completely surrounds the active region. Viewed in plan view on the first side, the connection structure forms, for example, a track or barrier or frame completely surrounding the active area. A lateral direction is presently a direction parallel to or along the first side. For example, the connection structure runs along the edge(s) of the first side 14 when viewed in plan view of the first side.
Die Breite der Verbindungstruktur, gemessen in einer lateralen Richtung senkrecht zur Haupterstreckungsrichtung der Verbindungstruktur, ist beispielsweise zumindest 10 pm oder zumindest 50 pm oder zumindest 100 pm . Alternativ oder zusätzlich kann die Breite höchstens 1 mm oder höchstens 500 pm oder höchstens 300 pm oder höchstens 200 pm betragen . Zum Beispiel ist die Breite der Verbindungsstruktur entlang ihres Verlaufs um den aktiven Bereich konstant . The width of the connection structure, measured in a lateral direction perpendicular to the main direction of extension the connection structure, is for example at least 10 pm or at least 50 pm or at least 100 pm. Alternatively or additionally, the width can be at most 1 mm or at most 500 μm or at most 300 μm or at most 200 μm. For example, the width of the interconnect structure is constant along its path around the active area.
Gemäß zumindest einer Aus führungs form ist die Verbindungstruktur für die Bildung einer mechanischen Verbindung zwischen dem Halbleiterchip und einem Träger mittels eines Verbindungsmaterials eingerichtet . Die Verbindung mittels des Verbindungsmaterials ist dabei insbesondere so , dass das Verbindungsmaterial den aktiven Bereich lateral vollständig umgibt . Beispielsweise umfasst die Verbindungstruktur bereits das Verbindungsmaterial , durch welches die Verbindung zum Träger hergestellt wird . Alternativ kann die Verbindungstruktur auch frei von dem Verbindungsmaterial sein, und zum Beispiel mit dem Verbindungsmaterial zur Herstellung der Verbindung benetzbar sein, beispielsweise stärker benetzbar als die Bereiche des Halbleiterchips lateral neben der Verbindungsstruktur . Bei der Verbindung handelt es sich zum Beispiel um eine stof f schlüssige Verbindung . In accordance with at least one embodiment, the connection structure is set up for forming a mechanical connection between the semiconductor chip and a carrier by means of a connection material. In this case, the connection by means of the connecting material is in particular such that the connecting material completely laterally surrounds the active region. For example, the connection structure already includes the connection material through which the connection to the carrier is established. Alternatively, the connection structure can also be free of the connection material and, for example, be wettable with the connection material to produce the connection, for example more wettable than the regions of the semiconductor chip laterally next to the connection structure. The connection is, for example, a material connection.
In mindestens einer Aus führungs form weist der Halbleiterchip ein Substrat mit einer ersten Seite , einen aktiven Bereich an der ersten Seite und eine Verbindungstruktur an der ersten Seite auf . Dem aktiven Bereich ist eine elektrische Funktionalität des Halbleiterchips zugeordnet , die während des Betriebs des Halbleiterchips ausgeführt wird . Die Verbindungstruktur umgibt den aktiven Bereich lateral vollständig und ist für die Bildung einer mechanischen Verbindung zwischen dem Halbleiterchip und einem Träger mittels eines Verbindungsmaterials eingerichtet , so dass das Verbindungsmaterial den aktiven Bereich lateral vollständig umgibt . In at least one embodiment, the semiconductor chip has a substrate with a first side, an active area on the first side, and an interconnection structure on the first side. An electrical functionality of the semiconductor chip is assigned to the active region and is executed during the operation of the semiconductor chip. The connection structure laterally completely surrounds the active area and is for the formation of a mechanical connection between the semiconductor chip and a carrier set up by means of a connecting material, so that the connecting material laterally completely surrounds the active region.
Eine solche Verbindungstruktur ermöglicht insbesondere eine hermetische Abdichtung des aktiven Bereichs direkt auf Chipebene . Eine hermetische Abdichtung auf Package-Level ist dann nicht mehr nötig . Dadurch kann das Package kompakter, weniger komplex und letztendlich kostengünstiger gestaltet werden . Da die hermetische Abdichtung beim Verbinden des Halbleiterchips mit dem Träger automatisch hergestellt wird, wird auch der Prozess fluss vereinfacht und kostengünstiger . Such a connection structure allows in particular a hermetic sealing of the active area directly at the chip level. A hermetic seal at package level is then no longer necessary. This allows the package to be more compact, less complex and ultimately more cost-effective. Since the hermetic seal is created automatically when the semiconductor chip is connected to the carrier, the process flow is also simplified and more cost-effective.
Gemäß zumindest einer Aus führungs form ist die Verbindungstruktur eine metallische Struktur zur Bildung einer Lötverbindung zwischen dem Träger und dem Halbleiterchip . Zum Beispiel umfasst oder besteht die Verbindungstruktur aus einem oder mehreren der folgenden Materialien : Au, Ag, Sn, Pt , AuSn, InAuSn, BiSn, SnAgCu, SnPb . In accordance with at least one embodiment, the connection structure is a metallic structure for forming a soldered connection between the carrier and the semiconductor chip. For example, the compound structure includes or consists of one or more of the following materials: Au, Ag, Sn, Pt, AuSn, InAuSn, BiSn, SnAgCu, SnPb.
Gemäß zumindest einer Aus führungs form weist die Verbindungstruktur das Verbindungsmaterial auf . Das Verbindungsmaterial kann ein Lotmaterial sein . Entsprechend kann die Verbindung eine Lötverbindung sein . Bei dem Lotmaterial kann es sich um eines oder mehrere der folgenden Lotmaterialien handeln : AuSn, AgSn, InAuSn, BiSn, SnAgCu, SnPb . According to at least one embodiment, the connection structure has the connection material. The connecting material can be a solder material. Correspondingly, the connection can be a soldered connection. The soldering material can be one or more of the following soldering materials: AuSn, AgSn, InAuSn, BiSn, SnAgCu, SnPb.
Zum Beispiel umfasst die Verbindungstruktur das gesamte für die Bildung der Verbindung zum Träger benötigte oder verwendete Verbindungsmaterial . Insbesondere kann die Verbindungstruktur eine Metallisierung aufweisen, zum Beispiel aus Au, die beim Lötprozess nicht schmil zt . Auf der Metallisierung kann das Lotmaterial angeordnet sein, welches bei dem Lötprozess auf geschmol zen wird . Die Metallisierung ist dann zum Beispiel zwischen dem Substrat und dem Verbindungsmaterial angeordnet . For example, the bonding structure includes all bonding material needed or used to form the bond to the carrier. In particular, the connection structure can have a metallization, for Example of Au that does not melt during the soldering process. The soldering material, which is melted on during the soldering process, can be arranged on the metallization. The metallization is then arranged, for example, between the substrate and the connecting material.
Alternativ kann die Verbindungstruktur auch nur die Metallisierung aufweisen und/oder frei von Verbindungsmaterial beziehungsweise Lotmaterial sein . In diesem Fall kann das Verbindungsmaterial bei der Herstellung der Verbindung zum Träger separat bereitgestellt werden und/oder auf dem Träger angeordnet sein . Alternatively, the connection structure can also only have the metallization and/or be free of connection material or solder material. In this case, the connecting material can be provided separately when the connection is made to the carrier and/or can be arranged on the carrier.
Zum Beispiel überragt die Verbindungsstruktur in Richtung weg vom Substrat den aktiven Bereich, insbesondere wenn die Verbindungsstruktur das Verbindungsmaterial aufweist . For example, the connection structure protrudes beyond the active area in the direction away from the substrate, in particular if the connection structure has the connection material.
Alternativ kann aber auch der aktive Bereich die Verbindungsstruktur in Richtung weg vom Substrat überragen, zum Beispiel wenn die Verbindungsstruktur nur die Metallisierung aufweist und/oder frei von dem Verbindungsmaterial ist . Alternatively, however, the active area can also protrude beyond the connection structure in the direction away from the substrate, for example if the connection structure only has the metallization and/or is free of the connection material.
Gemäß zumindest einer Aus führungs form ist der Halbleiterchip ein oberflächenmontierbarer Chip . Insbesondere sind mehrere oder alle für die elektrische Kontaktierung des Halbleiterchips notwendigen Kontaktelemente auf der ersten Seite angeordnet . According to at least one embodiment, the semiconductor chip is a surface-mountable chip. In particular, several or all of the contact elements required for making electrical contact with the semiconductor chip are arranged on the first side.
Gemäß zumindest einer Aus führungs form ist der Halbleiterchip ein optoelektronischer Halbleiterchip, zum Beispiel ein strahlungsemittierender Halbleiterchip, insbesondere ein LED- Chip . Gemäß zumindest einer Aus führungs form ist der aktive Bereich ein Bereich, in dem im Betrieb elektromagnetische Strahlung durch Rekombination von Ladungsträger erzeugt wird . Der aktive Bereich ist zum Beispiel eine aktive Schicht oder ein Bereich einer aktiven Schicht , in dem im Betrieb elektromagnetische Strahlung erzeugt wird . Zum Beispiel ist die aktive Schicht Teil einer Halbleiterschichtenfolge des Halbleiterchips , die auf der ersten Seite des Substrats angeordnet ist . Der aktive Bereich erzeugt im bestimmungsgemäßen Betrieb des Halbleiterchips zum Beispiel elektromagnetische Strahlung im UV-Bereich oder im sichtbaren Bereich oder im IR-Bereich . Das Substrat kann für die erzeugte Strahlung durchlässig oder transparent sein . In accordance with at least one embodiment, the semiconductor chip is an optoelectronic semiconductor chip, for example a radiation-emitting semiconductor chip, in particular an LED chip. According to at least one embodiment, the active area is an area in which electromagnetic radiation is generated during operation by recombination of charge carriers. The active area is, for example, an active layer or an area of an active layer in which electromagnetic radiation is generated during operation. For example, the active layer is part of a semiconductor layer sequence of the semiconductor chip, which is arranged on the first side of the substrate. When the semiconductor chip is operated as intended, the active region generates, for example, electromagnetic radiation in the UV range or in the visible range or in the IR range. The substrate can be transmissive or transparent for the generated radiation.
Gemäß zumindest einer Aus führungs form ist die elektromagnetische Strahlung UV-C-Strahlung . Insbesondere für Strahlung im UV-Bereich ist eine hermetische Verkapselung mithil fe eines Vergussmaterials , wie Silikon, problematisch, da dieses durch die UV-Strahlung spröde werden kann . Eine Verkapselung kann auf Package-Ebene erfolgen, zum Beispiel mit Hil fe eines Rahmens um den Halbleiterchip und einem Glasdeckel , der auf den Rahmen gelötet ist . Dies ist j edoch platzaufwendig und verhältnismäßig teuer . Eine Verkapselung mit Hil fe einer zum Halbleiterchip gehörenden Verbindungstruktur, wie sie vorliegend vorgeschlagen wird, ist zum Beispiel platzsparender und kostengünstiger . According to at least one embodiment, the electromagnetic radiation is UV-C radiation. In particular for radiation in the UV range, hermetic encapsulation using a potting material such as silicone is problematic, since this can become brittle as a result of the UV radiation. Encapsulation can be done at the package level, for example with the help of a frame around the semiconductor chip and a glass lid that is soldered onto the frame. However, this is space-consuming and relatively expensive. An encapsulation with the aid of a connection structure belonging to the semiconductor chip, as proposed here, saves space and is cheaper, for example.
Gemäß zumindest einer Aus führungs form ist das Substrat ein Aufwachssubstrat , auf dem der aktive Bereich, insbesondere die Halbleiterschichtenfolge mit der aktiven Schicht , gewachsen ist , zum Beispiel epitaktisch gewachsen ist . Beispielsweise basiert das Substrat auf Saphir, GaN, GaAs , Sili zium, SiC . Gemäß zumindest einer Aus führungs form ist der Halbleiterchip ein Dünnfilm-Chip . Ein Aufwachssubstrat , auf dem der aktive Bereich oder die Halbleiterschichtenfolge gewachsen ist , ist in diesem Fall abgelöst oder so stark gedünnt , dass der Rest des Aufwachssubstrats zum Beispiel nicht mehr selbsttragend ist . Das Substrat ist dann ein von dem Aufwachssubstrat verschiedenes Substrat , beispielsweise ein Kunststof f substrat oder ein Glassubstrat . In accordance with at least one embodiment, the substrate is a growth substrate on which the active region, in particular the semiconductor layer sequence with the active layer, has grown, for example grown epitaxially. For example, the substrate is based on sapphire, GaN, GaAs, silicon, SiC. According to at least one embodiment, the semiconductor chip is a thin-film chip. In this case, a growth substrate on which the active region or the semiconductor layer sequence has grown is detached or thinned to such an extent that the rest of the growth substrate is no longer self-supporting, for example. The substrate is then a different substrate from the growth substrate, for example a plastic substrate or a glass substrate.
Gemäß zumindest einer Aus führungs form bildet die Verbindungstruktur ein Kontaktelement des Halbleiterchips zur elektrischen Kontaktierung des Halbleiterchips . According to at least one embodiment, the connection structure forms a contact element of the semiconductor chip for making electrical contact with the semiconductor chip.
Beispielsweise bildet die Verbindungstruktur eine Kathode oder eine Anode des Halbleiterchips . Die Verbindungstruktur kann elektrisch leitend mit dem aktiven Bereich und/oder der Halbleiterschichtenfolge verbunden sein . Beispielsweise ist die Verbindungstruktur mit einem n-leitenden oder p-leitenden Bereich der Halbleiterschichtenfolge direkt elektrisch leitend verbunden . Beispielsweise überlappt in lateraler Richtung die Verbindungstruktur mit dem aktiven Bereich und/oder der Halbleiterschichtenfolge . In Draufsicht auf die erste Seite kann die Verbindungsstruktur also einen Teil des aktiven Bereichs und/oder der Halbleiterschichtenfolge überdecken . For example, the connection structure forms a cathode or an anode of the semiconductor chip. The connection structure can be electrically conductively connected to the active area and/or the semiconductor layer sequence. For example, the connection structure is directly electrically conductively connected to an n-conducting or p-conducting region of the semiconductor layer sequence. For example, the connection structure overlaps with the active region and/or the semiconductor layer sequence in the lateral direction. In a plan view of the first side, the connection structure can therefore cover part of the active region and/or the semiconductor layer sequence.
Gemäß zumindest einer Aus führungs form ist die Verbindungstruktur von dem aktiven Bereich elektrisch isoliert . Zum Beispiel ist die Verbindungstruktur dann von dem aktiven Bereich und/oder der Halbleiterschichtenfolge in lateraler Richtung beabstandet . Beispielsweise sind der aktive Bereich und/oder die Halbleiterschichtenfolge durch das Substrat von der Verbindungstruktur elektrisch isoliert . In Draufsicht auf die erste Seite betrachtet können der aktive Bereich und/oder die Halbleiterschichtenfolge von einer zusammenhängenden, umlaufenden Bahn aus dem Substrat umgeben sein . Der aktive Bereich beziehungsweise die Halbleiterschichtenfolge und die umlaufende Bahn aus dem Substrat können in der Draufsicht betrachtet wiederum von der umlaufenden Verbindungstruktur umgeben sein . According to at least one embodiment, the connection structure is electrically isolated from the active area. For example, the connection structure is then spaced apart from the active region and/or the semiconductor layer sequence in the lateral direction. For example, the active region and/or the semiconductor layer sequence are electrically insulated from the connection structure by the substrate. Viewed in a plan view of the first side, the active region and/or the semiconductor layer sequence can be surrounded by a cohesive, circumferential track made of the substrate. The active region or the semiconductor layer sequence and the peripheral path made of the substrate can in turn be surrounded by the peripheral connection structure, viewed in plan view.
Eine von dem aktiven Bereich elektrisch isolierte Verbindungstruktur wird beispielsweise im Betrieb des Halbleiterchips nicht zur Versorgung des Halbleiterchips mit Ladungsträger verwendet . Beispielsweise fließen durch die Verbindungstruktur im Betrieb des Halbleiterchips dann keine Ladungsträger . A connection structure that is electrically insulated from the active region is not used, for example, to supply the semiconductor chip with charge carriers during operation of the semiconductor chip. For example, no charge carriers then flow through the connection structure during operation of the semiconductor chip.
Der Halbleiterchip umfasst die Verbindungstruktur bereits im unmontierten Zustand des Halbleiterchips , also bevor die Verbindung zum Träger hergestellt ist . Die Verbindungstruktur und/oder die Kontaktelemente des Halbleiterchips können im unmontierten Zustand des Halbleiterchips an der ersten Seite freiliegen . The semiconductor chip already includes the connection structure in the unmounted state of the semiconductor chip, ie before the connection to the carrier is established. The connection structure and/or the contact elements of the semiconductor chip can be exposed on the first side in the unmounted state of the semiconductor chip.
Als nächstes wird das Halbleiterbauteil angegeben . Next, the semiconductor component is specified.
Gemäß zumindest einer Aus führungs form umfasst das Halbleiterbauteil einen Halbleiterchip gemäß einer oder mehreren der hier beschriebenen Aus führungs formen . Alle im Zusammenhang mit dem Halbleiterchip of fenbarten Merkmale sind auch für das Halbleiterbauteil of fenbart und umgekehrt . In accordance with at least one embodiment, the semiconductor component comprises a semiconductor chip in accordance with one or more of the embodiments described here. All features disclosed in connection with the semiconductor chip are also disclosed for the semiconductor component and vice versa.
Gemäß zumindest einer Aus führungs form umfasst das Halbleiterbauteil einen Träger . Bei dem Träger kann es sich insbesondere um einen Anschlussträger mit Kontaktbereichen und/oder Kontaktstrukturen handeln . Der Träger ist zum Beispiel ein Keramikträger oder Kunststof f träger mit integrierten Kontaktstrukturen . Bei dem Träger kann es sich auch um eine Leiterplatte , zum Beispiel ein PCB, handeln . In accordance with at least one embodiment, the semiconductor component comprises a carrier. The carrier can in particular be a connection carrier with contact areas and/or act contact structures. The carrier is, for example, a ceramic carrier or plastic carrier with integrated contact structures. The carrier can also be a printed circuit board, for example a PCB.
Gemäß zumindest einer Aus führungs form ist der Halbleiterchip mittels eines Verbindungsmaterials mit dem Träger verbunden . Bei der Verbindung handelt es sich insbesondere um eine stof f schlüssige Verbindung zwischen dem Halbleiterchip und dem Träger . Das Verbindungsmaterial kann ein Kleber oder ein Lotmaterial sein . Der Halbleiterchip ist zum Beispiel auf einer Oberseite des Trägers montiert . Insbesondere ist dabei der aktive Bereich zwischen dem Träger und dem Substrat des Halbleiterchips angeordnet . According to at least one embodiment, the semiconductor chip is connected to the carrier by means of a connecting material. The connection is in particular a material connection between the semiconductor chip and the carrier. The connecting material can be an adhesive or a solder material. The semiconductor chip is mounted on an upper side of the carrier, for example. In particular, the active area is arranged between the carrier and the substrate of the semiconductor chip.
Gemäß zumindest einer Aus führungs form umgibt das Verbindungsmaterial den aktiven Bereich des Halbleiterchips lateral vollständig . Das Verbindungsmaterial ist beispielsweise zusammenhängend ausgebildet , also frei von Löchern und/oder Unterbrechungen . In accordance with at least one embodiment, the connecting material laterally completely surrounds the active region of the semiconductor chip. The connecting material is designed to be continuous, for example, that is to say free of holes and/or interruptions.
Gemäß zumindest einer Aus führungs form ist der aktive Bereich von dem Träger, dem Substrat und dem Verbindungsmaterial hermetisch verkapselt . Zum Beispiel definieren das Substrat , der Träger und das Verbindungsmaterial eine Kavität , in dem der aktive Bereich angeordnet ist . Die Kavität ist nach oben und unten durch den Träger und das Substrat und in lateraler Richtung durch das Verbindungsmaterial hermetisch verschlossen . Die Kavität ist also durch den Träger, das Substrat und das Verbindungsmaterial nach außen hin abgedichtet , insbesondere gasdicht abgedichtet , so dass ein Gasaustausch zwischen der Kavität und der Außenwelt unterdrückt oder verhindert ist . Der aktive Bereich kann von dem Träger beziehungsweise der Oberseite des Träger beabstandet sein . According to at least one embodiment, the active area is hermetically encapsulated by the carrier, the substrate and the connecting material. For example, the substrate, carrier, and interconnect material define a cavity in which the active region is located. The cavity is hermetically sealed at the top and bottom by the carrier and the substrate and in the lateral direction by the connecting material. The cavity is thus sealed off from the outside by the carrier, the substrate and the connecting material, in particular in a gas-tight manner, so that gas exchange between the cavity and the outside world is suppressed or prevented. The active area can be from be spaced from the carrier or the top of the carrier.
Die Begri f fe „oben" , „oberer" , „unten" , „unterer" , „Oberseite" und „Unterseite" oder ähnliche Begri f fe sind keines falls einschränkend auf Richtungen antiparallel und parallel zur Gravitationsrichtung zu verstehen . Sie werden vielmehr verwendet , um zum Beispiel einander gegenüberliegende Bereiche oder Richtungen zu kennzeichnen . The terms "above", "upper", "below", "lower", "top" and "bottom" or similar terms are in no way to be understood as limiting to directions antiparallel and parallel to the direction of gravity. Rather, they are used, for example, to indicate opposite areas or directions.
Gemäß zumindest einer Aus führungs form weist der Träger eine Oberseite und eine gegenüberliegende Unterseite auf . Die Oberseite ist beispielsweise die dem Halbleiterchip zugewandte Seite . Die Unterseite ist zum Beispiel dem Halbleiterchip abgewandt . Der Halbleiterchip ist insbesondere so auf dem Träger montiert , dass der aktive Bereich der Oberseite des Halbleiterchips zugewandt ist . According to at least one embodiment, the carrier has an upper side and an opposite lower side. The upper side is, for example, the side facing the semiconductor chip. The underside faces away from the semiconductor chip, for example. The semiconductor chip is mounted on the carrier in particular in such a way that the active area faces the top side of the semiconductor chip.
Gemäß zumindest einer Aus führungs form weist der Träger einen Grundkörper und Kontaktstrukturen auf . Die Kontaktstrukturen können von der Oberseite bis zur Unterseite des Trägers geführt sein . Beispielsweise weisen die Kontaktstrukturen j eweils ein Metall auf oder bestehen daraus . Der Grundkörper kann aus einem elektrisch isolierenden Material , beispielsweise Keramik und/oder Kunststof f , gebildet sein . Die Kontaktstrukturen bilden an der Oberseite beispielsweise Kontaktbereiche . According to at least one embodiment, the carrier has a base body and contact structures. The contact structures can be routed from the top to the bottom of the carrier. For example, the contact structures each have or consist of a metal. The base body can be formed from an electrically insulating material, for example ceramic and/or plastic. The contact structures form contact areas on the upper side, for example.
Gemäß zumindest einer Aus führungs form ist der Halbleiterchip auf der Oberseite des Trägers befestigt . Zum Beispiel ist der Halbleiterchip an der Oberseite des Trägers elektrisch an die Kontaktstrukturen angeschlossen . Insbesondere sind dieAccording to at least one embodiment, the semiconductor chip is attached to the top side of the carrier. For example, the semiconductor chip is electrically connected to the contact structures on the upper side of the carrier. In particular, the
Kontakteelemente des Halbleiterchips der Oberseite zugewandt . Die elektrische Verbindung zwischen den Kontaktstrukturen des Trägers und den Kontakteelementen des Halbleiterchips ist beispielsweise durch ein Lotmaterial oder einen elektrisch leitenden Kleber hergestellt . Contact elements of the semiconductor chip facing the top. The electrical connection between the contact structures of the carrier and the contact elements of the semiconductor chip is established, for example, by a soldering material or an electrically conductive adhesive.
Gemäß zumindest einer Aus führungs form liegen die Kontaktstrukturen im Betrieb des Halbleiterbauteils auf unterschiedlichen elektrischen Potenzialen . Beispielsweise ist eine Kontaktstruktur mit einer Kathode des Halbleiterchips und eine andere Kontaktstruktur mit einer Anode des Halbleiterchips elektrisch leitend verbunden . According to at least one embodiment, the contact structures are at different electrical potentials during operation of the semiconductor component. For example, one contact structure is electrically conductively connected to a cathode of the semiconductor chip and another contact structure is electrically conductively connected to an anode of the semiconductor chip.
Gemäß zumindest einer Aus führungs form sind die Kontaktstrukturen über Durchführungen von der Oberseite zur Unterseite durch den Grundkörper geführt . Die Durchführungen sind insbesondere als Löcher im Grundkörper ausgeführt , die in lateraler Richtung vollständig von dem Grundkörper umgeben sein können . According to at least one embodiment, the contact structures are routed through the base body from the top to the bottom via feedthroughs. The passages are designed in particular as holes in the base body, which can be completely surrounded by the base body in the lateral direction.
Gemäß zumindest einer Aus führungs form überlappen die Durchführungen der Kontaktstrukturen in lateraler Richtung mit dem aktiven Bereich und/oder der Halbleiterschichtenfolge . „Überlappen in lateraler Richtung" heißt , dass die j eweilige Durchführung unterhalb des aktiven Bereichs beziehungsweise der Halbleiterschichtenfolge angeordnet ist . In Draufsicht auf die Oberseite des Trägers ist die j eweilige Durchführung also teilweise oder vollständig von dem aktiven Bereich und/oder der Halbleiterschichtenfolge überdeckt . In accordance with at least one embodiment, the feedthroughs of the contact structures overlap in the lateral direction with the active region and/or the semiconductor layer sequence. "Overlapping in the lateral direction" means that the respective feedthrough is arranged below the active region or the semiconductor layer sequence. In a plan view of the top side of the carrier, the respective feedthrough is therefore partially or completely covered by the active region and/or the semiconductor layer sequence.
Gemäß zumindest einer Aus führungs form überlappt eine erste Durchführung einer ersten Kontaktstruktur in lateraler Richtung mit dem aktiven Bereich und/oder der Haiblei ter schichtenfolge . According to at least one embodiment, a first feedthrough overlaps a first contact structure laterally Direction with the active area and / or the Haiblei ter layer sequence.
Gemäß zumindest einer Aus führungs form ist eine zweite Durchführung einer zweiten Kontaktstruktur bezüglich dem aktiven Bereich und/oder der Halbleiterschichtenfolge in lateraler Richtung versetzt . Das heißt , die zweite Durchführung überlappt in lateraler Richtung nicht mit dem aktiven Bereich und/oder der Halbleiterschichtenfolge . In Draufsicht auf die Oberseite ist die zweite Durchführung also von dem aktiven Bereich und/oder der Halbleiterschichtenfolge nicht überdeckt . In accordance with at least one embodiment, a second feedthrough of a second contact structure is offset in the lateral direction with respect to the active region and/or the semiconductor layer sequence. This means that the second feedthrough does not overlap with the active region and/or the semiconductor layer sequence in the lateral direction. In a plan view of the top side, the second feedthrough is therefore not covered by the active region and/or the semiconductor layer sequence.
Alternativ oder zusätzlich kann die zweite Kontaktstruktur auch an der Oberseite lateral über den Halbleiterchip hinausgeführt sein, den Halbleiterchip in lateraler Richtung also überragen . Alternatively or additionally, the second contact structure can also be led out laterally beyond the semiconductor chip on the upper side, that is to say project beyond the semiconductor chip in the lateral direction.
Das hier beschriebene Halbleiterbauelement kann beispielsweise zur Desinfektion oder im Automobilbereich, zum Beispiel in einem Scheinwerfer, verwendet werden . The semiconductor component described here can be used, for example, for disinfection or in the automotive sector, for example in a headlight.
Nachfolgend wird ein hier beschriebener Halbleiterchip sowie ein hier beschriebenes Halbleiterbauteil unter Bezugnahme auf Zeichnungen anhand von Aus führungsbeispielen näher erläutert . Gleiche Bezugs zeichen geben dabei gleiche Elemente in den einzelnen Figuren an . Es sind dabei j edoch keine maßstäblichen Bezüge dargestellt , vielmehr können einzelne Elemente zum besseren Verständnis übertrieben groß dargestellt sein . Soweit Elemente oder Halbleiterbauteile in den verschiedenen Figuren in ihrer Funktion übereinstimmen, wird ihre Beschreibung nicht für j ede der folgenden Figuren wiederholt . Aus Gründen der Übersichtlichkeit sind Elemente möglicherweise nicht in allen Abbildungen mit entsprechenden Bezugs zeichen versehen . A semiconductor chip described here and a semiconductor component described here are explained in more detail below with reference to drawings based on exemplary embodiments. The same reference symbols indicate the same elements in the individual figures. However, no references to scale are shown here; on the contrary, individual elements may be shown in exaggerated size for better understanding. To the extent that elements or semiconductor components in the various figures have the same function, their description is not repeated for each of the following figures. For the sake of clarity, elements may not be appropriately referenced in all figures.
Es zeigen : Show it :
Figuren 1 und 2 ein erstes Aus führungsbeispiel des Halbleiterchips in verschiedenen Ansichten, FIGS. 1 and 2 show a first exemplary embodiment of the semiconductor chip in different views,
Figur 3 ein zweites Aus führungsbeispiel des Halbleiterchips in Querschnittsansicht , FIG. 3 shows a second exemplary embodiment of the semiconductor chip in a cross-sectional view,
Figuren 4 und 6 ein Aus führungsbeispiel des Halbleiterbauteils in verschiedenen Ansichten, FIGS. 4 and 6 show an exemplary embodiment of the semiconductor component in different views,
Figur 5 ein Aus führungsbeispiel des Trägers in Draufsicht , FIG. 5 shows an exemplary embodiment of the carrier in a plan view,
Figuren 7 und 8 ein weiteres Aus führungsbeispiel des Halbleiterchips in verschiedenen Ansichten, FIGS. 7 and 8 show another exemplary embodiment of the semiconductor chip in different views,
Figuren 9 und 11 ein weiteres Aus führungsbeispiel des Halbleiterbauteils in verschiedenen Ansichten und Figures 9 and 11 from another exemplary embodiment of the semiconductor component in different views and
Figur 10 ein weiteres Aus führungsbeispiel des Trägers in Draufsicht . FIG. 10 shows a further exemplary embodiment of the carrier in plan view.
Figur 1 zeigt ein Aus führungsbeispiel des Halbleiterchips 100 in Querschnittsansicht . Der Halbleiterchip 100 ist beispielsweise ein optoelektronischer Halbleiterchip zur Erzeugung von elektromagnetischer Strahlung, beispielsweise zur Erzeugung von UV-C-Strahlung . Der Halbleiterchip 100 umfasst ein Substrat 1 , beispielsweise ein Saphirsubstrat . Auf einer ersten Seite 10 des Substrats 1 ist eine Halbleiterschichtenfolge 20 angeordnet , zum Beispiel epitaktisch gewachsen . Figur 2 zeigt eine Draufsicht auf die erste Seite 10 des Substrats 1 . FIG. 1 shows an exemplary embodiment of the semiconductor chip 100 in a cross-sectional view. The semiconductor chip 100 is, for example, an optoelectronic semiconductor chip for generating electromagnetic radiation, for example for generating UV-C radiation. The semiconductor chip 100 comprises a substrate 1, for example a sapphire substrate. A semiconductor layer sequence 20 is arranged on a first side 10 of the substrate 1, for example grown epitaxially. FIG. 2 shows a top view of the first side 10 of the substrate 1 .
Die Halbleiterschichtenfolge 20 umfasst eine aktive Schicht 2 , die vorliegend einen aktiven Bereich 2 des Halbleiterchips 100 bildet . Die Halbleiterschichtenfolge 20 basiert zum Beispiel auf AlGaN . In der aktiven Schicht 2 wird während des Betriebs des Halbleiterchips 100 durch Rekombination von Ladungsträger elektromagnetische Strahlung, beispielsweise UV-C-Strahlung, erzeugt . The semiconductor layer sequence 20 includes an active layer 2 , which in the present case forms an active region 2 of the semiconductor chip 100 . The semiconductor layer sequence 20 is based on AlGaN, for example. Electromagnetic radiation, for example UV-C radiation, is generated in the active layer 2 during the operation of the semiconductor chip 100 by recombination of charge carriers.
Auf die Halbleiterschichtenfolge 20 sind Kontakteelemente 5 , 6 zur elektrischen Kontaktierung der Halbleiterschichtenfolge 20 aufgebracht . Bei dem Kontaktelement 5 handelt es sich beispielsweise um eine Kathode und bei dem Kontaktelement 6 um eine Anode . Die Kontaktelemente 5 , 6 sind beispielsweise metallisch . Contact elements 5 , 6 for electrically contacting the semiconductor layer sequence 20 are applied to the semiconductor layer sequence 20 . The contact element 5 is, for example, a cathode and the contact element 6 is an anode. The contact elements 5 , 6 are metallic, for example.
Auf die erste Seite 10 des Substrats 1 ist außerdem eine Verbindungstruktur 3 , vorliegend bestehend aus einer Metallisierung 30 , aufgebracht . Die Metallisierung 30 enthält zum Beispiel Au oder besteht daraus . Die Verbindungstruktur 3 ist , wie insbesondere aus der Figur 2 ersichtlich, lateral vollständig und zusammenhängend um die Halbleiterschichtenfolge 20 beziehungsweise den aktiven Bereich 2 herum angeordnet . Die Verbindungstruktur 3 ist zur Bildung einer Verbindung zu einem Träger mittels eines Verbindungsmaterials eingerichtet . Vorliegend ist die Verbindungstruktur 3 zur Benetzung mit dem Verbindungsmaterial , zum Beispiel einem Lotmaterial , eingerichtet , durch welches dann eine stof f schlüssige Verbindung zum Träger gebildet wird . Wie in der Figur 2 zu sehen ist , ist die Verbindungstruktur 3 lateral von dem aktiven Bereich 2 beziehungsweise der Halbleiterschichtenfolge 20 beanstandet und dadurch auch von der Halbleiterschichtenfolge 20 beziehungsweise dem aktiven Bereich 2 elektrisch isoliert . Die Verbindungstruktur 3 ist also nicht zur elektrischen Kontaktierung der Halbleiterschichtenfolge 20 eingerichtet . Während des bestimmungsgemäßen Betriebs des Halbleiterchips 100 fließen durch die Verbindungstruktur 3 zum Beispiel keine Ladungsträger . Die Kontakteelemente 5 , 6 überlappen vollständig mit der Halbleiterschichtenfolge 20 . A connection structure 3 , presently consisting of a metallization 30 , is also applied to the first side 10 of the substrate 1 . The metallization 30 contains or consists of Au, for example. As can be seen in particular from FIG. 2, the connection structure 3 is arranged laterally completely and continuously around the semiconductor layer sequence 20 or the active region 2 . The connection structure 3 is set up to form a connection to a carrier by means of a connection material. In the present case, the connection structure 3 is set up for wetting with the connection material, for example a soldering material, which then forms a material connection to the carrier. As can be seen in FIG. 2, the connection structure 3 is laterally spaced apart from the active region 2 or the semiconductor layer sequence 20 and is therefore also electrically insulated from the semiconductor layer sequence 20 or the active region 2 . The connection structure 3 is therefore not set up for making electrical contact with the semiconductor layer sequence 20 . For example, no charge carriers flow through the connection structure 3 during the intended operation of the semiconductor chip 100 . The contact elements 5 , 6 completely overlap with the semiconductor layer sequence 20 .
In der Figur 3 ist ein weiteres Aus führungsbeispiel des Halbleiterchips 100 gezeigt . Im Unterschied zu dem vorherigen Aus führungsbeispiel umfasst hier die Verbindungstruktur 3 nicht nur eine Metallisierung 30 , sondern auch das Verbindungsmaterial 300 , mittels welchem die stof f schlüssige Verbindung zum Träger hergestellt wird . Das Verbindungsmaterial 300 ist hier zum Beispiel ein Lotmaterial , wie AuSn . In der Figur 3 überragt die Verbindungstruktur 3 den aktiven Bereich 2 beziehungsweise die Halbleiterschichtenfolge 20 in Richtung weg von der ersten Seite 10 . A further exemplary embodiment of the semiconductor chip 100 is shown in FIG. In contrast to the previous exemplary embodiment, the connection structure 3 here includes not only a metallization 30 but also the connection material 300 by means of which the material connection to the carrier is produced. The connection material 300 here is, for example, a solder material such as AuSn. In FIG. 3, the connection structure 3 protrudes beyond the active area 2 or the semiconductor layer sequence 20 in the direction away from the first side 10 .
Anders als in der Figur 3 dargestellt , könnten auch die Kontaktelemente 5 , 6 bereits mit Lotmaterial benetzt sein . Unlike what is shown in FIG. 3, the contact elements 5 , 6 could already be wetted with solder material.
Die Figuren 1 bis 3 zeigen Aus führungsbeispiele eines Halbleiterchips 100 im unmontierten Zustand, das heißt vor einer mechanischen und elektrischen Verbindung zu einem Träger . Figur 4 zeigt ein Aus führungsbeispiel eines Halbleiterbauteils 1000 , bei dem der Halbleiterchip 100 der Figuren 1 und 2 oder der Figur 3 auf der Oberseite 201 eines Trägers 200 mittels des Verbindungsmaterials 300 befestigt ist . Dabei ist der Halbleiterchip 100 mit der ersten Seite 10 voran auf die Oberseite 201 des Trägers 200 montiert . FIGS. 1 to 3 show exemplary embodiments of a semiconductor chip 100 in the unmounted state, that is to say before a mechanical and electrical connection to a carrier. FIG. 4 shows an exemplary embodiment of a semiconductor component 1000 in which the semiconductor chip 100 from FIGS. 1 and 2 or from FIG. In this case, the semiconductor chip 100 is mounted with the first side 10 first on the top side 201 of the carrier 200 .
Das Verbindungsmaterial 300 benetzt die Metallisierung 30 und umgibt den aktiven Bereich 2 beziehungsweise die Halbleiterschichtenfolge 20 in lateraler Richtung vollständig . An der Oberseite 201 benetzt das Verbindungsmaterial 300 eine Metallisierung 230 des Trägers 200 . Das den aktiven Bereich 2 vollständig lateral umgebende Verbindungsmaterial 300 , der Träger 200 und das Substrat 1 umschließen eine Kavität und dichten diese hermetisch nach außen ab . In der Kavität ist der aktive Bereich 2 angeordnet und somit hermetisch verkapselt und vor äußeren Einflüssen geschützt . The connecting material 300 wets the metallization 30 and completely surrounds the active region 2 or the semiconductor layer sequence 20 in the lateral direction. The connecting material 300 wets a metallization 230 of the carrier 200 on the upper side 201 . The connection material 300 that completely laterally surrounds the active region 2 , the carrier 200 and the substrate 1 enclose a cavity and hermetically seal it from the outside. The active area 2 is arranged in the cavity and is thus hermetically encapsulated and protected from external influences.
Die Kontaktelemente 5 , 6 des Halbleiterchips 1 sind elektrisch leitend an Kontaktstrukturen 205 , 206 des Trägers 200 angeschlossen, vorliegend ebenfalls über eine Lötverbindung . Die Kontaktstrukturen 205 , 206 sind beispielsweise metallisch . Die Kontaktstrukturen 205 , 206 erstrecken sich von der Oberseite 201 durch Durchführungen 207 , 208 eines Grundkörpers 204 des Trägers 200 bis zu einer Unterseite 202 des Trägers 200 . Der Grundkörper 204 ist beispielsweise aus Keramik oder aus Kunststof f . Dabei überlappen die Durchführungen 207 , 208 in lateraler Richtung mit dem aktiven Bereich 2 beziehungsweise der Halbleiterschichtenfolge 20 des Halbleiterchips 100 . An der Unterseite 202 sind die Kontaktstrukturen 205 , 206 lateral über den Halbleiterchip 100 hinausgeführt . Auch die Metallisierung 230 des Trägers 200 ist an der Oberseite 201 lateral über den Halbleiterchip 100 hinausgeführt . The contact elements 5, 6 of the semiconductor chip 1 are electrically conductively connected to contact structures 205, 206 of the carrier 200, in the present case also via a soldered connection. The contact structures 205 , 206 are metallic, for example. The contact structures 205 , 206 extend from the top 201 through bushings 207 , 208 of a base body 204 of the carrier 200 to a bottom 202 of the carrier 200 . The base body 204 is made of ceramic or plastic, for example. In this case, the feedthroughs 207 , 208 overlap in the lateral direction with the active region 2 or the semiconductor layer sequence 20 of the semiconductor chip 100 . On the underside 202 , the contact structures 205 , 206 extend laterally beyond the semiconductor chip 100 . Also the Metallization 230 of the carrier 200 is led out laterally beyond the semiconductor chip 100 on the upper side 201 .
In der Figur 6 ist das Halbleiterbauteil 1000 der Figur 4 in Draufsicht auf die Oberseite 201 des Trägers 200 dargestellt . Um die Elemente unterhalb des Substrats 1 sichtbar zu machen, ist das Substrat 1 halbtransparent gezeichnet . FIG. 6 shows the semiconductor component 1000 from FIG. 4 in a plan view of the top side 201 of the carrier 200 . In order to make the elements below the substrate 1 visible, the substrate 1 is drawn semi-transparent.
In der Figur 5 ist der Träger 200 aus den Figuren 4 und 6 in Draufsicht auf die Oberseite 201 gezeigt . Hier ist zu erkennen, dass die Kontaktstrukturen 205 , 206 Kontaktbereiche an der Oberseite 201 bilden . Die Metallisierung 230 des Trägers 200 verläuft zusammenhängend und vollständig um die Kontaktbereiche . FIG. 5 shows the carrier 200 from FIGS. 4 and 6 in a plan view of the upper side 201 . It can be seen here that the contact structures 205 , 206 form contact areas on the upper side 201 . The metallization 230 of the carrier 200 runs continuously and completely around the contact areas.
An der Oberseite 201 des Trägers 200 sind außerdem Montageflächen 209 für zumindest ein Schutzelement , zum Beispiel für ESD-Strukturen, gebildet . Mounting surfaces 209 for at least one protective element, for example for ESD structures, are also formed on the upper side 201 of the carrier 200 .
Figur 7 zeigt ein weiteres Aus führungsbeispiel eines Halbleiterchips 100 in Querschnittsansicht . Figur 8 zeigt das Aus führungsbeispiel in Draufsicht auf die erste Seite 10 des Substrats 1 . Im Unterschied zu dem Aus führungsbeispiel der Figuren 1 und 2 , ist hier die Verbindungstruktur 3 (vorliegend wieder durch eine Metallisierung 30 realisiert ) elektrisch nicht von dem aktiven Bereich 2 beziehungsweise der Halbleiterschichtenfolge 20 isoliert . Vielmehr kontaktiert die Verbindungstruktur 3 die Halbleiterschichtenfolge 20 und bildet ein Kontaktelement 6 zur elektrischen Kontaktierung der Halbleiterschichtenfolge 20 . Die Verbindungstruktur 3 überlappt in lateraler Richtung mit der Halbleiterschichtenfolge 20 . Wie in der Figur 8 zu erkennen ist , überdeckt die Verbindungstruktur 3 die Halbleiterschichtenfolge 20 an einer Seite teilweise . An drei weiteren Seiten der Halbleiterschichtenfolge 20 ist die Verbindungstruktur 3 von der Halbleiterschichtenfolge 20 in lateraler Richtung beabstandet . Allerdings könnte die Verbindungstruktur 3 auch an mehr als nur der einen Seite , beispielsweise an allen vier Seiten, die Halbleiterschichtenfolge 20 überdecken und so beispielsweise an allen vier Seiten die Halbleiterschichtenfolge 20 elektrisch kontaktieren . FIG. 7 shows a further exemplary embodiment of a semiconductor chip 100 in a cross-sectional view. FIG. 8 shows the exemplary embodiment in a top view of the first side 10 of the substrate 1 . In contrast to the exemplary embodiment in FIGS. 1 and 2, here the connection structure 3 (here again realized by a metallization 30 ) is not electrically isolated from the active region 2 or the semiconductor layer sequence 20 . Rather, the connection structure 3 makes contact with the semiconductor layer sequence 20 and forms a contact element 6 for making electrical contact with the semiconductor layer sequence 20 . The connection structure 3 overlaps with the semiconductor layer sequence 20 in the lateral direction. As can be seen in FIG. 8, the connection structure 3 partially covers the semiconductor layer sequence 20 on one side. On three further sides of the semiconductor layer sequence 20 the connection structure 3 is spaced apart from the semiconductor layer sequence 20 in the lateral direction. However, the connection structure 3 could also cover the semiconductor layer sequence 20 on more than just one side, for example on all four sides, and thus make electrical contact with the semiconductor layer sequence 20 on all four sides, for example.
Figur 9 zeigt ein weiteres Aus führungsbeispiel des Halbleiterbauteils 1000 . Hier ist der Halbleiterchip 100 der Figuren 7 und 8 auf einem Träger 200 montiert . Das Verbindungsmaterial 300 zusammen mit dem Träger 200 und dem Substrat 1 verkapselt die Halbleiterschichtenfolge 20 beziehungsweise den aktiven Bereich 2 hermetisch . Im Unterschied zu der Figur 4 überlappt hier nur eine Durchführung 207 durch den Grundkörper 204 mit der aktiven Schicht beziehungsweise dem aktiven Bereich 2 in lateraler Richtung . Die andere Durchführung 208 , nämlich die Durchführung für die Kontaktstruktur 206 , die elektrisch leitend mit der Verbindungstruktur 3 beziehungsweise dem Kontaktelement 6 verbunden ist , ist bezüglich des aktiven Bereichs 2 beziehungsweise der Halbleiterschichtenfolge 20 lateral versetzt und überlappt daher in lateraler Richtung nicht mit der Halbleiterschichtenfolge 20 beziehungsweise dem aktiven Bereich 2 . Außerdem ist die Kontaktstruktur 206 beziehungsweise der zugehörige Kontaktbereich an der Oberseite 201 lateral über den Halbleiterchip 100 hinausgeführt . Figur 11 zeigt das Halbleiterbauteil 1000 der Figur 9 wiederum in Draufsicht auf die Oberseite 201 des Trägers 200 , wobei aus Gründen der besseren Darstellung das Substrat 1 des Halbleiterchips 100 transparent gezeichnet ist . FIG. 9 shows a further exemplary embodiment of the semiconductor component 1000. Here the semiconductor chip 100 of FIGS. 7 and 8 is mounted on a carrier 200 . The connecting material 300 together with the carrier 200 and the substrate 1 hermetically encapsulates the semiconductor layer sequence 20 or the active region 2 . In contrast to FIG. 4, here only one feedthrough 207 through the base body 204 overlaps with the active layer or the active region 2 in the lateral direction. The other feedthrough 208, namely the feedthrough for the contact structure 206, which is electrically conductively connected to the connection structure 3 or the contact element 6, is offset laterally with respect to the active region 2 or the semiconductor layer sequence 20 and therefore does not overlap with the semiconductor layer sequence 20 in the lateral direction or the active area 2 . In addition, the contact structure 206 or the associated contact area on the upper side 201 is led out laterally beyond the semiconductor chip 100 . FIG. 11 again shows the semiconductor component 1000 of FIG. 9 in a plan view of the upper side 201 of the carrier 200 , the substrate 1 of the semiconductor chip 100 being shown as transparent for reasons of better illustration.
In der Figur 10 ist der Träger 200 der Figuren 9 und 11 in Draufsicht auf die Oberseite 201 dargestellt . Der Kontaktbereich des Kontaktelements 205 ist hier lateral vollständig von dem Kontaktbereich des Kontaktelements 206 umgeben . Der Kontaktbereich der Kontaktstruktur 206 bildet gleichzeitig die Metallisierung 230 für die Benetzung mit dem Verbindungsmaterial 300 . FIG. 10 shows the carrier 200 of FIGS. 9 and 11 in a plan view of the upper side 201 . The contact area of the contact element 205 is here laterally completely surrounded by the contact area of the contact element 206 . The contact area of the contact structure 206 simultaneously forms the metallization 230 for wetting with the connecting material 300 .
Diese Patentanmeldung beansprucht die Priorität der deutschen Patentanmeldung 102021129113 . 5 , deren Of fenbarungsgehalt hiermit durch Rückbezug aufgenommen wird . This patent application claims the priority of German patent application 102021129113. 5, the disclosure content of which is hereby incorporated by reference.
Die Erfindung ist nicht durch die Beschreibung anhand der Aus führungsbeispiele auf diese beschränkt . Vielmehr umfasst die Erfindung j edes neue Merkmal sowie j ede Kombination von Merkmalen, was insbesondere j ede Kombination von Merkmalen in den Patentansprüchen beinhaltet , auch wenn diese Merkmale oder diese Kombination selbst nicht expli zit in den Patentansprüchen oder Aus führungsbeispielen angegeben ist . The invention is not limited to the description based on the exemplary embodiments. Rather, the invention includes every new feature and every combination of features, which in particular includes every combination of features in the patent claims, even if these features or this combination themselves are not explicitly stated in the patent claims or exemplary embodiments.
Bezugs zeichenliste reference character list
1 Substrat 1 substrate
2 aktiver Bereich 2 active area
3 Verbindungstruktur 3 connection structure
5 Kontaktelement 5 contact element
6 Kontaktelement 6 contact element
10 erste Seite 10 first page
20 Halbleiterschichtenfolge 20 semiconductor layer sequence
30 Metallisierung 30 metallization
100 Halbleiterchip 100 semiconductor chip
200 Träger 200 porters
201 Oberseite 201 top
202 Unterseite 202 underside
205 Kontaktstruktur 205 contact structure
206 Kontaktstruktur 206 contact structure
207 Durchführung 207 implementation
208 Durchführung 208 execution
209 Montagefläche 209 mounting surface
230 Metallisierung/Kontaktbereich230 metallization/contact area
300 Verbindung 300 connection
1000 Halbleiterbauteil 1000 Semiconductor Device

Claims

22 Patentansprüche 22 patent claims
1. Halbleiterchip (100) aufweisend 1. Having a semiconductor chip (100).
- ein Substrat (1) mit einer ersten Seite (10) , - a substrate (1) with a first side (10),
- einen aktiven Bereich (2) an der ersten Seite (10) , - an active area (2) on the first side (10),
- eine Verbindungsstruktur (3) an der ersten Seite (10) , wobei - A connection structure (3) on the first side (10), wherein
- dem aktiven Bereich (2) eine elektrische Funktionalität des Halbleiterchips (100) zugeordnet ist, die während des Betriebs des Halbleiterchips (100) ausgeführt wird, - an electrical functionality of the semiconductor chip (100) is assigned to the active region (2) and is executed during the operation of the semiconductor chip (100),
- die Verbindungsstruktur (3) - the connection structure (3)
- den aktiven Bereich (2) lateral vollständig umgibt, und - the active area (2) laterally completely surrounds, and
- für die Bildung einer mechanischen Verbindung zwischen dem Halbleiterchip (100) und einem Träger (200) mittels eines Verbindungsmaterials (300) eingerichtet ist, sodass das Verbindungsmaterial (300) den aktiven Bereich (2) lateral vollständig umgibt. - Is set up for the formation of a mechanical connection between the semiconductor chip (100) and a carrier (200) by means of a connecting material (300), so that the connecting material (300) the active region (2) laterally completely surrounds.
2. Halbleiterchip (100) nach Anspruch 1, wobei Second semiconductor chip (100) according to claim 1, wherein
- die Verbindungsstruktur (3) ein Kontaktelement (6) des Halbleiterchips (100) zur elektrischen Kontaktierung des Halbleiterchips (100) bildet. - The connection structure (3) forms a contact element (6) of the semiconductor chip (100) for electrically contacting the semiconductor chip (100).
3. Halbleiterchip (100) nach Anspruch 1, wobei 3. semiconductor chip (100) according to claim 1, wherein
- die Verbindungsstruktur (3) von dem aktiven Bereich (2) elektrisch isoliert ist. - the connection structure (3) is electrically insulated from the active area (2).
4. Halbleiterchip (100) nach einem der vorhergehenden Ansprüche, wobei 4. semiconductor chip (100) according to any one of the preceding claims, wherein
- die Verbindungsstruktur (3) eine metallische Struktur zur Bildung einer Lötverbindung (300) zwischen dem Träger (200) und dem Halbleiterchip (100) ist. - The connection structure (3) is a metallic structure for forming a soldered connection (300) between the carrier (200) and the semiconductor chip (100).
5. Halbleiterchip (100) nach Anspruch 4, wobei5. semiconductor chip (100) according to claim 4, wherein
- die Verbindungsstruktur (3) das Verbindungsmaterial (300) aufweist und das Verbindungsmaterial (300) ein Lotmaterial ist . - The connection structure (3) has the connection material (300) and the connection material (300) is a solder material.
6. Halbleiterchip (100) nach einem der vorhergehenden Ansprüche, wobei 6. semiconductor chip (100) according to any one of the preceding claims, wherein
- der Halbleiterchip (100) ein oberflächenmontierbarer Chip mit für die elektrische Kontaktierung notwendigen Kontaktelementen (5, 6) auf der ersten Seite (10) ist. - the semiconductor chip (100) is a surface-mountable chip with contact elements (5, 6) required for electrical contacting on the first side (10).
7. Halbleiterchip (100) nach einem der vorhergehenden Ansprüche, wobei 7. semiconductor chip (100) according to any one of the preceding claims, wherein
- der Halbleiterchip (100) ein optoelektronischer Halbleiterchip ist, - the semiconductor chip (100) is an optoelectronic semiconductor chip,
- der aktive Bereich (2) ein Bereich ist, in dem im Betrieb elektromagnetische Strahlung durch Rekombination von Ladungsträgern erzeugt wird. - The active area (2) is an area in which electromagnetic radiation is generated by recombination of charge carriers during operation.
8. Halbleiterchip (100) nach Anspruch 7, wobei 8. semiconductor chip (100) according to claim 7, wherein
- die elektromagnetische Strahlung UV-C-Strahlung ist. - the electromagnetic radiation is UV-C radiation.
9. Halbleiterchip (100) nach einem der vorhergehenden Ansprüche, wobei 9. semiconductor chip (100) according to any one of the preceding claims, wherein
- das Substrat (2) ein Aufwachssubstrat ist, auf dem der aktive Bereich (2) gewachsen ist. - the substrate (2) is a growth substrate on which the active region (2) has grown.
10. Halbleiterchip (100) nach einem der Ansprüche 1 bis 8, wobei 10. semiconductor chip (100) according to any one of claims 1 to 8, wherein
- der Halbleiterchip (100) ein Dünnfilm-Chip ist. - the semiconductor chip (100) is a thin-film chip.
11. Halbleiterbauteil (1000) aufweisend - einen Halbleiterchip (100) nach einem der vorhergehenden Ansprüche, 11. Semiconductor component (1000) having - a semiconductor chip (100) according to any one of the preceding claims,
- einen Träger (200) , wobei - A carrier (200), wherein
- der Halbleiterchip (100) mit dem Träger (200) mittels eines Verbindungsmaterials (300) verbunden ist, - the semiconductor chip (100) is connected to the carrier (200) by means of a connecting material (300),
- das Verbindungsmaterial (300) den aktiven Bereich (2) lateral vollständig umgibt, - the connecting material (300) completely surrounds the active region (2) laterally,
- der aktive Bereich (2) von dem Träger (200) , dem Substrat (1) und dem Verbindungsmaterial (300) hermetisch verkapselt ist . - The active region (2) of the carrier (200), the substrate (1) and the connecting material (300) is hermetically encapsulated.
12. Halbleiterbauteil (1000) nach Anspruch 11, wobei 12. Semiconductor device (1000) according to claim 11, wherein
- der Träger (200) eine Oberseite (201) und eine gegenüberliegende Unterseite (202) aufweist, - the carrier (200) has an upper side (201) and an opposite lower side (202),
- der Träger (200) einen Grundkörper (204) und- The carrier (200) has a base body (204) and
Kontaktstrukturen (205, 206) aufweist, die von der Oberseite (201) bis zur Unterseite (202) geführt sind, Has contact structures (205, 206), which are guided from the top (201) to the bottom (202),
- der Halbleiterchip (100) auf der Oberseite (201) des Trägers (200) befestigt ist und an der Oberseite (201) elektrisch an die Kontaktstrukturen (205, 206) angeschlossen ist, - the semiconductor chip (100) is fixed on the upper side (201) of the carrier (200) and is electrically connected to the contact structures (205, 206) on the upper side (201),
- die Kontaktstrukturen (205, 206) im Betrieb des Halbleiterbauteils auf unterschiedlichen elektrischen Potenzialen liegen. - the contact structures (205, 206) are at different electrical potentials during operation of the semiconductor component.
13. Halbleiterbauteil (1000) nach Anspruch 12, wobei 13. Semiconductor device (1000) according to claim 12, wherein
- Durchführungen (207, 208) der Kontaktstrukturen (205, 206) von der Oberseite (201) zur Unterseite (202) durch den Grundkörper (204) hindurch in lateraler Richtung mit dem aktiven Bereich (2) überlappen. - Overlap feedthroughs (207, 208) of the contact structures (205, 206) from the top (201) to the bottom (202) through the base body (204) in the lateral direction with the active area (2).
14. Halbleiterbauteil (1000) nach Anspruch 12, wobei 25 14. Semiconductor device (1000) according to claim 12, wherein 25
- eine erste Durchführung (207) einer ersten Kontaktstruktur (205) von der Oberseite (201) zur Unterseite (202) durch den Grundkörper (204) hindurch in lateraler Richtung mit dem aktiven Bereich (3) überlappt, - eine zweite Durchführung (208) einer zweiten- a first feedthrough (207) of a first contact structure (205) from the top (201) to the bottom (202) through the base body (204) in the lateral direction with the active region (3) overlaps, - a second feedthrough (208) a second
Kontaktstruktur (206) von der Oberseite (201) zur Unterseite (202) durch den Grundkörper (204) hindurch bezüglich dem aktiven Bereich (3) in lateraler Richtung versetzt ist und/oder die zweite Kontaktstruktur (206) an der Oberseite (201) lateral über den Halbleiterchip (100) hinausgeführt ist . Contact structure (206) is offset from the top (201) to the bottom (202) through the base body (204) with respect to the active area (3) in the lateral direction and/or the second contact structure (206) on the top (201) laterally is led beyond the semiconductor chip (100).
PCT/EP2022/081095 2021-11-09 2022-11-08 Semiconductor chip and semiconductor component WO2023083793A1 (en)

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