WO2023083666A1

WO2023083666A1 - Switchable insulation for hts magnets

Info

Publication number: WO2023083666A1
Application number: PCT/EP2022/080585
Authority: WO
Inventors: Ivan KRASTEV; Robert Slade; Jeroen VAN NUGTEREN; Matthew Bristow
Original assignee: Tokamak Energy Ltd
Priority date: 2021-11-12
Filing date: 2022-11-02
Publication date: 2023-05-19
Also published as: GB2627642A; GB202116343D0; GB202407705D0

Abstract

A high temperature superconductor, HTS, magnet. The HTS magnet comprises an HTS field coil, an insulating layer, semiconductor material, and a controller. The HTS field coil comprises a plurality of turns of HTS material wound about an axis of the coil. The insulating layer separates the turns of HTS material along a radial direction perpendicular to the axis. The semiconductor material connects adjacent turns of HTS material, the semiconductor material forming one or more active semiconductor switches that can be switched between a low conductance state and a high conductance state, wherein current can flow radially between the adjacent turns via the or each active semiconductor switch when the active semiconductor switch is in a high conductance state. The controller is configured to switch the or each active semiconductor switch from a high conductance state to a low conductance state, and vice versa.

Description

Switchable Insulation for HTS Magnets

Field of the Invention

The present invention relates to high temperature superconductor (HTS) field coils.

Background

The challenge of producing fusion power is hugely complex. Many alternative devices apart from tokamaks have been proposed, though none have yet produced any results comparable with the best tokamaks currently operating such as JET.

World fusion research has entered a new phase after the beginning of the construction of ITER, the largest and most expensive (c15bn Euros) tokamak ever built. The successful route to a commercial fusion reactor demands long pulse, stable operation combined with the high efficiency required to make electricity production economic. These three conditions are especially difficult to achieve simultaneously, and the planned programme will require many years of experimental research on ITER and other fusion facilities, as well as theoretical and technological research. It is widely anticipated that a commercial fusion reactor developed through this route will not be built before 2050.

To obtain the fusion reactions required for economic power generation (i.e. much more power out than power in), the conventional tokamak has to be huge (as exemplified by ITER) so that the energy confinement time (which is roughly proportional to plasma volume) can be large enough so that the plasma can be hot enough for thermal fusion to occur.

WO 2013/030554 describes an alternative approach, involving the use of a compact spherical tokamak for use as a neutron source or energy source. The low aspect ratio plasma shape in a spherical tokamak improves the particle confinement time and allows net power generation in a much smaller machine. However, a small diameter central column is a necessity, which presents challenges for the design of the plasma confinement magnets. High temperature superconductor (HTS) field coils are a promising technology for such magnets. Superconducting materials are typically divided into “high temperature superconductors” (HTS) and “low temperature superconductors” (LTS). LTS materials, such as Nb and NbTi, are metals or metal alloys whose superconductivity can be described by BCS theory. All low temperature superconductors have a critical temperature (the temperature above which the material cannot be superconducting, even in zero magnetic field) below about 30 K. By contrast, the behaviour of HTS material is not described by BCS theory, and such materials may have critical temperatures above about 30 K (though it should be noted that it is the physical differences in composition and superconducting operation, rather than the critical temperature, which define HTS and LTS materials). The most commonly used HTS are “cuprate superconductors” - ceramics based on cuprates (compounds containing a copper oxide group), such as BSCCO, or ReBCO (where Re is a rare earth element, commonly Y or Gd). Other HTS materials include iron pnictides (e.g. FeAs and FeSe) and magnesium diboride (MgB2).

ReBCO is typically manufactured as tapes, with a structure as shown in Figure 1 . Such tape 100 is generally approximately 100 microns thick, and includes a substrate 101 (typically an electropolished nickel-molybdenum alloy, e.g. Hastelloy ® approximately 50 microns thick), on which is deposited by ion beam-assisted deposition (I BAD), magnetron sputtering, or another suitable technique a series of buffer layers known as the buffer stack 102, of approximate thickness 0.2 microns. An epitaxial ReBCO-HTS layer 103 (deposited by metal oxide chemical vapour deposition (MOCVD) or another suitable technique) overlays the buffer stack, and is typically 1 micron thick. A 1-2 micron silver layer 104 is deposited on the HTS layer by sputtering or another suitable technique, and a copper layer 105 is deposited on the tape by electroplating or another suitable technique, which often completely encapsulates the tape. The silver layer 104 and copper stabilizer layer 105 are deposited on the sides of the tape 100 and the substrate 101 too, so that these layers extend continuously around the perimeter of the tape 100, thereby allowing an electrical connection to be made to the ReBCO-HTS layer 103 from either face of the tape 100.

These layers 104, 105 may therefore also be referred to as “cladding”. Typically, the silver cladding has a uniform thickness on both the sides and edges of the tape of around 1-2 microns. Providing a silver layer 104 between the HTS layer 103 and the copper layer 105 prevents the HTS material contacting the copper, which might lead to the HTS material becoming poisoned by the copper. The parts of the silver layer 104 and copper stabilizer layer 105 on the sides of the tape 100 are not shown in Figure 1 for clarity. Figure 1 also does not show the silver layer 104 extending beneath the substrate 101 , as is normally the case. The silver layer 104 makes a low resistivity electrical interface to, and an hermetic protective seal around, the ReBCO layer 103, whilst the copper layer 105 enables external connections to be made to the tape (e.g. permits soldering) and provides a parallel conductive path for electrical stabilisation.

The substrate 101 provides a mechanical backbone that can be fed through a manufacturing line and which permits growth of subsequent layers. The buffer stack 102 provides a bi-axially textured crystalline template upon which to grow the HTS layer, and prevents chemical diffusion of elements from the substrate to the HTS which damage its superconducting properties. The silver layer 104 provides a low resistance interface from the ReBCO to the stabiliser layer, and the stabiliser layer 105 provides an alternative current path in the event that any part of the ReBCO ceases superconducting (enters the “normal” state).

In addition, “exfoliated” HTS tape can be manufactured, which lacks a substrate and buffer stack, but typically has a “surrounding coating” of silver, i.e. layers on both sides and the edges of the HTS layer. Tape that has a substrate will be referred to as “substrated” HTS tape.

HTS tapes may be arranged into HTS cables. An HTS cable comprises one or more HTS tapes, which are connected along their length via conductive material (normally copper). The HTS tapes may be stacked (i.e. arranged such that the HTS layers are parallel), or they may have some other arrangement of tapes, which varies along the length of the cable. Notable special cases of HTS cables are single HTS tapes, and HTS pairs. HTS pairs comprise a pair of HTS tapes, arranged such that the HTS layers are parallel. Where substrated tape is used, HTS pairs may be type-0 (with the HTS layers facing each other), type-1 (with the HTS layer of one tape facing the substrate of the other), or type-2 (with the substrates facing each other). Cables comprising more than two tapes may arrange some or all of the tapes in HTS pairs. Stacked HTS tapes may comprise various arrangements of HTS pairs, most commonly either a stack of type-1 pairs or a stack of type-0 pairs and (or, equivalently, type-2 pairs). HTS cables may comprise a mix of substrated and exfoliated tape. When describing coils in this document, the following terms will be used:

• “HTS cable” - a cable comprising one or more HTS tapes. In this definition, a single HTS tape is an HTS cable.

• “turn” - a section of HTS cable within a coil which encloses the inside of the coil (i.e. which can be modelled as a complete loop).

• “arc” - a continuous length of the coil which is less than the whole field coil

• “inner/outer radius” - the distance from the centre of the coil to the inside/outside of the HTS cables.

• “inner/outer perimeter” - the distance measured around the inside/outside of the coil.

• “thickness” - the radial depth of all of the turns of the coil, i.e. the difference between the inner and outer radius.

• “critical current” - the current, l_c, at which the HTS would become normal, at a given temperature and external magnetic field, where HTS is considered to have “become normal” at a characteristic point of the superconducting transition, where the tape generates a specified electrical field of Eo volts per metre. The choice of Eo is to some extent arbitrary, but is usually taken to be 10 or 100 microvolts per metre.

• “generation temperature” - the temperature, T_c, at which the HTS would become normal (i.e. generate a field of Eo V/m), at a given magnetic field and current Io (and other external factors).

• “critical temperature” - the temperature at which the HTS would become normal given no external magnetic field, and negligible current (with all other external factors favourable).

The generation temperature of an HTS material refers to the temperature at which the HTS material generates a significant voltage by turning normal (i.e. ceases to be considered superconducting). In particular, the generation temperature is the temperature at which the critical electric field Eo (in V/m) is generated by a transport current Io flowing in a tape. As mentioned above, Eo is a chosen threshold and defines the critical current l_c, so that l₀= l_c when the critical electric field Eo is generated. The generation temperature therefore depends on a number of factors that affect the critical current, including the local magnetic field strength (B), and the angle (theta) that the magnetic field makes with the c-axis of the HTS material. The generation temperature also depends on the HTS superconductor n-value, which characterises how sharply the transition from superconducting to normal behaviour occurs. Typical generation temperatures of around 35 K are found for ReBCO material in an HTS field coil 200 in which the current is around 80% of the critical current (l_c) and the magnetic field strength is around 20 T.

A superconducting magnet is formed by arranging HTS cables (or individual HTS tapes, which for the purpose of this description can be treated as a single-tape cable) into coils, either by winding the HTS cables or by providing sections of the coil made from HTS cables and joining them together. HTS coils come in three broad classes:

• Insulated, having electrically insulating material between the turns (so that current can flow only in a “spiral path” through the HTS cables).

• Non-insulated, where the turns are connected radially, as well as along the cables (e.g. by connecting the copper stabilising layers of the HTS cables).

• Partially insulated, where the turns are connected radially with a controlled resistance, either by the use of materials with a high resistance (e.g. compared to copper), or by providing intermittent insulation between the coils.

Non-insulated coils can also be considered as the low-resistance case of partially insulated coils. Partially insulated field coils are described in W02019150123.

HTS field coils are generally designed to operate with all the HTS tapes in all turns running at less than their local critical current, l_c, which varies around the coil, due to the inhomogeneous magnetic field, B, and coil temperature, T. However, various fault conditions can cause HTS tape currents to exceed the critical current:

• Cooling failure, increasing T (locally or globally) and thereby reducing l_c.

• Transient increase in transport current, Io, e.g. a power supply over-current fault.

• Damage to the HTS material (for example, due to stress cracking, fatigue from thermal cycling or energization cycling of the magnet, or, in a nuclear fusion device, radiation induced degradation, such as can be caused by neutron bombardment or runaway electrons).

• Localized energy deposition that is sufficient to cause a thermal runaway. This “minimum quench energy” is of order of 10 J, and it may be possible for plasma disruptions to dump this amount of energy in the HTS magnets, either inductively or via radiation (e.g. runaway electrons).

If the current in any tape exceeds the critical current l_c, a voltage will be developed in the HTS material layer which can drive transport of some of the current into the metal layers of the tape (principally the copper layer, which has a much lower resistance than the substrate). Current can also share into the “spare l_c capacity” of the other tapes within that turn. Current passing between tapes via the layers of “normal” (i.e. resistive) conductor generates heat and reduces the local critical current l_c further. Eventually, all the tapes within the affected turn of the HTS field coil in the vicinity of the original defect turn normal, typically within timescales measured in milliseconds to seconds, depending on the stacked tape cable materials mix and geometry.

The region of the HTS tape initially affected by a fault condition is known as a “hotspot”. Early detection of hotspots is important so that damage to the HTS magnet can be avoided by “quenching” the magnet and dissipating its energy. Various approaches to detecting hotspots are known, e.g. using temperature sensors, strain sensors or voltage taps. For example, a network of sensors and voltage taps distributed around the coils can be used to detect and identify the locations of hotspots that could lead to a damaging thermal runaway and quench. The amount of energy stored in a HTS magnet when it is operated depends on the size and shape of the magnet and is proportional to the integral of the square of magnetic flux over the volume of the magnet. Large HTS magnets are able to store huge amounts of magnetic energy, which needs to be dissipated safely and rapidly in the event of a quench.

WO2017039299 describes a superconducting coil comprising a metal-insulator transition (MIT) material layer interposed between windings of the coil. The resistivity of the MIT material decreases by a large factor for temperatures in excess of a transition temperature. When electrical current is supplied to the superconducting coil, formation of a resistive “hotspot” (i.e. a normal zone) in one of the windings may cause localised heating of the MIT material layer that raises its temperature above the transition temperature, thereby lowering its resistance and allowing electrical current in the coil to divert into neighbouring turns via the MIT material layer, bypassing the normal zone and reducing the rate at which its temperature rises. One issue with the superconducting coils described in WO2017039299 is that the electrical resistivity of the MIT material layer may not decrease rapidly enough to avoid damage to the coil and/or to prevent run-away heat generation within the coil, leading to a quench. Another issue with existing HTS coil designs is that there is a trade-off between the turn-to-turn resistance of the coil being low enough to allow rapid transverse (radial) propagation of hotspots, or high enough that the coil can be rapidly energised/de- energised, i.e. high enough that the time constant L/R of the coil is small (L and R being the inductance and resistance of the coil). The need for a small time constant is particularly important in large, high inductance coils.

Summary

According to an aspect of the invention, there is provided a high temperature superconductor, HTS, magnet. The HTS magnet comprises an HTS field coil, an insulating layer, semiconductor material, and a controller. The HTS field coil comprises a plurality of turns of HTS material wound about an axis of the coil. The insulating layer separates the turns of HTS material along a radial direction perpendicular to the axis. The semiconductor material connects adjacent turns of HTS material, the semiconductor material forming one or more active semiconductor switches that can be switched between a low conductance state and a high conductance state, wherein current can flow radially between the adjacent turns via the or each active semiconductor switch when the active semiconductor switch is in a high conductance state. The controller is configured to switch the or each active semiconductor switch from a high conductance state to a low conductance state, and vice versa.

Brief Description of the Drawings

Figure 1 is a diagram of HTS tape;

Figure 2 is a schematic illustration of a cross section of an exemplary HTS coil comprising switchable insulation;

Figure 3 is a schematic illustration of a cross section of a further exemplary HTS coil comprising switchable insulation; and

Figure 4 is a schematic illustration of a cross section of a yet further exemplary HTS coil comprising switchable insulation. Detailed Description

An ideal form of partial insulation would be a layer which would have high resistance during ramp-up of the coil (resulting in a small time constant L/R for the coil), but have a low resistance when a quench occurs (and/or when pre-quench conditions are detected). As described above, previous solutions involving metal-insulator transition materials are not adequate, as while the transition of the MIT to a low resistance state will be initiated as soon as the temperature reaches a threshold, it takes a small amount of time, during which damage to the magnet may occur.

Proposed herein is a “switchable insulation” concept in which the turns of the HTS magnet are connected by “switchable insulation”. The switchable insulation comprises a semiconductor, which is doped so as to form an active semiconductor switch which is normally highly resistive, but allows high currents to pass radially between the turns with low resistance when triggered.

The switchable insulation may be provided as a layer between the turns of the HTS magnet, or may be provided on the side of the HTS coils such that adjacent turns are radially electrically connected by the switchable insulation.

Suitable active semiconductor switches include transistors (e.g. field effect transistors, FETs, metal-oxide-seminconductor FETs, MOSFETs, insulated gate bipolar transistors, IGBTs, etc.) and thyristors (e.g. silicon controlled rectifiers, SCRs, triodes for alternating current, TRIACs, etc).

As an example, a switchable insulation layer may be a continuous strip of semiconductor as shown in cross section in Figure 2. Figure 2 shows a plurality of HTS turns 201 with each pair of adjacent turns separated by a semiconductor layer 202. The upper surface 211 of the semiconductor layer is doped to form the source (collector) of a transistor, its lower surface 212 is doped to form the drain (emitter) of the transistor, and the gate 213 is in the mid-plane, and accessed via side contacts 214 connected to the switchable insulation strip. During ramp-up of the magnet, the switchable insulation is kept in a low- conductance state. When a quench or pre-quench conditions (e.g. abnormal strain, temperature, or magnetic field) is detected, a voltage is provided to the gate to cause the transistor to enter a high conductance state, and allow the coil transport current to flow radially through the switchable insulation. Alternatively, the transistor may be maintained in a high conductance state during normal operation of the magnet (i.e. after ramp-up).

While Figure 2 is described above with reference to a transistor, other doping structures may be used - e.g. with a 4-layer structure to form a thyristor - such that when the active semiconductor switch is triggered, a high-conductance path is created between the HTS turns.

As an alternative, as shown in Figure 3, a plurality of semiconductor channels 311 may be provided within an insulating layer 312 sandwiched between two HTS turns 301., Each semiconductor channel is doped as described above to form a transistor, with electrical contacts 313 providing control of the transistor gates.

As a further alternative, an insulating layer may be provided having a plurality of active semiconductor switches integrated or embedded on it, for example the insulating layer may be a PCB having active semiconductor switches embedded or soldered to it.

As a further alternative, semiconductor elements may be provided within a more complex partially insulating layer, such as that disclosed in WO 2019150123 A1. For example, a semiconductor layer may be provided between two insulating layers, with each insulating layer having one or more windows which allows electrical contact between the HTS turns and the semiconductor layer.

Figure 4 illustrates an example where the switchable insulation is provided on the side of the coil. Figure 4 shows a cross-section of an HTS coil having a plurality of turns of HTS cable 401. An switchable insulation element 402 is provided on the side of the HTS coil, such that it is electrically connected to each of the HTS turns. The switchable insulation element comprises a plurality of active semiconductor switches 410, such that each switch connects two turns of the HTS coil, e.g. adjacent turns, and allows current to flow radially between those turns when the active semiconductor switch is in a high conductance state. An intermediate layer 403 may be provided between the turns, which may be fully insulating, resistive, or partially insulated. For example, a fully insulated intermediate layer may be used if no radial current transfer is desired when the active semiconductor switches are in a low conductance state. A resistive or partially insulated intermediate layer may be used to allow for some radial current flow without triggering the active switches, but a sharp drop in resistance when the active semiconductor switches are in a high conductance state.

As a further alternative, the intermediate layer 403 may be a layer comprising further active semiconductor switches as described in previous examples.

As an alternative to the single switchable insulation element shown in Figure 4, separate switchable insulation elements may be provided for each pair of adjacent turns, and/or switchable insulation elements may be provided on both sides of the coil.

While figures 1 to 4 show only a small number of HTS turns for the sake of clarity, it will be appreciated that the structures described above can be expanded to any number of HTS turns.

In general, the switchable insulation comprises semiconductor material doped to form an active semiconductor switch which can be switched between a high conductance state and a low conductance state, such that when the active semiconductor switch is in a high-conductance state, current can flow radially between the turns via the active semiconductor switch. Additional constantly conductive current paths (e.g. made from a metal or other conductor) may be provided to provide a lower resistance when the active semiconductor switch is in a low conductance state. The semiconductor material is doped two turns of the HTS coil are connected via the active semiconductor switch, e.g. where the active semiconductor switch is a transistor the source of the transistor is in electrical contact (i.e. connected via conductive elements) with one turn, and the drain of the transistor is in electrical contact with the other turn.

It will be appreciated that in some transistor doping profiles, e.g. JFETS, current can flow in either direction between the “source” and “drain” terminals when the gate is open, so the labelling of which side is the “source” and which is the “drain” may be somewhat arbitrary. In doping profiles where there is a significant advantage in having current flow from source to drain, the transistor may be oriented such that the current will flow in this direction during a quench event, i.e. the “source” and “drain” may be oriented in either direction depending on the current flows required. As an example of how the switchable insulation may be used, the active semiconductor switches can be maintained in a low-conductance state during ramp-up of the magnet, to ensure that the time constant L/R of the magnet is low, and therefore ramp-up can be completed faster. During steady-state operation of the magnet, the active semiconductor switches may be put into a high conductance state to allow easier current sharing between the turns. Alternatively, the active semiconductor switches may be maintained in the low conductance state during steady state operation, and switched into a high conductance state on detection of a quench or pre-quench conditions. Ensuring that the active semiconductor switches are in a high conductance state during a quench (either by maintaining it in such a state during steady state operation, or by actively switching it when a quench is detected) allows for the energy in the magnet to be quickly dissipated through the entire magnet via the procedure described in WO 2020104807 A1.

The state of the active semiconductor switches may be controlled by a controller. The controller determines the required state for the active semiconductor switches, and provides the required inputs to change them between the high and low conductance states. For example, where the active semiconductor switches are MOSFETs, the controller would provide a voltage to the gate of the MOSFET when the MOSFET is required to be in a high conductance state, and provide no voltage to the gate when the MOSFET is required to be in a low conductance state.

The controller may decide on the required state for the active semiconductor switches based on some combination of control inputs and sensor inputs (e.g. using control inputs to determine whether the magnet is to be ramped up or down or operated in steady state, and using sensor inputs to detect a quench). Alternatively, the controller may receive inputs from other control devices of the HTS coil, which instruct the controller to set the active semiconductor switches into the appropriate state.

The controller may be implemented as software running on a processor or a distributed array of processors, and may be integrated within the structure of the HTS coil and/or support systems (e.g. the cryostat), or may be remote.

Detection of a quench or pre-quench conditions may be achieved by any suitable means. For example, a quench may be detected by measuring the voltage across the coil, with a voltage above a threshold indicating a quench. As another option, a quench or pre- quench conditions may be detected by monitoring the temperature of the HTS material, e.g. by temperature sensors embedded in the coil, or by monitoring the magnetic field of the coil. As a further option, pre-quench conditions may be detected by monitoring the strain of the coil. As a yet further option, a quench or pre-quench conditions may be detected using a secondary HTS tape, configured to quench at the same conditions as the main HTS coil, or at conditions between normal operating conditions and conditions that would cause the main HTS coil to quench, with a voltage spike in the secondary HTS tape indicating pre-quench conditions or a likely quench in the main HTS coil. The above options may be deployed separately or in conjunction with each other, and quench detection may be based on a single factor (e.g. voltage) or a combination of factors (e.g. a heuristic taking into account temperature and strain). However, it should be noted that the exact method of quench (or pre-quench) detection is not directly relevant to this disclosure, only that the detection of a quench or pre-quench conditions may be used to trigger the switchable insulation into a high conductance state.

Claims

CLAIMS:

1. A high temperature superconductor, HTS, magnet comprising: an HTS field coil comprising a plurality of turns of HTS material wound about an axis of the coil; an insulating layer separating the turns of HTS material along a radial direction perpendicular to the axis; semiconductor material connecting adjacent turns of HTS material, the semiconductor material forming one or more active semiconductor switches that can be switched between a low conductance state and a high conductance state, wherein current can flow radially between the adjacent turns via the or each active semiconductor switch when the active semiconductor switch is in a high conductance state; a controller configured to switch the or each active semiconductor switch from a high conductance state to a low conductance state, and vice versa.

2. An HTS field coil according to claim 1 , wherein the controller is configured to maintain the or each active semiconductor switch in a low conductance state during ramp-up of the HTS field coil.

3. An HTS field coil according to any preceding claim, wherein the controller is configured to maintain the or each active semiconductor switch in a high conductance state during steady state operation of the coil.

4. An HTS field coil according to any preceding claim, wherein the or each active semiconductor switch is one of: a transistor; a thyristor; a field effect transistor; a metal oxide semiconductor field effect transistor, MOSFET; an insulated gate bipolar transistor, IGBT; a silicon controlled rectifier, SCR; and a triode for alternating current, TRIAC.

5. An HTS field coil according to any preceding claim, wherein the or each active semiconductor switch is provided within a layer between adjacent turns of HTS material.

6. An HTS field coil according to any of claims 1 to 4, wherein the or each active semiconductor switch is provided on a side of the HTS field coil

7. An HTS field coil according to any preceding claim, wherein the HTS field coil comprises a bulk semiconductor doped to form the active semiconductor switch.

8. An HTS field coil according to any of claims 1 to 6, wherein the HTS field coil comprises an insulator in which the or each active semiconductor switch is embedded.

9. An HTS field coil according to any preceding claim, and comprising a quench detection system configured to detect a quench or pre-quench conditions in the plurality of turns; wherein the controller is configured to, in response to detection of a quench or pre-quench conditions by the quench detection system, cause the or each active semiconductor switch to enter a high conductance state.