WO2023082954A1

WO2023082954A1 - Ddr access method and apparatus, electronic device, and system

Info

Publication number: WO2023082954A1
Application number: PCT/CN2022/125942
Authority: WO
Inventors: 熊晓竹; 郭青云
Original assignee: 哲库科技(北京)有限公司
Priority date: 2021-11-10
Filing date: 2022-10-18
Publication date: 2023-05-19
Also published as: CN113900595B; CN113900595A

Abstract

The present application provides a DDR access method and apparatus, an electronic device, and a system. A DDR may store decoding data of a first transmission block, and the first transmission block is transmitted by means of a PDSCH. For the DDR, the frequency and/or voltage of the DDR in a first time slot may be adjusted according to the throughput of the DDR in the first time slot, the first time slot being a time slot of the PDSCH. That is to say, in the present application, by using the time slot of the PDSCH as a unit, the frequency and/or voltage of the DDR in the first time slot is dynamically adjusted according to the throughput of the DDR in the first time slot. Since a decoder decodes, also by using the time slot of the PDSCH as a unit, a transmission block that is transmitted by the PDSCH, the throughput of the DDR between time slots may thus vary greatly. In the present application, by using the time slot of the PDSCH as a unit, the frequency and/or voltage of the DDR in the first time slot is dynamically adjusted according to the throughput of the DDR in the first time slot, and when DDR working requirements are met, the change of the frequency and/or voltage of the DDR is more accurate, thereby further optimizing the power consumption of the DDR.

Description

DDR access method, device, electronic equipment and system

This application cites the Chinese patent application titled "DDR access method, device, electronic device and system" with application number 2021113284177 filed on November 10, 2021, and claims the priority of the Chinese patent application, which is incorporated by reference All are incorporated into this application.

technical field

The present application relates to the technical field of communication, and in particular to a DDR access method, device, electronic equipment and system.

Background technique

Double Data Rate Synchronous Dynamic Random Access Memory (Double Data Rate SDRAM, DDR SDRAM) is an important memory of the terminal. During the operation of the terminal, DDR can participate in most data processing processes. For example, when the terminal decodes the received transport block, it needs the DDR to store the data generated during the decoding process.

At present, the voltage of DDR is usually determined by the network configuration of the terminal. For example, according to the carrier parameters configured by the network of the terminal, the maximum possible throughput rate of the DDR is calculated, and then the voltage of the DDR is set according to the maximum throughput rate.

Contents of the invention

Embodiments of the present application provide a DDR access method, device, electronic equipment, and system, which are beneficial to saving DDR power consumption.

In the first aspect, a DDR access method is provided, the method comprising:

According to the throughput rate of the DDR in the first time slot, adjust the frequency and/or voltage of the DDR in the first time slot, wherein the first time slot is a time slot of the physical downlink shared channel PDSCH;

In the first time slot, based on the frequency and/or voltage of the DDR in the first time slot, the DDR reads and/or writes the decoded data of the first transport block, which is transmitted via the PDSCH.

In the second aspect, a DDR-based data transmission method is provided, which is applicable to the DDR access method provided by any one of the first aspect, and the method includes:

Decoding the first transport block in the first time slot, the first transport block is transmitted via the PDSCH, and the first time slot is a time slot of the PDSCH;

The decoded data of the first transport block is read and/or written to the DDR.

In a third aspect, a DDR access device is provided, which includes:

An adjustment module, configured to adjust the frequency and/or voltage of the DDR in the first time slot according to the throughput rate of the DDR in the first time slot, wherein the first time slot is a time slot of the physical downlink shared channel PDSCH;

The access module is used to read and/or write the decoded data of the first transmission block to the DDR based on the frequency and/or voltage of the DDR in the first time slot in the first time slot, and the first transmission block is transmitted via the PDSCH Transmission.

In a fourth aspect, a DDR-based data transmission device is provided, the device comprising:

The decoding module is configured to decode the first transmission block in the first time slot, the first transmission block is transmitted via the PDSCH, and the first time slot is a time slot of the PDSCH;

The access module is used for reading and/or writing the decoded data of the first transmission block to the DDR.

According to a fifth aspect, an electronic device is provided, including a memory and a processor, the memory stores a computer program, and the processor implements the methods described in the first aspect and the second aspect when executing the computer program.

In a sixth aspect, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the methods described in the first aspect and the second aspect above are implemented.

In the seventh aspect, an access system of double rate synchronous dynamic random access memory is provided, including a control unit, a DDR and a power supply unit, wherein the power supply unit is used to supply power to the DDR under the control of the control unit;

A control unit, configured to execute the method described in any one of the first aspect and the second aspect above.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present application. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic diagram of a DDR system architecture;

Fig. 2 is a flowchart of the DDR access method in one embodiment;

Fig. 3 is a schematic diagram of a transmission mechanism of DDR in an embodiment;

Fig. 4 is a schematic diagram of a transmission mechanism of DDR in an embodiment;

Fig. 5 is a flowchart of the DDR access method in one embodiment;

Fig. 6 is a schematic diagram of the starting moment of decoding of transport blocks of different carriers in an embodiment;

Fig. 7 is a flowchart of the DDR access method in one embodiment;

Fig. 8 is a schematic diagram of the start time of decoding of transport blocks of different carriers in an embodiment;

FIG. 9 is a schematic diagram of timing adjustment in a DDR access method in an embodiment;

FIG. 10 is a schematic diagram of a timing sequence of merging throughput rate changes of different carriers in an embodiment;

Fig. 11 is a flowchart of a data transmission method based on DDR in an embodiment;

Fig. 12 is a flow chart of the initial transmission process in the data transmission process in one embodiment;

Fig. 13 is a flowchart of a data transmission method based on DDR in an embodiment;

FIG. 14 is a flowchart of a retransmission process during data transmission in an embodiment;

Fig. 15 is a structural block diagram of a DDR access device in an embodiment;

Fig. 16 is a structural block diagram of a DDR-based data transmission device in an embodiment;

Fig. 17 is a schematic diagram of the architecture of the DDR access system in one embodiment.

Detailed ways

In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

It can be understood that the terms "first", "second" and the like used in this application may be used to describe various elements herein, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first client could be termed a second client, and, similarly, a second client could be termed a first client, without departing from the scope of the present application. Both the first client and the second client are clients, but they are not the same client.

With the development of the terminal market, double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDR SDRAM) has become an important component to improve the terminal processing speed, and the power consumption of DDR is also increasing day by day. Exemplary, Fig. 1 is a kind of DDR system architecture schematic diagram, this DDR system architecture can be applied to mobile phone, panel computer, PDA (Personal Digital Assistant, personal digital assistant), POS (Point of Sales, sales terminal), vehicle-mounted computer, Any electronic device with digital processing capabilities such as wearable devices and base stations.

As shown in FIG. 1 , the system 10 includes a processor 11 and a memory 12 . During the operation of the terminal 10 , the processor 11 can provide computing and control capabilities to support the operation of the entire electrical terminal 10 . The memory 12 may include a non-volatile storage medium 121 and a DDR 122 . The nonvolatile storage medium 121 stores an operating system and computer programs. The computer program can be executed by the processor 11 to realize the calculation and control capabilities provided by the processor 11 . The DDR122 can provide a cache running environment for the processor 11 .

In a specific implementation, the processor 11 and the memory 12 may be independently distributed or integrated into the same chip, which is not limited in this embodiment of the present application. Exemplarily, the system 10 may be an application processor, a baseband processor, or a system on chip (system on chip, SOC) integrating the application processor and the baseband processor.

The DDR access method provided in this embodiment is applicable to the field of communication technology, and the DDR access method may be executed by the processor 11 shown in FIG. 1 , the system 10 , or an electronic device.

Exemplarily, the scenario of terminal communication is taken as an example. The system 10 shown in FIG. 1 may be a modem chip in the terminal, and may also be called a baseband chip. During the communication process of the terminal, the decoder in the processor 11 can decode the received transmission block. Wherein, the transport block may be transmitted to the terminal via a physical downlink shared channel (PDSCH). The transmission block may include multiple coding blocks, and decoding the transmission block also includes decoding the multiple coding blocks respectively.

During decoding, processor 11 needs to read and/or write decoded data of transport blocks from DDR 122 . Specifically, in the process of decoding the transport block, the decoded data of the transport block mainly includes the soft bit data of the physical layer, the hard bit data of the MAC layer of the data plane media access control layer, and the packet data convergence protocol (Packet Data Convergence Protocol) of the data plane. Convergence Protocol, PDCP) layer decrypted data.

Due to fluctuations in the data volume of the decoded data of the transport block, the throughput rate of the DDR will also fluctuate accordingly. Specifically, the throughput rate of DDR is mainly determined by the throughput rate of soft bits at the physical layer, the throughput rate of hard bits at the MAC layer on the data plane, and the throughput rate of decrypted data at the PDCP layer on the data plane. Among them, the throughput rate of hard bits in the MAC layer and the throughput rate of decrypted data in the PDCP layer on the data plane determine the average throughput rate of DDR, and the throughput rate of soft bits in the physical layer determines the peak throughput rate of DDR in the actual working process.

Generally speaking, in low block error rate (Block error rate, BLER) scenarios, the throughput rate of DDR is close to the average throughput rate. In high BLER scenarios, the throughput of DDR is close to the peak throughput. When the BLER rises and the network has not had time to reduce the transmission rate by adjusting the Modulation and Coding Scheme (MCS), the physical layer will frequently read and write soft bit data from DDR, resulting in a large throughput of DDR. rises to a peak.

Exemplarily, when the terminal modem chip experiences a fast-fading channel or receives other interference during the process of receiving the downlink Physical Downlink Shared Channel (PDSCH), it will cause a high BLER, which in turn leads to Decoding errors of a large number of coded blocks.

In the case of the initial transmission of the transmission block, that is, when the processor 11 decodes the transmission block for the first time, the soft bit data of the wrong coded block needs to be stored in the Hybrid Automatic Repeat request (HARQ) of the DDR. ) memory for HARQ combining during retransmission. In the case of retransmission of the transport block, that is, the processor 11 has decoded the transport block before, and the decoding fails. In this case, it is necessary to read the soft bit data stored in the HARQ memory of the DDR to the processor In the on-chip HARQ memory of 11, in the retransmission process, the soft bits of the received transport block and the soft bits in the on-chip HARQ memory are HARQ combined and then decoded. For each coded block in the transport block, if the coded block is decoded incorrectly, the soft bit data needs to be stored in the DDR again. In extreme cases, if all coded blocks of the transmission block are decoded incorrectly at the initial transmission and also decoded incorrectly during retransmission, then in the case of retransmission, read the soft bits of all coded blocks from the DDR to the on-chip HARQ memory, and then read them from the The on-chip HARQ memory is moved to DDR, and the read and write operations in this case will maximize the throughput of DDR.

Taking the data throughput rate of NR FR1 7Gbps as an example, in the initial transmission, if all the coded blocks in the transmission block are decoded incorrectly, the number of soft bit data of each coded block after compression is 4, and the bit error rate is assumed to be 2 /3, then the DDR throughput rate of soft bits is 7*1.5*4=42Gbps. When retransmitting, first read the soft bit data from DDR to the on-chip HARQ memory for HARQ combination. If the decoding error is then moved from the on-chip HARQ memory to DDR, the peak throughput rate of DDR can reach twice that of the initial transmission, that is, 84Gbps.

In order to meet the working requirements of DDR, in a possible technical solution, the maximum throughput rate that DDR can achieve under the current network configuration can be calculated according to the carrier parameters of the network configuration, and then the voltage and/or DDR can be set according to the maximum throughput rate. frequency.

Specifically, after the network configures parameters such as the number of carriers, carrier bandwidth, and subcarrier spacing of LTE/NR, the maximum throughput rate of DDR can be calculated according to the configured parameters, and then the voltage of DDR can be set according to the maximum throughput rate of DDR. and/or frequency. For example, if the network is configured with 3 LTE carriers, each carrier has a bandwidth of 20MHz, the highest modulation method is 256QAM, and the highest number of layers is 4, then the maximum data throughput rate of the 3 carriers is 1.2Gbps. Assuming that the number of compressed soft bits is 4 and the bit error rate is 2/3, the maximum throughput rate of DDR is 1.2*1.5*4*2=14.4Gbps.

Exemplarily, Table 1 lists the data throughput rate, the maximum throughput rate of DDR, and the voltage correspondence under common configurations of NR/LTE/ENDC, where Level 1 is the lowest voltage file, and Level 4 is the highest voltage file.

Table 1

It can be seen from Table 1 that the four network configurations correspond to four DDR voltage configurations, and each voltage configuration can be adapted to the maximum throughput rate of DDR under the corresponding network configuration.

As shown in Table 1, several situations are included in Table 1. For example, taking the LTE 3 carrier configuration scenario shown in Table 1 as an example, the actual throughput rate of DDR does not exceed the maximum throughput rate (14.4Gbps) under the network configuration. ), the DDR voltage configuration is Level 1. In another case, taking the ENDC (LTE 3 carrier + NR 1 carrier) configuration scenario shown in Table 1 as an example, the actual throughput rate of DDR is 3.5Gbps, which is far less than the maximum throughput rate of 40Gbps under this network configuration, but In this case, the voltage of DDR is still configured as Level 4. In this case, the power consumption of DDR will be greatly wasted.

It can be seen from the above examples that the voltage and/or frequency of the DDR is usually not lower than the voltage and/or frequency required by the maximum throughput of the DDR. Although this configuration method can meet the throughput requirements of DDR in various scenarios under the current network configuration, it is very unfriendly to DDR power consumption because the voltage and/or frequency of DDR are set according to the maximum throughput. In most cases, the throughput of DDR is close to the average throughput, and only in a few extreme cases will it be close to the maximum throughput. If the DDR always configures the corresponding voltage and/or frequency according to the maximum throughput rate, it will bring a large waste of power consumption to the DDR.

For example, the average throughput rate of DDR is determined by the hard bit throughput rate of the MAC layer of the data plane and the decrypted data throughput rate of the PDCP layer of the data plane. Under normal circumstances, the network ensures that the BLER is maintained within 10% by adjusting the MCS of the PDSCH, and the on-chip HARQ memory can meet the storage of soft bit data of the coded block under 10% BLER without reading and writing soft bit data to DDR. In this case, the type of access data to DDR is mainly that the PDCP layer on the data plane decrypts the hard bits of the code block with correct CRC, and the decrypted data has one read and one write operation for DDR. At this time, the throughput rate of DDR is the data transmission rate. 2 times. Taking the data throughput rate of NR FR1 7Gbps as an example, when the data transmission rate is 7Gbps, the average throughput rate of DDR is 14Gbps, which is far less than its maximum throughput rate of 84Gbps. If the voltage and frequency are set according to the maximum throughput rate, the power consumption of DDR is very high. Large, and cause a lot of waste.

On the other hand, actual networks do not always transmit data at the maximum throughput rate. In a relatively low SNR environment, in order to maintain a BLER of 10%, the network usually reduces the MCS of the transmission block. At this time, the data throughput rate will also decrease, and the corresponding DDR average throughput rate will also decrease. The required DDR voltage and / Or the frequency will become smaller, if the voltage and / or frequency are also set according to the maximum throughput rate, the power consumption of DDR will cause a lot of waste.

It can be seen that setting the voltage and/or frequency according to the maximum throughput rate is not conducive to optimizing the power consumption of the DDR. However, with the continuous evolution of communication technologies, terminals have increasingly strict requirements on power consumption. In view of this, the embodiment of the present application provides a DDR access method, using the time slot of the PDSCH as a unit, through Dynamic Voltage Frequency Scaling (Dynamic Voltage Frequency Scaling, DVFS) technology, according to the throughput of DDR, dynamically adjust the voltage and and/or frequency to reduce DDR power consumption.

Specifically, for the DDR storing the decoded data of the transport block, since the processor 11 decodes the transport block in units of PDSCH time slots, the throughput rate of the DDR is closely related to the PDSCH time slots. Next, the transmission block size scheduled by the network for each time slot, the signal-to-noise ratio of each time slot, and the decoding conditions of the initial transmission and retransmission of the transmission block of each time slot affect the throughput of DDR. factors are analyzed.

One of the factors affecting the throughput rate of DDR changes in each time slot: the change of the transmission block size scheduled by the network in each time slot.

To maintain a BLER of 10%, the network lowers the MCS and the transport block size becomes smaller when the SNR becomes low, and increases the MCS and the transport block size becomes larger when the SNR becomes higher. A change in the transport block size will result in a change in the average throughput of DDR.

The second factor that affects the throughput rate of DDR changes in each time slot: the change of the signal-to-noise ratio of each time slot.

When PDSCH passes through fast-fading channels or interference, the signal-to-noise ratio will decrease. Before the network adjusts the MCS, the BLER of the coding block will rise for a short period of time. At this time, the access to the soft bit data of DDR will cause the throughput of DDR to change suddenly. big.

The third factor that affects the throughput rate of DDR changes in each time slot: each time slot may be an initial transmission or a retransmission.

In the case of retransmission and incorrect decoding, the soft bit data needs to be moved from the DDR to the on-chip HARQ memory first. After decoding, if the decoding fails, the soft bit data needs to be moved from the on-chip HARQ memory to the DDR. , at this time, the throughput rate of DDR may reach the peak throughput rate.

To sum up, the applicant has found that the throughput rate of DDR will change due to changes in MCS, BLER, and decoding of initial transmission and retransmission in each time slot. Between different time slots, the throughput rate of DDR may change greatly. The embodiment of the present application takes the time slot as the unit, and dynamically adjusts the voltage and/or frequency of the DDR according to the change of the throughput rate of the DDR in different time slots, so that it can respond more accurately to the change of the DDR throughput rate, which is beneficial to further optimize the DDR power consumption.

FIG. 2 exemplarily shows a flow chart of a DDR access method provided by an embodiment of the present application. The DDR access method in this embodiment is described by taking the system 10 running on the system 10 in FIG. 1 as an example. As shown in Figure 2, it mainly includes the following steps:

Step 201 , adjust the frequency and/or voltage of the DDR in the first time slot according to the throughput rate of the DDR in the first time slot, wherein the first time slot is a time slot of the physical downlink shared channel PDSCH.

Among them, the throughput rate of DDR includes the throughput rate generated when the DDR is read and/or written. The throughput rate of the DDR in the first time slot is that the DDR reads and/writes the DDR in the first time slot. The resulting throughput rate.

It should be noted that the first time slot in this embodiment of the present application may be a PDSCH time slot, that is, in this embodiment of the present application, the voltage and/or frequency of DDR may be dynamically adjusted in units of PDCSH time slots.

In this embodiment of the application, the frequency and/or voltage of the DDR in the first time slot is adjusted according to the throughput rate of the DDR in the first time slot. There may be multiple possible implementations:

For example, when the throughput rate of DDR in the first time slot becomes larger, the frequency and/or voltage of DDR in the first time slot can be increased; when the throughput rate of DDR in the first time slot becomes smaller, reduce The frequency and/or voltage of the DDR in the first time slot.

Specifically, when the throughput of the DDR becomes larger, the voltage and/or frequency of the DDR is increased to meet the working requirements of the DDR. When the throughput rate of the DDR becomes smaller, the voltage and/or frequency of the DDR is correspondingly reduced, so as to reduce the power consumption of the DDR while meeting the working requirements of the DDR.

For another example, a throughput range may be set for the DDR throughput, and different throughput ranges correspond to different voltage and/or frequency configuration levels. Exemplarily, it can be shown in the following table 2:

Table 2

吞吐率区间Throughput range	电压和/或频率配置等级Voltage and/or Frequency Configuration Levels

区间1Interval 1	等级1 Grade 1
区间2 Interval 2	等级2 Level 2
区间3 Interval 3	等级3 Level 3

As shown in Table 2, the DDR throughput setting has 3 throughput rate intervals (interval 1-3), and each interval corresponds to a different voltage and/or frequency configuration level (level 1-3). Based on the corresponding relationship shown in Table 2, the corresponding voltage and/or frequency configuration level can be selected according to the throughput range of the throughput rate of DDR in the first time slot, and then the voltage and/or frequency configuration level of DDR in the first time slot can be adjusted. or frequency adjustment for that voltage and/or frequency configuration level.

For another example, Table 3 lists the corresponding relationship between different DDR voltages, frequencies and DDR throughput rates, where Level 1 is the lowest level, and Level 4 is the highest level. The voltage and frequency are adjusted according to the DDR throughput rate of the first time slot. details as follows:

When the throughput rate of DDR is less than or equal to the first level, the VDD voltage is set to the first level, and the frequency is set to the first level; when the DDR throughput rate is greater than the first level and less than or equal to the second level, the VDD voltage is set to the second level , the frequency is set to the second gear; when the DDR throughput rate is greater than the second gear and less than or equal to the third gear, the VDD voltage is set to the third gear, and the frequency is set to the third gear; when the DDR throughput rate is greater than the third gear and less than or equal to In the fourth gear, the VDD voltage is set to the fourth gear, and the frequency is set to the fourth gear; when the DDR throughput rate is greater than the fourth gear, the VDD voltage is set to the fourth gear, and the frequency is set to the fourth gear.

table 3

VDD电压VDD voltage	频率(MHz)Frequency (MHz)	DDR吞吐率(Gbps)DDR Throughput Rate(Gbps)
Level 4 Level 4	Level 4 Level 4	Level 4 Level 4
Level 3 Level 3	Level 3 Level 3	Level 3 Level 3
Level 2 Level 2	Level 2 Level 2	Level 2 Level 2
Level 1 Level 1	Level 1 Level 1	Level 1 Level 1

It can be understood that the specific implementations of adjusting the frequency and/or voltage of the DDR in the first time slot according to the throughput rate of the DDR in the first time slot are not limited to the above three, and the embodiments of the present application will not list them one by one. .

Step 202, in the first time slot, based on the frequency and/or voltage of the DDR in the first time slot, read and/or write the decoded data of the first transmission block to the DDR, the first transmission block is transmitted via the PDSCH .

That is to say, in the embodiment of the present application, the DDR can store the decoded data of the first transport block, and the first transport block is transmitted via the PDSCH. Therefore, the throughput rate of the DDR is limited between different PDSCH time slots. Larger changes are possible.

In the first time slot, the processor 11 decodes the first transmission block, and reads and/or writes the decoded data from the DDR according to the DDR transmission mechanism. Generally speaking, the DDR transmission mechanism is mainly determined by downlink control information (Downlink control information, DCI) and decoding conditions.

For example, in the process of decoding the first transmission block, each coded block in the first transmission block needs to be decoded separately. Taking one of the coding blocks as an example, a cyclic redundancy check (CRC) needs to be performed on the coding block first. The encoding block includes a CRC check code, and the so-called CRC check mainly includes checking the CRC check code of the encoding block.

Optionally, the CRC result mainly includes the following situations:

(1) When an error occurs in the CRC of the coded block, the compressed soft bit data corresponding to the coded block with the CRC error is written into the DDR;

(2) When the CRC of the coded block is correct, and in the first transmission block, when all the CRCs of the coded blocks before the coded block are correct, the coded block is decrypted, and the decrypted data obtained by decryption is written into the DDR; processor The Package Traffic Accelerator (PTA) in 11 can read the decrypted decrypted data in the DDR, and transmit the decrypted data to the upper layer;

3) When the CRC of the coded block is correct and there is a coded block with a CRC error before the coded block in the first transmission block, write the hard bit data of the coded block into the DDR.

When the current first transmission block is the first transmission block initially transmitted, if the first transmission block has a CRC error in the encoding block, the system 10 will receive the retransmitted first transmission block again, and The first transmission block of is decoded again, that is, retransmission decoding. During the retransmission decoding process:

(1) Carry out CRC again on the coding block whose CRC was wrong in the previous time. During this process, the compressed soft bit data needs to be read from the DDR to the on-chip memory, combined with the soft bit data in the on-chip memory, and CRC is performed on the combined soft bit data.

(2) Read the hard bit data of the encoded block from the DDR for the coded block whose CRC is correct but stores the hard bit data, and decrypt the read hard bit data, and write the decrypted decrypted data into the DDR . This decrypted data can then be read by the PTA.

In order to facilitate understanding, the embodiment of the present application next uses Figure 3 and Figure 4 as examples to illustrate the DDR transmission mechanism when the first transmission block is an initial transmission and when the first transmission block is a retransmission:

As shown in FIG. 3 , FIG. 3 gives an embodiment of each coding block in a transmission block in the case of initial transmission, and the transmission block TB0 includes coding blocks CB0 to CB4 . Assume that the CRCs of CB0, CB2 and CB3 are correct, and the CRCs of CB1 and CB4 are wrong.

Among them, the coding block CB0 is decoded correctly, and there is no decoding error coding block before CB0. In this case, the physical layer submits CB0 to the data plane, and the data plane decrypts the coding block CB0 and decrypts the decrypted Data is written to DDR. Then, the PTA reads the decrypted data corresponding to the encoded block CB0 from the DDR and transmits it to the upper layer.

The coded block CB1 is decoded incorrectly. In this case, the physical layer writes the soft bit data of the coded block CB1 into the DDR, waiting for retransmission and combination.

The coded blocks CB2 and CB3 are decoded correctly, but the coded block CB1 before CB2 and CB3 is decoded incorrectly. In this case, the data plane does not decrypt CB2 and CB3, but writes the hard bit data of CB2 and CB3 into Temporary storage in DDR.

As shown in FIG. 4, FIG. 4 gives an embodiment of each coded block in a transport block in the case of retransmission, and the transport block TB0 includes coded blocks CB0 to CB4. Assume that the CRCs of the coding blocks CB0, CB2, and CB3 are correct when they are initially transmitted, and the CRCs of CB1 and CB4 are wrong.

For coded blocks CB0, CB2, and CB3, since the CRC is correct at the initial transmission, there is no wrong coded block before CBO, and CB0 is directly sent to the data plane for decryption. The CRCs of CB2 and CB3 are correct, but CB1, which had a CRC error before, Therefore, the hard bits of CB2 and CB3 are written into the DDR. At the time of retransmission, read the soft bit data of the coding blocks CB1 and CB4 from the DDR, write them into the on-chip memory for merging, and after the CRC of the combined soft bit data of the coding blocks CB1 and CB4 is correct, transfer the combined soft bit data from the physical layer Submitted to the data plane, the data plane reads the hard bit data of CB2 and CB3 from DDR, and performs decryption operation together with CB1 and CB4. At this time, the decrypted data of CB1, CB2, CB3 and CB4 are obtained, and PTA reads them from DDR CB1, CB2, CB3, and B4 decrypt the data and transmit it to the upper layer.

Referring to Fig. 4, TB0 also includes coded blocks CB5, CB6, CB7, CB8, CB9, wherein, coded blocks CB5, CB6, CB8 decoding errors, at this time, the physical layer writes the soft bits of coded blocks CB5, CB6, CB8 DDR, waiting for retransmission coalescing. Coded blocks CB7 and CB9 are decoded correctly, but because the coded block (CB8) before CB7 and CB9 is decoded incorrectly, the data plane does not decrypt CB7 and CB9, and writes the hard bits of CB7 and CB9 into DDR.

Based on the above DDR transmission mechanism, in the process of writing to DDR, the soft bit data generated includes the soft bit data corresponding to the code block when the CRC of the code block is wrong; the hard bit data is included when the CRC of the code block is correct. , and for the transmission block where the coding block is located, when there is a coding block with a CRC error before the coding block, the hard bit data corresponding to the coding block; the decoded data is included in the coding block CRC is correct, and for the transmission block where the coding block is located, When there is no coded block with CRC error before the coded block, the decoded data corresponding to the coded block.

It can be understood that, in the embodiment of the present application, it is necessary to determine the throughput rate of the DDR in the first time slot before the first time slot. Exemplarily, the throughput rate of the next time slot may be determined according to the data access amount of the previous time slot. In one optional embodiment, as shown in FIG. 5, the method includes:

Step 301: Determine the data access amount of the DDR in the first time slot according to the data access amount of the DDR in the second time slot, where the second time slot is the previous time slot of the first time slot.

Wherein, the data access amount refers to the data access amount determined according to the data amount of decoded data read and/or written from the DDR during the decoding process of the transport block.

Optionally, the following formula is satisfied between the data access amount of the first time slot and the data access amount of the second time slot:

De=(1-a)*Dh+a*Dl

Wherein, De is the data access amount of the DDR calculated in the first time slot, Dh is the data access amount of the DDR in the previous time slot of the second time slot, and D1 is the data access amount of the DDR in the second time slot, a is greater than 0 and less than or equal to 1, for example, here a may be set to 0.4.

In this embodiment of the application, the data access amount of the DDR in the first time slot can be determined according to the data access amount of the DDR in the second time slot, wherein the data access amount of the DR in the second time slot includes the data access amount of the second time slot in the second time slot. The data volume of the decoded data of two transport blocks, the second transport block is the previous transport block of the first transport block, and the decoded data of the second transport block includes soft bit data or hard bit data of each coded block in the second transport block bit data or decrypted data; or, the data access amount of the first time slot DDR can also be determined according to the data access amount of the DDR of the historical time slot, wherein, the historical time slot can be the previous time slot of the first time slot, or It may be the first several time slots of the first time slot.

Exemplarily, it can be seen from the above-mentioned DDR transmission mechanism that the processing of coded blocks whose CRC succeeds or fails will cause different times of access to the DDR, thereby affecting the data access volume of the DDR. Therefore, in the embodiment of the present application, the data access amount of DDR can be determined according to the DDR transmission mechanism provided in this embodiment, by analyzing the second transmission block processed in the second time slot, each coding block performs corresponding The DDR access operation determines the data access amount of the DDR in the second time slot, and then calculates the data access amount of the DDR in the first time slot.

Step 302: Calculate the throughput rate of the DDR in the first time slot based on the calculated data access amount of the DDR in the first time slot and the decoding time for the first transport block.

In this embodiment, the throughput of the DDR refers to the data access volume of the DDR per unit time. After calculating the data access volume of the DDR in the first time slot, the throughput rate of the DDR in the first time slot can be determined.

Optionally, the throughput rate of the DDR in the first time slot may be calculated according to the data access amount of the DDR in the first time slot and the decoding time for the first transport block.

Wherein, the decoding time of the first transmission block may be understood as the time required for one decoding of the first transmission block.

Among them, the specific calculation formula of the throughput rate is as follows:

Throughput rate = data access volume of DDR/N1

Wherein, N1 is used for decoding the first transport block. It should be noted that the value of N1 is different according to the capabilities of different terminals.

In this embodiment, the data access amount of the first time slot is determined according to the data access amount caused by the access to the DDR in the second time slot, so as to calculate the throughput rate of the first time slot according to the data access amount of the first time slot. In the method of calculating the throughput rate based on the amount of data access, the obtained throughput rate is more accurate, so that the frequency and/or voltage of the first time slot can be adjusted more accurately.

In the above-mentioned embodiments, the present application mainly describes the case where the PDSCH is a single-carrier channel, that is, the processor 11 reads and/or writes decoded data of one transport block from the DDR within one time slot. It can be understood that the current PDSCH is mostly a multi-carrier channel, and multiple carriers can transmit multiple transport blocks in parallel at the same time. In a possible implementation manner, the respective throughput rates corresponding to the multiple transport blocks transmitted in parallel in the first time slot may be estimated according to the foregoing embodiments, so as to obtain the throughput rate of the DDR in the first time slot.

Exemplarily, each time the voltage and/or frequency of the DDR is adjusted, there will be a period of time when the DDR cannot be accessed. Therefore, it should be avoided to adjust the voltage and/or frequency of the DDR frequently and multiple times in each time slot. In this case In this case, especially for multi-carrier scenarios, the DDR frequency of the first time slot can be adjusted according to the DDR throughput rate corresponding to the transport block of each carrier in the second time slot and the decoding start time of the transport block of each carrier. moment.

In one of the optional embodiments, the first channel includes a plurality of carriers, each carrier is used to receive the transport block, and the frequency and/or frequency of the DDR in the first time slot is adjusted according to the throughput rate of the DDR in the first time slot or voltage, including:

When the time interval between the decoding start time of each transport block in the first time slot and the start time of the first time slot is not greater than the first threshold, according to the calculated DDR throughput in the first time slot , configure the frequency and/or voltage of the DDR at the start time point of the first time slot, and maintain the frequency and/or voltage of the DDR in the first time slot.

Exemplarily, as shown in FIG. 6, there are three transmission blocks TB0, TB1, and TB2 in FIG. 6, where t is the first threshold. Obviously, as shown in FIG. The code enlightenment moment, the time interval between the decoding revelation moment of TB2 and the start moment of the first time slot are all less than the first threshold t, in this case, the processor can , configure the frequency of the DDR at the start time point of the first time slot, and maintain the frequency of the DDR in the first time slot.

Further, in order to more accurately calculate the throughput and adjust the frequency and/or voltage of the DDR, optionally, after the first time slot, the actual throughput of the DDR in the first time slot and the calculated The difference between the throughput rates of the DDRs is used to correct the calculated throughput rates of the DDRs in the third time slot, where the third time slot may be the next time slot of the first time slot.

Taking Figure 6 as an example, there are three transmission blocks CC0 TB0, CC1 TB0, and CC2 TB1 in Figure 6, and the time intervals between their corresponding decoding start moments and the start moments of the second time slot are all smaller than the first threshold, in this case. The throughput rate of the first time slot is the sum of the throughput rates of the transmission blocks CC0 TB0, CC1 TB0, CC2 TB1, that is, by calculating the sum of the throughput rates of CC0 TB0, CC1 TB0, CC2 TB1 and CC0 TB0, CC1 TB0, CC2 The difference between the sums of the actual throughput rates of TB1, if the difference is greater than the first preset threshold, the throughput rate of the next time slot is corrected.

In the scenario shown in Figure 6, the actual throughput rate of DDR in the first time slot can be the sum of the actual throughput rates of CC0 TB0, CC1 TB0, and CC2 TB1, and the calculated DDR throughput rate is the calculated CC0 TB0, CC0 TB0, The sum of the throughput rates of CC1 TB0 and CC2 TB1. Based on the difference between the actual throughput rate of DDR in the first time slot and the calculated DDR throughput rate, correct the calculated throughput rate of DDR in the third time slot, if the actual throughput rate of DDR in the first time slot The difference between the calculated DDR throughput minus the calculated DDR is greater than the first preset threshold. In this case, the calculated DDR throughput in the third time slot needs to be increased. If the difference between the calculated DDR throughput minus the actual DDR throughput in the first time slot is greater than the first preset threshold, in this case, you need to reduce the calculated DDR throughput in the third time slot Rate.

Optionally, in another scenario, according to the throughput rate of the DDR in the first time slot, the frequency of the DDR in the first time slot is adjusted, as shown in FIG. 7 , including:

Step 401, when there is a third transmission block in the first time slot, configure the frequency and/or voltage of the DDR at the start time point of the first time slot according to the calculated throughput of the DDR in the first time slot.

Wherein, the interval between the decoding start time of the third transmission block and the start time of the first time slot is greater than the first threshold.

Optionally, the calculated throughput rate of the DDR in the first time slot includes transport blocks whose time interval between the start time of decoding and the start time of the first time slot for reading and/or writing from the DDR is smaller than the first threshold The sum of the throughput rates of the decoded data.

Referring to FIG. 8 , the PDSCH in FIG. 8 includes 3 carriers CC0/CC1/CC2, and the decoding start time of the transport blocks in each carrier can refer to FIG. 8 . In the first time slot, TB0 transmitted by CC0, TB0 transmitted by CC1, and TB1 transmitted by CC2 need to be decoded. Wherein, CC2 TB1 is the third transmission block, and the interval between CC2 TB1 and the start moment of the first time slot is greater than the first threshold t. Then, before the first time slot, the calculated throughput of the DDR in the first time slot includes the sum of the throughput rates of the decoded data read from and/or written to CC0 TB0 and CC1 TB0 from the DDR, according to the throughput The sum adjusts the frequency and/or voltage at the start time point of the first time slot.

In this embodiment, reference may also be made to FIG. 9, which involves three carriers CC0/CC1/CC2. After receiving the downlink control information (Downlink control information, DCI) of the transmission block TB0 of the carrier CC0, the transmission is received. Block TB0. And after receiving the transport block TB0, determine its corresponding throughput rate Tput1, and receive the transport block TB0 after receiving the DCI of the transport block TB0 of the carrier CC1. And after receiving the transport block TB0, determine its corresponding throughput rate Tput2, and after receiving the DCI of the transport block TB1 of the carrier CC2, receive the transport block TB1. And after receiving the transport block TB1, determine the corresponding throughput rate Tput3.

Step 402: Increase the frequency and/or voltage of the DDR after the decoding start moment of the third transmission block according to the data volume of the decoded data read and/or written into the third transmission block.

In this embodiment, during the DDR read and/or write operation on the third transmission block, the decoding of the third transmission block may also be adjusted based on the data amount of the decoded data of the third transmission block. The frequency after the start time, that is, as the data access to DDR based on the third transmission block increases, the frequency after the decoding start time of the third transmission block is dynamically increased to meet the bandwidth requirement of DDR.

Similar to the above, in order to more accurately calculate the throughput and adjust the frequency and/or voltage of the DDR, optionally, after the first time slot, it can also be calculated based on the actual throughput of the DDR in the first time slot and the calculated The difference between the throughput rates of the DDRs is corrected to the calculated throughput rate of the DDR in the third time slot, where the third time slot may be the next time slot of the first time slot.

As shown in Figure 8, the difference between the decoding start time of the transport block TB0 of CC0 and the transport block TB0 of CC1 in the first time slot and the start time of the first time slot (dotted circle 1 in Figure 8) can be set The time interval between is not greater than the first threshold, the time interval between the decoding start time of CC2 TB1 and the start time of the first time slot is greater than the first threshold, and CC2 TB1 is the third transport block. In the second time slot, during the read and/or write operation of DDR to CC2 TB1, the DDR can be increased in CC2 TB1 according to the amount of decoded data read and/or written to CC2 TB1. The frequency and/or voltage after the start of decoding.

Optionally, in this scenario, the processor may calculate the difference between the calculated throughput sum of multiple transport blocks and the actual throughput sum of each transport block in the first time slot, for the third time slot The throughput rate is corrected. Similar to the correction method above, if the difference is greater than the first preset threshold, the throughput of the third time slot is corrected, and if the difference is not greater than the first preset threshold, the throughput of the third time slot is not required. rate, which is not limited in this embodiment.

As shown in Figure 8, the time interval between the decoding start moment of transport block CC2 TB1 and the start moment of the first time slot is greater than the first threshold t, in this case, when the throughput rate of the first time slot is calculated There are two situations in the correction process.

In the first case, when obtaining the calculated throughput rate of the first time slot, the throughput rate of CC2 TB1 has not been obtained, that is, before the first time slot, the calculated throughput rate of the first time slot is only CC0 The sum of the throughput rates of TB0, CC1 TB0, at this time, calculate the difference between the sum of the throughput rates of CC0 TB0, CC1 TB0 and the actual sum of the throughput rates of CC0 TB0, CC1 TB0, if the difference is greater than the first preset threshold, the calculated throughput of the DDR in the third time slot is corrected.

In the second case, although the time interval between the decoding start time of CC2 TB1 and the start time of the current time slot is greater than the first threshold, CC0 TB0, CC1 TB0, and CC2 TB1 can still be calculated during the first time slot In this case, the processor can calculate the difference between the sum of the throughput of CC0 TB0, CC1 TB0, and CC2 TB1 and the actual sum of the throughput of CC0 TB0, CC1 TB0, and CC2 TB1 , if the difference is greater than the first preset threshold, modify the throughput of the next time slot.

In this embodiment, in the scenario where there are multiple carriers, the throughput rate of the first time slot is determined according to the data access volume of all coded blocks involved in the transport blocks involved in each carrier in the second time slot, which is calculated as The throughput rate is more accurate.

Optionally, in one of the optional embodiments, the threshold value of the DDR throughput rate includes a highest threshold value and a lowest threshold value, and the above method also includes:

When the throughput rate of DDR is greater than the highest threshold value, adjust the frequency and/or voltage of DDR in the first time slot according to the highest threshold value; Limits adjust the frequency and/or voltage of the DDR in the first time slot.

In this embodiment, if the throughput rate of DDR is greater than the highest threshold value, since the maximum throughput rate or maximum bandwidth supported by DDR is the highest threshold value, in this case, the maximum threshold value will be adjusted The throughput rate of DDR, and adjust the frequency and/or voltage of the first time slot based on the throughput rate of DDR after adjustment; If the throughput rate of DDR is less than the minimum threshold value, because the minimum throughput rate or minimum bandwidth supported by DDR is is the lowest threshold value, in this case, adjust the throughput rate of DDR according to the lowest threshold value, and adjust the frequency and/or voltage of the first time slot based on the adjusted DDR throughput rate, this embodiment No limit.

Further, based on the possibility of initial transmission and/or retransmission of the coding block in the downlink receiving process, in the case of initial transmission, the minimum threshold value includes the minimum threshold value for initial transmission, and the highest threshold value includes the highest threshold;

Wherein, the minimum threshold value of the initial transmission is equal to the data volume of the transmission block in the current time slot.

In this embodiment, the scenario where the lowest threshold of initial transmission occurs is that the CRCs of all coded blocks CB are decoded correctly. In this scenario, the operations to be performed include "decrypt the coded blocks with Write data into DDR; read the decrypted data in DDR through the packet traffic accelerator, and transmit the decrypted data to the upper layer", writing decrypted data into DDR involves access to DDR, and reading decrypted data in DDR also involves access to DDR access, but the decrypted data in the DDR read by the packet traffic accelerator is not within the statistical range of the physical layer. Therefore, in this scenario, the data access volume of the DDR includes writing the decrypted data corresponding to all encoded blocks into the DDR. At this point, the lowest threshold is equal to all transport block sizes.

The initial transmission maximum threshold value is determined according to at least one of the data volume of the transmission block, the code rate, the number of bits of each soft bit stored on the DDR, and the remaining capacity of the on-chip memory; the remaining capacity of the on-chip memory is based on the on-chip memory. The total capacity, the storage ratio threshold of the on-chip memory, and the on-chip memory are determined by at least one of the occupied capacity.

In this embodiment, the scenario where the highest threshold of initial transmission occurs is that the CRCs of all coded blocks CB are decoded incorrectly. In this scenario, the operation to be performed is "compressed soft Bits are written to DDR", at this time, the highest threshold is equal to the total amount of data of all soft bits stored on the DDR, that is, the size of all transport blocks * (1/code rate) * the number of bits of each soft bit - the remaining On-chip HARQ memory size. Wherein, the size of the remaining on-chip HARQ memory=the total size of the on-chip HARQ memory*the waterline moved from the on-chip memory to the DDR-the size of the already occupied on-chip memory. The water line moved from the on-chip memory to the DDR is determined according to the actual storage space of the on-chip memory. For example, the theoretical storage space of the on-chip memory is 1T, and the actual storage space is 0.8T. Then the water line moved from the on-chip memory to the DDR The line is 0=80%, which is not limited in this embodiment.

In the case of retransmission, the lowest threshold includes the lowest retransmission threshold, and the highest threshold includes the highest retransmission threshold;

The minimum threshold value for retransmission is determined according to the minimum value of the first data access amount and the second data access amount, and the amount of soft bits stored in the on-chip memory from the DDR. The first data access amount is retransmission When the CRCs of all coding blocks in the project are correct, the data volume of DDR is accessed, and the second data access volume is the data volume of accessing DDR when the CRCs of all coding blocks in the retransmission project are wrong;

The maximum retransmission threshold value is determined according to the maximum value of the first data access amount and the second data access amount, and the amount of soft bits moved from the DDR to the on-chip memory.

Optionally, the above-mentioned first data access amount is determined according to the number of coded blocks stored in soft bits, the number of coded blocks stored in hard bits, and the data volume of the coded blocks in DDR; the second data access amount is equal to that from DDR The amount of data moved to the soft bits stored in the on-chip memory.

In this embodiment, if the CRCs of all coded blocks CB for retransmission are all decoded correctly, then the first data access amount=(the number of coded blocks stored as soft bits+the number of coded blocks stored as hard bits*2 )*encoding block size. If the CRCs of all the retransmitted coded blocks CB are decoded incorrectly, the second data access amount=the amount of soft bit data moved from the DDR to the on-chip HARQ memory.

Determine the minimum threshold for retransmission and the maximum threshold for retransmission according to the possible extreme situations of retransmission above:

The minimum threshold for retransmission is equal to the sum of the amount of soft bit data moved from DDR to the on-chip HARQ memory and the minimum value in {the first data access amount, the second data access amount}. Specifically, the minimum threshold for retransmission=moved from DDR The amount of soft bit data to the on-chip HARQ memory+min{(number of coded blocks stored as soft bits+number of coded blocks stored as hard bits*2)*coded block size, soft bits moved from DDR to on-chip HARQ memory The amount of data}.

The highest threshold for retransmission is equal to the amount of soft bit data moved from DDR to the on-chip HARQ memory + the sum of the maximum value in {first data access amount, second data access amount}, specifically, the highest threshold for retransmission = from DDR The amount of soft bit data moved to the on-chip HARQ memory+max{(the number of coded blocks stored as soft bits+the number of coded blocks stored as hard bits*2)*coded block size, the soft bit data moved from DDR to the on-chip HARQ memory bit data amount}, which is not limited in this embodiment.

Optionally, considering that during the process of reading/writing the DDR, in another scenario, the above method further includes: decoding the transport block according to the decoding period. Exemplarily, reading and/or writing to the DDR may be stopped according to a clock gating signal.

As shown in Fig. 10, the dotted circle 1 is the start time of the decoding period, and the dotted circle 4 is the end time of the decoding. Corresponding to dotted circle 4, the clock gating signal (clock gating) is used to instruct the decoder to stop working, that is, the decoding of the code block will not be performed, and the DDR will stop reading and/or writing. For example, when the CPU receives the clock gating signal, at least one of the read and/or write operations is stopped for the DDR. Especially in the case of no encoding block transmission, the clock gating signal is used to instruct the decoder to stop working, which saves the power consumption of the decoder.

In view of this, the method provided by the present application further includes: in the decoding period, according to the throughput rate of the double rate synchronous dynamic random access memory DDR in the first time slot, adjusting the DDR in the first time slot frequency and/or voltage.

That is to say, the processor will execute decoding only in the decoding cycle, and will only read and/or write the decoding data from DDR in the decoding cycle. Therefore, the DDR can be used in the decoding cycle The throughput rate changes dynamically adjust the voltage and/or frequency of the DDR.

Exemplarily, before the decoding start moment of the first transport block, calculate the first throughput rate of the first time slot during the decoding of the first transport block; when the first throughput rate is greater than the previous adjusted voltage and/or frequency In the case of corresponding throughput rate, increase the frequency and/or voltage of DDR.

As shown in Figure 10, at the beginning of the decoding cycle (dotted circle 1), the sum of the throughput rates of CC0 TB0 and CC1 TB0 is calculated as Tput (CC0 TB0+CC1 TB0), and at the time of dotted circle 1 according to Tput (CC0 TB0+CC1 TB0) adjusts the voltage and/or frequency of DDR. Take CC2 TB1 as an example. At the beginning of CC2 TB1 decoding, calculate the first throughput rate. The first throughput rate is CC0 TB0, CC1 TB0 and CC2 The sum Tput(CC0 TB0+CC1 TB0+CC2 TB1) of the throughput rate of TB1, since Tput(CC0 TB0+CC1 TB0+CC2 TB1) is greater than Tput(CC0 TB0+CC1 TB0), at the start moment of CC2 TB1 decoding ( Dashed circle 2) Increase the frequency and/or voltage of DDR according to Tput(CC0 TB0+CC1 TB0+CC2 TB1).

Further, taking CC2 TB2 as an example, CC0 TB0, CC1 TB0 and CC2 TB1 have been decoded before the decoding start time of CC2 TB2 (dotted circle 3), and the corresponding throughput of CC0 TB0, CC1 TB0 and CC2 TB1 rate is released, therefore, the first throughput rate Tput(CC0 TB1+CC1 TB1+CC2 TB2) calculated at the moment of dotted circle 3, since the throughput rate of CC0 TB1 is equal to the throughput rate of CC0 TB0, the throughput rate of CC1 TB1 is equal to The throughput rate of CC1 TB0, and the throughput rate of CC2 TB2 is greater than that of CC2 TB1, so Tput(CC0 TB1+CC1 TB1+CC2 TB2) is greater than Tput(CC0 TB0+CC1 TB0+CC2 TB1), therefore, in CC2 TB2 The decoding start moment (dotted circle 3) needs to increase the frequency and/or voltage of DDR.

Exemplarily, when the first throughput rate is not greater than the corresponding throughput rate when the voltage and/or frequency was adjusted last time, the frequency and/or voltage of the DDR is maintained.

As shown in Figure 10, CC0 TB1 and CC1 TB1 are taken as examples. Before the decoding start time of CC0 TB1 (solid coil 6), CC0 TB0 and CC1 TB0 have completed decoding, that is, the throughput of CC0 TB0 and CC1 TB0 It has been released, and the first throughput rate at the starting moment of CC0 TB1 decoding is Tput(CC2 TB1+CC0 TB1), since Tput(CC2 TB1+CC0 TB1) is less than the corresponding The throughput rate Tput(CC0 TB0+CC1 TB0+CC2 TB1), therefore, does not adjust the frequency and/or voltage of the DDR. Similarly, at the initial moment of decoding of CC1 TB1 (solid coil 7), the first throughput rate is Tput (CC2 TB1+CC0 TB1+CC1 TB1), since the throughput rate of CC0 TB1 is equal to the throughput rate of CC0 TB0, CC1 TB1 The throughput rate of CC1 TB0 is equal to the throughput rate of CC1 TB0, so the first throughput rate Tput (CC2 TB1+CC0 TB1+CC1 TB1) at the decoding start moment of CC1 TB1 (solid coil 7) is equal to the throughput rate corresponding to dashed coil 2 Tput(CC0 TB0+CC1 TB0+CC2 TB1), therefore, maintain the frequency and/or voltage of the DDR.

Exemplarily, when the difference between the throughput rate corresponding to the previous voltage and/or frequency adjustment minus the first throughput rate is greater than the second preset threshold, the frequency and/or voltage of the DDR is reduced.

Assuming that the throughput rate corresponding to the previous voltage and/or frequency adjustment was Tput(CC0 TB0+CC1 TB0+CC2 TB1), calculate the first throughput rate Tput(CC0 TB1 +CC1 TB1+CC2 TB2), since the throughput of CC0 TB1 is equal to the throughput of CC0 TB0, the throughput of CC1 TB1 is equal to the throughput of CC1 TB0, and the throughput of CC2 TB2 is less than the throughput of CC2 TB1, the first throughput The rate Tput(CC0 TB1+CC1 TB1+CC2 TB2) is less than the corresponding throughput rate Tput(CC0 TB0+CC1 TB0+CC2 TB1) when the voltage and/or frequency were adjusted last time, and Tput(CC0 TB0+CC1 TB0+CC2 TB1) If the difference of subtracting Tput(CC0 TB1+CC1 TB1+CC2 TB2) is greater than the second preset threshold, the frequency and/or voltage of the DDR is reduced at the decoding start moment of CC2 TB2.

The DDR access method provided by the embodiment of the present application can be performed within the decoding period according to the first throughput calculated at the start of decoding of each first transmission block and the corresponding throughput when the voltage and/or frequency were adjusted last time. Size comparison, so as to flexibly adjust the frequency and/or voltage of DDR.

FIG. 11 is a flowchart of a data transmission method of DDR in an embodiment. The DDR data transmission method in this embodiment is described by taking the terminal or server running on the terminal or server in FIG. 1 as an example. As shown in FIG. 11 , the DDR data transmission method includes step 501 to step 502 .

Step 501: Decode a first transport block in a first time slot, where the first transport block is transmitted via a PDSCH, and the first time slot is a time slot of the PDSCH.

In this embodiment, the first transmission block of the first time slot is received, and a decoding operation is performed on the first transmission block to obtain the cyclic redundancy check CRC corresponding to each coding block in the transmission block.

Step 502, read and/or write the decoded data of the first transmission block to the DDR.

In this embodiment, the CRC of the first transmission block is decoded. Optionally, the decoding result includes correct decoding or decoding error, and an access operation is performed on the DDR according to the decoding result. Under different decoding results , perform different data processing operations on the coded block, for example, read the decoded data of the coded block from the DDR when the CRC of the coded block is correct.

Optionally, the DDR data transmission provided in this implementation can be applied to the DDR access methods provided in Figures 1 to 10 to realize the DDR-based data transmission method to calculate the DDR throughput, so that the DDR-based throughput can dynamically The purpose of adjusting the frequency of DDR.

In the data transmission method of the above DDR, the first transmission block is decoded in the first time slot, the decoded data of the first transmission block is read and/or written into the DDR, and the access operation of the DDR is performed according to different decoding results Not the same, to achieve the purpose of more accurately counting the total amount of data accessed by each time slot to the DDR.

An implementation in the above step 502, for each coding block in the first transmission block, write the decoded data of the first transmission block to the DDR, including at least one of the following situations:

One: When an error occurs in the CRC of the coded block, write the soft bit data corresponding to the coded block into the DDR.

In this embodiment, when it is determined that the CRC of the coding block is wrong, in this case, the compressed soft bits corresponding to the coding block are written into the DDR. At this time, the data access amount of DDR is determined by soft bit data.

Second: when the CRC of the coded block is correct and there is a coded block with a CRC error before the coded block in the first transmission block, write the hard bit data corresponding to the coded block into the DDR.

In this embodiment, when it is determined that the CRC decoding of the coded block is correct, and for the transport block where the coded block is located, when there is a coded block with a CRC error before the coded block, the hard bits corresponding to the coded block are written into the DDR. , the data access amount of DDR is determined by the hard bit data.

Third: when the CRC of the coded block is correct and there is no coded block with a CRC error before the coded block in the first transmission block, write the decrypted data corresponding to the coded block into the DDR.

In this embodiment, when it is determined that the CRC decoding of the coded block is correct, and for the first transmission block where the coded block is located, if there is no coded block with a CRC error before the coded block, the coded block is directly decrypted, and the decrypted The decoded data of the DDR is written into the DDR, at this time, the data access amount of the DDR is determined by the decoded data. Optionally, when the CRCs of all coded blocks are correct, that is, the flowchart of the DDR data transmission method in the initial transmission scenario may refer to FIG. 12 .

If the CRC of the first transmission block is wrong, the first transmission block needs to be retransmitted. In one scenario, the DDR reads the decoded data of the first transmission block, including:

In the case of retransmission decoding of the first transport block, the soft bit data or hard bit data of each coded block in the first transport block is read from the DDR.

In this embodiment, during the retransmission and decoding process of the transport block, the DDR access operation of the first transport block may also be determined according to whether there is a CRC decoding error in the transport block before the first transport block.

In one scenario, in the scenario of retransmission decoding, as shown in Figure 13, the method further includes:

Step 601, if the previous CRC of the coded block is wrong, read the soft bit data of the coded block from the DDR.

In summary of this embodiment, when the coded block is decoded again, it is the retransmission time of the coded block. From the above embodiment, it can be seen that when the coded block has a CRC error, the wrong coded block will be written into the on-chip memory, and the on-chip memory space In case of overflow, the wrong coded block is written to DDR. In this scenario, for example, if the coded blocks CB0 and CB1 in a transport block TB both have CRC errors during the initial transmission process, the soft bit data of the wrong CBO is stored in the on-chip memory. Due to the limited space of the on-chip memory, The soft bit data of error CB1 is stored in DDR. During the retransmission process of CB0 and CB1, it is necessary to read the soft bit data of error CB1 from DDR and store the soft bit data of error CB1 into the on-chip memory.

Step 602, perform CRC on the encoded block again based on the read soft bit data.

In this embodiment, at the time of retransmission, the CRC check is performed again on the coded block with CRC error based on the read soft bit data. Optionally, before performing the CRC check, the soft bit data of the new CB0 received by retransmission and the soft bit data of the new CB1 can be respectively combined with the soft bit data of the wrong CB0 and the soft bit data of the wrong CB1 in the on-chip memory. The data are merged to obtain the merged CB0 and the merged CB1.

Step 603, when the CRC is correct, decode the encoded block to obtain decrypted data of the encoded block.

In this embodiment, when the CRC is correct, decode the combined CB0 and/or the combined CB1 with the correct CRC to obtain the decoded data corresponding to the combined CB0 and/or the combined CB1, optional Alternatively, the decoded data can be written into the DDR.

In the retransmission decoding process, there is another scenario, including: when decoding the coded block again, if the previous CRC of the coded block is correct, then read the hard bit data of the coded block from the DDR. The data is decrypted to obtain the decoded data of the encoded block.

In this embodiment, if the CRC error of a certain coding block is determined, but the previous CRC of the coding block is correct, in this case, the hard bits corresponding to the coding block with the correct CRC can be temporarily stored in the DDR Among them, at the time of waiting for retransmission, the data plane reads out the code block with correct CRC temporarily stored in the DDR and performs decryption operation to obtain the decrypted data. Optionally, the decrypted data is written into the DDR, which is not limited in this embodiment. Optionally, the flowchart of the DDR data transmission method in the retransmission scenario may refer to FIG. 14 .

In this embodiment, according to the data transmission method for accessing DDR, the total amount of data accessed by each time slot to DDR can be counted during the decoding process, and based on the scenarios of initial transmission and retransmission, calculate the initial transmission and retransmission respectively. The data access volume of the DDR generated by transmitting the data access volume of the DDR is more accurate.

It should be understood that although the various steps in the flow charts of FIGS. 2-14 are displayed sequentially as indicated by the arrows, these steps are not necessarily executed sequentially in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in Figures 2-14 may include a plurality of sub-steps or stages, these sub-steps or stages are not necessarily performed at the same time, but may be performed at different times, these sub-steps or stages The order of execution is not necessarily performed sequentially, but may be performed alternately or alternately with at least a part of other steps or sub-steps or stages of other steps.

Fig. 15 is a structural block diagram of a DDR access device of an embodiment. As shown in Figure 15, the device includes:

The adjustment module 01 is configured to adjust the frequency and/or voltage of the DDR in the first time slot according to the throughput rate of the DDR in the first time slot, wherein the first time slot is a time slot of the physical downlink shared channel PDSCH;

The access module 02 is configured to read and/or write the decoded data of the first transmission block to the DDR based on the frequency and/or voltage of the DDR in the first time slot in the first time slot, the first transmission block is transmitted via the PDSCH.

In one of the optional embodiments, the adjustment module 01 is configured to increase the frequency and/or voltage of the DDR in the first time slot when the throughput rate of the DDR in the first time slot becomes larger; When the throughput rate of one slot decreases, the frequency and/or voltage of the DDR in the first slot is lowered.

In one of the optional embodiments, the adjustment module 01 is also used to determine the data access amount of the DDR in the first time slot according to the data access amount of the DDR in the second time slot, and the second time slot is the first time slot Based on the calculated data access amount of the DDR in the first time slot and the decoding time of the first transport block, the throughput rate of the DDR in the first time slot is calculated.

In one of the optional embodiments, the calculated DDR satisfies the following formula between the data access amount of the first time slot and the data access amount of DDR in the second time slot: De=(1-a)*Dh+ a*Dl

Wherein, De is the data access amount of the DDR calculated in the first time slot, Dh is the data access amount of the DDR in the previous time slot of the second time slot, and D1 is the data access amount of the DDR in the second time slot, a is greater than 0 and less than or equal to 1.

In one of the optional embodiments, the data access amount of the DDR in the second time slot includes the data amount of the decoded data of the second transmission block in the second time slot, wherein the second transmission block is the first transmission block The decoded data of the second transport block includes soft bit data or hard bit data or decrypted data of each encoded block in the second transport block.

In one of the optional embodiments, for each coded block in the first transmission block, the access module 02 is configured to write the soft bit data corresponding to the coded block into the DDR when the CRC of the coded block has an error; and /or, when the coded block CRC is correct, and there is a coded block with a CRC error before the coded block in the first transmission block, write the hard bit data corresponding to the coded block into the DDR; and/or, when the coded block CRC is correct, and When there is no coded block with a CRC error before the coded block in the first transmission block, the decrypted data corresponding to the coded block is written into the DDR.

In one of the optional embodiments, the access module 02 is configured to read the soft bit data or hard bits of each coded block in the first transmission block from the DDR when the first transmission block is retransmitted and decoded data.

In one of the optional embodiments, the PDSCH includes multiple carriers, and each carrier is used for a transport block, and the adjustment module 01 is used for decoding the start time and the first time of each transport block in the first time slot When the time interval between the start times of the slots is not greater than the first threshold, configure the frequency and/or voltage of the DDR at the start time of the first time slot according to the calculated throughput of the DDR in the first time slot , and maintain the frequency and/or voltage of the first time slot of the DDR.

In one of the optional embodiments, the adjustment module 02 is configured to configure the DDR in the first time slot according to the calculated throughput of the DDR in the first time slot when there is a third transmission block in the first time slot. The frequency and/or voltage of the start time point of , wherein the interval between the start time of decoding of the third transport block and the start time of the second time slot is greater than the first threshold; according to reading and/or writing The data volume of the decoded data of the third transport block increases the frequency and/or voltage of the DDR after the decoding start moment of the third transport block.

In an optional embodiment, the calculated throughput rate of the DDR in the first time slot includes a sum of throughput rates of reading and/or writing decoded data of transport blocks respectively corresponding to each carrier from the DDR.

In one of the optional embodiments, the adjustment module 01 is configured to adjust the frequency and/or voltage of the DDR in the first time slot according to the highest threshold value when the throughput rate of the DDR is greater than the highest threshold value; and/or , when the throughput rate of the DDR is less than the minimum threshold value, adjusting the frequency and/or voltage of the DDR in the first time slot according to the minimum threshold value.

In one of the optional embodiments, the access module 02 is further configured to start or stop reading and/or writing to the DDR according to the clock gating signal.

Fig. 16 is a structural block diagram of a DDR-based data transmission device according to an embodiment. As shown in Figure 16, the device includes:

The decoding module 11 is configured to decode a first transmission block in a first time slot, where the first transmission block is transmitted via a PDSCH, and the first time slot is a time slot of the PDSCH;

The access module 12 is configured to read and/or write decoded data of the first transmission block to the DDR.

In one of the optional embodiments, for each coded block in the first transmission block, the access module 12 is configured to write the soft bit data corresponding to the coded block into the DDR when the CRC of the coded block has an error; and /or, when the coded block CRC is correct, and there is a coded block with a CRC error before the coded block in the first transmission block, write the hard bit data corresponding to the coded block into the DDR; and/or, when the coded block CRC is correct, and When there is no coded block with a CRC error before the coded block in the first transmission block, the decrypted data corresponding to the coded block is written into the DDR.

In one of the optional embodiments, the access module 12 is configured to read the soft bit data or hard bits of each coded block in the first transmission block from the DDR when the first transmission block is retransmitted and decoded data.

In one of the optional embodiments, the access module 12 is configured to read the soft bit data of the encoded block from the DDR if the previous CRC of the encoded block is wrong; CRC; when the CRC is correct, decode the coded block to obtain decrypted data of the coded block.

In one of the optional embodiments, the operation module 12 is also used to read the hard bit data of the encoded block from the DDR if the previous CRC of the encoded block is correct; the hard bit data is decrypted to obtain the encoded block Decrypt data.

The division of each module in the above-mentioned DDR access device and the DDR-based data transmission device is only for illustration. In other embodiments, the DDR access device and the DDR-based data transmission device can be divided into different modules as required to complete All or part of the functions of the above-mentioned DDR voltage rate adjustment device and DDR-based data transmission device.

For the specific limitations of the DDR access device and the DDR-based data transmission device, refer to the above-mentioned limitations on the DDR access method and the DDR-based data transmission method, which will not be repeated here. Each module in the above-mentioned DDR access device and DDR-based data transmission device can be fully or partially realized by software, hardware and combinations thereof. The above-mentioned modules can be embedded in or independent of the processor in the form of hardware, and can also be stored in the memory in the form of software, so that the processor can call and execute the corresponding operations of the above modules.

The implementation of each module in the DDR access device and the DDR-based data transmission device provided in the embodiment of the present application may be in the form of a computer program. The computer program can run on a terminal or a server. The program modules constituted by the computer program can be stored in the memory of the electronic device. When the computer program is executed by the processor, the steps of the methods described in the embodiments of the present application are realized.

The embodiment of the present application also provides a computer-readable storage medium. One or more non-transitory computer-readable storage media containing computer-executable instructions that, when executed by one or more processors, cause the processors to perform the steps of the DDR access method.

The embodiment of the present application also provides a computer-readable storage medium. One or more non-volatile computer-readable storage media containing computer-executable instructions, when the computer-executable instructions are executed by one or more processors, causing the processors to perform the steps of the data transmission method of DDR .

A computer program product comprising instructions which, when run on a computer, cause the computer to perform a DDR access method.

A computer program product containing instructions, when running on a computer, causes the computer to execute the data transmission method of DDR.

Based on the same technical concept, the embodiment of the present application also provides a DDR access system, as shown in FIG. 1 and FIG. 17 for example. The architecture includes an IC that powers the DDR, a processor (computer device) that controls the IC, and the DDR.

Among them, the processor can realize the purpose of controlling the voltage and frequency of the DDR by executing the method provided by the embodiment shown in Fig. 2-Fig. power consumption.

Optionally, as shown in FIG. 17 , other modules may also be included in the system. Wherein, other modules may also use the time slot of the PDSCH as a unit to calculate the throughput rate of the first time slot. The decoder decoder and other modules in the system vote on the throughput rate of DDR in the first time slot, vote the predicted throughput rate to the local control unit LCU of this module, and the local control unit votes the throughput rate of this module to the system Control unit SCU. The system control unit SCU makes a decision to obtain the final DDR throughput, and then maps the frequency value and/or voltage value of the DDR according to the throughput rate, and sends the control word to the PMIC (that is, the IC that supplies power to the DDR), so that in the first time slot Within, the DDR can work at the frequency and/or voltage values set by the PMIC.

If the decoder works continuously in multiple time slots and does not receive the clock gating signal, the decoder will continue to perform decoding operations, that is, there will be multiple decoding start times of transport blocks. In this case Below, there will be more time points of throughput rate change, for example, as shown in FIG. 10 , there are 12 time points of throughput rate change (indicated by solid circles in the figure). In order to avoid frequent calculation of the throughput rate, the 12 throughput rate change time points are merged, and the combined time points are reduced to 4 (indicated by the dotted circle in the figure), and only when the throughput rate becomes larger. Throughput for predictive calculations.

As an example, you can still refer to Figure 10, which shows a schematic diagram of a combination of different carrier throughput change time points. Combining the above two scenarios, if voting is performed for each change, there will be There is a time of 3*6=18us that DDR cannot be accessed, which has a great impact on system performance. Therefore, it is necessary to combine the time points of throughput changes based on the decoding start time of the transport block of each carrier, that is, adjust the DDR voltage and/or Frequency, at the starting moment of decoding of CC2 TB1, the throughput rate of CC0 TB0, CC1 TB0 and CC2 TB1 is accumulated to obtain the throughput value at the time point of dotted circle 2, and the voltage and voltage of DDR are configured based on the calculated throughput value /or frequency; at the moment of

real coil

4, 5, 6, 7, 8, CC0 TB0, CC1 TB0 and CC2 TB1 have finished decoding successively, thus the throughput rate of CC0 TB0, CC1 TB0 and CC2 TB1 is released, then the actual At the moment of

coil

4 and 5, the throughput rate of CC0 TB0 and CC1 TB0 is released, and the throughput rate of

real coil

4 and 5 decreases, so the voltage and/or frequency of DDR will not be adjusted. At the moment of

solid coils

6 and 7, although the sum of the throughput rates of CC0 TB1 and CC1 TB1 is increased, since the throughput rate of CC0 TB1 is equal to the throughput rate of CC0 TB0, the throughput rate of CC1 TB1 is equal to the throughput rate of CC1 TB0, so At the moment of the

solid coils

6, 7 the voltage and/or frequency of the DDR is not adjusted. At the moment of solid coil 8, the throughput of CC2 TB1 is released, so the voltage and/or frequency of DDR will not be adjusted either. The throughput rate at the moment of the solid coil 9 is the sum of the throughput rates of CC0 TB1, CC1 TB1 and CC2 TB2, because the throughput rate of CC0 TB1 is equal to the throughput rate of CC0 TB0, the throughput rate of CC1 TB1 is equal to the throughput rate of CC1 TB0, and The throughput rate of CC2 TB2 is greater than the throughput rate of CC2 TB1, so the throughput rate at the time of the solid coil 9 is greater than the throughput rate of the dotted coil 2, so the voltage and/or frequency of the DDR is increased at the time of the solid coil 9.

In this year's implementation, the problem of frequently adjusting the voltage and frequency of DDR for each time slot has been avoided, and the number of frequency and voltage configurations of DDR has been combined to reduce the impact of configuring DDR voltage and frequency on DDR access.

In this system, if the decoder can determine whether to perform the decoding operation by whether it receives the gating signal clock gating. If during the decoding process, the decoder receives the gating signal clock gating, it will stop the current decoding operation. If the gating signal clock gating is not received, the transmission blocks are decoded sequentially according to the transmission sequence of the normal time slot and transmission block. The decoder is controlled to stop the decoding operation through the gate control signal clock gating, which can realize timely control of the decoder in a specified scene or in an emergency.

Any reference to memory, storage, database, or other medium as used herein may include non-volatile and/or volatile memory. Nonvolatile memory can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM), which acts as external cache memory. By way of illustration and not limitation, RAM is available in many forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

The above-mentioned embodiments only express several implementation modes of the present application, and the description thereof is relatively specific and detailed, but should not be construed as limiting the patent scope of the present application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the scope of protection of the patent application should be based on the appended claims.

Claims

A DDR access method, including:

Adjust the frequency and/or voltage of the DDR in the first time slot according to the throughput rate of the double rate synchronous dynamic random access memory DDR in the first time slot, wherein the first time slot is the physical downlink shared channel PDSCH time slot;

In the first time slot, based on the frequency and/or voltage of the DDR in the first time slot, read and/or write the decoded data of the first transport block to the DDR, the first Transport blocks are transmitted via the PDSCH.
The method according to claim 1, wherein the adjusting the frequency and/or voltage of the DDR in the first time slot according to the throughput rate of the DDR in the first time slot comprises:

When the throughput rate of the DDR in the first time slot becomes larger, increase the frequency and/or voltage of the DDR in the first time slot;

When the throughput rate of the DDR in the first time slot becomes smaller, reduce the frequency and/or voltage of the DDR in the first time slot.
The method according to claim 1, wherein the method further comprises:

Determine the data access amount of the DDR in the first time slot according to the data access amount of the DDR in the second time slot, the second time slot being a previous time slot of the first time slot;

The throughput rate of the DDR in the first time slot is calculated based on the calculated data access amount of the DDR in the first time slot and the decoding time for the first transport block.
The method according to claim 3, wherein the calculated data access amount of the DDR in the first time slot and the data access amount of the DDR in the second time slot satisfy the following formula:

De=(1-a)*Dh+a*Dl

Wherein, De is the calculated data access amount of the DDR in the first time slot, Dh is the data access amount of the DDR in the previous time slot of the second time slot, and D1 is the data access amount of the DDR in the second time slot. The amount of data access in the time slot, a is greater than 0 and less than or equal to 1.
The method according to claim 3, wherein the data access amount of the DDR in the second time slot includes the data amount of the decoded data of the second transport block in the second time slot, wherein the second The transport block is a previous transport block of the first transport block, and the decoded data of the second transport block includes soft bit data or hard bit data or decrypted data of each encoded block in the second transport block.
The method according to claim 1, wherein, for each coding block in the first transmission block, writing the decoded data of the first transmission block to the DDR includes:

When an error occurs in the CRC of the coding block, writing the soft bit data corresponding to the coding block into the DDR; and/or,

When the CRC of the coded block is correct and there is a coded block with a CRC error before the coded block in the first transmission block, writing the hard bit data corresponding to the coded block into the DDR; and/or,

When the CRC of the coded block is correct and there is no coded block with a CRC error before the coded block in the first transmission block, write the decrypted data corresponding to the coded block into the DDR.
The method according to claim 1, wherein reading the decoded data of the first transport block to the DDR comprises:

In the case of retransmission decoding of the first transmission block, reading soft bit data or hard bit data of each coded block in the first transmission block from the DDR.
The method according to claim 3, wherein the PDSCH includes a plurality of carriers, each carrier is used to transmit transport blocks, and the DDR is adjusted at the first time slot according to the throughput rate of the DDR at the first time slot. Gap frequency and/or voltage, including:

When the time interval between the decoding start time of each transport block in the first time slot and the start time of the first time slot is not greater than the first threshold, according to the calculated DDR at the The throughput rate of the first time slot, configuring the frequency and/or voltage of the DDR at the start time point of the first time slot, and maintaining the frequency and/or voltage of the DDR in the first time slot.
The method according to claim 8, wherein, adjusting the frequency and/or voltage of the DDR in the first time slot according to the throughput rate of the DDR in the first time slot comprises:

When there is a third transmission block in the first time slot, according to the calculated throughput rate of the DDR in the first time slot, configure the frequency and /or voltage, wherein the interval between the start of decoding of the third transport block and the start of the first time slot is greater than a first threshold;

Increase the frequency and/or voltage of the DDR after the decoding start moment of the third transmission block according to the amount of decoded data read and/or written into the third transmission block.
The method according to claim 8, wherein the calculated throughput rate of the DDR in the first time slot comprises reading and/or writing decoding of transport blocks respectively corresponding to each carrier from the DDR The sum of data throughput rates.
The method according to claim 3, further comprising:

If the difference between the calculated throughput of the DDR in the first time slot and the actual throughput of the DDR in the first time slot is greater than the first preset threshold, then the calculated first time slot The throughput rate of three time slots is corrected, and the third time slot is the next time slot of the first time slot.
The method according to claim 10, further comprising:

When the throughput rate of the DDR is greater than the highest threshold value, adjusting the frequency and/or voltage of the DDR in the first time slot according to the highest threshold value; and/or,

When the throughput rate of the DDR is less than a minimum threshold value, adjust the frequency and/or voltage of the DDR in the first time slot according to the minimum threshold value.
The method according to any one of claims 1-11, wherein the method further comprises:

Decoding the first transport block according to a decoding cycle;

In the decoding period, the frequency and/or voltage of the DDR in the first time slot is adjusted according to the throughput rate of the double rate synchronous dynamic random access memory DDR in the first time slot.
The method of claim 13, comprising:

calculating a first throughput rate of the first time slot during decoding of the first transport block before the decoding start moment of the first transport block;

When the first throughput rate is greater than the corresponding throughput rate when the voltage and/or frequency were adjusted last time, increase the frequency and/or voltage of the DDR.
The method of claim 14, comprising:

In a case where the first throughput rate is not greater than the corresponding throughput rate when the voltage and/or frequency were adjusted last time, the frequency and/or voltage of the DDR is maintained.
The method of claim 14, comprising:

When the difference between the throughput rate corresponding to the previous voltage and/or frequency adjustment minus the first throughput rate is greater than a second preset threshold, the frequency and/or voltage of the DDR is reduced.
A DDR-based data transmission method, wherein, applicable to the DDR access method provided by any one of claims 1-16, the method includes:

Decoding a first transport block in a first time slot, where the first transport block is transmitted via the PDSCH, where the first time slot is a time slot of the PDSCH;

Reading and/or writing decoded data of the first transport block to the DDR.
The method according to claim 17, wherein, for each coded block in the first transport block, writing the decoded data of the first transport block to the DDR, the method comprises:

When an error occurs in the CRC of the coding block, writing the soft bit data corresponding to the coding block into the DDR; and/or,

When the CRC of the coded block is correct and there is a coded block with a CRC error before the coded block in the first transmission block, writing the hard bit data corresponding to the coded block into the DDR; and/or,

When the CRC of the coded block is correct and there is no coded block with a CRC error before the coded block in the first transmission block, write the decrypted data corresponding to the coded block into the DDR.
The method according to claim 17, wherein reading the decoded data of the first transmission block for the DDR comprises:

In the case of retransmission decoding of the first transmission block, reading soft bit data or hard bit data of each coded block in the first transmission block from the DDR.
The method of claim 19, comprising:

If the previous CRC of the coded block is wrong, then read the soft bit data of the coded block from the DDR;

Performing CRC on the encoded block again based on the read soft bit data;

When the CRC is correct, decode the encoded block to obtain decrypted data of the encoded block.
The method of claim 19, comprising:

If the previous CRC of the encoded block is correct, then read the hard bit data of the encoded block from the DDR;

Decrypt the hard bit data to obtain decrypted data of the coded block.
A DDR access device, wherein the device includes:

An adjustment module, configured to adjust the frequency and/or voltage of the DDR in the first time slot according to the throughput rate of the DDR in the first time slot, wherein the first time slot is a physical downlink shared channel PDSCH time slot;

An access module, configured to read and/or write decoded data of a first transmission block to the DDR based on the frequency and/or voltage of the DDR in the first time slot in the first time slot , the first transport block is transmitted via the PDSCH.
A kind of data transmission device based on DDR, wherein, said device comprises:

A decoding module, configured to decode a first transport block in a first time slot, the first transport block is transmitted via the PDSCH, and the first time slot is a time slot of the PDSCH;

An access module, configured to read and/or write decoded data of the first transmission block to the DDR.
An electronic device, comprising a memory and a processor, wherein a computer program is stored in the memory, wherein, when the computer program is executed by the processor, the processor executes any one of claims 1 to 21 The steps of the method.
A computer-readable storage medium, on which a computer program is stored, wherein, when the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 21 are realized.
An access system for double rate synchronous dynamic random access memory, including a control unit, a DDR and a power supply unit, wherein the power supply unit is used to supply power to the DDR under the control of the control unit;

The control unit is configured to execute the method according to any one of claims 1-21.