WO2023079986A1 - 送信装置、送信方法、受信装置、及び、受信方法 - Google Patents
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/19—Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
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Definitions
- the present technology relates to a transmitting device, a transmitting method, a receiving device, and a receiving method, and in particular, for example, in data transmission using an LDPC code, a transmitting device and a transmitting method that can ensure good communication quality. , a receiving device, and a receiving method.
- LDPC Low Density Parity Check
- DVB Digital Video Broadcasting-S.2 in Europe, etc. It is widely used in transmission systems such as digital broadcasting such as ATSC (Advanced Television Systems Committee) 3.0 in the United States (Non-Patent Document 1).
- the LDPC code is a symbol of quadrature modulation (digital modulation) such as QPSK (Quadrature Phase Shift Keying) (symbolized), and the symbol is a signal point of quadrature modulation. Mapped and sent.
- This technology has been developed in view of this situation, and is intended to ensure good communication quality in data transmission using LDPC codes.
- a first transmission apparatus/method of the present technology includes an encoding unit/step that performs LDPC encoding based on an LDPC code parity check matrix having a code length N of 1224 bits and a coding rate r of 144/1224.
- the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing the positions of elements of 1 in the A matrix and the C matrix for every 36 columns.
- a first receiving apparatus/method of the present technology includes an encoding step of performing LDPC encoding based on a parity check matrix of an LDPC code having a code length N of 1224 bits and a coding rate r of 144/1224,
- the B matrix of M1 rows and NK-M1 columns which is a zero matrix adjacent to the right of the B matrix, the A matrix of NK-M1 rows and K + M1 columns, and including a C matrix adjacent below the B matrix and a D matrix that is a unit matrix of NK-M1 rows and NK-M1 columns adjacent to the right of the C matrix, and the predetermined value M1 is 108;
- the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing the positions of 1 elements in the A matrix and the C matrix for every 36 columns, 7 36 107 167 173 350 489 510 577 643 716 789 960 979 1061 1076 53 75 103 336 349 396 414 480 488 490 513 559 610 622 827 1039 13 69 101 108 122 277 483 532 546 587 612 710 713 858 982 1025 10 32 72 282 420 441
- a second transmission apparatus/method of the present technology includes an encoding unit/step that performs LDPC encoding based on an LDPC code parity check matrix having a code length N of 1152 bits and a coding rate r of 144/1152.
- the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing the positions of elements of 1 in the A matrix and the C matrix for every 36 columns.
- a second receiving apparatus/method of the present technology includes an encoding step of performing LDPC encoding based on an LDPC code parity check matrix having a code length N of 1152 bits and a coding rate r of 144/1152,
- the B matrix of M1 rows and NK-M1 columns which is a zero matrix adjacent to the right of the B matrix, the A matrix of NK-M1 rows and K + M1 columns, and including a C matrix adjacent below the B matrix and a D matrix that is a unit matrix of NK-M1 rows and NK-M1 columns adjacent to the right of the C matrix, and the predetermined value M1 is 144;
- the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing the positions of 1 elements in the A matrix and the C matrix for every 36 columns, 9 70 143 150 170 202 349 475 620 732 806 1005 11 72 77 201 220 258 389 431 680 761 958 12 47 142 193 195 279 496 552 587 703 871 24 41 66 213 352 427 589 647 738 824 845 153 639 860 892 984 314 377 470 80
- LDPC coding is performed based on an LDPC code parity check matrix with a code length N of 1224 bits and a coding rate r of 144/1224.
- the A matrix and the C matrix are represented by a parity check matrix initial value table
- the parity check matrix initial value table is a table representing the positions of elements of 1 in the A matrix and the C matrix for every 36 columns, , 7 36 107 167 173 350 489 510 577 643 716 789 960 979 1061 1076 53 75 103 336 349 396 414 480 488 490 513 559 610 622 827 1039 13 69 101 108 122 277 483 532 546 587 612 710 713 858 982 1025 10 32 72 282 420 441 482 553 784 808 977 139 178 778 803 813 1055 130 576 709 732 827 991 109 125 403 905 998 10
- the LDPC code obtained from the data transmitted by the first transmission method is decoded.
- LDPC coding is performed based on the parity check matrix of the LDPC code with the code length N of 1152 bits and the coding rate r of 144/1152.
- the A matrix and the C matrix are represented by a parity check matrix initial value table
- the parity check matrix initial value table is a table representing the positions of elements of 1 in the A matrix and the C matrix for every 36 columns, , 9 70 143 150 170 202 349 475 620 732 806 1005 11 72 77 201 220 258 389 431 680 761 958 12 47 142 193 195 279 496 552 587 703 871 24 41 66 213 352 427 589 647 738 824 845 153 639 860 892 984 314 377 470 803 994 147 342 721 732 766 206 415 670 749 778 It has become.
- the LDPC code obtained from the data transmitted by the second transmission method is decoded.
- the transmitting device and the receiving device may be independent devices, or may be internal blocks constituting one device. Also, the transmitting device and the receiving device can be composed of one or a plurality of semiconductor chips.
- a part or all of the transmitting device and receiving device can be functionally realized by causing a computer to execute a program.
- the program can be provided by being transmitted via a transmission medium or recorded on a recording medium.
- FIG. 1 is a diagram illustrating a configuration example of an embodiment of a transmission system to which the present technology is applied;
- FIG. 2 is a block diagram showing a configuration example of a transmission device 11;
- FIG. 3 is a diagram showing a configuration example of an OFDM signal generated by an OFDM signal generator 23;
- FIG. It is a figure which shows the example of a parity check matrix.
- FIG. 4 is a diagram showing an example of a parity matrix;
- FIG. 2 is a diagram illustrating a parity check matrix of an LDPC code stipulated in the DVB-T.2 standard;
- 5 is a flowchart for explaining an example of processing of the transmitting device 11;
- 4 is a flowchart for explaining an example of processing of an encoding unit 21;
- FIG. 10 is a diagram illustrating a method of obtaining a parity check matrix H from a parity check matrix initial value table; It is a figure which shows the structure of a parity check matrix. It is a figure which shows the example of a parity check matrix initial value table.
- FIG. 10 is a diagram illustrating an A matrix generated from a parity check matrix initial value table;
- FIG. 10 is a diagram illustrating parity interleaving of a B matrix;
- FIG. 4 is a diagram illustrating a C matrix generated from a check matrix initial value table;
- FIG. 4 is a diagram explaining parity interleaving of a D matrix;
- FIG. 10 is a diagram illustrating a method of obtaining a parity check matrix H from a parity check matrix initial value table; It is a figure which shows the structure of a parity check matrix. It is a figure which shows the example of a parity check matrix initial value table.
- FIG. 10 is a diagram illustrating an A matrix generated from
- FIG. 10 is a diagram showing a parity check matrix subjected to column permutation as parity de-interleaving for restoring parity interleaving.
- FIG. 4 is a diagram showing a transformed check matrix obtained by performing row permutation on a check matrix
- FIG. 10 is a diagram showing a first example of a parity check matrix initial value table for a new LDPC code
- FIG. 10 is a diagram showing a second example of a parity check matrix initial value table for the new LDPC code
- FIG. 10 is an example of a Tanner graph for an ensemble of degree sequences with a column weight of 3 and a row weight of 6
- FIG. 10 is a diagram showing an example of a Tanner graph of a multi-edge type ensemble
- FIG. 4 is a diagram explaining a parity check matrix of the type A scheme;
- FIG. 4 is a diagram showing parameters of a type A code;
- FIG. 4 is a diagram for explaining a simulation method for evaluating the performance of a new LDPC code;
- 2 is a block diagram showing a configuration example of a receiving device 12;
- FIG. 4 is a flowchart illustrating an example of processing of the receiving device 12;
- FIG. 4 is a diagram showing an example of a parity check matrix of an LDPC code
- FIG. 10 is a diagram showing an example of a matrix (transformed parity check matrix) obtained by subjecting a parity check matrix to row permutation and column permutation; It is a figure which shows the example of the conversion check matrix divided
- FIG. 4 is a block diagram showing a configuration example of a decoding device that performs P node operations collectively; 3 is a block diagram showing a configuration example of a decoding unit 64;
- FIG. 1 is a block diagram showing a configuration example of an embodiment of a computer to which the present technology is applied;
- FIG. 1 shows an example of a transmission system to which this technology is applied (a system refers to a logical assembly of a plurality of devices, regardless of whether or not the devices of each configuration are in the same housing). It is a figure which shows the structural example of embodiment.
- the transmission system is composed of a transmitting device 11 and a receiving device 12.
- the transmission device 11 transmits (broadcasts) (transmits) television broadcast programs, for example. That is, the transmitting device 11 encodes target data to be transmitted, such as image data and audio data as a program, into an LDPC code, for example, a satellite line, a terrestrial wave, a cable (wired line), etc. It transmits via the communication channel 13 .
- target data to be transmitted such as image data and audio data as a program
- an LDPC code for example, a satellite line, a terrestrial wave, a cable (wired line), etc. It transmits via the communication channel 13 .
- the receiving device 12 receives the LDPC code transmitted from the transmitting device 11 via the communication path 13, decodes it into target data, and outputs it.
- the transmission system of Fig. 1 information is transmitted according to the advanced terrestrial broadcasting system, unless otherwise specified.
- the transmission method to which the present technology is applied is not limited to the advanced terrestrial broadcasting method.
- FIG. 2 is a block diagram showing a configuration example of the transmission device 11 of FIG.
- the transmitting device 11 has an encoding unit 21, a DBPSK (differential binary phase shift keying) modulation unit 22, and an OFDM signal generation unit 23.
- DBPSK differential binary phase shift keying
- the encoding unit 21 is supplied with LL data, which is data transmitted on a low-delay transmission channel (hereinafter also referred to as LLch) for low-delay transmission.
- LL data is data transmitted on a low-delay transmission channel (hereinafter also referred to as LLch) for low-delay transmission.
- the L0 data transmitted on the channel (L0ch) within the partial reception band is more rapid than the L1 data transmitted on the channel (L1ch) of the band other than the partial reception band. Therefore, the L0 data is particularly useful for transmitting highly urgent information such as the fact that a disaster has occurred and the type of disaster, for example, when a disaster occurs.
- the encoding unit 21 has an L0 encoding unit 31 and an L1 encoding unit 32.
- the L0 data is supplied to the L0 encoding unit 31, and the L1 data is supplied to the L1 encoding unit 32.
- the L0 encoding unit 31 treats the L0 data supplied thereto as LDPC target data that is the target of LDPC encoding, and regarding the LDPC target data, for example, the parity matrix ( LDPC encoding according to a predetermined parity check matrix such as a parity check matrix having a dual diagonal structure, and outputs an LDPC code having LDPC target data as information bits.
- LDPC target data that is the target of LDPC encoding
- the parity matrix LDPC encoding according to a predetermined parity check matrix such as a parity check matrix having a dual diagonal structure
- the L1 encoding unit 32 uses the L1 data supplied thereto as LDPC target data that is the target of LDPC encoding, and the LDPC target data according to a predetermined check matrix LDPC encoding is performed, and an LDPC code having LDPC target data as information bits is output.
- the parity check matrix used for LDPC encoding in the L0 encoding unit 31 and the L1 encoding unit 32 may be different or may be the same.
- LDPC code obtained as a result of LDPC encoding in the L0 encoding unit 31 and the L1 encoding unit 32 for example, similar to the LDPC code specified in standards such as DVB-S.2 and ATSC3.0, IRA (irregular repeat accumulate) code can be adopted.
- the LDPC codes output by the L0 encoding unit 31 and the L1 encoding unit 32 are supplied to the DBPSK modulation unit 22.
- the DBPSK modulation unit 22 performs DBPSK modulation (mapping corresponding to) of each of the LDPC codes from the L0 encoding unit 31 and the L1 encoding unit 32, and the resulting L0 data and L1 data LDPC code carrier (IQ signal points on the constellation).
- L0 carriers and L1 carriers are hereinafter also referred to as L0 carriers and L1 carriers, respectively.
- the L0 carrier and L1 carrier output by the DBPSK modulation unit 22 are supplied to the OFDM signal generation unit 23.
- the OFDM signal generation unit 23 is supplied with the L0 carrier and the L1 carrier from the DBPSK modulation unit 22, as well as the TMCC carrier of TMCC (transmission and multiplexing configuration control) information, the pilot carrier of the pilot signal, the A layer to the C layer.
- TMCC transmission and multiplexing configuration control
- a main data carrier of each hierarchical data (main data), etc., is supplied from a circuit (not shown).
- the OFDM signal generation unit 23 configures an OFDM frame including L0 carriers and L1 carriers, TMCC carriers, pilot carriers, main data carriers, etc., IFFT (inverse fast Fourier transform), and GI (guard interval) is added to generate an OFDM signal.
- IFFT inverse fast Fourier transform
- GI guard interval
- the transmitting device 11 transmits the OFDM signal generated by the OFDM signal generating section 23 .
- FIG. 3 is a diagram showing a configuration example of an OFDM signal generated by the OFDM signal generating section 23.
- FIG. 3 is a diagram showing a configuration example of an OFDM signal generated by the OFDM signal generating section 23.
- An OFDM signal is composed of units called OFDM symbols arranged in the time direction.
- An OFDM symbol is a unit of IFFT, and is composed of a plurality of, for example, 35 OFDM segments arranged in the frequency direction.
- FIG. 3 shows a configuration example of OFDM symbols that constitute an OFDM signal.
- the frequency band assigned to one channel for transmitting OFDM signals is divided into 36 segments, and out of the 36 segments (frequency bands) after division, 35 segments are used for OFDM symbols. 35 OFDM segments are transmitted respectively.
- the central 9 OFDM segments are partially receivable OFDM segments, i.e., OFDM segments in which information can be restored simply by receiving the 9 OFDM segments.
- a segment (band) in which the central nine OFDM segments that can be partially received are transmitted is a partial reception band.
- OFDM segments in the range of 1 to 9 out of the central 9 OFDM segments that can be partially receivable can be set in layer A and used for mobile reception.
- 8 L0 carriers can be allocated to each partially receivable OFDM segment.
- all different L0 carriers can be adopted, or the same L0 carrier can be adopted in multiple units.
- 72 bits can be transmitted with one OFDM symbol.
- L0 carriers for example, when the same L0 carrier is adopted in units of two, only 36 bits can be transmitted in one OFDM symbol, but error resilience can be improved. can.
- FIG. 4 is a diagram showing an example of parity check matrix H used for LDPC encoding in the encoding unit 21 of FIG.
- the parity check matrix H has an LDGM (low-density generation matrix) structure, and includes an information matrix H A of a portion corresponding to the information bits of the code bits of the LDPC code, and a parity matrix H T corresponding to the parity bits.
- H [H A
- the parity check matrix H is a matrix with M ⁇ N rows and columns (a matrix with M rows and N columns).
- the information matrix H A is an M ⁇ K matrix
- the parity matrix H T is an M ⁇ M matrix.
- FIG. 5 is a diagram showing an example of parity matrix H T of parity check matrix H used for LDPC encoding in encoding section 21 of FIG.
- parity matrix H T of the parity check matrix H used for LDPC encoding in the encoding unit 21 for example, parity matrix H T similar to the parity matrix H of the LDPC code specified in standards such as DVB-T.2 can be adopted.
- the parity matrix H T of the parity check matrix H of the LDPC code specified in standards such as DVB-T.2 is a matrix with a staircase structure (lower bidiagonal matrix) in which elements of 1 are arranged in a stepped manner, as shown in FIG. matrix).
- the row weight of the parity matrix H T is 1 for the first row and 2 for all remaining rows.
- the column weight is 1 for the last column and 2 for all remaining columns.
- an LDPC code for a parity check matrix H whose parity matrix H T has a staircase structure can be easily generated using the parity check matrix H.
- an LDPC code (one codeword) is represented by a row vector c, and a column vector obtained by transposing the row vector is represented by cT . Also, in the row vector c of the LDPC code, the information bit portion is represented by row vector A, and the parity bit portion is represented by row vector T.
- row vector c [A
- the check matrix H and the row vector c [A
- FIG. 6 is a diagram explaining the parity check matrix H of the LDPC code specified in standards such as DVB-T.2.
- the column weight is X
- the column weight is 3, and then has a column weight of 2 for the M-1 columns of , and a column weight of 1 for the last column.
- KX+K3+M-1+1 is equal to code length N.
- FIG. 7 is a flowchart explaining an example of processing of the transmission device 11 of FIG.
- the encoding unit 21 is supplied with the L0 data and the L1 data that make up the LL data.
- step S101 in the encoding unit 21, the L0 encoding unit 31 performs LDPC encoding on the L0 data as LDPC target data according to a predetermined parity check matrix.
- the L0 encoding unit 31 supplies the LDPC code of the L0 data obtained as a result of the LDPC encoding to the DBPSK modulation unit 22 .
- step S101 in the encoding unit 21, the L1 encoding unit 32 uses the L1 data as LDPC target data, and performs LDPC encoding on the LDPC target data according to a predetermined parity check matrix.
- the L1 encoder 32 supplies the LDPC code of the L1 data obtained as a result of the LDPC encoding to the DBPSK modulator 22 .
- step S101 the process proceeds from step S101 to step S102, and the DBPSK modulation unit 22 performs DBPSK modulation of the LDPC codes of the L0 data and L1 data from the L0 encoding unit 31 and the L1 encoding unit 32, respectively.
- the DBPSK modulation unit 22 supplies the L0 carrier and L1 carrier obtained by DBPSK modulation to the OFDM signal generation unit 23, and the process proceeds from step S102 to step S103.
- step S103 the OFDM signal generation unit 23 generates an OFDM signal including the L0 carrier and L1 carrier from the DBPSK modulation unit 22, and the TMCC carrier, pilot carrier, and main data carrier supplied from a circuit (not shown). Generate and send.
- FIG. 8 is a flowchart illustrating an example of processing of the encoding unit 21 in FIG.
- FIG. 8 shows an example of LDPC encoding processing performed in step S101 of FIG.
- step S111 the L0 encoding unit 31 and the L1 encoding unit 32 generate parity check matrix H using a parity check matrix initial value table described later, and the process proceeds to step S112.
- step S113 the L0 encoding unit 31 and the L1 encoding unit 32 use the information bits of the information length K and the parity check matrix H to sequentially calculate the parity bits of the codeword c that satisfies Equation (1).
- Equation (1) c represents a row vector as a codeword (LDPC code), and c T represents transposition of row vector c.
- the information bit portion is represented by the row vector A
- the parity bit portion is represented by the row vector T.
- c [A
- the check matrix H and the row vector c [A
- L0 encoding unit 31 and L1 encoding unit 32 from the LDPC target data, in time series, to obtain a bit of information length K as an information bit, to calculate the parity bit of the information bit, from the LDPC target data , until there are no more bits to acquire as information bits.
- parity check matrix initial value tables (representing parity check matrices) for LDPC codes with various code lengths N and encoding rates r can be prepared in advance.
- the L0 encoding unit 31 and the L1 encoding unit 32 generate a parity check matrix H from a parity check matrix initial value table according to an external designation such as an operator among the parity check matrix initial value tables prepared in advance, and perform a check.
- LDPC encoding can be performed using the matrix H.
- the L0 encoding unit 31 and the L1 encoding unit 32 can perform parity interleaving in which the parity bits of the LDPC code obtained by LDPC encoding are interleaved at the positions of other parity bits.
- Information matrix H A of parity check matrix H corresponding to LDPC code obtained by L0 encoding unit 31 and L1 encoding unit 32 performing LDPC encoding is LDPC specified in standards such as DVB-T.2 Similar to the information matrix of the parity check matrix H corresponding to the code, it has a cyclic structure.
- a cyclic structure is a structure in which a column corresponds to a cyclic shift of another column, for example, for every P columns, the position of 1 in each row of that P column is the first of that P column. columns are cyclically shifted in the column direction by a predetermined value, such as a value proportional to the value q obtained by dividing the parity length M.
- a predetermined value such as a value proportional to the value q obtained by dividing the parity length M.
- the parallel factor P is defined as 360, which is one of the divisors of the parity length M, excluding 1 and M. .
- x be an integer greater than or equal to 0 and less than P
- y be an integer greater than or equal to 0 and less than q. is interleaved at the K+Py+x+1th sign bit position.
- Both the K+qx+y+1th code bit and the K+Py+x+1th code bit are the code bits after the K+1th code bit, so they are parity bits. Interleaving moves the position of the parity bit of the LDPC code.
- the decoding of the LDPC code is performed using an algorithm proposed by Gallager called Probabilistic Decoding, that is, a variable node (also called a message node) and a check node. It can be done by the Sum Product Algorithm, which is a message passing algorithm by belief propagation on a so-called Tanner graph consisting of:
- the variable node and the check node will be simply referred to as nodes as appropriate.
- the reception LLR log likelihood ratio
- the real value expressing the "0" likelihood of the value of each bit as a logarithmic likelihood ratio is used as the initial value.
- a variable node operation as a predetermined operation is performed at the variable node.
- variable node outputs the result of the variable node operation as a message v.
- the check node uses the message v output by the variable node to perform a check node operation as a predetermined operation, and outputs the result of the check node operation as a message u.
- variable node uses the message u output by the check node to perform the variable node operation, and outputs the result of the variable node operation as the message u.
- variable node and a check node are connected by an edge according to the parity check matrix.
- a variable node corresponds to each column of the check matrix, and a check node corresponds to each row of the check matrix.
- a branch connects a variable node corresponding to a column of an element with 1 and a check node corresponding to a row of that element.
- Messages v and u are passed between the branched variable node and the check node.
- variable node operation and check node operation After the set of variable node operation and check node operation is repeated for a predetermined number of decoding iterations, at the variable node, using the message u last output from the check node, a predetermined An operation is performed to obtain the decoding result of the LDPC code.
- variable nodes the parity bits corresponding to them connected to the same check node are separated by the parallel factor P. Therefore, if the burst length is less than the parallel factor P, it is possible to avoid a situation in which multiple variable nodes connected to the same check node become erroneous at the same time, thereby improving robustness against burst errors. .
- the LDPC code after parity interleaving which interleaves the K+qx+y+1st code bit at the position of the K+Py+x+1th code bit, is K+qx+
- Matches the LDPC code of a parity check matrix obtained by performing column permutation in which the y+1-th column is replaced with the K+Py+x+1-th column hereinafter also referred to as a transformed parity check matrix).
- the pseudo-cyclic structure means a structure in which the part other than a part has a cyclic structure.
- the transform parity check matrix obtained by applying column permutation corresponding to parity interleaving to the parity check matrix of the LDPC code specified in standards such as DVB-T.2 is the P rows in the upper right corner of the transform parity check matrix ⁇
- the column P 360 rows x 360 columns (shift matrix described later)
- the transform parity check matrix is similar to the transform parity check matrix for the parity check matrix of the LDPC code specified in standards such as DVB-T.2.
- a matrix with a pseudo-cyclic structure can be adopted.
- transformation parity check matrix is applied to the original parity check matrix H, in addition to column permutation corresponding to parity interleaving, row permutation (row permutation ) is also a procession.
- FIG. 9 is a diagram explaining a method for obtaining a parity check matrix H from a parity check matrix initial value table for the type B method.
- the parity check matrix initial value table is, for example, information matrix H corresponding to information length K corresponding to code length N and coding rate r of LDPC code (LDPC code defined by parity check matrix H) of parity check matrix H A table representing the position of 1 element in A (FIG. 4) for each P column, which is a parallel factor, and is created in advance for each parity check matrix H.
- the parity check matrix initial value table represents at least the position of 1 element of the information matrix H A for each P columns.
- the check matrix H includes a check matrix in which the entire parity matrix H T has a staircase structure, a part of the parity matrix H T has a staircase structure, and the other part is a diagonal matrix (unit matrix).
- the expression method of the parity check matrix initial value table representing the parity check matrix in which part of the parity matrix H T has a staircase structure and the other part is a diagonal matrix is also referred to as a type A method.
- the expression method of the parity check matrix initial value table representing the parity check matrix in which the entire parity matrix H T has a staircase structure is also called the type B method.
- An LDPC code for a parity check matrix represented by a parity check matrix initial value table for the type A method is also called a type A code
- an LDPC code for a parity check matrix represented by a parity check matrix initial value table for the type B method is also called a type B code.
- Type A and Type B designations conform to the ATSC 3.0 standard.
- ATSC 3.0 employs both type A and type B codes.
- DVB-T.2 and others use type B codes.
- Fig. 9 shows a parity check matrix initial value table for a type B code with a code length N of 16200 bits and a coding rate r of 2/3, which is specified in the DVB-T.2 standard.
- check matrix H is obtained as follows.
- the parity check matrix initial value table of the type B method represents the position of the entire 1 element of the information matrix H A corresponding to the information length K according to the code length N and coding rate r of the LDPC code for each P column. It's a table.
- the parallel factor P of the type B code specified in the DVB-T.2 standard is 360, and the i-th row of the parity check matrix initial value table contains 1+360 ⁇ (i-1) of the parity check matrix H.
- the row number of the 1 element in the column (the row number where the row number of the first row of the check matrix H is 0) is equal to the number of column weights of the 1 + 360 ⁇ (i-1)th column Lined up.
- the parity matrix H T (FIG. 4) corresponding to the parity length M of the parity check matrix H of the type B method is determined to have a staircase structure as shown in FIG. If the information matrix H A (FIG. 4) corresponding to the information length K can be obtained, the parity check matrix H can be obtained.
- the number of rows k+1 in the check matrix initial value table of the type B method differs depending on the information length K.
- the parallel factor P in equation (2) is 360 as described above for the type B code specified in the DVB-T.2 standard.
- the column weights of the parity check matrix H obtained from the parity check matrix initial value table of FIG. From the (3-1)th column to the Kth column are 3.
- the first row of the parity check matrix initial value table in FIG. In the first column of the row numbers 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622 row elements are 1 (and other elements is 0).
- the parity check matrix initial value table represents the position of the 1 element of the information matrix H A of the parity check matrix H for every 360 columns.
- H i,j be the number in the i-th row (i-th from the top) and j-th column ( j -th from the left) of the parity check matrix initial value table.
- H wj be the row number of the 1st element in the parity check matrix H. wj can be calculated by equation (3).
- Hwj mod( hi,j + mod((w-1),P) x q, M) ...
- mod (x, y) means the remainder when x is divided by y.
- the row number of the 1 element in the 1+360 ⁇ (i ⁇ 1)th column of the parity check matrix H is specified by the parity check matrix initial value table.
- the row number H wj of the 1 element in the w-th column which is a column other than the 1+360 ⁇ (i ⁇ 1)-th column of the parity check matrix H, is identified according to Equation (3).
- a parity check matrix H is generated in which the element of the row number specified as described above is set to 1.
- FIG. 10 is a diagram showing the structure of the parity check matrix H of the type A method.
- the check matrix of the type A method consists of A matrix, B matrix, C matrix, D matrix, and Z matrix.
- the B matrix is an M1-by-M1 matrix with a staircase structure adjacent to the right of the A matrix.
- the C matrix is a matrix that is adjacent below the A and B matrices, with N-K-M1 rows and K+M1 columns.
- the D matrix is the identity matrix adjacent to the right of the C matrix, with N-K-M1 rows and N-K-M1 columns.
- the Z matrix is a zero matrix (zero matrix) adjacent to the right of the B matrix, with M1 rows and N-K-M1 columns.
- the C matrix is a matrix with M2 rows and K+M1 columns
- the D matrix is an identity matrix with M2 rows and M2 columns
- the Z matrix is a zero matrix with M1 rows and M2 columns, respectively.
- the B matrix is a matrix with a staircase structure
- the D matrix is a unit matrix, so part of the parity matrix of the parity matrix H of the type A method (part of the B matrix) has a staircase structure. , and the other part (part of the D matrix) is a diagonal matrix (identity matrix).
- the A matrix and C matrix have a cyclic structure for each P column, which is a parallel factor, in the same way as the information matrix of the parity check matrix H of the type B method. Represents the position of the 1 element in the C matrix for each P column.
- the parallel factor for type A codes specified in the ATSC 3.0 standard is 360.
- the parity check matrix initial value table of the type A method represents the positions of 1 elements in the A matrix and C matrix of the parity check matrix for each P columns, the position of some 1 elements in the parity check matrix is It can be said that it represents each
- the type A system parity check matrix initial value table representing the position of the element of 1 in the A matrix and the C matrix for each P column is at least , represents the position of the 1 element of the information matrix for each P columns.
- FIG. 11 is a diagram showing an example of a check matrix initial value table for the type A method.
- FIG. 11 shows an example of a parity check matrix initial value table representing a parity check matrix H with a code length N of 35 bits and a coding rate r of 2/7.
- the parity check matrix initial value table of the type A method is a table that represents the position of the element of 1 in the A matrix and the C matrix for each parallel factor P, and the ith row contains 1+P ⁇ ( The row number of the 1 element in the i-1)th column (row number where the row number of the first row of the parity check matrix H is 0) is the column that the 1+P ⁇ (i-1)th column has They are lined up by the number of weights.
- parity check matrix H of the type A method there are M1, M2, Q1, and Q2 as parameters other than the parallel factor P, etc.
- M1 (Fig. 10) is a parameter that determines the size of the B matrix, and takes a value that is a multiple of the parallel factor P.
- M1 the performance of the LDPC code changes and is adjusted to a predetermined value when parity check matrix H is determined.
- 15, which is three times the parallel factor P 5, is adopted as M1.
- M2 (Fig. 10) is the value M-M1 obtained by subtracting M1 from the parity length M.
- the parity check matrix initial value table of FIG. 11 three numerical values are arranged in the first and second rows, and one numerical value is arranged in the third to fifth rows.
- the first row of the parity check matrix initial value table in FIG. 1 (and other elements are 0).
- the A matrix (FIG. 10) is a matrix of 15 rows and 10 columns (M1 rows and K columns)
- the C matrix (FIG. 10) is a matrix of 10 rows and 25 columns (N-K-M1 rows and K+M1 columns)
- the rows with row numbers 0 to 14 of the parity check matrix H are the rows of the A matrix
- the rows with row numbers 15 to 24 of the parity check matrix H are the rows of the C matrix.
- rows #2, #6, and #18 are rows of the A matrix
- row #18 is the row of the C matrix.
- the second row of the parity check matrix initial value table in FIG. It shows that the elements of 2, #10, and #19 are 1.
- rows #2 and #10 among rows #2, #10, and #19 are rows of the A matrix
- row #19 is a row of the C matrix.
- row #22 is the row of the C matrix.
- FIG. 12 is a diagram showing the A matrix generated from the parity check matrix initial value table of FIG.
- FIG. 13 is a diagram showing parity interleaving of the B matrix.
- FIG. 13 shows the A matrix and B matrix after parity interleaving of the B matrix in FIG.
- FIG. 14 is a diagram showing a C matrix generated from the parity check matrix initial value table of FIG.
- the element in row #15 of the ⁇ (5-1)) column is 1.
- a C matrix is generated using the check matrix initial value table, and the C matrix is placed under the A matrix and the B matrix (after parity interleaving). placed in
- the Z matrix is arranged to the right of the B matrix
- the D matrix is arranged to the right of the C matrix to generate the parity check matrix shown in FIG.
- FIG. 15 is a diagram showing parity interleaving of the D matrix.
- FIG. 15 shows a parity check matrix H obtained by parity interleaving the D matrix for the check matrix of FIG.
- the LDPC code generated using the parity check matrix H in FIG. 15 is an LDPC code with parity interleaving. Therefore, for the LDPC code generated using the parity check matrix H of FIG. 15, there is no need to perform parity interleaving separately after generating the LDPC code.
- FIG. 16 restores parity interleaving to the B matrix, part of the C matrix (the part of the C matrix located below the B matrix), and the D matrix of the parity check matrix H in FIG.
- FIG. 10 is a diagram showing a parity check matrix that has been subjected to column permutation as parity deinterleaving;
- LDPC encoding can be performed using the parity check matrix of FIG. 16 instead of the parity check matrix H of FIG.
- FIG. 17 is a diagram showing a transformed parity check matrix obtained by performing row permutation on the parity check matrix H of FIG.
- the transformation check matrix is a P ⁇ P identity matrix, a quasi-identity matrix in which one or more of 1 of the identity matrix is 0, a shift matrix obtained by cyclically shifting the identity matrix or the quasi-identity matrix, It is a matrix represented by a combination of a sum matrix that is the sum of two or more of the unit matrix, quasi-unit matrix, or shift matrix, and a P ⁇ P zero matrix.
- FIG. 18 is a diagram showing a first example of a parity check matrix initial value table representing the parity check matrix of the new LDPC code.
- FIG. 19 is a diagram showing a second example of the parity check matrix initial value table representing the parity check matrix of the new LDPC code.
- one method of ensuring good communication quality is to use LDPC codes with good performance.
- a new LDPC code with good performance (hereinafter also referred to as a new LDPC code) will be described below.
- parity check matrix initial value tables of FIGS. 18 and 19 are type A code parity check matrix initial value tables (type A system parity check matrix initial value tables).
- the LDPC code of L0 data is DBPSK modulated and becomes the L0 carrier. Therefore, one L0 carrier transmits a 1-bit LDPC code.
- 8 L0 carriers are arranged in each of the central 9 OFDM segments that can be partially receivable. 8) L0 carriers are deployed.
- LDPC codes For LDPC codes, if the code length is 1000 bits or more, the performance is improved over turbo codes, and the longer the code length, the better the performance. On the other hand, if the code length is long, the time required to decode the LDPC code increases as the code length increases.
- the code length N of the new LDPC code as the LDPC code of the L0 data is a multiple of 72 and is a value of 1000 bits. For example, 1224 bits or 1152 bits are adopted.
- the LDPC code with a code length N of 1224 bits has better performance than the LDPC code with a code length N of 1152 bits.
- an LDPC code with a code length N of 1152 bits can be transmitted with a lower delay than an LDPC code with a code length N of 1224 bits.
- the LDPC code is adopted as the new LDPC code.
- the information length K with which the coding rate r is about 0.1 For example, 144 bits are adopted.
- FIG. 18 shows an LDPC code with a code length N of 1224 bits and an information length K of 144 bits, therefore, an example of a parity check matrix initial value table representing a parity check matrix of a new LDPC code with a coding rate r of 144/1224. ing.
- FIG. 19 shows an LDPC code with a code length N of 1152 bits and an information length K of 144 bits, therefore, an example of a parity check matrix initial value table representing a parity check matrix of a new LDPC code with a coding rate r of 144/1152. ing.
- the new LDPC code corresponding to the parity check matrix initial value table in FIGS. 18 and 19 can be applied to arbitrary LDPC coding in addition to LDPC coding of L0 data transmitted in the partial reception band.
- the new LDPC code has a short code length N of 1224 or 1152 bits, so it is particularly useful for low-delay information transmission.
- the parallel factor P of the new LDPC code is 36.
- the parallel factor P of the new LDPC code is 36, which is large for the code length N, and the check node for decoding the LDPC code of the parity check matrix represented by the P ⁇ P constituent matrix described later
- an LDPC code with good performance is an LDPC code obtained from an appropriate parity check matrix H.
- An appropriate parity check matrix H is, for example, an LDPC code obtained from the parity check matrix H with a low E s /N 0 (signal power to noise power ratio per symbol) or E b /N 0 (per bit BER (bit error rate) (and FER (frame error rate)) is a parity check matrix that satisfies a predetermined condition when transmitted with a signal power to noise power ratio).
- An appropriate parity check matrix H can be obtained, for example, by performing a simulation of measuring BER when LDPC codes obtained from various parity check matrices satisfying predetermined conditions are transmitted at low E s /N o .
- Predetermined conditions that an appropriate parity check matrix H should satisfy are, for example, that the analysis result obtained by a code performance analysis method called Density Evolution is good, and that the number of elements of 1 called cycle 4 There is no loop, and so on.
- the decoding performance of the LDPC code is degraded when the information matrix H A is densely populated with 1 elements like cycle 4. Therefore, the parity check matrix H includes cycles 4 should be absent.
- the minimum loop length (loop length) composed of 1 elements is called girth. Absence of cycle 4 means that girth is greater than 4.
- the predetermined condition that an appropriate parity check matrix H should satisfy can be appropriately determined from the viewpoint of improving the decoding performance of the LDPC code, facilitating (simplifying) the decoding process of the LDPC code, and the like.
- Figs. 20 and 21 are diagrams for explaining density evolution for obtaining analysis results as predetermined conditions that an appropriate parity check matrix H should satisfy.
- Density evolution is a code analysis method that calculates the expected value of the error probability for the entire LDPC code (ensemble) with a code length N of ⁇ characterized by the degree sequence described later. is.
- AWGN additive white Gaussian noise
- the performance of the ensemble is evaluated by comparing the threshold value of the noise variance value (hereinafter also referred to as the performance threshold) at which the expected value of the error probability is not 0. can decide.
- an LDPC code with good performance can be found among the LDPC codes belonging to that ensemble.
- the above-mentioned degree sequence represents the ratio of variable nodes and check nodes with weights of each value to the code length N of the LDPC code.
- a regular(3,6) LDPC code with a rate of 1/2 has a degree of 3 in which all variable nodes have a weight (column weight) and all check nodes have a weight (row weight) of 6. Belongs to an ensemble characterized by a sequence.
- Fig. 20 shows the Tanner graph of such an ensemble.
- Each variable node is connected to 3 edges equal to the column weight, so there are a total of 3N edges connecting to N variable nodes.
- each check node is connected to 6 branches equal to the row weight, so there are a total of 3N branches connecting to N/2 check nodes.
- the interleaver randomly permutes the 3N branches connected to N variable nodes, and converts each permuted branch to one of the 3N branches connected to N/2 check nodes. Connect to one of us.
- a multi-edge type ensemble can be used in density evolution.
- the interleaver through which the branches connected to the variable nodes and the branches connected to the check nodes go through is divided into multiple (multi edges), which makes the ensemble characterization more strictly done.
- FIG. 21 shows an example of a Tanner graph of a multi-edge type ensemble.
- Density Evolution and its implementation see, for example, “On the Design of Low-Density Parity-Check Codes within 0.0045 dB of the Shannon Limit", S.Y. Leggers, VOL.5, NO.2, Feb 2001.
- an LDPC code that reduces the BER when using one or more orthogonal modulations such as DBPSK can be selected as an LDPC code with good performance from among the LDPC codes belonging to the ensemble.
- the parity check matrix initial value table representing the parity check matrix As the new LDPC code (the parity check matrix initial value table representing the parity check matrix), it is possible to adopt an LDPC code with good performance obtained by the above simulation.
- FIG. 22 is a diagram explaining the column weights of the parity check matrix H of the type A code as the new LDPC code.
- the column weight of the subsequent K3 column of the A and C matrices as X3 the column weight of the subsequent M1 column of the C matrix as XM1, respectively.
- K1+K2+K3 is equal to the information length K.
- the column weight of the B matrix from the 1st column to the M1-1 column is 2, and the column weight of the M1th column (the last column) of the B matrix is 1. Furthermore, the column weight of the D matrix is 1 and the column weight of the Z matrix is 0.
- FIG. 23 is a diagram showing the parameters of (the parity check matrix of) the type A code as the new LDPC code (represented by the parity check matrix initial value table) in FIGS.
- FIG. 24 is a diagram explaining a simulation method for evaluating the performance of the new LDPC code.
- the information bit (info) as L0 data is LDPC encoded (LDPC enc) into the new LDPC code, each bit of the new LDPC code is differentially encoded, and then output by differential encoding.
- the L0 carrier is generated by performing DBPSK modulation by mapping the output bits to BPSK signal points on the IQ constellation (BPSK map).
- Differential encoding is the process of EXORing the bits of the new LDPC code and the output bits output immediately before by differential encoding, and using them as the current output bits.
- the initial value of the output bit is 0, for example.
- the L0 carrier was further differentially demodulated after passing through an AWGN channel, and the LDPC code obtained by the differential demodulation was LDPC-decoded (LDPC dec) to obtain information bits as L0 data. is restored.
- LDPC dec LDPC-decoded
- the FER which is an index for evaluating the performance of the new LDPC code, is calculated by comparing the restored information bits as L0 data with the original information bits.
- the horizontal axis represents CNR and the vertical axis represents FER.
- the parity check matrix is obtained from the parity check matrix initial value table, and LDPC encoding is performed using the parity check matrix.
- the parity check matrix initial value table is Since it is information equivalent to a parity check matrix, LDPC coding (calculation of parity bits of an LDPC code) can be performed by a predetermined operation using a parity check matrix initial value table without obtaining a parity check matrix.
- FIG. 27 is a block diagram showing a configuration example of the receiving device 12 of FIG.
- the receiving device 12 has an OFDM demodulator 61, an LL extractor 62, a differential demodulator 63, and a decoder 64.
- the OFDM demodulator 61 receives the OFDM signal from the transmitter 11 .
- the OFDM demodulator 61 demodulates the OFDM signal by AD (analog to digital) conversion, orthogonal demodulation, FFT, etc., and outputs the resulting demodulated signal.
- AD analog to digital
- the demodulated signal output by the OFDM demodulator 61 is supplied to the LL extractor 62 and to a circuit (not shown).
- a circuit (not shown) processes carriers other than the L0 carrier and L1 carrier included in the demodulated signal, such as TMCC carriers, pilot carriers, main data carriers, and the like.
- the LL extractor 62 extracts the L0 carrier and the L1 carrier from the demodulated signal from the OFDM demodulator 61 and supplies them to the differential demodulator 63 .
- the differential demodulator 63 performs differential demodulation of each of the L0 carrier and L1 carrier from the LL extractor 62, and calculates the likelihood (received LLR) is supplied to the decoding unit 64 .
- the decoding unit 64 performs LDPC decoding of the likelihood of each bit of the LDPC code of each of the L0 data and L1 data from the differential demodulation unit 63, and outputs the resulting L0 data and L1 data.
- the LDPC decoding in the decoding unit 64 can also be performed using the parity check matrix itself used for LDPC encoding, and for the parity check matrix of the type B scheme used for LDPC encoding, parity interleaving Transformation parity check matrix obtained by performing at least the corresponding column permutation, or transformation parity check matrix (FIG. 17) obtained by performing row permutation on the parity check matrix of the type A method used for LDPC coding (FIG. 15) can also be done.
- LDPC decoding is performed using a transform parity check matrix
- an architecture can be adopted for LDPC decoding in which check node operations and variable node operations are simultaneously performed for a number of parallel factors of P or less.
- FIG. 28 is a flowchart illustrating an example of processing of the receiving device 12 of FIG.
- step S201 the OFDM demodulator 61 receives and demodulates the OFDM signal from the transmitter 11.
- the OFDM demodulator 61 supplies the demodulated signal obtained as a result of demodulating the OFDM signal to the LL extractor 62 (and a circuit not shown), and the process proceeds from step S201 to step S202.
- the LL extractor 62 extracts the L0 carrier and the L1 carrier from the demodulated signal from the OFDM demodulator 61, supplies them to the differential demodulator 63, and the process proceeds to step S203.
- step S203 the differential demodulation unit 63 performs differential demodulation of each of the L0 carrier and L1 carrier from the LL extraction unit 62, and each bit of the LDPC code of each of the L0 data and L1 data obtained by the differential demodulation.
- the likelihood is supplied to the decoding unit 64, and the process proceeds to step S204.
- step S204 the decoding unit 64 performs LDPC decoding of the likelihood of each bit of the LDPC code of each of the L0 data and L1 data from the differential demodulation unit 63, and outputs the resulting L0 data and L1 data.
- FIGS. 29 to 32 are diagrams for explaining LDPC decoding using the transform parity check matrix performed by the decoding unit 64 in FIG.
- LDPC decoding is obtained by performing at least column permutation corresponding to parity interleaving for the parity check matrix H of the type B scheme used by the encoding unit 21 of FIG. 2 for LDPC encoding. This can be done using a transformation check matrix or a transformation check matrix (FIG. 17) obtained by performing row permutation on the type A system check matrix (FIG. 15).
- LDPC decoding has been previously proposed, in which it is possible to suppress the operating frequency within a sufficiently feasible range while suppressing the circuit scale by performing LDPC decoding using a transform parity check matrix (for example, , see Patent No. 4224777).
- FIG. 29 is a diagram showing an example of parity check matrix H of an LDPC code as a type B code with a code length N of 90 and a coding rate of 2/3.
- 0 is represented by a period (.).
- the parity matrix has a staircase structure.
- FIG. 30 is a diagram showing parity check matrix H' obtained by performing row permutation of formula (4) and column permutation of formula (5) on parity check matrix H of FIG.
- s, t, x, and y are integers in the range of 0 ⁇ s ⁇ 5, 0 ⁇ t ⁇ 6, 0 ⁇ x ⁇ 5, 0 ⁇ y ⁇ 6, respectively is.
- the 1st, 7th, 13th, 19th and 25th rows which are divided by 6 and the remainder is 1, are the 1st, 2nd, 3rd, 4th and 5th rows, respectively.
- the 2nd, 8th, 14th, 20th and 26th rows, which have a remainder of 2 when divided, are replaced with the 6th, 7th, 8th, 9th and 10th rows, respectively.
- the 61st, 67th, 73rd, 79th, and 85th columns, which have a remainder of 1 when divided by 6, are respectively 61 , the 62nd, 63rd, 64th, and 65th columns, and the 62nd, 68th, 74th, 80th, and 86th columns that have a remainder of 2 when divided by 6 are the 66th, 67th, 68th, 69th, and 70th columns, respectively. Substitutions are made accordingly.
- the matrix (matrix) obtained by permuting the rows and columns of the parity check matrix H of FIG. 29 is the parity check matrix H' of FIG.
- the parity check matrix H' of FIG. 30 is the parity check matrix of FIG. is a transformed parity check matrix obtained by performing at least column permutation to replace with .
- a 0 vector is output. That is, if the row vector c obtained by performing the column permutation of equation (5) on the row vector c as the LDPC code (one codeword) of the original check matrix H is denoted by c′, then from the properties of the check matrix , Hc T is a 0 vector, so H'c' T is also a 0 vector.
- the transformed parity check matrix H' in FIG. 30 is the parity check matrix of the LDPC code c' obtained by performing the column permutation of Equation (5) on the LDPC code c of the original parity check matrix H.
- the LDPC code c of the original parity check matrix H is subjected to the column permutation of Equation (5), and the LDPC code c' after the column permutation is decoded using the transform parity check matrix H' of FIG. 30 (LDPC decoding). Then, by performing the inverse permutation of the column permutation of Equation (5) on the decoding result, the same decoding result as when the LDPC code of the original parity check matrix H is decoded using the parity check matrix H can be obtained. can be done.
- FIG. 31 is a diagram showing the transformation parity check matrix H' of FIG. 30 spaced in units of 5 ⁇ 5 matrices.
- the transformation check matrix H' in FIG. 31 is composed of a 5 ⁇ 5 identity matrix, a quasi-identity matrix, a shift matrix, a sum matrix, and a 0 matrix. Therefore, these 5 ⁇ 5 matrices (identity matrix, quasi-identity matrix, shift matrix, sum matrix, zero matrix) that constitute the transform check matrix H′ are hereinafter referred to as constituent matrices as appropriate.
- FIG. 32 is a block diagram showing a configuration example of a decoding device that performs such decoding.
- FIG. 32 decodes the LDPC code using at least the transform parity check matrix H′ of FIG. 1 shows a configuration example of a decoding device.
- the decoding device of FIG. 32 includes a branch data storage memory 300 consisting of six FIFOs 300 1 to 300 6 , a selector 301 for selecting FIFOs 300 1 to 300 6 , a check node calculator 302, two cyclic shift circuits 303 and 308, Branch data storage memory 304 consisting of 18 FIFOs 304 1 to 304 18 , selector 305 for selecting FIFOs 304 1 to 304 18 , received data memory 306 for storing received data, variable node calculator 307 , decoded word calculator 309 , a received data rearranging section 310 and a decoded data rearranging section 311.
- the edge data storage memory 300 is composed of six FIFOs 300 1 to 300 6 obtained by dividing the number of rows of 30 in the transform parity check matrix H′ of FIG. 31 by the number of rows of the component matrix (parallel factor P) of 5. .
- the number of stages of the storage area of the FIFO 300 y is 9, which is the maximum number of 1s (Hamming weights) in the row direction of the transformation parity check matrix in FIG.
- data (message v from the variable node) corresponding to the position of 1 in the first to fifth rows of the conversion parity check matrix H′ in FIG. is stored in (ignoring 0). That is, if the j-th row and i-th column are represented as (j, i), the memory area of the first stage of the FIFO 300 1 stores (1, 1) to (5, 5) of the transform parity check matrix H'. The data corresponding to the position of 1 in the 5 ⁇ 5 unit matrix of is stored.
- a shift matrix from (1,21) to (5,25) of the transformation parity matrix H' (a shift matrix obtained by cyclically shifting a 5 ⁇ 5 unit matrix by three places to the right) is stored in the second storage area.
- the data corresponding to the position of 1 in is stored. Similarly, data is stored in the third to eighth storage areas according to the transformation parity check matrix H'. Then, the shift matrix from (1,86) to (5,90) of the transformation check matrix H' (1 in the first row of the 5 ⁇ 5 identity matrix is replaced with 0) is stored in the storage area of the ninth stage. Data corresponding to the position of 1 in the shift matrix obtained by cyclically shifting the shift matrix to the left by one is stored.
- the FIFO 300 2 stores data corresponding to the position of 1 from the 6th row to the 10th row of the transformation parity check matrix H' in FIG. That is, in the storage area of the first stage of the FIFO 300 2 , the sum matrix of (6, 1) to (10, 5) of the transform parity check matrix H' (a 5 ⁇ 5 identity matrix is cyclically shifted to the right by one The data corresponding to the position of 1 in the first shift matrix constituting the sum matrix (which is the sum of the first shift matrix obtained by shifting the first shift matrix and the second shift matrix obtained by cyclically shifting two to the right) is stored. Further, in the storage area of the second stage, data corresponding to the position of 1 of the second shift matrix forming the sum matrix of (6, 1) to (10, 5) of the transformation parity check matrix H' is stored. be.
- the component matrix is a P ⁇ P identity matrix with a weight of 1, a quasi-identity matrix in which one or more of the 1 elements of the identity matrix are 0, or , corresponding to the position of 1 in the identity matrix, the quasi-identity matrix, or the shift matrix whose weight is 1 when the identity matrix or the quasi-identity matrix is expressed in the form of the sum of a plurality of shift matrices obtained by cyclically shifting the identity matrix or the quasi-identity matrix.
- Data (messages corresponding to branches belonging to the identity matrix, quasi-identity matrix, or shift matrix) are stored in storage areas of different stages at the same address (same FIFO among FIFOs 300 1 to 300 6 ).
- data is also stored in the third to ninth storage areas according to the transformation parity check matrix H'.
- the FIFOs 300 3 to 300 6 similarly store data according to the transform check matrix H'.
- the branch data storage memory 304 is composed of 18 FIFOs 304 1 to 304 18 obtained by dividing the 90 columns of the transform parity check matrix H' by 5, which is the number of columns of the component matrix (parallel factor P).
- the sum matrix of (6,1) to (10,5) of the transformation check matrix H' (the first shift obtained by cyclically shifting the 5 ⁇ 5 identity matrix by one
- the storage area of the third stage stores data corresponding to the position of 1 in the second shift matrix forming the sum matrix of (6, 1) to (10, 5) of the transform parity check matrix H'. be.
- the component matrix is a P ⁇ P identity matrix with a weight of 1, a quasi-identity matrix in which one or more of the 1 elements of the identity matrix are 0, or , corresponding to the position of 1 in the identity matrix, the quasi-identity matrix, or the shift matrix whose weight is 1 when the identity matrix or the quasi-identity matrix is expressed in the form of the sum of a plurality of shift matrices obtained by cyclically shifting the identity matrix or the quasi-identity matrix.
- Data (messages corresponding to branches belonging to the identity matrix, quasi-identity matrix, or shift matrix) are stored in storage areas of different stages at the same address (same FIFO among FIFOs 304 1 to 304 18 ).
- Data is stored in the fourth and fifth storage areas according to the transformation parity check matrix H′.
- the number of stages of the storage area of the FIFO 304 1 is 5, which is the maximum number of 1's in the column direction (column weight) in the first to fifth columns of the transform parity check matrix H′.
- the FIFOs 304 2 and 304 3 also store data according to the conversion parity check matrix H′, and each has a length (number of stages) of five.
- the FIFOs 304 4 to 304 12 similarly store data according to the conversion parity check matrix H', each having a length of three.
- the FIFOs 304 13 to 304 18 similarly store data according to the conversion parity check matrix H', each having a length of two.
- the branch data storage memory 300 consists of six FIFOs 300 1 to 300 6 , and indicates to which row of the transform parity check matrix H′ of FIG. 31 the five messages D311 supplied from the preceding cyclic shift circuit 308 belong. According to information (matrix data) D312, a FIFO for storing data is selected from among FIFOs 3001 to 3006 , and five messages D311 are collectively stored in the selected FIFO in order.
- the branch data storage memory 300 sequentially reads five messages D3001 from the FIFO 3001 and supplies them to the selector 301 in the next stage.
- the branch data storage memory 300 sequentially reads the messages from the FIFOs 300 2 to 300 6 and supplies them to the selector 301 .
- the selector 301 selects five messages from the FIFOs from which data is currently being read out of the FIFOs 300 1 to 300 6 according to the select signal D301, and supplies them to the check node calculator 302 as messages D302.
- the check node calculator 302 consists of five check node calculators 302 1 to 302 5 , and uses messages D 302 (D 302 1 to D 302 5 ) supplied through the selector 301 (message v from variable node) to calculate check node An operation is performed, and five messages D303 (D303 1 to D303 5 ) (message u from the check node) obtained as a result of the check node operation are supplied to the cyclic shift circuit 303 .
- the cyclic shift circuit 303 shifts the five messages D303 1 through D303 5 obtained by the check node calculation unit 302 by the number of unit matrices (or quasi-unit matrices) whose corresponding branches are the originals in the transform parity check matrix H′. Cyclic shift is performed on the basis of the information as to whether it has been click-shifted, and the result is supplied to the branch data storage memory 304 as a message D304.
- the branch data storage memory 304 consists of 18 FIFOs 304 1 to 304 18 , and information D 305 ( Matrix data), a FIFO for storing data is selected from FIFOs 304 1 to 304 18 , and five messages D304 are collectively stored in the selected FIFO in order.
- the branch data storage memory 304 sequentially reads five messages D3061 from the FIFO 3041 and supplies them to the selector 305 in the next stage.
- the branch data storage memory 304 sequentially reads messages from the FIFOs 304 2 to 304 18 and supplies them to the selector 305 .
- the selector 305 selects five messages from the FIFOs from which data is currently being read out of the FIFOs 304 1 to 304 18 according to the select signal D307, and outputs them as messages D308 from the variable node calculator 307 and the decoded word calculator. 309.
- the received data rearrangement unit 310 rearranges the LDPC code D313 corresponding to the parity check matrix H in FIG. It is supplied to the received data memory 306 .
- Received data memory 306 calculates and stores received LLRs (logarithmic likelihood ratios) from received data D314 supplied from received data rearrangement section 310, and collects the received LLRs by five as received value D309. , to the variable node calculator 307 and the decoded word calculator 309 .
- received LLRs logarithmic likelihood ratios
- variable node calculator 307 consists of five variable node calculators 307 1 to 307 5 , and receives messages D 308 (D 308 1 to D 308 5 ) supplied through the selector 305 (message u from the check node) and a memory for received data.
- Variable node calculation is performed using five received values D309 supplied from 306, and messages D310 ( D3101 to D3105) obtained as a result of the calculation (message v from variable node) are sent to cyclic shift circuit 308. supply to
- the cyclic shift circuit 308 cyclically shifts the messages D310 1 to D310 5 calculated by the variable node calculation unit 307 by the unit matrix (or quasi-unit matrix) from which the corresponding branch is the original in the transform check matrix H′. Based on the information as to whether or not the data has been cyclically shifted, the result is supplied to the branch data storage memory 300 as a message D311.
- one decoding of the LDPC code (variable node operation and check node operation) can be performed.
- the decoding device in FIG. 32 decodes the LDPC code for a predetermined number of times of repeated decoding, and then obtains and outputs the final decoding result in decoded word calculation section 309 and decoded data rearrangement section 311 .
- the decoded word calculator 309 consists of five decoded word calculators 309 1 to 309 5 , and five messages D308 (D308 1 to D308 5 ) output by the selector 305 (message u from the check node) and Using the five received values D309 supplied from the data memory 306, as the final stage of decoding a plurality of times, a decoding result (decoded word) is calculated by performing an operation similar to a variable node operation, and the result The obtained decoded data D315 is supplied to the decoded data rearrangement section 311 .
- the decoded data rearrangement unit 311 performs inverse permutation of the column permutation of formula (5) on the decoded data D315 supplied from the decoded word calculation unit 309, thereby rearranging the order, and the final decoding result Output as D316.
- one or both of row permutation and column permutation is applied to the check matrix (original check matrix) to obtain a check matrix (transformed check matrix) that can be represented by a P ⁇ P constituent matrix.
- a check matrix transformed check matrix
- P node operations check node operations and variable node operations
- the decoding unit 64 that configures the receiving device 12 in FIG. 27 can perform LDPC decoding that simultaneously executes P node operations, for example, like the decoding device in FIG.
- the parity check matrix of the LDPC code output by the encoding unit 21 constituting the transmitting device 11 is, for example, the parity check matrix H shown in FIG. .
- the LDPC code when performing LDPC decoding of the parity-interleaved LDPC code that is LDPC-encoded using the parity check matrix H using the transform parity check matrix H 'obtained by performing the column permutation of equation (5) , the LDPC code does not need to be subjected to the column permutation of equation (5).
- the decoding unit 64 can be configured in the same way as the decoding device in FIG. On the other hand, when parity interleaving is applied to the LDPC code, the decoding unit 64 can be configured not to perform the column permutation of equation (5) for the LDPC code in the decoding device of FIG.
- type A code is an example of type A code, but the same applies to type B code.
- FIG. 33 is a diagram showing a configuration example of the decoding unit 64 in FIG. 27 when parity interleaving is applied to the LDPC code.
- decoding section 64 is configured in the same manner as the decoding device of FIG. 32 except that received data rearrangement section 310 of FIG. Since the processing is the same as that of the decoding device in FIG. It should be noted that the decoding unit 64 can be separately provided with portions that perform LDPC decoding of the LDPC codes of the L0 data and the L1 data.
- the decoding unit 64 can be configured without the received data rearranging unit 310, so the scale can be reduced more than the decoding device in FIG.
- the code length N of the LDPC code is 90
- the information length K is 60
- the parallel factor (the number of rows and columns of the constituent matrix) P is 5.
- each of the code length N, the information length K, and the parallel factor P is not limited to the values described above.
- the encoding unit 21 outputs the new LDPC code described in FIGS. 18 and 19, but the decoding unit 64 in FIG. This method can be applied to LDPC decoding by simultaneously performing P node operations.
- the decoding unit 64 without the decoded data rearrangement unit 311 can be configured.
- FIG. 34 shows a configuration example of one embodiment of a computer in which a program for executing the series of processes described above is installed.
- the program can be recorded in advance in the hard disk 705 or ROM 703 as a recording medium built into the computer.
- the program may be stored temporarily or It can be permanently stored (recorded).
- a removable recording medium 711 can be provided as so-called package software.
- the program can be wirelessly transferred from the download site to the computer via an artificial satellite for digital satellite broadcasting, LAN (Local Area Network),
- the program can be transferred to a computer by wire via a network such as the Internet, and the computer can receive the transferred program in the communication section 708 and install it in the hard disk 705 incorporated therein.
- the computer incorporates a CPU (Central Processing Unit) 702.
- An input/output interface 710 is connected to the CPU 702 via a bus 701.
- the CPU 702 is operated by a user through the input/output interface 710 with an input unit 707 including a keyboard, mouse, microphone, and the like.
- the program stored in the ROM (Read Only Memory) 703 is executed according to the command.
- the CPU 702 can receive a program stored in the hard disk 705, a program transferred from a satellite or a network, received by the communication unit 708 and installed in the hard disk 705, or a removable recording medium 711 attached to the drive 709.
- the program read and installed on the hard disk 705 is loaded into a RAM (Random Access Memory) 704 and executed.
- the CPU 702 performs the processing according to the above-described flowchart or the processing performed by the configuration of the above-described block diagram.
- the CPU 702 outputs the processing result from an output unit 706 composed of an LCD (Liquid Crystal Display), a speaker, etc. via an input/output interface 710, or from a communication unit 708 as necessary. It is transmitted, and furthermore, it is recorded in the hard disk 705 or the like.
- processing steps describing a program for causing a computer to perform various processes do not necessarily have to be processed in chronological order according to the order described as a flow chart, and can be performed in parallel or individually. It also includes the processing that is performed (eg, parallel processing or processing by objects).
- the program may be processed by one computer, or may be processed by a plurality of computers in a distributed manner. Furthermore, the program may be transferred to a remote computer and executed.
- the above-mentioned new LDPC code (parity check matrix initial value table) can be used for satellite lines, terrestrial waves, cables (wired lines), and other communication channels 13 (Fig. 1). Furthermore, the new LDPC code can also be used for data transmission other than digital broadcasting.
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Abstract
Description
7 36 107 167 173 350 489 510 577 643 716 789 960 979 1061 1076
53 75 103 336 349 396 414 480 488 490 513 559 610 622 827 1039
13 69 101 108 122 277 483 532 546 587 612 710 713 858 982 1025
10 32 72 282 420 441 482 553 784 808 977
139 178 778 803 813 1055
130 576 709 732 827 991
109 125 403 905 998 1068
である送信装置/方法である。
7 36 107 167 173 350 489 510 577 643 716 789 960 979 1061 1076
53 75 103 336 349 396 414 480 488 490 513 559 610 622 827 1039
13 69 101 108 122 277 483 532 546 587 612 710 713 858 982 1025
10 32 72 282 420 441 482 553 784 808 977
139 178 778 803 813 1055
130 576 709 732 827 991
109 125 403 905 998 1068
である送信方法により送信されてくるデータから得られる前記LDPC符号を復号する復号部/ステップを備える受信装置/方法である。
9 70 143 150 170 202 349 475 620 732 806 1005
11 72 77 201 220 258 389 431 680 761 958
12 47 142 193 195 279 496 552 587 703 871
24 41 66 213 352 427 589 647 738 824 845
153 639 860 892 984
314 377 470 803 994
147 342 721 732 766
206 415 670 749 778
である送信装置/方法である。
9 70 143 150 170 202 349 475 620 732 806 1005
11 72 77 201 220 258 389 431 680 761 958
12 47 142 193 195 279 496 552 587 703 871
24 41 66 213 352 427 589 647 738 824 845
153 639 860 892 984
314 377 470 803 994
147 342 721 732 766
206 415 670 749 778
である送信方法により送信されてくるデータから得られる前記LDPC符号を復号する復号部/ステップを備える受信装置/方法である。
7 36 107 167 173 350 489 510 577 643 716 789 960 979 1061 1076
53 75 103 336 349 396 414 480 488 490 513 559 610 622 827 1039
13 69 101 108 122 277 483 532 546 587 612 710 713 858 982 1025
10 32 72 282 420 441 482 553 784 808 977
139 178 778 803 813 1055
130 576 709 732 827 991
109 125 403 905 998 1068
になっている。
9 70 143 150 170 202 349 475 620 732 806 1005
11 72 77 201 220 258 389 431 680 761 958
12 47 142 193 195 279 496 552 587 703 871
24 41 66 213 352 427 589 647 738 824 845
153 639 860 892 984
314 377 470 803 994
147 342 721 732 766
206 415 670 749 778
になっている。
・・・(1)
・・・(2)
・・・(3)
・・・(4)
・・・(5)
Claims (12)
- 符号長Nが1224ビットであり、符号化率rが144/1224のLDPC符号の検査行列に基づき、LDPC符号化を行う符号化部を備え、
前記検査行列は、
所定値M1と、前記LDPC符号の情報長K=N×rとで表されるM1行K列の、前記検査行列の左上のA行列と、
M1行M1列の、前記A行列の右に隣接する階段構造のB行列と、
M1行N-K-M1列の、前記B行列の右に隣接するゼロ行列であるZ行列と、
N-K-M1行K+M1列の、前記A行列及び前記B行列の下に隣接するC行列と、
N-K-M1行N-K-M1列の、前記C行列の右に隣接する単位行列であるD行列と
を含み、
前記所定値M1は、108であり、
前記A行列及び前記C行列は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記A行列及び前記C行列の1の要素の位置を36列ごとに表すテーブルであって、
7 36 107 167 173 350 489 510 577 643 716 789 960 979 1061 1076
53 75 103 336 349 396 414 480 488 490 513 559 610 622 827 1039
13 69 101 108 122 277 483 532 546 587 612 710 713 858 982 1025
10 32 72 282 420 441 482 553 784 808 977
139 178 778 803 813 1055
130 576 709 732 827 991
109 125 403 905 998 1068
である
送信装置。 - 前記LDPC符号を、部分受信可能なOFDM(orthogonal frequency-division multiplexing)セグメントで送信する
請求項1に記載の送信装置。 - 符号長Nが1224ビットであり、符号化率rが144/1224のLDPC符号の検査行列に基づき、LDPC符号化を行う符号化ステップを備え、
前記検査行列は、
所定値M1と、前記LDPC符号の情報長K=N×rとで表されるM1行K列の、前記検査行列の左上のA行列と、
M1行M1列の、前記A行列の右に隣接する階段構造のB行列と、
M1行N-K-M1列の、前記B行列の右に隣接するゼロ行列であるZ行列と、
N-K-M1行K+M1列の、前記A行列及び前記B行列の下に隣接するC行列と、
N-K-M1行N-K-M1列の、前記C行列の右に隣接する単位行列であるD行列と
を含み、
前記所定値M1は、108であり、
前記A行列及び前記C行列は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記A行列及び前記C行列の1の要素の位置を36列ごとに表すテーブルであって、
7 36 107 167 173 350 489 510 577 643 716 789 960 979 1061 1076
53 75 103 336 349 396 414 480 488 490 513 559 610 622 827 1039
13 69 101 108 122 277 483 532 546 587 612 710 713 858 982 1025
10 32 72 282 420 441 482 553 784 808 977
139 178 778 803 813 1055
130 576 709 732 827 991
109 125 403 905 998 1068
である
送信方法。 - 符号長Nが1224ビットであり、符号化率rが144/1224のLDPC符号の検査行列に基づき、LDPC符号化を行う符号化ステップを備え、
前記検査行列は、
所定値M1と、前記LDPC符号の情報長K=N×rとで表されるM1行K列の、前記検査行列の左上のA行列と、
M1行M1列の、前記A行列の右に隣接する階段構造のB行列と、
M1行N-K-M1列の、前記B行列の右に隣接するゼロ行列であるZ行列と、
N-K-M1行K+M1列の、前記A行列及び前記B行列の下に隣接するC行列と、
N-K-M1行N-K-M1列の、前記C行列の右に隣接する単位行列であるD行列と
を含み、
前記所定値M1は、108であり、
前記A行列及び前記C行列は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記A行列及び前記C行列の1の要素の位置を36列ごとに表すテーブルであって、
7 36 107 167 173 350 489 510 577 643 716 789 960 979 1061 1076
53 75 103 336 349 396 414 480 488 490 513 559 610 622 827 1039
13 69 101 108 122 277 483 532 546 587 612 710 713 858 982 1025
10 32 72 282 420 441 482 553 784 808 977
139 178 778 803 813 1055
130 576 709 732 827 991
109 125 403 905 998 1068
である
送信方法により送信されてくるデータから得られる前記LDPC符号を復号する復号部を備える
受信装置。 - 前記LDPC符号は、部分受信可能なOFDM(orthogonal frequency-division multiplexing)セグメントで送信される
請求項4に記載の受信装置。 - 符号長Nが1224ビットであり、符号化率rが144/1224のLDPC符号の検査行列に基づき、LDPC符号化を行う符号化ステップを備え、
前記検査行列は、
所定値M1と、前記LDPC符号の情報長K=N×rとで表されるM1行K列の、前記検査行列の左上のA行列と、
M1行M1列の、前記A行列の右に隣接する階段構造のB行列と、
M1行N-K-M1列の、前記B行列の右に隣接するゼロ行列であるZ行列と、
N-K-M1行K+M1列の、前記A行列及び前記B行列の下に隣接するC行列と、
N-K-M1行N-K-M1列の、前記C行列の右に隣接する単位行列であるD行列と
を含み、
前記所定値M1は、108であり、
前記A行列及び前記C行列は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記A行列及び前記C行列の1の要素の位置を36列ごとに表すテーブルであって、
7 36 107 167 173 350 489 510 577 643 716 789 960 979 1061 1076
53 75 103 336 349 396 414 480 488 490 513 559 610 622 827 1039
13 69 101 108 122 277 483 532 546 587 612 710 713 858 982 1025
10 32 72 282 420 441 482 553 784 808 977
139 178 778 803 813 1055
130 576 709 732 827 991
109 125 403 905 998 1068
である
送信方法により送信されてくるデータから得られる前記LDPC符号を復号する復号ステップを備える
受信方法。 - 符号長Nが1152ビットであり、符号化率rが144/1152のLDPC符号の検査行列に基づき、LDPC符号化を行う符号化部を備え、
前記検査行列は、
所定値M1と、前記LDPC符号の情報長K=N×rとで表されるM1行K列の、前記検査行列の左上のA行列と、
M1行M1列の、前記A行列の右に隣接する階段構造のB行列と、
M1行N-K-M1列の、前記B行列の右に隣接するゼロ行列であるZ行列と、
N-K-M1行K+M1列の、前記A行列及び前記B行列の下に隣接するC行列と、
N-K-M1行N-K-M1列の、前記C行列の右に隣接する単位行列であるD行列と
を含み、
前記所定値M1は、144であり、
前記A行列及び前記C行列は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記A行列及び前記C行列の1の要素の位置を36列ごとに表すテーブルであって、
9 70 143 150 170 202 349 475 620 732 806 1005
11 72 77 201 220 258 389 431 680 761 958
12 47 142 193 195 279 496 552 587 703 871
24 41 66 213 352 427 589 647 738 824 845
153 639 860 892 984
314 377 470 803 994
147 342 721 732 766
206 415 670 749 778
である
送信装置。 - 前記LDPC符号を、部分受信可能なOFDM(orthogonal frequency-division multiplexing)セグメントで送信する
請求項7に記載の送信装置。 - 符号長Nが1152ビットであり、符号化率rが144/1152のLDPC符号の検査行列に基づき、LDPC符号化を行う符号化ステップを備え、
前記検査行列は、
所定値M1と、前記LDPC符号の情報長K=N×rとで表されるM1行K列の、前記検査行列の左上のA行列と、
M1行M1列の、前記A行列の右に隣接する階段構造のB行列と、
M1行N-K-M1列の、前記B行列の右に隣接するゼロ行列であるZ行列と、
N-K-M1行K+M1列の、前記A行列及び前記B行列の下に隣接するC行列と、
N-K-M1行N-K-M1列の、前記C行列の右に隣接する単位行列であるD行列と
を含み、
前記所定値M1は、144であり、
前記A行列及び前記C行列は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記A行列及び前記C行列の1の要素の位置を36列ごとに表すテーブルであって、
9 70 143 150 170 202 349 475 620 732 806 1005
11 72 77 201 220 258 389 431 680 761 958
12 47 142 193 195 279 496 552 587 703 871
24 41 66 213 352 427 589 647 738 824 845
153 639 860 892 984
314 377 470 803 994
147 342 721 732 766
206 415 670 749 778
である
送信方法。 - 符号長Nが1152ビットであり、符号化率rが144/1152のLDPC符号の検査行列に基づき、LDPC符号化を行う符号化ステップを備え、
前記検査行列は、
所定値M1と、前記LDPC符号の情報長K=N×rとで表されるM1行K列の、前記検査行列の左上のA行列と、
M1行M1列の、前記A行列の右に隣接する階段構造のB行列と、
M1行N-K-M1列の、前記B行列の右に隣接するゼロ行列であるZ行列と、
N-K-M1行K+M1列の、前記A行列及び前記B行列の下に隣接するC行列と、
N-K-M1行N-K-M1列の、前記C行列の右に隣接する単位行列であるD行列と
を含み、
前記所定値M1は、144であり、
前記A行列及び前記C行列は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記A行列及び前記C行列の1の要素の位置を36列ごとに表すテーブルであって、
9 70 143 150 170 202 349 475 620 732 806 1005
11 72 77 201 220 258 389 431 680 761 958
12 47 142 193 195 279 496 552 587 703 871
24 41 66 213 352 427 589 647 738 824 845
153 639 860 892 984
314 377 470 803 994
147 342 721 732 766
206 415 670 749 778
である
送信方法により送信されてくるデータから得られる前記LDPC符号を復号する復号部を備える
受信装置。 - 前記LDPC符号は、部分受信可能なOFDM(orthogonal frequency-division multiplexing)セグメントで送信される
請求項10に記載の受信装置。 - 符号長Nが1152ビットであり、符号化率rが144/1152のLDPC符号の検査行列に基づき、LDPC符号化を行う符号化ステップを備え、
前記検査行列は、
所定値M1と、前記LDPC符号の情報長K=N×rとで表されるM1行K列の、前記検査行列の左上のA行列と、
M1行M1列の、前記A行列の右に隣接する階段構造のB行列と、
M1行N-K-M1列の、前記B行列の右に隣接するゼロ行列であるZ行列と、
N-K-M1行K+M1列の、前記A行列及び前記B行列の下に隣接するC行列と、
N-K-M1行N-K-M1列の、前記C行列の右に隣接する単位行列であるD行列と
を含み、
前記所定値M1は、144であり、
前記A行列及び前記C行列は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記A行列及び前記C行列の1の要素の位置を36列ごとに表すテーブルであって、
9 70 143 150 170 202 349 475 620 732 806 1005
11 72 77 201 220 258 389 431 680 761 958
12 47 142 193 195 279 496 552 587 703 871
24 41 66 213 352 427 589 647 738 824 845
153 639 860 892 984
314 377 470 803 994
147 342 721 732 766
206 415 670 749 778
である
送信方法により送信されてくるデータから得られる前記LDPC符号を復号する復号ステップを備える
受信方法。
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Citations (4)
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JP4224777B2 (ja) | 2003-05-13 | 2009-02-18 | ソニー株式会社 | 復号方法および復号装置、並びにプログラム |
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