WO2023077875A1 - 用于并行执行核心程序的方法和装置 - Google Patents
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- 238000010586 diagram Methods 0.000 description 10
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
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- Embodiments of the present disclosure relate generally to the field of electronics, and more particularly to a method and apparatus for executing kernel programs in parallel.
- the memory in the processor (especially the dynamic random access memory) is difficult to match with the high-speed computing processor due to the long delay in access speed. This causes the processor to often waste time waiting for data.
- kernel program refers to a piece of code executable on a processor. For example, when the execution of instructions of one kernel program is blocked for some reason, another kernel program can be automatically selected and its instructions executed. In this way, the efficiency of the processor can be increased.
- the execution efficiency of the kernel program is also limited by the register space in the processor. Therefore, there is a need for a method that can comprehensively consider the computing resources and storage resources of the processor to execute the core program in parallel, so as to further improve the efficiency of the processor.
- Embodiments of the present disclosure provide a technical solution for executing core programs in parallel.
- a method of executing kernel programs in parallel includes: executing the first core program by accessing the shared space and the first private space in the register space.
- the method also includes executing a second kernel program different from the first kernel program by accessing a second private space in the register space in response to execution of the first kernel program being blocked.
- the shared space, the first private space and the second private space are separated from each other.
- the method also includes continuing to execute the second kernel program by accessing the shared space and the second private space in response to the completion of the execution of the first kernel program.
- a computer readable storage medium stores a plurality of programs configured to be executed by one or more processing engines, the plurality of programs including instructions for performing the method of the first aspect of the present disclosure.
- a computer program product comprises a plurality of programs configured for execution by one or more processing engines, the plurality of programs comprising instructions for performing the method of the first aspect of the present disclosure.
- an accelerator system comprising: a processor; and a memory coupled to the processor, the memory having instructions stored therein that when executed by the processor cause the device to implement.
- an apparatus for executing kernel programs in parallel includes: a first parallel execution unit configured to execute a first kernel program by accessing a shared space and a first private space in a register space of the device.
- the device further includes: a second parallel execution unit configured to execute a second kernel program different from the first kernel program by accessing a second private space in the register space in response to the execution of the first kernel program being blocked, sharing The space, the first private space and the second private space are separated from each other.
- the apparatus further includes: a third parallel execution unit configured to continue executing the second kernel program by accessing the shared space and the second private space in response to the completion of the execution of the first kernel program.
- the efficiency of executing a single kernel program can be improved by preferentially allocating computing resources and storage resources to the main kernel program when the kernel programs are executed in parallel.
- the efficiency of executing kernel programs in parallel can be generally improved.
- Figure 1 shows a schematic diagram of an example environment in which various embodiments of the present disclosure can be implemented
- FIG. 2 shows a schematic diagram of a chip according to an embodiment of the present disclosure
- Figure 3 shows a schematic diagram of a processing engine according to one embodiment of the present disclosure
- FIG. 4 shows a schematic diagram of a register space according to an embodiment of the present disclosure
- FIG. 5 shows a flowchart of a method for executing kernel programs in parallel according to an embodiment of the present disclosure
- Fig. 6 shows a schematic block diagram of an apparatus for executing kernel programs in parallel according to an embodiment of the present disclosure.
- the term “comprise” and its variants mean open inclusion, ie “including but not limited to”.
- the term “or” means “and/or” unless otherwise stated.
- the term “based on” means “based at least in part on”.
- the terms “one example embodiment” and “one embodiment” mean “at least one example embodiment.”
- the term “another embodiment” means “at least one further embodiment”.
- the terms “first”, “second”, etc. may refer to different or the same object. Other definitions, both express and implied, may also be included below.
- FIG. 1 shows a schematic diagram of an example environment 100 in which various embodiments of the present disclosure can be implemented.
- Example environment 100 may include, for example, electronic devices with computing capabilities, such as computers.
- the example environment 100 includes, for example, a central processing unit (CPU) 120, a system memory 110, a north bridge/memory bridge 130, an accelerator system 140, an external storage device 150, and a south bridge/input output (IO) bridge 160.
- System memory 110 may include, for example, volatile memory such as dynamic random access memory (DRAM).
- DRAM dynamic random access memory
- the north bridge/memory bridge 130 for example, integrates a memory controller, a PCIe controller, etc., and is responsible for data exchange between the CPU 120 and the high-speed interface as well as bridging the CPU 120 and the south bridge/IO bridge 160.
- the South Bridge/IO Bridge 160 is used for low-speed interfaces of computers, such as Serial Advanced Technology Interface (SATA) controllers and the like.
- the accelerator system 140 may include, for example, devices or chips such as a graphics processing unit (GPU) and an artificial intelligence (AI) accelerator for accelerated processing of data such as graphics and video.
- the external storage device 150 may be, for example, a volatile memory such as DRAM located outside the accelerator system 140 .
- the external storage device 150 is also referred to as an off-chip memory, that is, a memory located outside the chip of the accelerator system 140 .
- the chip of the accelerator system 140 also has a volatile memory, such as a first-level (L1) cache (cache) and an optional second-level (L2) cache. It will be described in detail below in conjunction with some embodiments of the present disclosure. While an example environment 100 in which embodiments of the disclosure can be implemented is shown in FIG. 1 , the disclosure is not limited thereto. Some embodiments of the present disclosure may also be used in other application environments with accelerator systems such as GPUs, such as ARM architectures and RISC-V architectures.
- FIG. 2 shows a schematic block diagram of an accelerator system 200 according to one embodiment of the present disclosure.
- the accelerator system 200 may be, for example, a specific implementation manner of the chip of the accelerator system 140 in FIG. 1 .
- the accelerator system 200 includes, for example, an accelerator system-on-a-chip such as a GPU.
- the accelerator system 200 may include a stream processor (SP) 210, a page table device 220, a processing engine (Processing Engine, PE) unit 230, a direct memory access (DMA) controller 240, a L1 cache 260 and L2 cache 250 .
- SP stream processor
- PE processing engine
- DMA direct memory access
- the accelerator system 200 may be controlled by a host device such as the CPU 120 and receive instructions from the CPU 120.
- the SP 210 analyzes instructions from the CPU 120, and assigns the analyzed operations to the PE unit 230, the page table device 220, and the DMA controller 240 for processing.
- the page table device 220 is used to manage virtual storage accessible by the accelerator system 200 .
- the virtual storage may include, for example, the L2 cache 250 and off-chip memory such as the external storage device 150 in FIG. 1 .
- the page table device 220 is jointly maintained by the SP 210, the PE unit 230 and the DMA controller 240.
- the PE unit 230 may include a plurality of processing engines PE_1 , PE_2 . . . PE_N, where N represents an integer greater than 1.
- Each processing engine may be associated with a corresponding L1 cache.
- PE_1 can be associated with L1_1
- PE_2 can be associated with L1_2.
- Each PE in PE unit 230 may be a single instruction multiple thread (SIMT) device.
- SIMT single instruction multiple thread
- each thread can have its own register file, and all threads of each PE also share a uniform register file.
- Multiple PEs can perform the same or different processing jobs in parallel. For example, PE can perform processing such as sorting and convolution on the data to be processed.
- the application program can be divided into multiple parts, and the multiple parts are run in parallel on multiple PEs.
- the efficiency of a PE is also limited by the storage resources within the PE, namely the register space.
- the storage resources in the PE need to be divided into at least two storage spaces, so as to allocate storage spaces to the two Kernels respectively for storing temporary data generated by the execution of the Kernels.
- the efficiency improvement of PE brought about by executing Kernels in parallel will be weakened.
- a technical solution for executing Kernels in parallel is provided.
- the first Kernel is executed by accessing the shared space and the first private space in the register space.
- a second Kernel different from the first Kernel is executed by accessing the second private space in the register space, and the shared space, the first private space and the second private space are separated from each other.
- the second Kernel continues to execute the second Kernel by accessing the shared space and the second private space.
- the efficiency of executing a single Kernel by the PE can be improved.
- the efficiency of PE parallel execution of Kernels can be improved on the whole.
- FIG. 3 shows a schematic block diagram of a PE 300 according to one embodiment of the present disclosure.
- PE 300 may be implemented by processing engines PE_1, PE_2...PE_N shown in FIG. 2 .
- PE 300 may include multiple threads, such as thread 310, thread 320, and thread 330.
- threads can be started at a PE.
- Each thread can have its own register space and execution unit.
- thread 310 may have register space 311 and execution unit 312 .
- Thread 320 may have register space 321 and execution unit 322 .
- Thread 330 may have register space 331 and execution unit 332 .
- a register space may refer to a storage space including a plurality of registers. Each register space can use its own storage address, such as a typical register access architecture (load-store architecture).
- load-store architecture typical register access architecture
- PE 300 may also include a controller 350 (also referred to as a scheduler or an instruction transmitter).
- the controller 350 is used for scheduling instructions of different Kernels and sending instructions to multiple threads in the PE 300.
- all execution units in PE 300 execute the same instruction synchronously.
- predicate predicate register
- part of the execution unit can be shielded, so as to realize the function of the branch instruction.
- Examples of instructions may include access instructions and operation instructions.
- memory read and write instructions can provide data exchange between register space and on-chip/off-chip memory.
- the operation instruction can make the execution unit carry out the corresponding operation.
- the operands used by the execution units can come from the corresponding register space.
- a PE may also include other units, such as a unified register file shared by multiple threads of the PE.
- FIG. 4 shows a schematic block diagram of a register space 400 according to an embodiment of the present disclosure.
- the register space 400 may be implemented as the register spaces 311, 321, and 331 shown in FIG. 3 .
- the register space 400 may be divided into a shared space (for example, a shared space 410 ) and a private space (for example, a first private space 420 and a second private space 430 ) which are separated from each other.
- the private space can also be divided into multiple private spaces to be allocated to multiple Kernels executed in parallel.
- the number of private spaces may correspond to a predetermined number of Kernels executed in parallel.
- the PE 300 can be predetermined to execute two active Kernels in parallel.
- the private space of the register space 400 can be divided into two private spaces.
- PE 300 can execute three active Kernels in parallel.
- the private space of the register space 400 can be divided into three private spaces.
- the size of the shared space 410 may be greater than the size of each private space (eg, the first private space 420 and the third private space 430 ).
- the shared space 410 may include more than 200 registers, while the private space (eg, the first private space 320 or the second private space 430 ) may include 16 registers.
- each private space may be equal in size.
- the first private space 420 and the third private space 430 may respectively include 16 registers.
- the size of the shared space 410 and the private space can be set according to specific applications.
- FIG. 5 shows a flowchart of a method 500 for executing Kernels in parallel according to an embodiment of the present disclosure.
- Method 500 can be implemented at PE 300. Additionally, some steps in method 500 may be implemented at each thread in PE 300. For ease of description only, details of method 500 will be described below with reference to thread 310 .
- the first Kernel is executed by accessing the shared space 410 and the first private space 420 in the register space 311 .
- the shared space 410 and the first private space 420 can store instructions and data related to the execution of the first Kernel.
- the PE 300 can execute the first Kernel by accessing the shared space 410 and the first private space 420, and store the temporary data generated by the execution in the shared space 410 and the first private space 420.
- PE 300 can receive at least one Kernel to be executed from SP 210. It should be understood that the multiple Kernels to be executed received by the SP 210 from the host device are sorted, and the order may be related to the dependencies among the multiple Kernels. Therefore, at least one Kernel to be executed received by the PE 300 from the SP 210 is also sorted.
- the PE 300 can execute multiple Kernels in the received Kernels in parallel. For example, PE 300 may first execute two Kernels in the received Kernels in parallel. The remaining Kernels in the received Kernels may be executed after the execution of the first two Kernels is completed.
- the Kernel may be executed in a strict first-in-first-out order.
- the PE 300 can execute the Kernel first received from the SP 210 (that is, the Kernel that is ranked first among the Kernels to be executed received by the PE 300) and then execute the Kernel received later.
- the first Kernel may be the Kernel received first by the PE 300 in a group of Kernels executed in parallel.
- the PE 300 can continue to execute the first Kernel based on the temporary data stored in the shared space 410 and the first private space 420.
- the PE 300 may use the computing resource of the thread 310 (ie, the execution unit 312) to execute the second Kernel.
- the second Kernel may be a Kernel executed in parallel with the first Kernel.
- the PE 300 can execute the second Kernel by accessing the second private space 430 in the register space 400.
- the second private space 430 can store instructions and data related to the execution of the second Kernel.
- the PE 300 can execute the second Kernel based on the instructions and data in the second private space 430, and store the temporary data generated by the execution in the second private space 430.
- the controller 350 in the PE 300 can check the execution of the second Kernel. Whether the instruction to be executed needs to access the shared space 410 .
- the controller 350 may determine whether the instruction to be executed of the second Kernel needs to access the shared space 410 according to the definition in the program by the programmer.
- the PE 300 can execute the instruction by only accessing the second private space 430 without accessing the shared space 410.
- the PE 300 may execute the instruction to be executed of the second Kernel.
- the PE 300 can perform some simple tasks by accessing the second private space 430, so as to prepare for the subsequent execution of the second private space 430.
- the PE 300 may need to access the second private space 430 and additional register space to execute the instruction.
- Controller 350 since the data related to the instruction of the first Kernel is stored in the shared space 410 and the execution of the first Kernel has not been completed, when the controller 350 determines that the instruction to be executed of the second Kernel needs to access the shared space 410 to be executed, Controller 350 will not execute this instruction. In this case, the controller 350 may reselect the next instruction to be executed. For example, the controller 350 may choose to wait for the instructions of the first Kernel to recover from the blocked state to the executable state.
- the controller 350 in the PE 300 may check whether the blocked instruction of the first Kernel has been restored to an executable state. In response to the blocked instruction of the first Kernel having been restored to an executable state, the PE 300 can continue to execute the instruction by accessing the shared space 410 and the first private space 420.
- the PE 300 may not continue to execute the instruction of the second Kernel, but the controller 350 re-determines the next instruction to be executed. Moreover, when determining the next instruction to be executed, the instruction of the first Kernel is preferentially selected for execution. In this way, the PE 300 can preferentially allocate the computing resources and storage resources of the thread 310 to the first Kernel at the same time, so that the execution efficiency of the first Kernel is greatly improved.
- the PE 300 can preferentially allocate computing resources and storage resources of the thread 310 to the second Kernel.
- the PE 300 can continue to execute the second Kernel by accessing the shared space 410 and the second private space 420.
- the shared space 410 and the first private space 420 store instructions and data related to the execution of the first Kernel. Therefore, when the execution of the first Kernel is completed, data related to the execution of the first Kernel, such as calculation results, is stored in the shared space 410 .
- the state of the shared space 410 may be reset when the execution of the first Kernel is completed, that is, data related to the first Kernel in the shared space 410 may be cleared.
- the PE 300 can continue to execute the second Kernel by accessing the reset shared space 410 and the second private space 420.
- the state of the shared space 410 may not be reset when the execution of the first Kernel is completed, that is, the state of the shared space 410 when the execution of the first Kernel is completed may be maintained.
- the state of the shared space 410 may not be reset when the execution of the first Kernel is completed. Properties can be specified by the programmer in the program. Alternatively, the attribute may indicate that the corresponding register space 400 is reset at the beginning, end, or both start and end of Kernel execution.
- the PE 300 can continue to execute the second Kernel based on the state of the shared space 410 when the execution of the first Kernel is completed.
- the state of the shared space 410 when the execution of the first Kernel is completed may indicate the result of the first operator specified by the first Kernel. Therefore, the PE 300 can execute a second operator specified by the second Kernel based on the result of the first operator and write the result of the second operator into a memory outside the register space 311, for example, the L1 cache 260 and the L2 cache Cache 250.
- the inheritance of the shared space 410 can be used to directly transfer the calculation result of the first Kernel to the second Kernel without going through the process of writing the calculation result into the memory and reading the calculation result from the memory, thereby reducing the need for external memory. to read.
- the calculation process of the artificial intelligence model on the hardware can be abstracted into a calculation graph.
- the nodes in the graph can represent operations (also called operators) performed on variables, such as matrix multiplication (MatMul), bias addition (Add), activation value (Sigmoid), etc.
- Each operation can be implemented with a corresponding Kernel.
- shared interval 410 may be utilized to transfer data. Taking the first Kernel and the second Kernel discussed above as an example, since the execution of the second Kernel can access the shared area 410 after the execution of the first Kernel is completed (assuming that it is not reset), the second Kernel can directly use the legacy of the first Kernel. The calculation results in the shared section 410 save a large amount of stored data streams and improve calculation efficiency.
- the PE 300 can execute the third Kernel by accessing the first private space 420 . It should be noted that when the execution of the first Kernel is completed, although the shared space 410 storing data relevant to the execution of the first Kernel may not be reset, the first private space storing data relevant to the execution of the first Kernel will be reset. reset. In this way, the storage resource in the thread 310 can be released for use by the third Kernel.
- the PE 300 can continue to execute the third Kernel by accessing the shared space 410 and the first private space 420.
- the third Kernel can be executed as the new main Kernel, and at the same time, the PE 300 can preferentially allocate computing resources and storage resources of the thread 310 to the third Kernel.
- the above only describes how to execute Kernels in parallel by taking the first Kernel, the second Kernel and the third Kernel as examples, but does not limit the number of Kernels executed in parallel. According to this solution, the efficiency of executing a single Kernel can be improved by preferentially allocating computing resources and storage resources to the main Kernel when executing Kernels in parallel. In addition, by adjusting the latter Kernel as the main Kernel after the execution of the previous Kernel is completed, the efficiency of executing Kernels in parallel can be generally improved.
- FIG. 6 shows a schematic block diagram of an apparatus 600 for executing kernel programs in parallel according to an embodiment of the present disclosure.
- Apparatus 600 may be implemented as or included in accelerator system 200 of FIG. 2 .
- the apparatus 600 may include a plurality of units for performing corresponding steps in the method 500 as discussed in FIG. 5 .
- the device 600 includes: a first parallel execution unit 610 configured to execute the first kernel program by accessing the shared space and the first private space in the register space of the device; the second parallel execution unit 620, configured to, in response to the execution of the first kernel program being blocked, execute a second kernel program different from the first kernel program by accessing a second private space in the register space, the shared space, the first private space and the second private space are separated from each other; and the third parallel execution unit 630 is configured to respond to the completion of the execution of the first kernel program, by accessing the shared space and The second private space continues to execute the second kernel program.
- the second parallel execution unit 620 includes: a first checking unit configured to: in response to the execution of the first instruction of the first kernel program being blocked, check the Whether the instruction to be executed of the program needs to access the shared space; and the first instruction execution unit is configured to: execute the to-be-executed of the second kernel program in response to the instruction to be executed does not need to access the shared space Execute instructions.
- the apparatus 600 further includes: a second checking unit configured to: check whether the execution of the first instruction is no longer blocked in response to the completion of the execution of the instruction to be executed; And a second instruction execution unit configured to continue executing the first instruction by accessing the shared space and the first private space in response to the execution of the first instruction being no longer blocked.
- the third parallel execution unit 630 includes: a state maintenance unit configured to: maintain the state of the shared space when the execution of the first kernel program is completed; and a fourth parallel execution A unit configured to continue executing the second kernel program based on the state of the shared space when the execution of the first kernel program is completed.
- the state maintenance unit includes: a first reset unit configured to: based on the attribute of the first kernel program indicating that the shared space can be inherited, in the first kernel program The state of the shared space is not reset when the execution completes.
- the fourth The parallel execution unit includes: an operation unit configured to: execute a second operator specified by the second core program based on a result of the first operator; and a writing unit configured to: The results of the two operators are written to memory external to the register space.
- the first kernel program is received before the second kernel program.
- the device further includes: a fifth parallel execution unit configured to: in response to the continuation of execution of the second kernel program being blocked, execute the second kernel program by accessing the first private space Three kernel programs, the third kernel program being different from the first kernel program and the second kernel program; and a sixth parallel execution unit configured to: respond to the continued execution of the second kernel program has been completed, continue to execute the third kernel program by accessing the shared space and the first private space.
- the fifth parallel execution unit includes: a second reset unit configured to: reset the state of the first private space when the execution of the first kernel program is completed .
- the shared space is larger than the first private space and the second private space.
- a computer-readable storage medium stores a plurality of programs configured to be executed by one or more processing engines, the plurality of programs including instructions for performing the methods described above.
- a computer program product comprises a plurality of programs configured for execution by one or more processing engines, the plurality of programs comprising instructions for performing the methods described above.
- an accelerator system includes: a processor; and a memory coupled to the processor, the memory having instructions stored therein that, when executed by the processor, cause the device to perform the method described above.
- the present disclosure may be a method, apparatus, system and/or computer program product.
- a computer program product may include a computer-readable storage medium having computer-readable program instructions thereon for carrying out various aspects of the present disclosure.
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Abstract
本公开涉及用于并行执行核心程序的方法和装置。在方法中,通过访问寄存器空间中的共享空间和第一私有空间,执行第一核心程序。响应于第一核心程序的执行被阻塞,通过访问寄存器空间中的第二私有空间,执行不同于第一核心程序的第二核心程序。响应于第一核心程序的执行已经完成,通过访问共享空间和第二私有空间,继续执行第二核心程序。利用本公开的示例性实现方式,通过在并行执行核心程序时将计算资源和存储资源优先分配给主核心程序,以及动态切换主核心程序,可以在总体上提高并行执行核心程序的效率。此外,通过利用共享空间,可以将第一核心程序的数据直接传递给第二核心程序,从而减少对寄存器空间外部的存储器的读写。
Description
本申请要求于2021年11月8日提交中国专利局、申请号为202111314392.5、发明名称为“用于并行执行核心程序的方法和装置”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
本公开的实施方式一般地涉及电子领域,更具体而言涉及用于并行执行核心程序的方法和装置。
通常,处理器中的存储器(特别是动态随机存取存储器)由于存取速度时延较长而难以与高速计算的处理器匹配。这使得处理器常常因等待数据而浪费时间。
目前,已经提出了一些并行执行核心程序(Kernel)的方法来解决这样的问题。核心程序指代在处理器上可执行的一段代码。例如,可以在一个核心程序的指令的执行由于某种原因被阻塞时,自动选择另一个核心程序并执行其指令。以此方式,可以提高处理器的效率。
然而,核心程序的执行效率还受限于处理器中的寄存器空间。因此,需要能够综合考虑处理器的计算资源和存储资源来并行执行核心程序的方法,以实现处理器的效率的进一步提高。
发明内容
本公开的实施方式提供了一种并行执行核心程序的技术方案。
在第一方面,提供了一种并行执行核心程序的方法。该方法包括:通过访问寄存器空间中的共享空间和第一私有空间,执行第一核心程序。方法还包括:响应于第一核心程序的执行被阻塞,通过访问寄存器空间中的第二私有空间,执行不同于第一核心程序的第 二核心程序。共享空间、第一私有空间和第二私有空间彼此分离。方法还包括:响应于第一核心程序的执行已经完成,通过访问共享空间和第二私有空间,继续执行第二核心程序。
在第二方面,提供了一种计算机可读存储介质。该介质存储多个程序,多个程序被配置为一个或多个处理引擎执行,多个程序包括用于执行本公开的第一方面的方法的指令。
在第三方面,提供了一种计算机程序产品。该计算机程序产品包括多个程序,多个程序被配置为一个或多个处理引擎执行,多个程序包括用于执行本公开的第一方面的方法的指令。
在第四方面,提供了加速器系统,包括:处理器;以及与所述处理器耦合的存储器,所述存储器具有存储于其中的指令,所述指令在被所述处理器执行时使得所述设备执行。
在第五方面,提供了一种用于并行执行核心程序的装置。该装置包括:第一并行执行单元,被配置用于通过访问装置的寄存器空间中的共享空间和第一私有空间,执行第一核心程序。装置还包括:第二并行执行单元,被配置用于响应于第一核心程序的执行被阻塞,通过访问寄存器空间中的第二私有空间,执行不同于第一核心程序的第二核心程序,共享空间、第一私有空间和第二私有空间彼此分离。装置还包括:第三并行执行单元,被配置用于响应于第一核心程序的执行已经完成,通过访问共享空间和第二私有空间,继续执行第二核心程序。
利用本公开的示例性实现方式,通过在并行执行核心程序时将计算资源和存储资源优先分配给主核心程序,可以提高执行单个核心程序的效率。此外,通过在前一个核心程序执行完毕后,将后一个核心程序调整为主核心程序,可以在总体上提高并行执行核心程序的效率。
通过结合附图对本公开示例性实施方式进行更详细的描述,本 公开的上述以及其他目的、特征和优势将变得更加明显,其中,在本公开示例性实施方式中,相同的参考标号通常代表相同部件。
图1示出了本公开的多个实施方式能够在其中实现的示例环境的示意图;
图2示出了根据本公开的一个实施方式的芯片示意图;
图3示出了根据本公开的一个实施方式的处理引擎的示意图;
图4示出了根据本公开的一个实施方式的寄存器空间的示意图;
图5示出了根据本公开的一个实施方式的并行执行核心程序的方法的流程图;以及
图6示出了根据本公开的一个实施方式的并行执行核心程序的装置的示意框图。
下面将参照附图更详细地描述本公开的优选实施方式。虽然附图中示出了本公开的优选实施方式,然而应该理解,本公开可以以各种形式实现而不应被这里阐述的实施方式限制。相反,提供这些实施方式是为了使本公开更加透彻和完整,并且能够将本公开的范围完整地传达给本领域的技术人员。
在本文中使用的术语“包括”及其变形表示开放性包括,即“包括但不限于”。除非特别申明,术语“或”表示“和/或”。术语“基于”表示“至少部分地基于”。术语“一个示例实施方式”和“一个实施方式”表示“至少一个示例实施方式”。术语“另一实施方式”表示“至少一个另外的实施方式”。术语“第一”、“第二”等等可以指代不同的或相同的对象。下文还可能包括其他明确的和隐含的定义。
首先参见图1描述用于执行本公开的多个示例性实现方式的环境的概要。图1示出了本公开的多个实施方式能够在其中实现的示例环境100的示意图。示例环境100例如可以包括诸如计算机之类的具有计算能力的电子设备。在一个实施方式中,示例环境100例 如包括中央处理器(CPU)120、系统存储器110、北桥/存储器桥130、加速器系统140、外部存储设备150和南桥/输入输出(IO)桥160。系统存储器110例如可以包括诸如动态随机存取存储器(DRAM)之类的易失性存储器。北桥/存储器桥130例如集成了内存控制器、PCIe控制器等,其负责CPU 120和高速接口之间的数据交换以及桥接CPU 120和南桥/IO桥160。南桥/IO桥160用于计算机的低速接口,例如串行高级技术接口(SATA)控制器等。加速器系统140例如可以包括诸如图形处理器(GPU)和人工智能(AI)加速器等用于对图形、视频等数据进行加速处理的装置或芯片。外部存储设备150例如可以是诸如DRAM之类的位于加速器系统140外部的易失性存储器。
在本公开中,外部存储设备150也被称为片外存储器,即,位于加速器系统140的芯片外部的存储器。相对而言,加速器系统140的芯片内部也具有易失性存储器,例如一级(L1)高速缓存(cache)以及可选的二级(L2)高速缓存。将在下文结合本公开的一些实施方式具体描述。虽然在图1中示出了本公开的多个实施方式能够在其中实现的一种示例环境100,但是本公开不限于此。本公开的一些实施方式也可以在诸如ARM架构和RISC-V架构之类的具有诸如GPU之类的加速器系统的其他应用环境中使用。
图2示出了根据本公开的一个实施方式的加速器系统200的示意框图。加速器系统200例如可以是图1中加速器系统140的芯片的一种具体实现方式。加速器系统200例如包括诸如GPU之类的加速器系统芯片。根据本公开的一个示例性实现方式,加速器系统200可以包括流处理器(SP)210、页表装置220、处理引擎(Processing Engine,PE)单元230、直接存储器访问(DMA)控制器240、L1高速缓存260和L2高速缓存250。
加速器系统200可以由诸如CPU 120之类的主机设备控制,并且接收来自CPU 120的指令。SP 210对来自CPU 120的指令进行分析,并且将经分析的操作指派给PE单元230、页表装置220和DMA 控制器240进行处理。页表装置220用于管理加速器系统200可访问的虚拟存储。在本公开中,除了L1高速缓存260,虚拟存储例如可以包括L2高速缓存250和诸如图1中的外部存储设备150之类的片外存储器。页表装置220由SP 210、PE单元230和DMA控制器240共同维护。
PE单元230可以包括多个处理引擎PE_1、PE_2……PE_N,其中N表示大于1的整数。每个处理引擎可以与对应的L1高速缓存关联。例如,如图1所示,PE_1可以与L1_1关联,PE_2可以与L1_2关联。PE单元230中的每个PE可以是单指令多线程(SIMT)装置。在PE中,每个线程可以具有自己的寄存器堆(register file),并且每个PE的所有线程还共享统一寄存器堆(uniform register file)。多个PE可以并行地执行相同或不同的处理工作。例如,PE可以针对待处理的数据执行排序、卷积等处理。
用户(例如,程序员)可以编写应用程序来实现特定的目的。对于需要较大计算量的应用程序而言,可以将该应用程序划分为多个部分,并且分别在多个PE处并行地运行多个部分。
目前已经提供了通过并行执行Kernel来提高PE的效率的方法。通过在一个Kernel的指令的执行被阻塞时自动选择另一个Kernel并执行其指令,可以提高PE的效率。
然而,PE的效率还受限于PE内的存储资源,也即寄存器空间。例如,如果PE并行地执行两个Kernel,则需要将PE内的存储资源划分为至少两个存储空间,以分别给两个Kernel分配存储空间以用于存储Kernel的执行所产生的临时数据。在这种情况下,由于每个Kernel的执行仅能访问存储资源的一部分,因此由于并行执行Kernel而带来的PE的效率提升将被弱化。
为了至少部分地解决已有技术方案的上述以及其他缺陷,根据本公开的一个示例性实现方式,提供了一种并行执行Kernel的技术方案。在本方案中,通过访问寄存器空间中的共享空间和第一私有空间,执行第一Kernel。响应于第一Kernel的执行被阻塞,通过访 问寄存器空间中的第二私有空间,执行不同于第一Kernel的第二Kernel,共享空间、第一私有空间和第二私有空间彼此分离。以及,响应于第一Kernel的执行已经完成,通过访问共享空间和第二私有空间,继续执行第二Kernel。
以此方式,通过在并行执行Kernel时将PE的计算资源和存储资源优先分配给其中一个优先Kernel(也称为主Kernel),可以提高PE执行单个Kernel的效率。此外,通过在前一个Kernel执行完毕后,将后一个Kernel调整为优先Kernel,可以在总体上提高PE并行执行Kernel的效率。
下文将参考图3至图5来详细描述本方案的细节。
首先参考图3来描述PE的概要。图3示出了根据本公开的一个实施方式的PE 300的示意框图。PE 300可以被实现图2中所示的处理引擎PE_1、PE_2……PE_N。
如图3所示,PE 300可以包括多个线程,例如线程310、线程320和线程330。可以在PE处启动一个或多个线程。每个线程可以具有自己的寄存器空间和执行单元。例如,线程310可以具有寄存器空间311和执行单元312。线程320可以具有寄存器空间321和执行单元322。线程330可以具有寄存器空间331和执行单元332。
寄存器空间(例如,寄存器空间311、321和331)可以指代包括多个寄存器的存储空间。每个寄存器空间可以使用自己的存储地址,例如可以采用典型的寄存器存取架构(load-store architecture)。
执行单元(例如,执行单元312、322和332)可以包括一个支持多种数据类型的浮点/定点单元以及一个算术逻辑单元,以用于执行算术和逻辑运算。算术运算例如浮点和定点数的加、减、乘、除。逻辑运算例如逻辑与、或、非等。
如图3所示,PE 300还可以包括控制器350(也称为调度器或指令发射器)。控制器350用于调度不同Kernel的指令以及向PE 300中的多个线程发送指令。一般地,PE 300中的所有执行单元同步执行一样的指令。此外,通过使用谓词(predicate)寄存器,可以屏蔽部 分执行单元,从而实现分支指令的功能。
指令的示例可以包括存取指令和运算指令。例如,存储器读写指令可以提供寄存器空间与片上/片外存储器之间的数据交换。运算指令可以使执行单元进行相应的运算。执行单元所使用的操作数可以来自相应的寄存器空间。
应理解,图3所示的PE 300仅是示例性的,而不构成对本公开的范围的限制。例如,PE还可以包括其他单元,例如由PE的多个线程共享的统一寄存器堆。
下文将参考图4来描述寄存器空间的概要。图4示出了根据本公开的一个实施方式的寄存器空间400的示意框图。寄存器空间400可以被实现图3中所示的寄存器空间311、321和331。
如图4所示,寄存器空间400可以被划分为彼此分离的共享空间(例如共享空间410)和私有空间(例如,第一私有空间420和第二私有空间430)。私有空间还可以被划分为多个私有空间以分配给并行执行的多个Kernel。
根据本公开的一个示例性实现方式,私有空间的数目可以对应于预先确定的并行执行的Kernel的数目。例如,PE 300可以被预先确定并行执行两个活跃的Kernel。在这种情况下,可以将寄存器空间400的私有空间划分为两个私有空间。备选地,PE 300可以并行执行三个活跃的Kernel。在这种情况下,可以将寄存器空间400的私有空间划分为三个私有空间。
根据本公开的一个示例性实现方式,共享空间410的大小可以大于每个私有空间(例如,第一私有空间420和第三私有空间430)的大小。例如,共享空间410可以包括多于200个寄存器,而私有空间(例如,第一私有空间320或第二私有空间430)可以包括16个寄存器。
根据本公开的一个示例性实现方式,每个私有空间的大小可以相等。例如,第一私有空间420和第三私有空间430可以分别包括16个寄存器。备选地,共享空间410和私有空间的大小可以根据具 体应用而设置。
在下文中,将参考图3至图5描述根据本方案的更多细节。图5示出了根据本公开的一个实施方式的并行执行Kernel的方法500的流程图。方法500可以在PE 300处实现。此外,方法500中的一些步骤可以在PE 300中的每个线程处实现。仅出于方便描述的目的,下文将参考线程310来描述方法500的细节。
在框502处,通过访问寄存器空间311中的共享空间410和第一私有空间420,执行第一Kernel。共享空间410和第一私有空间420可以存储与第一Kernel的执行有关的指令和数据。PE 300可以通过访问共享空间410和第一私有空间420来执行第一Kernel,并将执行所产生的临时数据存储在共享空间410和第一私有空间420中。
如上所述,PE 300可以从SP 210接收待执行的至少一个Kernel。应理解,SP 210从主机设备接收的待执行的多个Kernel是经排序的,并且顺序可以与多个Kernel之间的依赖关系有关。因此,PE 300从SP 210接收的待执行的至少一个Kernel也是经排序的。
取决于设置,PE 300可以并行执行所接收的Kernel中的多个Kernel。例如,PE 300可以首先并行执行所接收的Kernel中的两个Kernel。所接收的Kernel中的剩余Kernel可以在前两个Kernel执行完毕后被执行。
根据本公开的一个示例性实现方式,可以按照严格的先进先出顺序来执行Kernel。换言之,PE 300可以先执行从SP 210先接收到的Kernel(也即,PE 300所接收的待执行Kernel中排序靠前的Kernel)而后执行后接收到的Kernel。在这种实现方式中,第一Kernel可以是并行执行的一组Kernel中PE 300先接收到的Kernel。
在框504处,响应于第一Kernel的执行被阻塞,通过访问寄存器空间400中的第二私有空间430,执行不同于第一Kernel的第二Kernel。第一Kernel的执行可以因为多种原因而被阻塞。例如,第一Kernel的执行所需的数据尚未被存入寄存器空间311中。又例如, 第一Kernel的执行需要等待某个事件的发生才可以继续。
当第一Kernel的执行被阻塞时,与第一Kernel对应的共享空间410和第一私有空间420中存储有与第一Kernel的执行有关的临时数据。当第一Kernel的执行不再被阻塞时,PE 300可以基于共享空间410和第一私有空间420中所存储的临时数据而继续执行第一Kernel。
响应于第一Kernel的执行被阻塞,PE 300可以将线程310的计算资源(也即,执行单元312)用于执行第二Kernel。第二Kernel可以是与第一Kernel并行执行的Kernel。
PE 300可以通过访问寄存器空间400中的第二私有空间430来执行第二Kernel。第二私有空间430可以存储与第二Kernel的执行有关的指令和数据。PE 300可以基于第二私有空间430中的指令和数据来执行第二Kernel,并将执行所产生的临时数据存储在第二私有空间430中。
根据本公开的一个示例性实现方式,响应于第一Kernel的执行被阻塞,也即第一Kernel的某个指令的执行被阻塞),可以由PE 300中的控制器350来检查第二Kernel的待执行指令是否需要访问共享空间410。控制器350可以根据程序员在程序中的定义来确定第二Kernel的待执行指令是否需要访问共享空间410。
例如,对于需要较少寄存器空间的简单指令,PE 300可以通过仅访问第二私有空间430来执行该指令而不需要访问共享空间410。在这种情况下,响应于待执行指令不需要访问共享空间410,PE 300可以执行第二Kernel的待执行指令。PE 300可以通过访问第二私有空间430来进行一些简单的工作,以为第二私有空间430的后续执行做准备。
相反,对于需要较多寄存器空间的复杂指令,PE 300可能需要访问第二私有空间430以及附加的寄存器空间才能执行该指令。然而,由于共享空间410中存储有与第一Kernel的指令有关的数据并且第一Kernel的执行尚未完成,因此当控制器350确定第二Kernel 的待执行指令需要访问共享空间410才能被执行时,控制器350将不会执行该指令。在这种情况下,控制器350可以重新选择待执行的下一个指令。例如,控制器350可以选择等待第一Kernel的指令从阻塞状态恢复到可执行状态。
根据本公开的一个示例性实现方式,响应于第二Kernel的待执行指令的执行已经完成,可以由PE 300中的控制器350检查第一Kernel的被阻塞的指令是否已经恢复到可执行状态。响应于第一Kernel的被阻塞的指令已经恢复到可执行状态,PE 300可以通过访问共享空间410和第一私有空间420来继续执行该指令。
换言之,在第二Kernel的待执行指令的执行已经完成时,PE 300可以不继续执行第二Kernel的指令,而是由控制器350重新确定下一个待执行的指令。并且,在确定下一个待执行的指令时优先选择执行第一Kernel的指令。以此方式,PE 300可以同时将线程310的计算资源和存储资源优先分配给第一Kernel,使得第一Kernel的执行效率得到较大提升。
在框506处,响应于第一Kernel的执行已经完成,通过访问共享空间410和第二私有空间420,继续执行第二Kernel。当第一Kernel的执行已经完成时,PE 300可以将第二Kernel作为主Kernel来继续执行第二Kernel,同时将所接收的另一个Kernel(下文称为第三Kernel)作为与第二Kernel并行执行的Kernel。
基于第二Kernel是目前的主Kernel,PE 300可以将线程310的计算资源和存储资源优先分配给第二Kernel。PE 300可以通过访问共享空间410和第二私有空间420来继续执行第二Kernel。
如上所述,在PE 300执行第一Kernel时,共享空间410和第一私有空间420中存储有与第一Kernel的执行有关的指令和数据。因此,在第一Kernel的执行完成时,共享空间410中存储有与第一Kernel的执行有关的数据,例如运算结果。
根据本公开的一个示例性实现方式,可以在第一Kernel的执行完成时重置共享空间410的状态,也即,清除共享空间410中与第 一Kernel有关的数据。以此方式,PE 300可以通过访问经重置的共享空间410和第二私有空间420来继续执行第二Kernel。
根据本公开的一个示例性实现方式,在第一Kernel的执行完成时可以不重置共享空间410的状态,也即可以维持第一Kernel的执行完成时的共享空间410的状态。例如,可以基于第一Kernel的、指示共享空间410可继承的属性,在第一Kernel的执行完成时不重置共享空间410的状态。属性可以由程序员在程序中指定。备选地,属性可以指示在Kernel执行的开始、结束、或开始和结束时重置对应的寄存器空间400。
在这种实现方式下,PE 300可以基于第一Kernel的执行完成时的共享空间410的状态来继续执行第二Kernel。根据本公开的一个示例性实现方式,第一Kernel的执行完成时的共享空间410的状态可以指示由第一Kernel指定的第一算子的结果。因此,PE 300可以基于第一算子的结果,执行由第二Kernel指定的第二算子以及将第二算子的结果写入寄存器空间311外部的存储器,例如,L1高速缓存260和L2高速缓存250。
应理解,在此实现方式中,第一Kernel和第二Kernel之间存在依赖关系。也即,由第二Kernel指定的第二算子需要使用由第一Kernel指定的第一算子的运算结果。此外还应理解,如果第二算子的运算结果可以被其他Kernel使用,则可以继续维持第二Kernel执行完成时的共享空间410的状态,而不将第二算子的结果写入外部的存储器。这样,可以将第二算子的运算结果继续传递给其他Kernel。
以此方式,可以利用共享空间410的继承来将第一Kernel的运算结果直接传递给第二Kernel,而无需经历将运算结果写入存储器以及从存储器读取运算结果的过程,从而减少对外部存储器的读取。
下文将描述这种实现方式在人工智能领域的示例实现。可以将人工智能模型在硬件上的计算过程抽象为计算图。图中的节点可以表示对变量执行的操作(也称为算子),例如矩阵乘(MatMul)、加偏置(Add)、求激活值(Sigmoid)等。每个操作可以用相应的 Kernel实现。
目前,可以通过将多个节点合并成单个节点来对计算图进行优化。通过合并节点(也即,融合Kernel),可以利用单个Kernel来执行多个操作,从而节省大量的存储数据流并提高计算的效率。然而,融合Kernel一方面需要改变图本身,另一方面需要做大量的静态整合工作。
根据本公开的一个示例性实现方式,可以利用共享区间410来传递数据。以上述讨论的第一Kernel和第二Kernel为例,由于第二Kernel的执行可以访问第一Kernel执行完成后的共享区间410(假设未重置),因此第二Kernel可以直接使用第一Kernel遗留在共享区间410中的计算结果,从而节省大量的存储数据流并提高计算的效率。
根据本公开的一个示例性实现方式,类似于第一Kernel和第二Kernel的并行执行,响应于第二Kernel的继续执行被阻塞,PE 300可以通过访问第一私有空间420执行第三Kernel。应注意,在第一Kernel的执行完成时,尽管存储与第一Kernel的执行有关的数据的共享空间410可以不被重置,存储与第一Kernel的执行有关的数据的第一私有空间将被重置。以此方式,可以释放线程310中的存储资源以供第三Kernel使用。
类似地,响应于第二Kernel的继续执行已经完成,PE 300可以通过访问共享空间410和第一私有空间420,继续执行第三Kernel。换言之,在第二Kernel的继续执行已经完成时,第三Kernel可以作为新的主Kernel而被执行,同时PE 300可以将线程310的计算资源和存储资源优先分配给第三Kernel。
应理解,上文仅以第一Kernel、第二Kernel和第三Kernel为示例描述了如何并行执行Kernel,而非限制了并行执行的Kernel的数目。根据本方案,通过在并行执行Kernel时将计算资源和存储资源优先分配给主Kernel,可以提高执行单个Kernel的效率。此外,通过在前一个Kernel执行完毕后,将后一个Kernel调整为主Kernel, 可以在总体上提高并行执行Kernel的效率。
图6示出了根据本公开的一个实施方式的用于并行执行核心程序的装置600的示意框图。装置600可以被实现为或者被包括在图2的加速器系统200中。装置600可以包括多个单元,以用于执行如图5中所讨论的方法500中的对应步骤。
如图6所示,装置600包括:第一并行执行单元610,被配置用于通过访问所述装置的寄存器空间中的共享空间和第一私有空间,执行第一核心程序;第二并行执行单元620,被配置用于响应于所述第一核心程序的执行被阻塞,通过访问所述寄存器空间中的第二私有空间,执行不同于所述第一核心程序的第二核心程序,所述共享空间、所述第一私有空间和所述第二私有空间彼此分离;以及第三并行执行单元630,被配置用于响应于所述第一核心程序的执行已经完成,通过访问所述共享空间和所述第二私有空间,继续执行所述第二核心程序。
根据本公开的一个示例性实现方式,第二并行执行单元620包括:第一检查单元,被配置为:响应于所述第一核心程序的第一指令的执行被阻塞,检查所述第二核心程序的待执行指令是否需要访问所述共享空间;以及第一指令执行单元,被配置为:响应于所述待执行指令不需要访问所述共享空间,执行所述第二核心程序的所述待执行指令。
根据本公开的一个示例性实现方式,装置600还包括:第二检查单元,被配置为:响应于所述待执行指令的执行已经完成,检查所述第一指令的执行是否不再被阻塞;以及第二指令执行单元,被配置为:响应于所述第一指令的执行不再被阻塞,通过访问所述共享空间和所述第一私有空间,继续执行所述第一指令。
根据本公开的一个示例性实现方式,第三并行执行单元630包括:状态维持单元,被配置为:维持所述第一核心程序的执行完成时的所述共享空间的状态;以及第四并行执行单元,被配置为:基于所述第一核心程序的执行完成时的所述共享空间的状态来继续执 行所述第二核心程序。
根据本公开的一个示例性实现方式,其中状态维持单元包括:第一重置单元,被配置为:基于所述第一核心程序的、指示共享空间可继承的属性,在所述第一核心程序的执行完成时不重置所述共享空间的状态。
根据本公开的一个示例性实现方式,其中所述第一核心程序的执行完成时的所述共享空间的状态指示由所述第一核心程序指定的第一算子的结果,并且所述第四并行执行单元包括:运算单元,被配置为:基于所述第一算子的结果,执行由所述第二核心程序指定的第二算子;以及写入单元,被配置为:将所述第二算子的结果写入所述寄存器空间外部的存储器。
根据本公开的一个示例性实现方式,所述第一核心程序在所述第二核心程序之前被接收。
根据本公开的一个示例性实现方式,装置还包括:第五并行执行单元,被配置为:响应于所述第二核心程序的所述继续执行被阻塞,通过访问所述第一私有空间执行第三核心程序,所述第三核心程序不同于所述第一核心程序和所述第二核心程序;以及第六并行执行单元,被配置为:响应于所述第二核心程序的所述继续执行已经完成,通过访问所述共享空间和所述第一私有空间,继续执行所述第三核心程序。
根据本公开的一个示例性实现方式,所述第五并行执行单元包括:第二重置单元,被配置为:重置所述第一核心程序的执行完成时的所述第一私有空间的状态。
根据本公开的一个示例性实现方式,所述共享空间大于所述第一私有空间和所述第二私有空间。
根据本公开的一个示例性实现方式,提供了一种计算机可读存储介质。该介质存储多个程序,多个程序被配置为一个或多个处理引擎执行,多个程序包括用于执行上文描述的方法的指令。
根据本公开的一个示例性实现方式,提供了一种计算机程序产 品。该计算机程序产品包括多个程序,多个程序被配置为一个或多个处理引擎执行,多个程序包括用于执行上文描述的方法的指令。
根据本公开的一个示例性实现方式,提供了加速器系统。该加速器系统包括:处理器;以及与所述处理器耦合的存储器,所述存储器具有存储于其中的指令,所述指令在被所述处理器执行时使得所述设备执行上文描述的方法。
本公开可以是方法、设备、系统和/或计算机程序产品。计算机程序产品可以包括计算机可读存储介质,其上载有用于执行本公开的各个方面的计算机可读程序指令。
此外,虽然采用特定次序描绘了各操作,但是这应当理解为要求这样操作以所示出的特定次序或以顺序次序执行,或者要求所有图示的操作应被执行以取得期望的结果。在一定环境下,多任务和并行处理可能是有利的。同样地,虽然在上面论述中包含了若干具体实现细节,但是这些不应当被解释为对本公开的范围的限制。在单独的实施方式的上下文中描述的某些特征还可以组合地实现在单个实现中。相反地,在单个实现的上下文中描述的各种特征也可以单独地或以任何合适的子组合的方式实现在多个实现中。
尽管已经采用特定于结构特征和/或方法逻辑动作的语言描述了本主题,但是应当理解所附权利要求书中所限定的主题未必局限于上面描述的特定特征或动作。相反,上面所描述的特定特征和动作仅仅是实现权利要求书的示例形式。
Claims (22)
- 一种并行执行核心程序的方法,包括:通过访问寄存器空间中的共享空间和第一私有空间,执行第一核心程序;响应于所述第一核心程序的执行被阻塞,通过访问所述寄存器空间中的第二私有空间,执行不同于所述第一核心程序的第二核心程序,所述共享空间、所述第一私有空间和所述第二私有空间彼此分离;以及响应于所述第一核心程序的执行已经完成,通过访问所述共享空间和所述第二私有空间,继续执行所述第二核心程序。
- 根据权利要求1所述的方法,其中执行所述第二核心程序包括:响应于所述第一核心程序的第一指令的执行被阻塞,检查所述第二核心程序的待执行指令是否需要访问所述共享空间;以及响应于所述待执行指令不需要访问所述共享空间,执行所述第二核心程序的所述待执行指令。
- 根据权利要求2所述的方法,还包括:响应于所述待执行指令的执行已经完成,检查所述第一指令的执行是否不再被阻塞;以及响应于所述第一指令的执行不再被阻塞,通过访问所述共享空间和所述第一私有空间,继续执行所述第一指令。
- 根据权利要求1所述的方法,其中继续执行所述第二核心程序包括:维持所述第一核心程序的执行完成时的所述共享空间的状态;以及基于所述第一核心程序的执行完成时的所述共享空间的状态来继续执行所述第二核心程序。
- 根据权利要求4所述的方法,其中维持所述第一核心程序的 执行完成时的所述共享空间的状态包括:基于所述第一核心程序的、指示共享空间可继承的属性,在所述第一核心程序的执行完成时不重置所述共享空间的状态。
- 根据权利要求4所述的方法,其中所述第一核心程序的执行完成时的所述共享空间的状态指示由所述第一核心程序指定的第一算子的结果,并且继续执行所述第二核心程序包括:基于所述第一算子的结果,执行由所述第二核心程序指定的第二算子;以及将所述第二算子的结果写入所述寄存器空间外部的存储器。
- 根据权利要求1所述的方法,其中所述第一核心程序在所述第二核心程序之前被接收。
- 根据权利要求1所述的方法,还包括:响应于所述第二核心程序的所述继续执行被阻塞,通过访问所述第一私有空间执行第三核心程序,所述第三核心程序不同于所述第一核心程序和所述第二核心程序;以及响应于所述第二核心程序的所述继续执行已经完成,通过访问所述共享空间和所述第一私有空间,继续执行所述第三核心程序。
- 根据权利要求8所述的方法,其中通过访问所述第一私有空间执行第三核心程序包括:重置所述第一核心程序的执行完成时的所述第一私有空间的状态。
- 根据权利要求1所述的方法,其中所述共享空间大于所述第一私有空间和所述第二私有空间。
- 一种用于并行执行核心程序的装置,包括:第一并行执行单元,被配置为:通过访问所述装置的寄存器空间中的共享空间和第一私有空间,执行第一核心程序;第二并行执行单元,被配置为:响应于所述第一核心程序的执行被阻塞,通过访问所述寄存器空间中的第二私有空间,执行不同于所述第一核心程序的第二核心程序,所述共享空间、所述第一私 有空间和所述第二私有空间彼此分离;以及第三并行执行单元,被配置为:响应于所述第一核心程序的执行已经完成,通过访问所述共享空间和所述第二私有空间,继续执行所述第二核心程序。
- 根据权利要求11所述的装置,其中所述第二并行执行单元包括:第一检查单元,被配置为:响应于所述第一核心程序的第一指令的执行被阻塞,检查所述第二核心程序的待执行指令是否需要访问所述共享空间;以及第一指令执行单元,被配置为:响应于所述待执行指令不需要访问所述共享空间,执行所述第二核心程序的所述待执行指令。
- 根据权利要求12所述的装置,还包括:第二检查单元,被配置为:响应于所述待执行指令的执行已经完成,检查所述第一指令的执行是否不再被阻塞;以及第二指令执行单元,被配置为:响应于所述第一指令的执行不再被阻塞,通过访问所述共享空间和所述第一私有空间,继续执行所述第一指令。
- 根据权利要求11所述的装置,其中所述第三并行执行单元包括:状态维持单元,被配置为:维持所述第一核心程序的执行完成时的所述共享空间的状态;以及第四并行执行单元,被配置为:基于所述第一核心程序的执行完成时的所述共享空间的状态来继续执行所述第二核心程序。
- 根据权利要求14所述的装置,其中所述状态维持单元包括:第一重置单元,被配置为:基于所述第一核心程序的、指示共享空间可继承的属性,在所述第一核心程序的执行完成时不重置所述共享空间的状态。
- 根据权利要求14所述的装置,其中所述第一核心程序的执行完成时的所述共享空间的状态指示由所述第一核心程序指定的第 一算子的结果,并且所述第四并行执行单元包括:运算单元,被配置为:基于所述第一算子的结果,执行由所述第二核心程序指定的第二算子;以及写入单元,被配置为:将所述第二算子的结果写入所述寄存器空间外部的存储器。
- 根据权利要求11所述的装置,其中所述第一核心程序在所述第二核心程序之前被接收。
- 根据权利要求11所述的装置,还包括:第五并行执行单元,被配置为:响应于所述第二核心程序的所述继续执行被阻塞,通过访问所述第一私有空间执行第三核心程序,所述第三核心程序不同于所述第一核心程序和所述第二核心程序;以及第六并行执行单元,被配置为:响应于所述第二核心程序的所述继续执行已经完成,通过访问所述共享空间和所述第一私有空间,继续执行所述第三核心程序。
- 根据权利要求18所述的装置,其中所述第五并行执行单元包括:第二重置单元,被配置为:重置所述第一核心程序的执行完成时的所述第一私有空间的状态。
- 根据权利要求11所述的装置,其中所述共享空间大于所述第一私有空间和所述第二私有空间。
- 一种计算机可读存储介质,存储多个程序,所述多个程序被配置为由一个或多个处理引擎执行,所述多个程序包括用于执行权利要求1-10中任一项所述的方法的指令。
- 一种计算机程序产品,所述计算机程序产品包括多个程序,所述多个程序被配置为由一个或多个处理引擎执行,所述多个程序包括用于执行权利要求1-10中任一项所述的方法的指令。
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