WO2023075791A1 - Port d'affichage à commutation connecté à un afficheur externe entre des processeurs graphiques distinct et intégré - Google Patents

Port d'affichage à commutation connecté à un afficheur externe entre des processeurs graphiques distinct et intégré Download PDF

Info

Publication number
WO2023075791A1
WO2023075791A1 PCT/US2021/057334 US2021057334W WO2023075791A1 WO 2023075791 A1 WO2023075791 A1 WO 2023075791A1 US 2021057334 W US2021057334 W US 2021057334W WO 2023075791 A1 WO2023075791 A1 WO 2023075791A1
Authority
WO
WIPO (PCT)
Prior art keywords
computing device
graphics processor
graphics
performance mode
discrete
Prior art date
Application number
PCT/US2021/057334
Other languages
English (en)
Inventor
Chia-Cheng Lin
Thong Thai
Tsue-Yi HUANG
Original Assignee
Hewlett-Packard Development Company, L.P.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett-Packard Development Company, L.P. filed Critical Hewlett-Packard Development Company, L.P.
Priority to PCT/US2021/057334 priority Critical patent/WO2023075791A1/fr
Publication of WO2023075791A1 publication Critical patent/WO2023075791A1/fr

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • Computing devices such as desktop, laptop, notebook, and all-in- one (AIO) computers, can include integrated graphics processors and/or dedicated graphics processors to drive internal and/or external displays.
  • Integrated graphics processors can also be referred to as integrated graphics processing units (iGPUs), or simply as integrated or internal graphics.
  • iGPUs integrated graphics processing units
  • An iGPU is built into the same silicon chip as the central or main processor of a computing device, and shares the same memory as this processor.
  • An iGPU typically uses less power and generates less heat than a discrete graphics processor, which can result in longer battery life in the case of portable computers like laptop and notebook computers, but usually at the cost of worse performance.
  • Discrete graphics processors can also be referred to as dedicated graphics processors, discrete graphics processing units (dGPUs), or simply as discrete or dedicate graphics.
  • a dGPU has a processor separate from the central or main processor of a computing device, and has its own dedicated memory that it does not share with the central or main processor.
  • a dGPU may be implemented as a separate silicon chip on the same logic board of a computer as the central or main processor, or may be implemented on a separate logic board that is plugged in as a graphics card into a corresponding card slot of the computer.
  • a dGPU typically uses more power and generates more heat than an integrated graphics processor, but usually provides better performance.
  • FIG. 1 is a diagram of an example computing device having both integrated and discrete graphics processors that can drive an internal display and an external display connected to a display port of the computing device.
  • FIG. 2 is a diagram of the example computing device of FIG. 1 in detail, depicting how the display port can be switchably connected between the discrete graphics processor and the integrated graphics processor.
  • FIG. 3 is a flowchart of an example method for switching the display port of the computing device of FIG. 2 between the discrete graphics processor and the integrated graphics processor depending on whether the computing device is to operate in a high graphics performance mode or a low graphics performance mode.
  • FIG. 4 is a flowchart of an example method for determining whether to operate the computing device of FIG. 2 in a high graphics performance mode or a low graphics performance mode, and which can be used in conjunction with the method of FIG. 3.
  • FIG. 5 is a diagram of an example non-transitory computer- readable data storage medium storing program code executable by a computing device.
  • a computing device such as a computer can include both an integrated graphics processor and a dedicated graphics processor.
  • a computer such as a laptop or notebook computer or an all-in-one (AIO) computers includes an internal display, which may be driven by the integrated graphics processor or the dedicated graphics processor.
  • a computer having an internal display may also have a display port to which an external display can be connected.
  • the dedicated graphics processor may drive the display. This can be the case regardless of whether a currently run application would benefit from the higher graphics performance afforded by the dedicated graphics processor. Therefore, the computer may unnecessarily run hotter, consume more power, and create more fan noise than if the integrated graphics processor were used to drive the external display.
  • Techniques described herein provide for switching a display port connected to an external display between discrete and integrated graphics processors. If the computing device is to operate in a high graphics performance mode, the discrete graphics processor is turned on and the display port is switched to the discrete graphics processor. By comparison, if the computing device is to operate in a low graphics performance mode, the display port is switched to the integrated graphics processor and the discrete graphics processor is turned off.
  • the graphics performance of a computing device is better than in the low graphics performance mode.
  • the graphics performance of the computing device is worse than in the high graphics performance mode.
  • the graphics performance of the computing device can be measured using a variety of different parameters.
  • the number of frames per second (fps) that a graphics processor can render can be indicative of graphics performance.
  • the frame rate that a graphics processor is capable of rendering may be dependent upon the number of triangles or vertices that can be calculated per second and the pixel fill rate in which a frame can be rasterized.
  • Graphics performance can also or instead be indicated by whether a graphics processor is able to provide for certain graphics-oriented features, such as full scene anti-aliasing (FSAA), anisotropic filtering (AF), and real-time physics and particle effects.
  • FSAA full scene anti-aliasing
  • AF anisotropic filtering
  • real-time physics and particle effects real-time physics and particle effects.
  • FIG. 1 shows an example computing device 100.
  • the computing device 100 includes an internal display 102, an integrated graphics processor 104, a discrete graphics processor 106, and a display port 108 that is communicatively connected to an external display 110 of an external device 112.
  • the computing device 100 can include other hardware components as well, such as one or multiple main or central processors, semiconductor memory such as dynamic random-access memory (DRAM), and storage devices like hard disk drives and solid-state drives (SSDs), among other types of hardware components. Whereas one display port 108 is depicted in the example, the computing device 100 may have multiple display ports 108 for communicative connection to the same or different external displays 110.
  • DRAM dynamic random-access memory
  • SSDs solid-state drives
  • the computing device 100 may be a computer, such as a portable computer like a laptop or notebook computer that can operate either on battery power or by being plugged into an external power source such as a wall outlet.
  • the internal display 102 is integrated within the same housing or case as the aforementioned hardware components, as well as other hardware components including input devices like a keyboard and a touchpad.
  • the computer may instead be an AIO device, which is a type of desktop computer in which the aforementioned hardware components and other hardware components, besides input devices like a keyboard and a pointing device such as a mouse or a touchpad, are integrated within the same housing or case as the internal display 102.
  • the internal display 102 may be a flat-panel display (FPD), such as a liquid crystal display (LCD), an organic light-emitting diode (OLED) display, or another type of display.
  • the integrated graphics processor 104 may be integrated within the same semiconductor chip as the main or central processor of the computing device 100, and shares the same memory as the main or central processor.
  • the discrete graphics processor 106 may include a processor separate from the main or central processor, which accesses dedicated memory separate from the memory used by the main or central processor, and which is integrated within a different semiconductor chip than the main or central processor.
  • the integrated graphics processor 104 may drive the internal display 102, either by default or exclusively.
  • the integrated graphics processor 104 driving the internal display 102 means that the processor 104 is responsible for rendering the images displayed on the display 102.
  • the discrete graphics processor 106 may also drive the display 102.
  • the discrete graphics processor 106 driving the internal display 102 means that the processor 106 is responsible for rendering the images displayed on the display 102.
  • the display port 108 may be one of a variety of different display ports, such as a DisplayPort (DP) port, a High-Definition Multimedia Interface (HDMI) port, or a Universal Serial Bus (USB)-C or Thunderbolt port that can transfer DP signals in a DP Alt Mode and thus can be referred to as a USB-C DisplayPort.
  • the external display 110 is communicatively connected to the display port 108 via a corresponding port of the device 112 of which the external display 110 is a part.
  • the device 112 may be an external monitor having a housing or case separate from the housing or case of the computing device 100.
  • a cable may be used to directly or indirectly connect the display port 108 to the corresponding port of the device 112.
  • both the integrated graphics processor 104 and the discrete graphics processor 106 of the computing device 100 are capable of driving the external display 110.
  • the graphics processor 104 or 106 driving the external display 110 means that the processor 104 or 106 is responsible for rendering the images displayed on the display 110.
  • the graphics processor 104 is switchably connected to the display port 108.
  • the discrete graphics processor 106 is to drive the external display 110, the graphics processor 106 is switchably connected to the display port 108.
  • FIG. 2 shows the computing device 100 in example detail.
  • the computing device 100 is depicted in FIG. 2 as including the integrated graphics processor 104, the discrete graphics processor 106, and the display port 108.
  • the internal display 102 and the external display 110 that is part of the external device 112 of FIG. 1 are not depicted in FIG. 2 for illustrative clarity and convenience.
  • the computing device 100 includes firmware 202, which may be in the form of a basic input/output system (BIOS).
  • the firmware 202 refers to hardware or hardware and instructions to initialize, control, or operate the computing device 100, including prior to execution of an operating system 210 of the computing device 100.
  • Instructions included within the firmware 202 may be software, firmware, microcode, or other programming that defines or controls functionality or operation of the firmware 202.
  • the firmware 202 may be implemented using instructions, such as platform firmware of the computing device 100, executable by a processor 204.
  • the firmware 202 may initialize, control, or operate components such as hardware components of the computing device 100, and may load or boot the operating system 210 of the computing device 100.
  • the firmware 202 may provide or establish an interface between the hardware devices or platform firmware of the computing device 100 and the operating system 210 of the computing device 100.
  • the operating system 210 may control or operate the hardware devices or platform firmware via this interface.
  • the firmware 202 may implement the Unified Extensible Firmware Interface (UEFI) specification or another specification or standard for initializing, controlling, or operating the computing device 100.
  • UEFI Unified Extensible Firmware Interface
  • the computing device 100 includes the processor 204, which can be the main or central processor of the computing device 100. There may be more than one processor 204, and each processor 204 may include multiple processing cores.
  • the computing device 100 includes memory 206, such as dynamic random-access memory (DRAM) or another type of volatile memory, and which may be integrated with the processor 204 as a system on chip (SoC) or may be one or multiple semiconductor chips separate from the processor 204.
  • the memory 206 may be on the same logic board as the processor 204, or may be on a separate logic board, such as in the form of memory modules such as dual inline memory modules (DIMMs), which are inserted into corresponding memory slots or sockets on the logic board.
  • DIMMs dual inline memory modules
  • the memory 206 stores program code 208 executable by the processor 204.
  • the program code 208 includes the operating system 210.
  • the operating system 210 is system software that manages computer hardware and software resources, and provides common drivers, including a graphics driver 212, and services for computer programs such as the application 214.
  • a device driver is a computer program that operates or controls a particular type of device that is attached to or that is part of the computing device 100, and provides abstraction by acting as a translator between a hardware device and the operating system 210 and the application 214.
  • the graphics driver 212 is specifically a device driver for the integrated graphics processor 104 and the discrete graphics processor 106.
  • the application 214 runs in the context of the operating system 210. Whereas one such application 214 is depicted, in actuality there can be multiple applications 214 that can each be loaded from an internal or external non-volatile storage device, such as a hard disk drive or an SSD, into the memory 206 for execution.
  • the application 214 may also be referred to an application program, and is a computer program designed to carry out a specific task other than one relating to the operation of the computing device 100 itself. Examples of applications 214 include word processors, media players, and accounting software.
  • Software that runs on the computing device 100 can thus be classified as application software, system software such as the operating system 210 and the graphics driver 212, and utility software, or utilities, which are designed to help analyze, configure, optimize, or maintain the computing device
  • the computing device 100 includes circuitry 216.
  • the circuitry 216 is a type of hardware, and can be or include a chipset of the computing device.
  • the chipset is a set of electronic components that manages the data flow among the processor 204, the memory 206, and peripheral devices such as the external display 110, data flow to and from the latter occurs via the graphics processor 104 or 106.
  • the circuitry 216 may be in the form of a single-chip chipset, such as a Platform Controller Hub (PCH).
  • PCH Platform Controller Hub
  • the circuitry 216 includes two or more than two registers, including an interrupt register 218 and a select register 220, information regarding which is provided later in the detailed description.
  • the computing device 100 includes a multiplexer 222, which is more generally a switch.
  • the multiplexer 222 or mux, switchably connects the integrated graphics processor 104 and the discrete graphics processor 106 to the display port 108 and thus to the external display 110.
  • the multiplexer 222 has a first input line 224 connected to the integrated graphics processor 104, a second input line 226 connected to the discrete graphics processor 106, and an output line 228 connected to the display port 108 and thus to the external display 110.
  • the multiplexer 222 has a select line 230 that governs whether the first input line 224 is connected to the output line 228 or whether the second input line 226 is connected to the output line 228.
  • the select line 230 therefore governs whether the integrated graphics processor 104 or the discrete graphics processor 104 is connected to the display port 108 and thus to the external display 110.
  • the circuitry 216 controls the multiplexer 222 via connection to the input lines 224 and 226 and the select line 230. If the select register 220 is set to a first value, then the circuitry 216 specifies via the select line 230 that the multiplexer 222 is to connect the first input line 224 to the output line 228. Similarly, if the select register 220 is set to a second value, then the circuitry 216 specifies via the select line 230 that the multiplexer 222 is to connect the second input line 226 to the output line 228.
  • the firmware 202 may write the first value or the second value to the select register 220 so that the integrated graphics processor 104 or the discrete graphics processor 106 is connected to the display port 108 and thus drives the external display 110.
  • the circuitry 216 further controls connection of the graphics processors 104 and 106 to their respective input lines 224 and 226 of the multiplexer 222. If the interrupt register 218 undergoes a first transition, such as from high (i.e., logic one) to low (i.e., logic zero), then the circuitry 216 may disconnect the graphics processors 104 and 106 from their respective input lines 224 and 226. If the interrupt register 218 undergoes a second transition, such as from low to high, then the circuitry 216 may reconnect the graphics processors 104 and 106 to their respective input lines 224 and 226.
  • a first transition such as from high (i.e., logic one) to low (i.e., logic zero)
  • the circuitry 216 may reconnect the graphics processors 104 and 106 to their respective input lines 224 and 226.
  • the firmware 202 may issue a corresponding interrupt to cause the interrupt register 218 to transition from high to low to simulate disconnection of the external display 110 from the computing device 100 or to cause the register 218 to transition from low to high to simulate reconnection of the display 110 to the device 100.
  • the external display 110 is not actually physically disconnected from the display port 108, but because neither graphics processor 104 or 106 is connected to the display port 108 (since neither is connected to its corresponding input line 224 or 226), the display 110 is in effect disconnected from the computing device 100.
  • the external display 110 is not physically reconnected to the display port 108 (since it is already connected to the port 108), but because either graphics processor 104 or 106 is again connected to the display port 108 (since both are again connected to their corresponding input lines 224 and 226), the display 110 is in effect reconnected to the computing device 100.
  • FIG. 3 shows an example method 300 for switching the display port 108 between the integrated graphics processor 104 and the discrete graphics processor 106 depending on whether the computing device 100 is to operate in a high graphics performance mode or a low graphics performance mode.
  • the method 300 is performed so long as an external display 110 is connected to the display port 108.
  • the method 300 may be implemented as program code stored on a non-transitory computer-readable data storage medium and executable by a processor such as the processor 204.
  • the program code may include the program code 208 implementing the operating system 210 and the graphics driver 212, as well as the program code of the firmware 202.
  • the operating system 210, the graphics driver 212, and the firmware 202 thus in conjunction with one another can perform the method 300.
  • the operating system 210 can determine whether the computing device 100 is to operate in the high graphics performance mode or the low graphics performance mode (302). For example, this determination may be based on an application-level setting of the operating system 210 for the application 214 that is currently running on the computing device 100, such as the application 214 that is in the foreground of the graphical user interface (GUI) provided by the operating system 210 and/or that has focus within the GUI. The determination may also or instead be based on a computing device-level setting of the graphics driver 212, which has priority over the application-level setting. A specific implementation as to how to determine whether the computing device 100 is to operate in a low or high graphics performance mode is presented later in the detailed description.
  • GUI graphical user interface
  • the operating system 210 determines whether the device 100 is currently operating in this mode (304), in which case the method 300 proceeds back to part 302. However, if the computing device 100 is currently operating in the low graphics performance mode, then this means that discrete graphics processor 106 has been turned (i.e., powered) off, and the integrated graphics processor 104 is connected to the display port 108 and is currently driving the external display 110. Therefore, the discrete graphics processor 106 has to be turned (i.e., powered) on and the discrete graphics processor 106 connected to the display port 108 to drive the external display 110.
  • the operating system 210 calls a discrete graphics processor turn-on sequence of the graphics driver 212 (306).
  • This may be considered a discrete graphics processor runtime device 3 (RTD3) power-on sequence, which is a sequence that provides power to the discrete graphics processor 106 so that the graphics processor 106 can transition to a D3 power state in which it is actively running.
  • RTD3 discrete graphics processor runtime device 3
  • the graphics driver 212 turns on the discrete graphics processor 106 (308).
  • the graphics driver 212 also initiates or issues an event to the firmware 202 for or corresponding to the high graphics performance mode (310).
  • the event may be an extension to or a part of the Advanced Configuration Power Interface (ACPI) specification.
  • ACPI Advanced Configuration Power Interface
  • the firmware 202 simulates disconnection of the external display 110 from the integrated graphics processor 104 (312).
  • the firmware 202 may transition an interrupt via the interrupt register 218 of the circuitry 216 according to a first transition. Such an interrupt transition causes the circuitry 216 to responsively disconnect the graphics processors 104 and 106 from their respective input lines 224 and 226 and thus from the multiplexer 222, the display port 108, and the external display 110.
  • the firmware 202 then configures the multiplexer 222 (i.e., the switch) to connect the display port 108 to the discrete graphics processor 106 (314).
  • the firmware 202 may select the input line 226 corresponding to the discrete graphics processor 106 by writing a corresponding value in the select register 220 of the circuitry 216.
  • the circuitry 216 responsively controls the select line 230 of the multiplexer 222 to connect the output line 228 and thus the display port 108 to the input line 226 and thus to the discrete graphics processor 106 when the graphics processor 106 is reconnected to the input line 226.
  • the firmware 202 finally simulates connection of the external display 110 to the discrete graphics processor 106 (316).
  • the firmware 202 may transition an interrupt via the interrupt register 218 of the circuitry 216 according to a second transition. Such an interrupt transition causes the circuitry 216 to responsively reconnect the graphics processors 104 and 106 to their respective input lines 224 and 226 and thus to the multiplexer 222. Because the input line 226 has been selected via the select line 230, the discrete graphics processor 106 is connected to the output line 228 and thus to the display port 108 and to the external display 110. The method 300 then proceeds back to part 302.
  • the operating system 210 determines whether the device 100 is currently operating in this mode (318), in which case the method 300 proceeds back to part 302.
  • the computing device 100 is currently operating in the high graphics performance mode, then this means that the discrete graphics processor 106 has been turned (i.e., powered) on, is connected to the display port 108, and is currently driving the external display 110. Therefore, the integrated graphics processor 104 has to be connected to the display port 108 to drive the external display 110, and the discrete graphics processor 106 turned off.
  • the graphics driver 212 thus initiates an event to the firmware 202 for or corresponding to the low graphics performance mode (322). This event may also be an extension to or a part of the ACPI specification.
  • the firmware 202 simulates disconnection of the external display 110 from the discrete graphics processor
  • the firmware 202 transitions an interrupt via the interrupt register 218 of the circuitry 216 according to a first transition.
  • the firmware 202 then configures the multiplexer 222 (i.e., the switch) to connect the display port 108 to the integrated graphics processor 104 (326).
  • the firmware 202 may select the input line 224 corresponding to the integrated graphics processor 104 by writing a corresponding value to the select register 220.
  • the circuitry 216 responsively controls the select line 230 of the multiplexer 222 to connect the output line 228 and thus the display port 108 to the input line 224 and thus to the integrated graphics processor 104 when the graphics processor 104 is reconnected to the input line 224.
  • the firmware 202 finally simulates connection of the external display 110 to the integrated graphics processor 104 (328). For instance, the firmware 202 may transition an interrupt via the interrupt register 218 of the circuitry 216 according to a second transition. Because the input line 224 has been selected via the select line 230, the integrated graphics processor 104 is connected to the output line 228 and thus to the display port 108 and to the external display 110.
  • the operating system 210 then calls a discrete graphics processor turn-off sequence of the graphics driver 212 (320).
  • This may be considered a discrete graphics processor RTD3 power-off sequence, which is a sequence that removes power from the discrete graphics processor 106 so that the graphics processor 106 can transition out of the D3 state in which it is actively running.
  • the graphics driver 212 in response to the discrete graphics processor turn-off sequence being called by the operating system 210, then turns off the discrete graphics processor 106 (330).
  • the method 300 then proceeds back to part 302.
  • the disconnection of the external display 110 from the graphics processor 104 or 106 and the connection of the display 110 to the other graphics processor 106 or 104 are respectively simulated before and after the display port 108 is switched between the graphics processors 104 and 106. Simulating disconnection of the external display 110 can ensure that the external display 110 does not operate in an unintended or incorrect manner as a result of switching the graphics processor 104 or 106 that is currently driving the display 110 to the other processor 106 or 104. Simulating connection of the external display 110 then allows the newly selected graphics processor 104 or 106 to drive the display 110. Between disconnection and reconnection being simulated, the external display 110 may momentarily flicker, such as for one frame, however.
  • FIG. 4 shows an example method 400 for determining whether to operate the computing device 100 in the high graphics performance mode in which the discrete graphics processor 106 is used to drive the external display 110 or in the low graphics performance mode in which the integrated graphics processor 104 is used to drive the display 110.
  • the method 400 may be performed to implement part 302 of the method 300.
  • the method 400 may be implemented as program code stored on a non-transitory computer-readable data storage medium and executable by a processor.
  • the method 400 realizes the case in which determining the graphics performance mode is based on two settings.
  • the first setting is an application-level setting of the operating system 210 for the application 214 that is currently running on the computing device 100.
  • the second setting is computing device-level setting of the graphics driver 212.
  • the second, computing device-level setting has priority over the first, application-level setting.
  • the driver (i.e., computing device-level) setting indicates the high graphics performance mode is to be used (402)
  • the high graphics performance mode is selected (404). That is, the method 400 concludes that the computing device 100 is to operate in the high graphics performance mode in which the discrete graphics processor 106 is used to drive the external display 110.
  • the driver i.e., computing device-level
  • the low graphics performance mode is selected (408). That is, the method 400 concludes that the computing device 100 is to operate in the low graphics performance mode in which the integrated graphics processor 104 is used to drive the external display 110.
  • the driver i.e., computing device-level
  • the operating system 210 selects the graphics performance mode.
  • the operating system 210 may or may not have an application-level setting for the currently running application 214. A user may have to manually specify this setting for desired applications, such that if the user does not for the application 214, then there will be no such setting for the application 214. T
  • the operating system setting for the application 214 may specify that the computing device 100 is to operate in the high graphics performance mode, the low graphics performance mode, or in a graphics performance mode selected by the operating system 210. Therefore, if the operating system (i.e., application-level) setting for the application 214 is present (412) and indicates that the high graphics performance mode is to be used for the application 214 (414), then the high graphics performance mode is selected (404). If the operating system (i.e., application-level) setting for the application 214 indicates that the low graphics performance mode is to be used for the application 214 (416), then the low graphics performance mode is selected (408).
  • the operating system 210 may determine whether the application 214 is a 3D application (420). The operating system 210 may also make this determination if the operating system (i.e., application-level) setting for the application 214 is not present (that is, if the application 214 is not specified within the operating system setting regarding which graphics performance mode should be used at an application level).
  • a 3D application is an application that employs or displays 3D graphics, and which can thus benefit from the higher performance afforded by the discrete graphics processor 106. If the application 214 is a 3D application, then the high graphics performance mode is selected (406). If the application 214 is not a 3D application, then the low graphics performance mode is selected (408).
  • FIG. 5 shows an example non-transitory computer-readable data storage medium 500 storing program code 502 executable by the computing device 100 to perform processing, such as the methods 300 and 400 that have been described.
  • the processing includes detecting that the display port 108 is connected to an external display 110 (504).
  • the processing includes responsively determining whether the computing device 100 is to operate in a high graphics performance mode or a low graphics performance mode (506).
  • the processing includes turning on the discrete graphics processor 106 and switching the display port 108 to the graphics processor 106 (508).
  • the processing includes switching the display port 108 to the integrated graphics processor 104 and turning off the discrete graphics processor 106 (510).

Abstract

Selon l'invention, un port d'affichage d'un dispositif informatique est connecté à un afficheur externe. En réponse à la détermination du fait que le dispositif informatique doit fonctionner dans un mode de performance graphique élevée, le dispositif informatique active un processeur graphique distinct du dispositif informatique et commute le port d'affichage vers le processeur graphique distinct. En réponse à la détermination du fait que le dispositif informatique doit fonctionner dans un mode de performance graphique faible, le dispositif informatique commute le port d'affichage vers un processeur graphique intégré du dispositif informatique et éteint le processeur graphique distinct.
PCT/US2021/057334 2021-10-29 2021-10-29 Port d'affichage à commutation connecté à un afficheur externe entre des processeurs graphiques distinct et intégré WO2023075791A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2021/057334 WO2023075791A1 (fr) 2021-10-29 2021-10-29 Port d'affichage à commutation connecté à un afficheur externe entre des processeurs graphiques distinct et intégré

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2021/057334 WO2023075791A1 (fr) 2021-10-29 2021-10-29 Port d'affichage à commutation connecté à un afficheur externe entre des processeurs graphiques distinct et intégré

Publications (1)

Publication Number Publication Date
WO2023075791A1 true WO2023075791A1 (fr) 2023-05-04

Family

ID=86158438

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2021/057334 WO2023075791A1 (fr) 2021-10-29 2021-10-29 Port d'affichage à commutation connecté à un afficheur externe entre des processeurs graphiques distinct et intégré

Country Status (1)

Country Link
WO (1) WO2023075791A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103370690A (zh) * 2011-07-13 2013-10-23 Flex Electronics ID Co.,Ltd. 动态跨环境应用方位
US20160077682A1 (en) * 2011-07-13 2016-03-17 Z124 Dynamic cross-environment application configuration/orientation
CN109584141A (zh) * 2017-09-29 2019-04-05 英特尔公司 可切换的混合图形
US20210097640A1 (en) * 2019-09-27 2021-04-01 Intel Corporation Switchable image source in a hybrid graphics systems

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103370690A (zh) * 2011-07-13 2013-10-23 Flex Electronics ID Co.,Ltd. 动态跨环境应用方位
US20160077682A1 (en) * 2011-07-13 2016-03-17 Z124 Dynamic cross-environment application configuration/orientation
CN109584141A (zh) * 2017-09-29 2019-04-05 英特尔公司 可切换的混合图形
US20210097640A1 (en) * 2019-09-27 2021-04-01 Intel Corporation Switchable image source in a hybrid graphics systems

Similar Documents

Publication Publication Date Title
EP2428948B1 (fr) Dispositif ayant plusieurs sous-systèmes graphiques et un mode de consommation d'énergie réduite, logiciels et procédés associés
US8555099B2 (en) Device having multiple graphics subsystems and reduced power consumption mode, software and methods
US9529646B2 (en) Power-efficient interaction between multiple processors
US8487943B2 (en) Driver architecture for computing device having multiple graphics subsystems, reduced power consumption modes, software and methods
TWI431532B (zh) 用於經由一虛擬圖形裝置驅動程式於一顯示器上顯示一影像之方法、系統及儲存媒體
JP2007508583A (ja) 電力管理イベントの検出によるディスプレイ更新特性の切り替え
JP2012256223A (ja) 情報処理装置および情報処理方法
US10228750B2 (en) Reducing the power consumption of an information handling system capable of handling both dynamic and static display applications
TW200928982A (en) Host device and computer system for reducing power consumption in graphic cards
JPH11194847A (ja) コンピュータシステムおよび初期化制御装置
WO2023075791A1 (fr) Port d'affichage à commutation connecté à un afficheur externe entre des processeurs graphiques distinct et intégré
KR20230164087A (ko) 활용된 전원에 기초한 그래픽 프로세싱 유닛(gpu) 선택
JP4988036B2 (ja) 情報処理装置および同装置における映像信号の出力制御方法
US11922855B2 (en) Changing LCD display timing controller settings for different graphics processor requirements
US11893962B2 (en) Graphics processor switching based on coupled display devices
TWI823253B (zh) 計算系統、由電腦執行的方法以及電腦程式產品
WO2023277869A1 (fr) Activation d'unités de traitement graphique intégrées
JP5201231B2 (ja) 情報処理装置、情報処理方法及びそのプログラム

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21962722

Country of ref document: EP

Kind code of ref document: A1