WO2023070337A1 - 单端存储器 - Google Patents

单端存储器 Download PDF

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Publication number
WO2023070337A1
WO2023070337A1 PCT/CN2021/126524 CN2021126524W WO2023070337A1 WO 2023070337 A1 WO2023070337 A1 WO 2023070337A1 CN 2021126524 W CN2021126524 W CN 2021126524W WO 2023070337 A1 WO2023070337 A1 WO 2023070337A1
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WO
WIPO (PCT)
Prior art keywords
transistor
bit line
read bit
terminal
level
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Application number
PCT/CN2021/126524
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English (en)
French (fr)
Inventor
蔡江铮
程宽
布明恩
张雨晴
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202180100253.4A priority Critical patent/CN117616501A/zh
Priority to EP21961713.1A priority patent/EP4386753A1/en
Priority to PCT/CN2021/126524 priority patent/WO2023070337A1/zh
Publication of WO2023070337A1 publication Critical patent/WO2023070337A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Definitions

  • the present application relates to the technical field of storage, and in particular to a single-ended memory.
  • Single-ended memory is a common type of memory that includes memory cells distributed in an array. Wherein, in a row of memory cells of the single-ended memory, a plurality of memory cells are connected to the same read bit line (read bit line, RBL), and in the row of memory cells, each memory cell is also connected to a read word line (read word line, RWL).
  • RBL read bit line
  • RWL read word line
  • the read bit line RBL is first set to a high level, and when the memory cell is selected by the read word line RWL connected to any memory cell, the selected memory cell outputs the memory to the read bit line RBL. information.
  • the stored information will affect the level of the read bit line RBL, so that the stored information of the selected memory cell can be determined according to the level change on the read bit line RBL.
  • FIG. 1 a schematic diagram of a circuit structure of a row of storage cells of a single-ended memory is provided, the single-ended memory is connected with a storage unit 1, a storage unit 2 and a storage unit 3, and the storage unit 1 is also connected to the read word line RWL1 , the memory cell 2 is also connected to the read word line RWL2, and the memory cell 3 is also connected to the read word line RWL3.
  • the read bit line RBL is also connected to the power supply Vdd through the pre-charging unit (the pre-charging unit in FIG. transistor M12 as an example).
  • the transistor M11 When reading the stored information of the memory cell 1, the transistor M11 is first turned on, and the read bit line RBL is connected to the power supply Vdd through the transistor M11, and the power supply Vdd charges the read bit line RBL, so that the read bit line RBL becomes a high level. Subsequently, the transistor M11 is turned off, and the read bit line RBL maintains a high level.
  • the read word line RWL1 selects memory cell 1, while memory cell 2 and memory cell 3 are not selected. Therefore, the memory cell 1 outputs storage information to the read bit line RBL. If the storage information of the memory cell 1 is at a high level at this time, the memory cell 1 outputs a high level to the read bit line RBL, and the read bit line RBL will maintain a high level.
  • the single-ended memory will introduce a leakage current compensation unit (that is, transistor M12) in the circuit design, and the transistor M12 will be turned on initially, and the read bit line RBL is connected to the power supply Vdd through the transistor M12, and the power supply Vdd charges the read bit line RBL , so that the level of the read bit line RBL rises to compensate for the level of the read bit line RBL lowered due to the leakage current. Therefore, the read bit line RBL maintains a high level, and the high level of the read bit line RBL can be accurately It is determined that the storage information of the storage unit 1 is at a high level.
  • a leakage current compensation unit that is, transistor M12
  • the memory cell 1 If the stored information of the memory cell 1 is at a low level, the memory cell 1 outputs a low level to the read bit line RBL, and the level of the read bit line RBL starts to decrease.
  • the transistor M12 is not turned off in time at this time, the transistor M12 is still turned on, the read bit line RBL is still connected to the power supply Vdd through the transistor M12, the power supply Vdd is still charging the read bit line RBL, and the level of the read bit line RBL rises, so As a result, the level of the read bit line RBL decreases slowly.
  • the embodiment of the present application provides a single-ended memory, which relates to the field of storage technology and can solve the problem of slow reading speed of the existing single-ended memory.
  • a single-ended memory which includes memory cells distributed in an array, and the memory cells are connected to a read bit line and a read word line.
  • the read bit line is connected to the precharge unit through the column selection unit, the read bit line is connected to the output terminal of the leakage current compensation unit through the column selection unit, and the read bit line is also connected to the control terminal of the leakage current compensation unit through the feedback circuit.
  • the feedback circuit determines that the level of the read bit line is lower than the first predetermined value, it outputs a feedback signal to the control terminal of the leakage current compensation unit to stop the leakage current compensation unit from charging the read bit line through the output terminal.
  • the precharge unit charges the read bit line through the column selection unit, and the read bit line remains at a high level. If selected, the storage unit outputs storage information to the read bit line. When the stored information is at a low level, the level of the read bit line also begins to decrease, and the feedback circuit outputs a feedback signal to the control terminal of the leakage current compensation unit after determining that the level of the read bit line is lower than a predetermined value. The signal can stop the leakage current compensation unit from charging the read bit line through the output terminal.
  • the leakage current compensation unit of the single-ended memory is controlled by the feedback signal output by the feedback circuit, and the feedback signal output by the feedback circuit is changed in time according to the level change of the read bit line, so that the leakage current compensation unit can be more timely Closed, because the leakage current compensation unit is stopped in time to charge the read bit line, so the level of the read bit line can be lowered faster under the effect of storing information as a low level, so that the single-ended memory can be faster Since the stored information is read on the read bit line, the reading speed of the single-ended memory becomes faster.
  • the feedback circuit determines that the level of the read bit line is higher than the second predetermined value, it outputs a feedback signal to the control terminal of the leakage current compensation unit, so as to control the leakage current compensation unit to charge the read bit line through the output terminal, wherein
  • the above-mentioned first predetermined value is less than or equal to the above-mentioned second predetermined value.
  • the leakage current compensation unit when the storage information of the selected memory cell is at a high level, the read bit line will remain at a high level, and when the feedback circuit determines that the level of the read bit line is higher than a second predetermined value, the leakage current compensation unit
  • the control terminal of the control terminal outputs a feedback signal, and the feedback signal can control the leakage current compensation unit to charge the read bit line through the output terminal, so as to compensate the leakage current generated by other storage units on the read bit line. Since the feedback signal output by the feedback circuit can also control the leakage current compensation unit to be turned on in time, it can also ensure the reading performance of the single-ended memory to read and store information at a high level.
  • the above feedback circuit includes: an inverter.
  • the input end of the inverter is connected to the read bit line, and the output end of the inverter is connected to the control end of the leakage current compensation unit, wherein the inverter is used to generate a feedback signal according to the level of the read bit line.
  • the embodiment of the present application also provides a specific structure of the inverter.
  • the inverter includes: a first transistor and a second transistor. The first end of the first transistor is connected to the power supply, the second end of the first transistor is connected to the first end of the second transistor, the second end of the second transistor is connected to the ground, and the control end of the first transistor is connected to the control end of the second transistor.
  • the input terminal of the inverter and the second terminal of the first transistor are also connected to the output terminal of the inverter, and the types of the first transistor and the second transistor are different.
  • the embodiment of the present application also provides another specific structure of an inverter, where the inverter includes: a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; the first terminal of the third transistor connected to the power supply, the second end of the third transistor is connected to the first end of the fourth transistor, the second end of the fourth transistor is connected to the first end of the fifth transistor; the second end of the fifth transistor is connected to ground; the second end of the sixth transistor is connected to the ground; One end is connected to the second end of the fourth transistor, the control end of the sixth transistor is connected to the second end of the third transistor, and the second end of the sixth transistor is connected to the power supply; the control end of the third transistor, the control end of the fourth transistor and The control terminal of the fifth transistor is connected to the input terminal of the inverter; the second terminal of the third transistor is also connected to the output terminal of the inverter; the types of the fourth transistor, the fifth transistor and the sixth transistor are the same, and the third transistor is the same as the first transistor.
  • the above feedback circuit may also realize generating a feedback signal according to the level of the read bit line by setting a logic gate circuit.
  • the feedback circuit includes: a first NOR gate and a first NOT gate.
  • the input terminal of the first NOT gate is connected to the control terminal of the column selection unit, the output terminal of the first NOT gate is connected to the first input terminal of the first NOR gate, and the second input terminal of the first NOR gate is connected to the read bit line ;
  • the output terminal of the first NOR gate is connected to the control terminal of the leakage current compensation unit.
  • the precharge unit charges the read bit line through the column selection unit, if the read word line selects the memory cell, the memory cell outputs stored information to the read bit line.
  • the feedback circuit is connected to the transmission path between the storage unit and the column selection unit.
  • the single-ended memory further includes: a first switch unit, the leakage current compensation unit is connected to the read bit line through the first switch unit, and the control terminal of the first switch unit is connected to the control terminal of the column selection unit.
  • the first switch unit ensure that when the column selection unit is turned on by the signal of its control terminal to select the read bit line, the first switch unit can be turned on at the same time to connect the leakage current compensation unit to the read bit line, so that the leakage current compensation unit can be read.
  • the level of the read bit line is compensated or stopped in time, so that the leakage current compensation unit works adaptively when the read bit line is selected.
  • the above-mentioned single-end memory further includes: a discharge unit.
  • the control terminal of the discharge unit is connected to the control terminal of the leakage current compensation unit, the first terminal of the discharge unit is connected to the read bit line through the column selection unit, and the second terminal of the discharge unit is connected to the ground.
  • the discharge unit can connect the read bit line to the ground through the column selection unit and the discharge unit after receiving the feedback signal, so that the level of the read bit line decreases faster, ensuring that the read The level of the bit line can be lowered to the low level as soon as possible, which improves the reading speed of the single-ended memory.
  • the above discharge unit may include a seventh transistor and an eighth transistor; the control terminal of the seventh transistor is connected to the control terminal of the leakage current compensation unit, and the first terminal of the seventh transistor is connected to the read bit line through the column selection unit; the seventh The second terminal of the transistor is connected to the control terminal of the eighth transistor, the second terminal of the seventh transistor is also connected to the first terminal of the eighth transistor, and the second terminal of the eighth transistor is connected to the ground.
  • the connection of the seventh transistor and the eighth transistor will increase the equivalent resistance of the current discharge cell, and then the discharge speed of the discharge cell will slow down. If the level of the current read bit line is reduced due to the existence of leakage current, the discharge unit set in this way will not directly connect the read bit line to the ground, causing the problem of reading the stored information incorrectly, making the single-ended memory Read performance is more stable.
  • the above discharge unit may further include: a ninth transistor.
  • the control end of the leakage current compensation unit is connected to the control end of the ninth transistor through the second NOT gate, the first end of the ninth transistor is connected to the read bit line through the column selection unit; the second end of the ninth transistor is connected to the ground.
  • the ninth transistor is a P-type transistor, and there is a threshold loss when the P-type transistor transfers a level, thereby slowing down the discharge speed of the discharge unit.
  • a second switch unit is further provided between the first end of the discharge unit and the column selection unit.
  • the existence of the second switch unit is to control the discharge unit to work or not work adaptively according to needs.
  • the above-mentioned single-ended memory further includes: a second NOR gate and a third NOT gate.
  • the input terminal of the third NOT gate is connected to the control terminal of the column selection unit, the output terminal of the third NOT gate is connected to the first input terminal of the second NOR gate; the second input terminal of the second NOR gate is connected to the read bit line; The output end of the second NOR gate is connected to the control end of the discharge unit.
  • FIG. 1 is a schematic structural diagram of a single-ended memory provided by the prior art
  • FIG. 2 is a schematic structural diagram of a single-ended memory provided in Embodiment 1 of the present application;
  • Fig. 3 is a typical structural schematic diagram of the storage unit in Fig. 2;
  • FIG. 4 is a first schematic diagram of the current flow of a single-ended memory provided in Embodiment 2 of the present application;
  • FIG. 5 is a second schematic diagram of the current flow of a single-ended memory provided in Embodiment 2 of the present application;
  • FIG. 6 is a schematic structural diagram of a single-ended memory provided in Embodiment 3 of the present application.
  • FIG. 7 is a schematic structural diagram of a single-ended memory provided in Embodiment 4 of the present application.
  • FIG. 8 is a schematic structural diagram of a single-ended memory provided in Embodiment 5 of the present application.
  • FIG. 9 is a schematic structural diagram of a single-ended memory provided in Embodiment 6 of the present application.
  • FIG. 10 is a schematic structural diagram of a single-ended memory provided in Embodiment 7 of the present application.
  • FIG. 11 is a schematic structural diagram of a single-ended memory provided in Embodiment 8 of the present application.
  • FIG. 12 is a schematic structural diagram of a single-ended memory provided in Embodiment 9 of the present application.
  • FIG. 13 is a schematic structural diagram of a single-ended memory provided in Embodiment 10 of the present application.
  • FIG. 14 is a schematic structural diagram of a single-ended memory provided in Embodiment 11 of the present application.
  • FIG. 15 is a schematic structural diagram of a single-ended memory provided in Embodiment 12 of the present application.
  • FIG. 16 is a performance simulation diagram 1 of a single-ended memory provided by an embodiment of the present application.
  • FIG. 17 is the performance simulation diagram 2 of the single-ended memory provided by the embodiment of the present application.
  • At least one (unit) of a, b or c can represent: a, b, c, a and b, a and c, b and c or a, b and c, wherein a, b and c can be It can be single or multiple.
  • words such as "first" and "second” do not limit the quantity and order.
  • the transistor can be a metal-oxide-semiconductor field effect transistor (MOSFET), and the transistor is divided into N (negative, negative) type transistor and P (positive, positive)
  • MOSFET metal-oxide-semiconductor field effect transistor
  • the transistor includes a source (source), a drain (drain) and a gate (gate), and the transistor can be turned on or off by controlling the level input to the gate of the transistor.
  • the source and drain are turned on to generate a turn-on current; when the transistor is turned off, the source and drain will not be turned on, but due to the structural characteristics of the transistor, there will be a small gap between the source and the drain. leakage current.
  • the gate of the transistor is also called the control terminal, the source is called the first terminal, and the drain is called the second terminal; or, the gate is called the control terminal, and the drain is called the second terminal. is called the first terminal, and the source is called the second terminal.
  • the N-type transistor is turned on when the level of the control terminal is high, the first terminal and the second terminal are turned on, and a turn-on current is generated between the first terminal and the second terminal; the level of the N-type transistor is low at the control terminal. It is usually closed, the first terminal and the second terminal are not conducted, and there is a leakage current between the first terminal and the second terminal.
  • the P-type transistor is turned on when the level of the control terminal is low, and the first terminal and the second terminal are turned on to generate a turn-on current; the P-type transistor is turned off when the level of the control terminal is high, and the first terminal and the second terminal are not connected. conduction, there is a leakage current.
  • the storage information of the storage unit is high level representing that the data stored in the current storage unit is “1” (also called logic “1”); the storage information of the storage unit is low level representing the current
  • the data stored in the memory cell is "0" (also referred to as logic "0").
  • a high level also means that the current voltage is higher than a predetermined value;
  • a low level also means that the current voltage is lower than a predetermined value (the predetermined value can be changed according to changes in the circuit).
  • the high level of the signal indicates that the current signal is logic high (also called HIGH sometimes); the low level of the signal indicates that the current signal is logic low (also called LOW sometimes).
  • the embodiment of the present application provides a schematic structural view of a single-ended memory, which includes a memory array 20, and input/output (inpit/output, I) coupled with the memory array 20 respectively.
  • /O input/output circuit 21
  • reference circuit 22 and decoder 23 reference circuit 22 and decoder 23
  • control logic circuit 24 coupled to input/output circuit 21 and decoder 23 .
  • the memory array 20 includes a plurality of storage units distributed in an array in the memory array 20 , and each storage unit includes a plurality of transistors.
  • storage unit 201 and storage unit 202 are arranged in a row, storage unit 203 and storage unit 204 are arranged in b row; storage unit 201 and storage unit 203 are arranged in A column, storage unit 202 and storage unit 204 are arranged in column B.
  • Each storage unit is used to store one bit of data, i.e. data "1" or data "0".
  • the storage information of the storage unit is high level (subsequent application In the embodiment, the storage information of the storage unit is high level to indicate that the data stored in the storage unit is “1”).
  • the storage information of the storage unit is low level ( In subsequent embodiments of the present application, the storage information of the storage unit is low level to indicate that the data stored in the storage unit is “0”).
  • the memory array 20 also includes a plurality of bit lines (bit lines, BL) (which may be read bit lines (read bit lines, RBL) or write bit lines (write bit lines, WBL)) arranged along corresponding columns and/or A bit bar line (which can be a write bit bar line (WBBL)), and a plurality of word lines (word line, WL) arranged along the corresponding row (which can be a read word line (read word line, RWL) or Write word line (write word line, WWL)).
  • bit lines bit lines
  • BL bit lines
  • RBL read bit lines
  • WBL write bit lines
  • the input/output circuit 21 includes a plurality of sense amplifiers (sense amplifier, SA) (sense amplifier SA-A and sense amplifier SA-B as shown in Figure 2), and the reference circuit (reference circuit, RC) 22 includes a plurality of sub-reference circuits (sub-reference circuit RC-A and sub-reference circuit RC-B as shown in FIG. 2).
  • SA sense amplifier
  • RC reference circuit
  • Each column of memory cells in the above-mentioned memory array 20 is coupled to the corresponding sense amplifier and sub-reference circuit through a read bit line RBL.
  • RBL read bit line
  • the input/output circuit 21 will increase the sense amplifier corresponding to the column in the memory array 20
  • the reference circuit 22 will increase the sub-reference circuit corresponding to the column in the memory array 20 .
  • the decoder 23 coupled to the memory array 20 can be used to receive address information (eg, row address) provided by the control logic circuit 24 to assert one or more word lines of the memory array 20 .
  • control logic circuitry 24 may be coupled to input/output circuitry 21 to retrieve data read by sense amplifiers (eg, sense amplifier SA-A, sense amplifier SA-B, etc.) during a read operation.
  • the single-ended memory shown in FIG. 2 may also include other memory arrays and/or other one or more functional circuits (such as buffer circuits, sequential circuits, etc.), and each memory array may include more or less storage unit.
  • each memory array may include more or less storage unit.
  • FIG. 3 a schematic diagram of a typical structure of a storage unit 201 in FIG. 2 provided for an embodiment of the present application, wherein the storage unit 201 includes 8 transistors (the storage unit formed by the 8 transistors is also called Eight-transistor SRAM cell), the eight transistors are transistor M1, transistor M2, transistor M3, transistor M4, transistor M5, transistor M6, transistor M7, and transistor M8.
  • the transistors M1 and M3 are P-type transistors, and the other transistors are N-type transistors.
  • the memory unit 201 further includes a write word line WWL, a write bit line WBL, a write bit bar line WBBL, a read bit line RBL-A, and a read word line RWL.
  • the first end of the transistor M1 is connected to the power supply Vdd
  • the second end of the transistor M1 is connected to the first end of the transistor M2
  • the second end of the transistor M2 is connected to the ground GND.
  • the first terminal of the transistor M3 is connected to the power supply Vdd
  • the second terminal of the transistor M3 is connected to the first terminal of the transistor M4
  • the second terminal of the transistor M4 is connected to the ground GND
  • the second terminal of the transistor M3 is also connected to the control terminal of the transistor M1
  • the control terminal of the transistor M1 is also connected to the control terminal of the transistor M2.
  • the write bit line WBL is connected to the first end of the transistor M5, the second end of the transistor M5 is connected to the second end of the transistor M1, the second end of the transistor M5 is also connected to the control end of the transistor M3, and the control end of the transistor M3 is also connected to the The control terminal of the transistor M4.
  • the write word line WWL is connected to the control end of the transistor M5, the write word line WWL is also connected to the control end of the transistor M6, the first end of the transistor M6 is connected to the second end of the transistor M3, and the second end of the transistor M6 is connected to the write bit bar line WBBL .
  • the second end of the transistor M3 is also connected to the control end of the transistor M7, the second end of the transistor M7 is connected to the ground, the first end of the transistor M7 is connected to the first end of the transistor M8, and the second end of the transistor M8 is connected to the read On the bit line RBL-A, the control terminal of the transistor M8 is connected to the read word line RWL.
  • the second terminal of the transistor M1 is also coupled to the first node 2011 of the storage unit 201
  • the second terminal of the transistor M3 is also coupled to the second node 2012 of the storage unit 201 .
  • the transistors M1-M6 form the core of the memory unit 201, and the core is mainly used for performing write operations (ie, the core includes a write interface).
  • the transistor M1 and the transistor M2 are connected to form a first inverter, and the transistor M3 and the transistor M4 are connected to form a second inverter, and the first inverter and the second inverter are cross-coupled to each other (as shown in FIG. 3 ) . More specifically, the first inverter and the second inverter are respectively coupled between the power supply Vdd and the ground GND. Additionally, a first inverter is coupled to transistor M5 and a second inverter is coupled to transistor M6.
  • Transistor M5 and transistor M6 are also coupled to the write word line WWL of the memory cell, transistor M5 is also coupled to the write bit line WBL, and transistor M6 is also coupled to the write bit bar line WBBL. The on and off of the transistor M5 and the transistor M6 are controlled by the write word line WWL.
  • the core of the storage unit 201 makes the storage function of the storage unit 201 more stable.
  • the transistor M7 and the transistor M8 form a read buffer of the memory unit 201, and the read buffer is mainly used to perform a read operation (ie, the read buffer provides a read interface).
  • the read word line RWL controls the transistor M8 to turn on or off
  • the read word line RWL being high level represents that the current memory cell 201 is selected for storage information output
  • the read word line RWL being low level represents that the current memory cell 201 is not selected. selected.
  • the storage information of the storage unit 201 controls the transistor M7 to be turned on or off. When the storage information of the storage unit 201 is at a high level, the high level storage information controls the transistor M7 to be closed. When the storage information of the storage unit 201 is at a low level, the transistor M7 is turned off. The storage information of the low level controls the transistor M7 to be turned on.
  • the storage unit 201 When writing storage information into the storage unit 201, as shown in FIG. Write the address information (for example, row address) of the storage unit storing the information, and then set (assert) one or more word lines corresponding to the storage unit in the memory array 20 through the decoder 23 .
  • the write word line WWL is set at a high level, and at this time, the transistor M5 and the transistor M6 are turned on.
  • the write bit line WBL transmits the corresponding low-level/high-level storage information to the storage unit 201, and at the same time, the bit bar line WBBL receives the reverse signal of the storage information (for example, when the storage information received by WBL is a high level Usually, the bit bar line receives low level; when the storage information received by WBL is low level, the bit bar line receives high level).
  • the transistor M3 and the transistor M2 in the corresponding storage unit 201 are turned on, the transistor M1 and the transistor M4 are turned off, and the first node 2011 in the storage unit 201 is at a low level.
  • the second node 2012 is at a high level, and the storage information at a low level transmitted by the write bit line WBL is accurately written into the core of the memory unit 201 .
  • the storage information transmitted by the current write bit line WBL is at a high level
  • the transistor M3 and the transistor M2 in the corresponding storage unit 201 are turned off, the transistor M1 and the transistor M4 are turned on, and the first node 2011 in the storage unit 201 is at a high level.
  • the second node 2012 is at a low level, and the storage information at a high level transmitted by the write bit line WBL is accurately written into the core of the memory unit 201 .
  • the first node 2011 in the storage unit 201 is at a high level
  • the second node 2012 is at a low level, representing that the storage information of the current storage unit 201 is at a high level
  • the first node 2011 in the storage unit 201 is at a low level
  • the second node 2012 is at high level, which means that the storage information of the storage unit 201 is at low level.
  • the read word line RWL and the read bit line RBL-A are set to high level.
  • the read word line RWL is set at a high level so that the memory cell 201 is selected, and the transistor M8 in the memory cell 201 is turned on. At this time, a current I1 is formed between the transistor M8 and the read bit line RBL-A.
  • the storage information of the current storage unit 201 is at a high level
  • the first node 2011 in the storage unit 201 is at a high level
  • the second node 2012 is at a low level
  • the transistor M7 is turned off, and the read bit line RBL-A will not
  • the transistor M7 and the transistor M8 are connected to GND, and the current I2 flowing through the transistor M7 and the transistor M8 will not be generated, so the storage unit 201 outputs a high level to the read bit line RBL-A, and the level of the read bit line RBL-A remains initial high level.
  • the input/output circuit 21 receives the level of the read bit line RBL-A and the level of the sub-reference circuit RC-A, and judges that the level of the read bit line RBL-A is greater than that of the sub-reference circuit RC-A. level, it is determined that the information stored in the storage unit 201 is at a high level at this time. Referring to FIG.
  • the storage unit 201 outputs a low level to the read bit line RBL-A, and the level of the read bit line RBL-A start lowering.
  • the input/output current 21 receives the level of the read bit line RBL-A and the level of the sub-reference circuit RC-A, and it is judged that the level of the read bit line RBL-A is lower than that of the sub-reference circuit RC-A. level, it is determined that the information stored in the storage unit 201 is at a low level at this time.
  • the reference circuit 21 may be provided, or the reference circuit 21 may not be provided.
  • the input/output circuit 22 only receives the level on the read bit line, and determines whether the stored information of the current memory cell is high level or low level according to the level on the read bit line.
  • the selected memory cell When reading the stored information of the selected memory cell in the above-mentioned single-ended memory, the selected memory cell outputs the stored information to the read bit line, and the stored information will affect the level of the read bit line. At this time, other memory cells in the same column as the selected memory cell will generate a leakage current, and the leakage current will also affect the level of the read bit line, resulting in abnormal changes in the level of the read bit line. For this reason, single-ended A leakage current compensation unit is mostly set in the memory.
  • the embodiment of the present application provides a schematic structural diagram of a single-ended memory, which includes a read bit line RBL-1 and other read bit lines RBL-n, and each read bit line Both of them include a plurality of storage units, taking the read bit line RBL-1 as an example, the read bit line RBL-1 is connected with 3 storage units (respectively storage unit c1, storage unit c2, storage unit c3), through the read bit line Line RBL-1 can read the stored information in these 3 memory cells.
  • the memory cell c1 is also connected to the read word line RWL-1
  • the memory cell c2 is also connected to the read word line RWL-2
  • the memory cell c3 is also connected to the read word line RWL-3.
  • the read bit line RBL-1 is also connected to the power supply Vdd through the pre-charging unit (the pre-charging unit in FIG. 1), the read bit line RBL-1 is connected to the power supply Vdd through the leakage current compensation unit (the leakage current compensation unit in FIG. bit line RBL-1).
  • the read bit line RBL-1 is coupled to the first input end of the NAND gate 401
  • the memory cells of other columns are coupled to the second input end of the NAND gate 401 through other read bit lines RBL-n
  • the output of the NAND gate 401 The end is coupled to the control end of the transistor M45, the first end of the transistor M45 is connected to the ground GND, the second end of the transistor M45 is connected to the global bit line (global bit line, GBL), and the output end of the NAND gate 401 is also coupled to the transistor M42. Control terminal.
  • the above-mentioned transistor M41 and the transistor M42 are P-type transistors as an example
  • the transistor M45 is an N-type transistor as an example.
  • the structure of the three storage units in the single-ended memory shown in Figure 4 can refer to the schematic structural diagram of the storage unit 201 shown in Figure 3, where the core cc in the storage unit in Figure 4 is equivalent to the storage unit in Figure 3
  • Transistors M1-M6 in cell 201, the core cc are used to save storage information and perform write operations.
  • the transistor M44 in FIG. 4 is equivalent to the transistor M7 in the storage unit 201 in FIG. 3, and the core cc in each storage unit is coupled to the transistor M44.
  • the storage information stored in the core cc of the storage unit is at a high level
  • the transistor M44 is turned off, and the transistor M44 is turned on when the storage information stored in the core cc of the memory unit is at a low level.
  • Transistor M43 in the memory cell in FIG. 4 is equivalent to transistor M8 in memory cell 201 in FIG. Transistor M43 in the memory cell is turned off.
  • the precharge signal (precharge) S1 is switched from high level to low level, and the control terminal level of the transistor M41 controlled by this is low level. level, the transistor M41 is turned on, the power supply Vdd is connected to the read bit line RBL-1, and the power supply Vdd charges the read bit line RBL-1, so that the level of the read bit line RBL-1 is high, and then the precharge signal S1 is generated by The low level becomes high level, the level of the control terminal of the control transistor M41 is high level, the transistor M41 is turned off, the power supply Vdd stops charging the read bit line RBL-1, and the read bit line RBL-1 remains high level.
  • the other read bit lines RBL-n connected to the memory cells in other columns are connected to the power supply Vdd through the switch 1, and the global bit line GBL is also connected to the power supply Vdd through the switch 2, and the precharge signal (precharge) S1 is controlled by a high level Switching to a low level to control the level of the read bit line RBL-1 to become high, switch 1 and switch 2 will also be turned on, so that other read bit lines RBL-n and the global bit line GBL are connected to the power supply Vdd, so Other read bit lines RBL-n and global bit line GBL will also be set at high level, and because the transistor M45 is turned off (because the high levels on the read bit line RBL-1 and other read bit lines RBL-n are combined with
  • the NOT gate 401 outputs a low level when the NAND operation is performed, and controls M45 to turn off), and the global bit line GBL maintains a high level.
  • the reading process of the single-ended memory is described by taking reading the stored information of the storage unit c1 as an example.
  • the read word line RWL-1 connected to the memory cell c1 is at a high level to control the level of the control terminal of the transistor M43 to be at a high level, so that the memory cell c1 is selected, and the memory cell c1 outputs stored information to the read bit line RBL-1.
  • the read word line RWL-2 connected to the memory cell c2 is at a low level to control the level of the control terminal of the transistor M43 to be at a low level, and the memory cell c2 is not selected.
  • the read word line RWL-3 connected to the memory cell c3 is at a low level to control the level of the control terminal of the transistor M43 to be at a low level, and the memory cell c3 is not selected.
  • the transistor M44 controlled by the storage information in the storage unit c1 is turned off, and the read bit line RBL-1 is not affected by the transistor M43 and the transistor M43 in the storage unit c1.
  • the transistor M44 is connected to the ground GND, and the level of the read bit line RBL-1 remains high, which means that the memory cell c1 outputs a high level to the read bit line RBL-1.
  • the NAND gate 401 since the other read bit lines RBL-n are placed at high level, the high levels on the read bit line RBL-1 and other read bit lines RBL-n are executed by the NAND gate 401 to output a low level level, the low level is transmitted to the control terminal of the leakage current compensation unit (that is, the transistor M42), so that the transistor M42 is turned on, and the read bit line RBL-1 is connected to the power supply Vdd through the transistor M42, and the power supply Vdd charges the read bit line RBL-1 , and the output terminal of the NAND gate 401 outputs a low level, which also controls the transistor M45 to close, and the global bit line GBL will not be connected to the ground through the transistor M45, so the input/output circuit coupled with the global bit line GBL can determine the global bit line
  • the level of GBL is high level, and it can also be determined that the stored information in the currently selected storage unit c1 is high level.
  • the read bit line RBL-1 is connected to the ground GND through the transistor M43 and the transistor M44 in the storage unit c2 as shown in FIG. Leakage current Ic2 of M43 and transistor M44.
  • the read bit line RBL-1 is also connected to the ground GND through the transistor M43 and the transistor M44 in the memory cell c3, and the memory cell c3 generates a leakage current Ic3 flowing through the transistor M43 and the transistor M44.
  • the leakage current Ic2 and the leakage current Ic3 will cause the level of the read bit line RBL-1 to drop.
  • the leakage current compensation unit (that is, the transistor M42) is provided in the single-ended memory, the transistor M42 is turned on so that the read bit line RBL-1 is connected to the power supply Vdd through the transistor M42, and the level of the read bit line RBL-1 rises, compensating The reduced level on the read bit line RBL-1 due to the generation of leakage current Ic2 and leakage current Ic3 is realized.
  • the transistor M44 controlled by the storage information in the storage unit c1 is turned on, and the read bit line RBL-1 will be activated by the transistor M43 and the transistor M43 in the storage unit c1.
  • the memory cell c1 When M44 is turned on and connected to GND, the memory cell c1 generates the turn-on current Ic1 flowing through the transistor M43 and the transistor M44. Therefore, the memory cell c1 outputs a low level to the read bit line RBL-1, and the voltage of the read bit line RBL-1 level began to drop.
  • the NAND gate 401 When the level of the read bit line RBL-1 is reduced to a low level, the NAND gate 401 performs a NAND operation on the levels of the read bit line RBL-1 and other read bit lines RBL-n, and outputs a high level to the transistor M45 , the transistor M45 is turned on, so that the global bit line GBL is connected to the ground GND through the transistor M45, and the level of the global bit line GBL begins to decrease.
  • the The input/output circuit can determine that the storage information of the storage unit c1 is at a low level.
  • the control terminal of the transistor M42 can also receive a high level, the transistor M42 is turned off, and the power supply Vdd stops charging the read bit line RBL-1.
  • the transistor M42 is always turned on, and the power supply Vdd charges the read bit line RBL-1, which affects the read bit line RBL-1.
  • the falling speed of the bit line RBL-1 causes the reading speed of the single-ended memory to slow down.
  • a single-ended memory it may also include a leakage current compensation unit, a precharge unit, and a NAND gate corresponding to other read bit lines RBL-n one-to-one.
  • the leakage current compensation unit, precharge unit and NAND gate corresponding to the one read bit line work.
  • the single-ended memory may also include a leakage current compensation unit and a precharge unit corresponding to other read bit lines RBL-n one by one, and the control terminal of each leakage current compensation unit is connected to the output terminal of the NAND gate 401 through a switch
  • the switch connected to the corresponding leakage current compensation unit on the one read bit line is turned on, and the corresponding leakage current compensation unit on the one read bit line works.
  • FIG. 6 is a schematic structural diagram of a single-ended memory provided by an embodiment of the present application.
  • the single-ended memory includes memory cells 601 distributed in an array, and the memory cells 601 are connected to the read bit line RBL-1 and the read word line;
  • the read bit line RBL-1 connects the precharge unit (the precharge unit in FIG. 6 takes transistor M62 as an example) through the column selection unit (the column select unit in FIG.
  • the read bit line RBL-1 passes through
  • the column selection unit is connected to the output terminal of the leakage current compensation unit (the leakage current compensation unit in FIG.
  • a feedback signal (feedback) is output to the control terminal of the leakage current compensation unit to stop the leakage current compensation unit from charging the read bit line RBL-1 through the output terminal.
  • the column selection unit of the single-ended memory includes a transistor M61
  • the precharging unit includes a transistor M62
  • the leakage current compensation unit includes a transistor M63 .
  • the read bit line RBL-1 is connected to the memory cell 601 .
  • the power supply Vdd is connected to the first terminal of the transistor M62
  • the second terminal of the transistor M62 is connected to the second terminal of the transistor M61
  • the first terminal of the transistor M61 is connected to the read bit line RBL-1.
  • the read bit line RBL-1 is connected to the control end of the transistor M63 through the feedback circuit 602, the feedback circuit 602 is connected to the transmission path between the storage unit 601 and the transistor M61, the first end of the transistor M63 is connected to the power supply Vdd, and the second end of the transistor M63 The two terminals are connected to the second terminal of the transistor M61.
  • the read bit line RBL-1 is also connected to the first input end of the NAND gate 603, and the memory cells of other columns are connected to the second input end of the NAND gate 603 through other read bit lines RBL-n, and the output of the NAND gate 603 terminal is connected to the control terminal of the transistor M64, the first terminal of the transistor M64 is connected to the ground GND, and the second terminal of the transistor M64 is connected to the global bit line GBL.
  • column selection unit, pre-charging unit and leakage current compensation unit may also include other more or less electronic components, and their connection relationship may also be simpler or more complex.
  • Read bit line RBL-1 can also be connected to more memory cells.
  • the single-ended memory reads the storage information of the storage unit 601 since the storage unit 601 is connected to the read bit line RBL-1, it is necessary to change the column selection signal S2 from low level to high level first. Ping, the control transistor M61 is turned on, indicating that the read bit line RBL-1 is selected. Then, the precharge signal S3 changes from a high level to a low level, and the control transistor M62 is turned on, and the read bit line RBL-1 is connected to the power supply Vdd through the transistor M61 and the transistor M62, and the power supply Vdd charges the read bit line RBL-1, so that Read bit line RBL-1 is high.
  • the precharge signal S3 changes from a low level to a high level
  • the control transistor M62 is turned off
  • the power supply Vdd stops charging the read bit line RBL-1
  • the read bit line RBL-1 maintains a high level.
  • the read word line selects the memory cell 601, and the memory cell 601 outputs storage information to the read bit line RBL-1.
  • the level of the read bit line RBL-1 will start to drop.
  • the feedback circuit 602 after determining that the level of the read bit line RBL-1 has dropped to the first predetermined value, will control the transistor M63 terminal outputs the feedback signal S4, and the control transistor M63 is turned off (for example, when the transistor M63 is a P-type transistor, the feedback signal S4 is at a high level; when the transistor M63 is an N-type transistor, the feedback signal S4 is at a low level), and the transistor M63
  • the read bit line RBL-1 is disconnected from the power supply Vdd, the power supply Vdd stops charging the read bit line RBL-1, and the level of the read bit line RBL-1 decreases to a low level.
  • the level of read bit line RBL-1 is low level, other read bit lines RBL-n keep high level all the time, then through the NAND processing of NAND gate 603, the output end of NAND gate 603 outputs high level
  • the global bit line GBL is connected to the ground GND through the transistor M64, the level of the global bit line GBL will gradually decrease to a low level, and the input/output circuit coupled with the global bit line GBL can determine the global bit line If the level of the line GBL is low level, it can also be determined that the storage information in the currently selected storage unit 601 is low level.
  • the precharge unit charges the read bit line through the column selection unit, and the read bit line remains at a high level. If selected, the storage unit outputs storage information to the read bit line. When the stored information is at a low level, the level of the read bit line also begins to decrease, and the feedback circuit outputs a feedback signal to the control terminal of the leakage current compensation unit after determining that the level of the read bit line is lower than a predetermined value. The signal can stop the leakage current compensation unit from charging the read bit line through the output terminal.
  • the leakage current compensation unit of the single-ended memory is controlled by the feedback signal output by the feedback circuit, and the feedback signal output by the feedback circuit is changed in time according to the level change of the read bit line, so that the leakage current compensation unit can be more timely Closed, because the current compensation unit is stopped in time to charge the read bit line, so the level of the read bit line can be lowered faster under the effect of the stored information being low, so that the single-ended memory can be read faster Since the stored information is read on the bit line, the reading speed of the single-ended memory becomes fast.
  • the storage information in the storage unit 601 is at a high level (for example, as shown in FIG. 4, the transistor M44 in the storage unit c1 is turned off, and the storage unit c1 outputs a high voltage to the read bit line RBL-1. level, when the memory cell 601 is the same as the memory cell c1), the read bit line RBL-1 maintains a high level, but other unselected memory cells connected to the current read bit line RBL-1 will leak electricity, resulting in leakage current.
  • the feedback circuit 602 connected to the read bit line RBL-1, when determining that the level of the read bit line RBL-1 is higher than the second predetermined value, outputs the feedback signal S4 to the control terminal of the transistor M63, and controls the transistor M63 to turn on (Exemplary, when the transistor M63 is a P-type transistor, the feedback signal S4 is low level; when the transistor M63 is an N-type transistor, the feedback signal S4 is high level), the read bit line RBL-1 passes through the transistor M63 and the transistor M61 Connected to the power supply Vdd, the power supply Vdd charges the read bit line RBL-1, and compensates the leakage current generated by the unselected memory cells on the read bit line RBL-1, so that the read bit line RBL-1 maintains a high level.
  • the output end of the NAND gate 603 outputs a low level through the NAND processing of the NAND gate 603, so as to control the closing of the transistor M64, and the global bit line GBL will not Connect the ground GND through the transistor M64, the level of the global bit line GBL maintains the initial high level, and the input/output circuit coupled with the global bit line GBL can determine that the level of the global bit line GBL is high level, or can determine The storage information in the currently selected storage unit 601 is at a high level.
  • the above-mentioned first predetermined value is less than or equal to the above-mentioned second predetermined value.
  • the first predetermined value needs to be greater than the low level, and only when the first predetermined value is greater than the low level, the feedback circuit 602 can send a signal to the transistor M63 before the level of the read bit line RBL-1 drops to the low level. The feedback signal is output, and the power supply Vdd is stopped to charge the read bit line RBL-1 through the transistor M63.
  • the second predetermined value also needs to be less than the high level, and only when the second predetermined value is less than the high level, then when the level of the read bit line RBL-1 decreases due to the generation of leakage current, the feedback circuit 602 can output a feedback signal to the transistor M63 , the control power supply Vdd charges the read bit line RBL-1 through the transistor M63.
  • the read bit line when the storage information of the selected memory cell is at a high level, the read bit line will maintain a high level, and when the feedback circuit determines that the level of the read bit line is higher than the second predetermined value, it will compensate the leakage current.
  • the control terminal of the unit outputs a feedback signal, which can control the leakage current compensation unit to charge the read bit line through the output terminal, and compensate the leakage current generated by other storage units on the read bit line. Since the feedback signal output by the feedback circuit can also control the leakage current compensation unit to be turned on in time, it can also ensure the reading performance of the single-ended memory to read and store information at a high level.
  • the above feedback circuit includes: an inverter.
  • the input end of the inverter is connected to the read bit line, and the output end of the inverter is connected to the control end of the leakage current compensation unit; wherein the inverter is used to generate a feedback signal according to the level of the read bit line to control the leakage current compensation unit Turn on or off in time.
  • the inverter in the feedback circuit 602 includes: a first transistor and a second transistor (such an inverter is also called a pull-bias inverter).
  • the embodiment of the present application provides a schematic structural diagram of a single-ended memory.
  • the specific structure of the inverter in the feedback circuit 602 is shown in detail, wherein , the inverter in the feedback circuit 602 shown in FIG. 7 includes a transistor Mf1 (that is, the above-mentioned first transistor, and the transistor Mf1 is an example of a P-type transistor) and a transistor Mf2 (that is, the above-mentioned second transistor, the transistor Mf2 takes an N-type transistor as an example).
  • the first end of the transistor Mf1 is connected to the power supply Vdd
  • the second end of the transistor Mf1 is connected to the first end of the transistor Mf2
  • the second end of the transistor Mf2 is connected to the ground GND
  • the control end of the transistor Mf1 is connected to the control end of the transistor Mf2
  • the feedback circuit 602 includes The input end of the inverter; the second end of the transistor Mf1 is also connected to the output end of the inverter included in the feedback circuit 602 .
  • the storage unit 601 When the single-ended memory reads the stored information in the storage unit 601, the stored information is at a high level, and the storage unit 601 outputs a high level to the read bit line RBL-1, although at this time the voltage of the read bit line RBL-1 The level will decrease due to the existence of the leakage current, but when the level of the read bit line RBL-1 is between the second predetermined value and the high level, the level of the input terminal of the inverter included in the feedback circuit 602 is considered to be High level, so that the level of the control terminal of the transistor Mf1 is high level, the transistor Mf1 is turned off, and the level of the control terminal of the transistor Mf2 is high level, and the transistor Mf2 is turned on.
  • the feedback circuit 602 feeds the leakage current compensation unit (that is, the transistor M63.
  • the feedback signal S4 output by the control terminal of the transistor M63 (take a P-type transistor as an example) is low level, so as to control the transistor M63 to turn on, and the read bit line RBL-1 is connected to the power supply Vdd through the transistor M63, and the power supply Vdd is the read bit line RBL-1 is charged, and the read bit line RBL-1 remains high.
  • the storage information is at a low level, and the storage unit 601 outputs a low level to the read bit line RBL-1, and the level of the read bit line RBL-1 begins to decrease , when the level of the read bit line RBL-1 drops to a first predetermined value, the level of the input terminal of the inverter included in the feedback circuit 602 is considered to be low level, so that the level of the control terminal of the transistor Mf1 is low level , the transistor Mf1 is turned on, the level of the control terminal of the transistor Mf2 is low level, and the transistor Mf2 is turned off.
  • the feedback circuit 602 feeds the leakage current compensation unit (that is, the transistor M63.
  • the feedback signal S4 output by the control terminal of the transistor M63 (take a P-type transistor as an example) is high level, so as to control the transistor M63 to turn off, the read bit line RBL-1 will not be connected to the power supply Vdd through the transistor M63, and the power supply Vdd will not To charge the read bit line RBL-1, the level of the read bit line RBL-1 continues to drop to a low level.
  • the embodiment of the present application provides a schematic structural diagram of a single-ended memory.
  • the inversion in the feedback circuit 602 is shown in detail
  • the inverter in the feedback circuit 602 includes: a third transistor, a fourth transistor, a fifth transistor and a sixth transistor (such an inverter is also called a half-Schmitt inverter ).
  • the inverter in the feedback circuit 602 includes a transistor Mf3 (that is, the above-mentioned third transistor, and the transistor Mf3 is an example of a P-type transistor), a transistor Mf4 (that is, the above-mentioned fourth transistor , the transistor Mf4 takes an N-type transistor as an example), the transistor Mf5 (that is, the above-mentioned fifth transistor, and the transistor Mf5 takes an N-type transistor as an example) and the transistor Mf6 (that is, the above-mentioned sixth transistor, and the transistor Mf6 takes an N-type transistor as an example) type transistors as an example).
  • a transistor Mf3 that is, the above-mentioned third transistor, and the transistor Mf3 is an example of a P-type transistor
  • a transistor Mf4 that is, the above-mentioned fourth transistor , the transistor Mf4 takes an N-type transistor as an example
  • the transistor Mf5 that is, the above-mentioned fifth transistor
  • the first end of the transistor Mf3 is connected to the power supply Vdd
  • the second end of the transistor Mf3 is connected to the first end of the transistor Mf4
  • the second end of the transistor Mf4 is connected to the first end of the transistor Mf5
  • the second end of the transistor Mf5 is connected to the ground GND
  • the transistor Mf6 The first end of the transistor Mf4 is connected to the second end of the transistor Mf6, the control end of the transistor Mf6 is connected to the second end of the transistor Mf3, and the second end of the transistor Mf6 is connected to the power supply Vdd;
  • the control end of the transistor Mf3, the control end of the transistor Mf4 and the transistor Mf5 The control terminal is connected to the input terminal of the inverter included in the feedback circuit 602 ; the second terminal of the transistor Mf3 is also connected to the output terminal of the inverter included in the feedback circuit 602 .
  • the storage unit 601 When the single-ended memory reads the stored information in the storage unit 601, the stored information is at a high level, and the storage unit 601 outputs a high level to the read bit line RBL-1, although at this time the voltage of the read bit line RBL-1 The level will decrease due to the existence of the leakage current, but the level of the read bit line RBL-1 is at a second predetermined value (the second predetermined value may be the positive threshold voltage of the half-Smitt inverter) and a high level In between, the input levels of the inverters included in the feedback circuit 602 are all considered to be high level, so that the control terminal level of the transistor Mf3 is high level, the transistor Mf3 is turned off, and the control terminals of the transistor Mf4 and the transistor Mf5 The terminal level is high level, and the transistor Mf4 and the transistor Mf5 are turned on.
  • the second predetermined value may be the positive threshold voltage of the half-Smitt inverter
  • the transistor Mf3 Since the transistor Mf3 is turned off, the transistor Mf4 and the transistor Mf5 are turned on, so that the second end of the transistor Mf3 is connected to the ground GND, the level of the second end of the transistor Mf3 is a low level, and the second end of the transistor Mf3 is connected to the control end of the transistor Mf6 The level is also low level, and the transistor Mf6 is turned off.
  • the output level of the output terminal of the inverter is low level, at this time, the feedback signal S4 outputted by the feedback circuit 602 to the control terminal of the leakage current compensation unit (that is, the transistor M63, the transistor M63 is a P-type transistor as an example) is low level, thereby controlling the transistor M63 to turn on, the read bit line RBL-1 is connected to the power supply Vdd through the transistor M63, the power supply Vdd charges the read bit line RBL-1, and the read bit line RBL-1 maintains a high level.
  • the feedback signal S4 outputted by the feedback circuit 602 to the control terminal of the leakage current compensation unit that is, the transistor M63, the transistor M63 is a P-type transistor as an example
  • the storage information is at a low level, and the storage unit 601 outputs a low level to the read bit line RBL-1, and the level of the read bit line RBL-1 begins to decrease , when the level of the read bit line RBL-1 drops to a first predetermined value (the first predetermined value may be the negative threshold voltage of the half-Smitt inverter), the input terminal of the inverter included in the feedback circuit 602
  • the level is considered to be low level, so that the control terminal level of the transistor Mf3 is low level, and the transistor Mf3 is turned on, and when the control terminal levels of the transistor Mf4 and the transistor Mf5 are low level, the transistor Mf4 and the transistor Mf5 are turned off.
  • the transistor Mf3 is turned on, the transistor Mf4 and the transistor Mf5 are turned off, so that the second end of the transistor Mf3 is connected to the power supply Vdd, the level of the second end of the transistor Mf3 is a high level, and the second end of the transistor Mf3 is connected to the control end of the transistor Mf6
  • the level is high, the transistor Mf6 is turned on, and the second terminal of the transistor Mf4 is also connected to the power supply Vdd through the transistor Mf6, so that the second terminal of the transistor Mf3 maintains a high level.
  • the output level of the output terminal of the inverter is a high level, and at this time, the feedback signal S4 output by the feedback circuit 602 to the control terminal of the leakage current compensation unit (that is, the transistor M63, the transistor M63 is a P-type transistor as an example) is high level, so as to control the transistor M63 to turn off, the read bit line RBL-1 cannot be connected to the power supply Vdd through the transistor M63, the power supply Vdd will not charge the read bit line RBL-1, and the level of the read bit line RBL-1 continues reduced to low level.
  • the feedback signal S4 output by the feedback circuit 602 to the control terminal of the leakage current compensation unit that is, the transistor M63, the transistor M63 is a P-type transistor as an example
  • the feedback circuit 602 can also generate a feedback signal according to the level of the read bit line by setting a logic gate circuit. Referring to FIG. In the single-ended memory shown, the feedback circuit 602 includes: a first NOR gate and a first NOT gate.
  • the feedback circuit 602 of the single-ended memory includes a NOT gate 6020 (that is, the above-mentioned first NOT gate) and a NOR gate 6021 (that is, the above-mentioned first NOR gate), and the NOT gate
  • the input terminal of the 6020 is connected to the control terminal of the transistor M61 (that is, the above-mentioned column selection unit, the transistor M61 is an N-type transistor as an example), and the output terminal of the NOT gate 6020 is connected to the first input terminal of the NOR gate 6021;
  • the second input terminal of 6021 is connected to the read bit line RBL-1; the output terminal of the NOR gate 6021 is connected to the control terminal of the leakage current compensation unit (that is, the transistor M63, which is a P-type transistor for example).
  • the input terminal of the NOT gate 6020 is connected to the control terminal of the column selection unit, which specifically means that the control terminal of the transistor M61 inputs the column selection signal S2, and the input terminal of the NOT gate 6020 also inputs the column selection unit. Signal S2.
  • the storage unit 601 When the single-ended memory reads the stored information in the storage unit 601, the stored information is at a high level, and the storage unit 601 outputs a high level to the read bit line RBL-1, although at this time the voltage of the read bit line RBL-1 The level will decrease due to the existence of the leakage current, but when the level of the read bit line RBL-1 is between the second predetermined value and the high level, the voltage input by the second input terminal of the NOR gate 6021 included in the feedback circuit 602 level is considered a high level.
  • the column selection signal S2 Since the column selection signal S2 will be high level when the read data occurs, the level of the column selection signal S2 output to the first input end of the NOR gate 6021 through the NOR gate 6020 is low level, and the NOR gate 6021 performs NOR operation, so that the output terminal of the NOR gate 6021 is at low level, at this time, the feedback signal S4 output from the feedback circuit 602 to the control terminal of the transistor M63 is at low level, the transistor M63 is turned on, and the read bit line RBL-1 passes through the transistor M63 is connected to the power supply Vdd, the power supply Vdd charges the read bit line RBL-1, and the read bit line RBL-1 maintains a high level.
  • the storage information is at a low level, and the storage unit 601 outputs a low level to the read bit line RBL-1, and the level of the read bit line RBL-1 begins to decrease
  • the level input to the second input terminal of the NOR gate 6021 included in the feedback circuit 602 is regarded as a low level.
  • the column selection signal S2 Since the column selection signal S2 will be high level when the read data occurs, the level of the column selection signal S2 output to the first input end of the NOR gate 6021 through the NOR gate 6020 is low level, and the NOR gate 6021 performs NOR operation, so that the output end of the NOR gate 6021 is at a high level, at this time the feedback signal S4 output by the feedback circuit 602 to the control end of the transistor M63 is at a high level, the transistor M63 is turned off, and the read bit line RBL-1 will not The transistor M63 is connected to the power supply Vdd, the power supply Vdd no longer charges the read bit line RBL-1, and the level of the read bit line RBL-1 continues to drop to a low level.
  • the leakage current compensation unit of the single-ended memory may be connected to the read bit line through the first switch unit, and the control terminal of the first switch unit is connected to the control terminal of the column selection unit.
  • the embodiment of the present application provides a schematic structural diagram of a single-ended memory, which also includes a transistor M65 (that is, the above-mentioned first switch unit, and the transistor M65 is an N-type transistor example).
  • a transistor M65 that is, the above-mentioned first switch unit, and the transistor M65 is an N-type transistor example.
  • the first end of the transistor M65 is connected to the second end of the transistor M63 (that is, the above-mentioned leakage current compensation unit, the transistor M63 is a P-type transistor as an example), the first end of the transistor M63 is connected to the power supply Vdd, and the first end of the transistor M65
  • the two terminals are connected to the second terminal of the transistor M61 (that is, the column selection unit mentioned above, the transistor M61 is an N-type transistor for example), and the first terminal of the transistor M61 is connected to the read bit line RBL-1.
  • the control terminal of the above-mentioned first switch unit connected to the control terminal of the column selection unit means that the input of the control terminal of the column selection unit is the column selection signal S2, and the input of the control terminal of the transistor M65 is also the column selection signal S2.
  • the column selection signal S2 will be set to a high level, so the levels of the control terminals of the transistor M61 and the transistor M65 are high, and the transistor M61 and the transistor M65 are turned on.
  • Power supply Vdd is connected to read bit line RBL-1 through transistor M61, transistor M65 and transistor M63.
  • the column select single-ended control terminal signal also controls the opening or closing of the first switch unit at the same time, it is ensured that when the column selection unit is turned on by the signal of its control terminal to select the read bit line, the first switch unit can be opened at the same time to reduce the leakage current.
  • the current compensation unit is connected to the read bit line, so that the leakage current compensation unit can compensate or stop the compensation for the level of the read bit line in time when the read bit line is selected, and realizes that the leakage current compensation unit is self-adaptive when the read bit line is selected work.
  • an embodiment of the present application provides a single-ended memory.
  • the single-ended memory also includes: a discharge unit, the control terminal of the discharge unit is connected to the control terminal of the leakage current compensation unit; the first terminal of the discharge unit is connected to the read bit line through the column selection unit; the second terminal of the discharge unit is connected to the ground.
  • the embodiment of the present application provides a schematic structural diagram of a single-ended memory.
  • the single-ended memory also includes a discharge unit 604, and the discharge unit 604 includes a transistor Md1 (the transistor Md1 is an N-type transistor as an example).
  • the control terminal of the transistor Md1 is connected to the control terminal of the leakage current compensation unit (that is, the transistor M63, the transistor M63 is a P-type transistor as an example), the second terminal of the transistor Md1 is connected to the ground GND, and the first terminal of the transistor Md1 is connected to the transistor M61 (That is, the above-mentioned column selection unit, the transistor M61 is an N-type transistor as an example), the second terminal of the transistor M61 is connected to the read bit line RBL-1.
  • the storage unit 601 When the single-ended memory reads the storage information in the storage unit 601, the storage information is at a high level, the storage unit 601 outputs a high level to the read bit line RBL-1, and the feedback circuit 602 determines the read bit line RBL-1 When the level is higher than the second predetermined value, the feedback signal S4 is output to the control terminal of the transistor M63, the feedback signal S4 is low level, and the transistor M63 is turned on to control the power supply Vdd to charge the read bit line RBL-1 through the transistor M63 , so that the read bit line RBL-1 maintains a high level.
  • control terminal of the transistor Md1 also receives the feedback signal S4, because the feedback signal S4 is low, so the transistor Md1 is turned off, and the read bit line RBL-1 will not be connected to the ground GND through the transistor Md1 to ensure the read bit Line RBL-1 remains high.
  • the storage information is at a low level, and the storage unit 601 outputs a low level to the read bit line RBL-1, and the level of the read bit line RBL-1 begins to decrease
  • the feedback circuit 602 outputs a feedback signal S4 to the control terminal of the transistor M63, the feedback signal S4 is at a high level, and the transistor M63 is turned off to stop the power supply Vdd from passing through
  • the transistor M63 charges the read bit line RBL-1, so that the level of the read bit line RBL-1 continues to drop to a low level.
  • the control terminal of the transistor Md1 also receives the feedback signal S4, because the feedback signal S4 is at a high level, the transistor Md1 is turned on, and the read bit line RBL-1 is connected to the ground GND through the transistor Md1, and the read bit line RBL- The level of 1 decreases, and the transistor Md1 makes the level of the read bit line RBL-1 decrease faster.
  • Such a single-ended memory ensures that the level of the read bit line RBL-1 can be reduced to a low level as soon as possible when the stored information is at a low level through the synergistic effect of the transistor M63 and the transistor Md1, thereby increasing the reading speed of the single-ended memory.
  • the embodiment of the application also provides a discharge unit of a single-ended memory, and the discharge unit of the single-ended memory includes a seventh transistor and an eighth transistor.
  • the embodiment of the present application provides a schematic structural diagram of a single-ended memory.
  • the discharge unit 604 includes a transistor Md2 (that is, the above-mentioned seventh transistor, and the transistor Md2 is an N-type transistor for example) and a transistor Md3 (that is, the above-mentioned eighth transistor, and the transistor Md3 is an N-type transistor for example).
  • the control terminal of the transistor Md2 is connected to the control terminal of the transistor M63 (that is, the above-mentioned leakage current compensation unit is connected, and the transistor M63 is an example of a P-type transistor), and the first terminal of the transistor Md2 is connected to the second terminal of the transistor M61 (that is, the above-mentioned
  • the column selection unit of the transistor M61 is an N-type transistor as an example), the first end of the transistor M61 is connected to the read bit line RBL-1, the second end of the transistor Md2 is connected to the control end of the transistor Md3, and the second end of the transistor Md2 is connected to the control end of the transistor Md3.
  • the first end of the transistor Md3 is connected, and the second end of the transistor Md3 is connected to the ground.
  • the storage unit 601 When the single-ended memory reads the storage information in the storage unit 601, the storage information is at a high level, the storage unit 601 outputs a high level to the read bit line RBL-1, and the feedback circuit 602 determines the read bit line RBL-1 When the level is higher than the second predetermined value, the feedback signal S4 is output to the control terminal of the transistor M63, the feedback signal S4 is low level, and the transistor M63 is turned on to control the power supply Vdd to charge the read bit line RBL-1 through the transistor M63 , so that the read bit line RBL-1 maintains a high level.
  • the control terminal of the transistor Md2 also receives the feedback signal S4, because the feedback signal S4 is at a low level, the transistor Md2 is turned off, and since the second terminal of the transistor Md2 is connected to the control terminal of the transistor Md3, the transistor Md3 is also turned off,
  • the read bit line RBL-1 is not connected to the ground GND through the transistor Md2 and the transistor Md3 to ensure that the read bit line RBL-1 maintains a high level.
  • the storage information is at a low level, and the storage unit 601 outputs a low level to the read bit line RBL-1, and the level of the read bit line RBL-1 begins to decrease
  • the feedback circuit 602 outputs a feedback signal S4 to the control terminal of the transistor M63, the feedback signal S4 is at a high level, and the transistor M63 is turned off to stop the power supply Vdd from passing through
  • the transistor M63 charges the read bit line RBL-1, so that the level of the read bit line RBL-1 continues to drop to a low level.
  • the control terminal of the transistor Md2 also receives the feedback signal S4, because the feedback signal S4 is high level, so the transistor Md2 is turned on, because the second terminal of the transistor Md2 is connected to the control terminal and the first terminal of the transistor Md3, the transistor Md3 The second end of the second terminal is connected to the ground GND, which proves that the discharge unit 604 is connected to the ground GND through the transistor Md2 and the transistor Md3 at this time.
  • the connection method of the transistor Md2 and the transistor Md3 will make the equivalent resistance of the current discharge unit 604 larger. , then the discharge rate of the discharge unit 604 will slow down.
  • the discharge unit 604 set in this way will not directly connect the read bit line RBL-1 to the ground, causing the problem of reading the stored information incorrectly , making the reading performance of the single-ended memory more stable.
  • the single-ended memory includes a second NOT gate
  • the discharge unit includes: a ninth transistor
  • the embodiment of the present application provides a schematic structural diagram of a single-ended memory.
  • the discharge unit 604 includes a transistor Md4 (that is, the above-mentioned ninth transistor, and the transistor Md4 is a P-type transistor as an example).
  • the single-ended memory also includes a NOT gate 605 (that is, the above-mentioned second NOT gate), and the control terminal of the transistor M63 (that is, the above-mentioned leakage current compensation unit, the transistor M63 is a P-type transistor) is connected to the NOT gate 605
  • the input terminal of the inverting gate 605 is connected to the control terminal of the transistor Md4
  • the second terminal of the transistor Md4 is connected to the ground GND
  • the first terminal of the transistor Md4 is connected to the second terminal of the transistor M61 (that is, the above-mentioned column selection unit,
  • the transistor M61 is an N-type transistor for example), and the first end of the transistor M61 is connected to the read bit line RBL-1.
  • the storage unit 601 When the single-ended memory reads the storage information in the storage unit 601, the storage information is at a high level, the storage unit 601 outputs a high level to the read bit line RBL-1, and the feedback circuit 602 determines the read bit line RBL-1 When the level is higher than the second predetermined value, the feedback signal S4 is output to the control terminal of the transistor M63, the feedback signal S4 is low level, and the transistor M63 is turned on to control the power supply Vdd to charge the read bit line RBL-1 through the transistor M63 , so that the read bit line RBL-1 maintains a high level.
  • the feedback signal S4 becomes high level through the negation operation of the inverting gate 605, and is input to the control terminal of the transistor Md4, the transistor Md4 is turned off, and the read bit line RBL-1 is not connected to the ground GND through the transistor Md4, so that Make sure the read bit line RBL-1 remains high.
  • the storage information is at a low level, and the storage unit 601 outputs a low level to the read bit line RBL-1, and the level of the read bit line RBL-1 begins to decrease
  • the feedback circuit 602 outputs a feedback signal S4 to the control terminal of the transistor M63, the feedback signal S4 is at a high level, and the transistor M63 is turned off to stop the power supply Vdd from passing through
  • the transistor M63 charges the read bit line RBL-1, so that the level of the read bit line RBL-1 continues to drop to a low level.
  • the feedback signal S4 becomes low level through the NOT gate 605, and is input to the control terminal of the transistor Md4, the transistor Md4 is turned on, and the read bit line RBL-1 is connected to the ground GND through the transistor Md4, however, since the transistor Md4 is The P-type transistor, when the P-type transistor transfers the level, there will be a threshold loss, which also slows down the discharge speed of the discharge unit 604 . If the level of the current read bit line RBL-1 is lowered due to the existence of leakage current, the discharge unit 604 set in this way will not directly lower the level of the read bit line RBL-1 to a low level, so that the single-ended The memory read performance is more stable.
  • the embodiment of the present application also provides a single-ended memory, and the single-ended memory is further provided with a second switch unit between the first end of the discharge unit and the column selection unit.
  • the embodiment of the present application provides a schematic structural diagram of a single-ended memory, which also includes a transistor M66 (that is, the above-mentioned second switch unit, and the transistor M66 is an N-type transistor example).
  • the first end of the discharge unit 604 is connected to the second end of the transistor M66, and the first end of the transistor M66 is connected to the second end of the transistor M61 (that is, the above-mentioned column selection unit, the transistor M61 is an N-type transistor as an example), and the transistor M61 is an N-type transistor.
  • the first end of M61 is connected to the read bit line RBL-1.
  • control terminal of the transistor M66 can be connected to the tracking circuit (tracking) of the single-ended memory, wherein the tracking circuit can track the level change on the global bit line GBL, and before the global bit line GBL reads a low level, the The transistor M66 is turned on; before the global bit line GBL reads a high level, the transistor M66 is turned off. Specifically, before the global bit line GBL reads a low level, a high level can be output to the control terminal of M66 in advance of the time of ⁇ t1 to control the transistor M66 to turn on, and the discharge unit 604 is connected to the read bit line RBL through the transistor M66 and the transistor M61.
  • the discharge unit 604 will accelerate the discharge of the read bit line RBL-1, so that the read bit line RBL-1 will fall to the low level faster.
  • a low level can be output to the control terminal of the transistor M66 in advance of the time amount of ⁇ t2 to control the transistor M66 to be turned off, and the discharge unit 604 cannot be read through the connection between the transistor M66 and the transistor M61.
  • the discharge unit 604 will not discharge the read bit line RBL-1 to ensure that the single-ended memory read Take the storage information as a high-level performance.
  • the above-mentioned time amount of ⁇ t1 and the above-mentioned time amount of ⁇ t2 may be configured by default or adaptively adjusted.
  • the control terminal of the transistor M66 can be connected to the external test pin of the single-ended memory.
  • the transistor M66 can be controlled to be turned off through the external test tube transmission low level, so that the discharge unit 604 cannot be connected to the read bit line RBL-1 through the transistor M66 and the transistor M61, if When the level of the current read bit line RBL-1 is lowered due to the generation of leakage current, the discharge unit 604 will not discharge the read bit line RBL-1 to ensure that the single-ended memory reads and stores information at a high level performance.
  • the transistor M66 when reading the stored information of the storage unit 601, the transistor M66 can be controlled to be turned on through the high-level transmission of the external test tube, so that the discharge unit 604 is connected to the read bit line RBL-1 through the transistor M66 and the transistor M61, and discharges Cell 604 will accelerate the discharge of the read bit line RBL-1, so that the read bit line RBL-1 falls to the low level faster.
  • control terminal of the discharge unit can be controlled to be turned on or off through a circuit connection structure similar to the feedback circuit 602 .
  • the single-ended memory further includes: a second NOR gate and a third NOT gate.
  • FIG. 15 is a schematic structural diagram of a single-ended memory provided by an embodiment of the present application.
  • the single-ended memory also includes a NOT gate 606 (that is, the third NOT gate mentioned above) and a NOR gate 607.
  • the input terminal of the NOT gate 606 is connected to the control terminal of the transistor M61 (that is, the above-mentioned column selection unit, and the transistor M61 is an N-type transistor as an example), and the output terminal of the NOT gate 606 connected to the first input terminal of the NOR gate 607 , the read bit line RBL- 1 is connected to the second input terminal of the NOR gate 607 , and the output terminal of the NOR gate 607 is connected to the control terminal of the discharge unit 604 .
  • the input terminal of the NOT gate 606 is connected to the control terminal of the column selection unit, which specifically means that the control terminal of the transistor M61 inputs the column selection signal S2, and the input terminal of the NOT gate 606 also inputs the column selection signal. Signal S2.
  • the storage unit 601 When the single-ended memory reads the stored information in the storage unit 601, the stored information is at a high level, and the storage unit 601 outputs a high level to the read bit line RBL-1, although at this time the voltage of the read bit line RBL-1 The level will decrease due to the existence of the leakage current, but when the level of the read bit line RBL-1 is between the second predetermined value and the high level, the level input by the second input terminal of the NOR gate 607 is considered to be high level.
  • the level at which the column selection signal S2 is output to the first input terminal of the NOR gate 607 through the NOT gate 606 is at a low level, and the NOR gate 607 performs an OR The non-operation makes the level transmitted from the NOR gate 607 to the control terminal of the discharge unit 604 be low level.
  • the storage information is at a low level, and the storage unit 601 outputs a low level to the read bit line RBL-1, and the level of the read bit line RBL-1 begins to decrease , when the level of the read bit line RBL-1 drops to the first predetermined value, the level input to the second input terminal of the NOR gate 607 is considered to be a low level.
  • the level at which the column selection signal S2 is output to the first input terminal of the NOR gate 607 through the NOT gate 606 is at a low level, and the NOR gate 607 performs an OR The non-operation makes the level transmitted from the NOR gate 607 to the control terminal of the discharge unit 604 be a high level.
  • the low level transmitted by the NOR gate 607 to the control terminal of the discharge unit 604 may be to control the transistor in the discharge unit 604 to turn on (a P-type transistor is set in the discharge unit 604) to discharge, or to control the discharge unit
  • the transistor in 604 is turned off (the N-type transistor is set in the discharge unit 604 ) and no discharge is performed.
  • the high level transmitted by the NOR gate 607 to the control terminal of the discharge unit 604 can be to control the transistor in the discharge unit 604 to turn on (the N-type transistor is set in the discharge unit 604) to discharge, or to control the transistor in the discharge unit 604 to turn off (A P-type transistor is provided in the discharge unit 604) No discharge is performed.
  • the feedback circuit 602 of the single-ended memory includes an inverter
  • the discharge unit 604 when the discharge unit 604 is set, by selecting a slow N-type transistor and a fast P-type transistor process angle (slow NMOS fast PMOS concer, SNFP concer), The level is set to 0.6 volts and the temperature is set to -40 degrees Celsius. Or select a typical process angle (tipical concer, TT concer), set the level to 1.2 volts, set the temperature to 25 degrees Celsius, and simulate the feedback signal and read time of the single-ended memory.
  • the simulation diagrams are shown in Figure 16 and Figure 17 .
  • the read bit line RBL-1 is strobed, and at the time t1, the pre-charge unit M41 is turned on, and the pre-charge unit M41 sends a charge to the read bit line RBL -1 is charged, and at the same time the levels of other read bit lines RBL-n and global bit line GBL are also rising continuously. That is, from the time t1 to the time t2 of the curve 1, the level of the global bit line GBL continuously rises to the high level.
  • the read word line selects the storage unit c1, and the storage unit c1 outputs low-level storage information to the read bit line RBL-1, and the low-level storage information is low level so that the level of the read bit line RBL-1 keeps decreasing.
  • the level of the read bit line RBL-1 is lowered to a low level
  • the level of the read bit line RBL-1 received by the first end of the NAND gate 401 is high level
  • the second end of the NAND gate 401 The level of other read bit lines RBL-n received by the terminal is high level
  • the NAND gate 401 performs the NAND operation to output a low level, so that the control terminal level of the transistor M42 is low level, the transistor M42 is turned on, and the read bit
  • the line RBL-1 is connected to the power supply Vdd through the transistor M42, the power supply Vdd charges the read bit line RBL-1, and the level of the read bit line RBL-1 decreases slowly.
  • the NAND gate 401 When the level of the read bit line RBL-1 drops to a low level, the NAND gate 401 performs a NAND operation to output a high level, the transistor M42 is turned off, and the transistor M45 is turned on, and the global bit line GBL is connected to the ground through the transistor M45, so that the global bit line
  • the level of the line GBL keeps decreasing, that is, from time t3 to time t6, the level of the global bit line GBL keeps decreasing to a low level.
  • the input/output circuit coupled with the global bit line GBL can determine that the current level of the global bit line GBL is low level, and can also determine that the current storage information of the storage unit c1 is low level.
  • the pre-charge unit M62 At time t1, the pre-charge unit M62 is turned on, the pre-charge unit M62 charges the read bit line RBL-1, and the level of the read bit line RBL-1 continues to rise, while the other read bit lines RBL-n and global bits
  • the level of the line GBL also keeps rising, that is, from the time t1 to the time t3 of the curve 1, the level of the global bit line GBL keeps rising to the high level.
  • the feedback circuit 602 determines that the level of the read bit line RBL-1 is higher than the second predetermined value, it outputs a feedback signal to the control terminal of the leakage current compensation unit M63, so as to control the leakage current compensation unit M63 to send a signal to the read bit line through the output terminal.
  • RBL-1 is charged so that the read bit line RBL-1 remains high.
  • the read word line RWL selects the storage unit 601, and the storage unit 601 outputs stored information to the read bit line RBL-1, and the stored information is at a low level so that the level of the read bit line RBL-1 begins to decrease, because of this
  • the leakage current compensation unit M63 is not turned off, the leakage current compensation unit M63 is still charging the read bit line RBL-1, so that the level of the read bit line RBL-1 decreases slowly.
  • the feedback circuit 602 determines that the level of the read bit line RBL-1 is lower than the first predetermined value, it outputs a feedback signal to the control terminal of the leakage current compensation unit M63, so as to stop the leakage current compensation unit M63 from sending the output signal to the read bit line RBL through the output terminal.
  • the NAND gate 603 performs a NAND operation, the transistor M64 is turned on, and the global bit The line GBL is connected to the ground through the transistor M64, so that the level of the global bit line GBL keeps decreasing, that is, from the time t3 to the time t5, the level of the global bit line GBL keeps decreasing.
  • the level of the read bit line RBL-1 begins to decrease rapidly, and when it is reflected on the global bit line GBL, it can be seen that the level of the global bit line GBL (that is, curve 2) at the time t4 The lowering speed is also significantly faster.
  • the input/output circuit coupled with the global bit line GBL can determine that the level of the global bit line GBL is low level at time t5, and can also determine that the storage information of the current storage unit 601 is low level.
  • the existing single-ended memory takes t6-t1, which is 1.4 nanoseconds, from the arrival of the rising edge of the CLK clock until the global bit line GBL reads the stored information to be at a low level. read time); and the single-ended memory provided by the embodiment of the present application arrives from the rising edge of the CLK clock until the global bit line GBL reads the stored information as a low level, and the time spent is t5-t1, which is 0.8 nanoseconds (The duration is the read time).
  • the reading time of the single-ended memory provided by the embodiment of the present application is improved by 40% compared with the existing single-ended memory.
  • Figure 17 shows the level change of the feedback signal received by the leakage current compensation unit in the existing single-ended memory (curve three), the feedback received by the leakage current compensation unit in the single-ended memory provided by the embodiment of the application Signal level changes (curve 4). Specifically, the reading process of the storage information (low level) of the storage unit of the conventional single-ended memory is described as follows with reference to curve 3 and FIG. 5 .
  • the read bit line RBL-1 is strobed, and at the time t1, the pre-charge unit M41 is turned on, and the pre-charge unit M41 sends a charge to the read bit line RBL -1 charging, the level of the read bit line RBL-1 keeps rising, and the levels of other read bit lines RBL-n and the global bit line GBL also keep rising, and the read bit received by the first end of the NAND gate 401
  • the level of the line RBL-1 is high level
  • the level of other read bit lines RBL-n received by the second end of the NAND gate 401 is high level, and the NAND gate 401 performs a NAND operation and outputs a low level
  • the level of the control terminal of the transistor M42 (that is, the feedback signal received by the transistor M42) is low, and the transistor M42 is turned on, that is, at the time t2', the feedback signal output by the NAND gate 401 to the
  • the level of the read bit line RBL-1 is reduced to low level, the level of the read bit line RBL-1 received by the first end of the NAND gate 401 is low level, and the level of the read bit line RBL-1 received by the first end of the NAND gate 401 is low level, The level of the other read bit lines RBL-n received by the second end is high level, and the NAND gate 401 performs a NAND operation to output a high level, that is, at the time t5', referring to curve 3, the NAND gate 401 is connected to the transistor The control terminal of M42 outputs a feedback signal, and the feedback signal is at a high level to control the transistor M42 to be turned off.
  • the high level output by the NAND gate 401 also turns on the transistor M45, the global bit line GBL starts to discharge through the transistor M45, and the level of the global bit line GBL becomes low.
  • the input/output circuit coupled to the global bit line GBL determines that the stored information of the memory cell c1 is at a low level.
  • a feedback signal is output to the control terminal of the leakage current compensation unit M63, and the feedback signal is at a low level. Referring to curve 4, that is, at time t3', the feedback signal becomes a low level to control the leakage current
  • the current compensation unit M63 charges the read bit line RBL-1 through the output terminal.
  • the storage unit 601 When the read word line RWL selects the storage unit 601, the storage unit 601 outputs storage information to the read bit line RBL-1, and the storage information is at a low level so that the level of the read bit line RBL-1 begins to decrease, and the feedback circuit 602 determines the read
  • a feedback signal is output to the control terminal of the leakage current compensation unit M63, and the feedback signal is at a high level. Referring to curve 4, that is, at time t4', the feedback signal Change to a high level to stop the leakage current compensation unit M63 from charging the read bit line RBL-1 through the output terminal.
  • the level reduction speed of the read bit line RBL-1 becomes faster, and due to the existence of the discharge unit 604, the read bit line The level of line RBL-1 quickly drops to low level.
  • the NAND gate 603 performs a NAND operation to output a high level, then the transistor M64 is turned on, the global bit line GBL is connected to the ground through the transistor M64, the level of the global bit line GBL becomes low, and the input/output circuit coupled with the global bit line GBL The storage information of the read storage unit 601 is low level.
  • the existing single-ended memory arrives from the rising edge of the CLK clock, and the feedback signal changes from high level to low level and then to high level, and the time consumed is t5'-t1, which is 1.47 nanoseconds ; and the single-ended memory provided by the embodiment of the present application arrives from the rising edge of the clock of the column selection signal, and the feedback signal changes from high level to low level and then to high level, and the time consumed is t4'-t1, which is 1.01 nanoseconds.
  • the change time of the feedback signal of the single-ended memory provided by the embodiment of the present application is improved by 46% compared with the existing single-ended memory.
  • the feedback signal of the single-ended memory provided by the embodiment of the present application can change to a high level earlier than the feedback signal of the existing single-ended memory.

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Abstract

本申请提供了一种单端存储器，涉及存储技术领域，可以解决现有的单端存储器的读取速度慢的问题。该单端存储器包括阵列分布的存储单元，存储单元连接读位线以及读字线；读位线通过列选择单元连接预充电单元；读位线通过列选择单元连接漏电电流补偿单元的输出端；读位线还通过反馈电路连接漏电电流补偿单元的控制端；反馈电路在确定读位线的电平低于第一预定值时，向漏电电流补偿单元的控制端输出反馈信号，以停止漏电电流补偿单元通过输出端向读位线充电。

Description

单端存储器 技术领域
本申请涉及存储技术领域，尤其涉及一种单端存储器。
背景技术
单端存储器是一种常见的存储器，其包括阵列分布的存储单元。其中，在单端存储器的一列存储单元中，多个存储单元连接同一条读位线(read bit line，RBL)，并且在该一列存储单元中，每个存储单元还连接一条读字线(read word line，RWL)。在一次读取操作中，读位线RBL首先被设置为高电平，当通过任一存储单元连接的读字线RWL选中该存储单元时，该被选中的存储单元向读位线RBL输出存储信息。该存储信息会影响读位线RBL的电平，从而可以根据读位线RBL上的电平变化确定被选中的存储单元的存储信息。
参照图1所示，提供了一种单端存储器的一列存储单元的电路结构示意图，该单端存储器连接有存储单元1、存储单元2以及存储单元3，存储单元1还连接于读字线RWL1，存储单元2还连接于读字线RWL2，存储单元3还连接于读字线RWL3。读位线RBL还通过预充电单元连接至电源Vdd(图1中预充电单元以晶体管M11为例)，读位线RBL也通过漏电电流补偿单元连接至电源Vdd(图1中漏电电流补偿单元以晶体管M12为例)。
在读取存储单元1的存储信息时，首先晶体管M11开启，读位线RBL通过晶体管M11连接至电源Vdd，电源Vdd对读位线RBL进行充电，使得读位线RBL变为高电平。随后，晶体管M11关闭，读位线RBL保持高电平。读字线RWL1将存储单元1选中，存储单元2和存储单元3则不被选中。因此，存储单元1向读位线RBL输出存储信息，如果此时存储单元1的存储信息为高电平，则存储单元1向读位线RBL输出高电平，读位线RBL会保持高电平。但是，存储单元2和存储单元3会产生漏电电流，该漏电电流的存在会使得读位线RBL的电平降低，严重时会直接影响读取存储单元1的存储信息的准确性。因此，该单端存储器在电路设计时会引入漏电电流补偿单元(也就是晶体管M12)，晶体管M12初始就会开启，读位线RBL通过晶体管M12连接至电源Vdd，电源Vdd对读位线RBL充电，使得读位线RBL的电平升高，补偿读位线RBL由于漏电电流的产生而降低的电平，因此，读位线RBL保持高电平，根据读位线RBL的高电平可以准确确定存储单元1的存储信息为高电平。
如果存储单元1的存储信息为低电平，存储单元1就向读位线RBL输出低电平，则读位线RBL的电平开始降低。但是，此时的晶体管M12没有及时关闭，晶体管M12依旧开启，读位线RBL依旧通过晶体管M12连接至电源Vdd，电源Vdd依旧对读位线RBL充电，读位线RBL的电平升高，这样导致该读位线RBL的电平降低速度缓慢。在确定存储单元1的存储信息时，需要先等待读位线RBL的电平变为低电平，才能准确确定存储单元1的存储信息为低电平，由此使得该单端存储器的读取速度变慢。
发明内容
本申请的实施例提供了一种单端存储器，涉及存储技术领域，能够解决现有的单 端存储器读取速度慢的问题。
为达到上述目的，本申请的实施例提供了如下技术方案：
第一方面，提供一种单端存储器，包括阵列分布的存储单元，该存储单元连接读位线以及读字线。读位线通过列选择单元连接预充电单元，读位线通过列选择单元连接漏电电流补偿单元的输出端，读位线还通过反馈电路连接漏电电流补偿单元的控制端。反馈电路在确定读位线的电平低于第一预定值时，向漏电电流补偿单元的控制端输出反馈信号，以停止漏电电流补偿单元通过输出端向读位线充电。在上述的单端存储器中，当列选择单元选中读位线，预充电单元通过列选择单元向该读位线充电，读位线保持高电平，若此时读字线将某一个存储单元选中，则该存储单元向该读位线输出存储信息。在存储信息为低电平时，读位线的电平也开始降低，反馈电路在确定读位线的电平低于某一预定值后，向漏电电流补偿单元的控制端输出反馈信号，该反馈信号可以停止漏电电流补偿单元通过输出端向读位线充电。由于单端存储器的漏电电流补偿单元是通过反馈电路输出的反馈信号控制的，而且反馈电路输出的反馈信号是根据读位线的电平变化而及时改变，这样使得漏电电流补偿单元能更及时地关闭，由于及时地停止了漏电电流补偿单元向读位线充电，因此读位线的电平能够在存储信息为低电平的作用下更快的降低，从而使得该单端存储器能够更快的在读位线上读取该存储信息，因此单端存储器的读取速度变快。
可选的，上述反馈电路确定读位线的电平高于第二预定值时，向漏电电流补偿单元的控制端输出反馈信号，以控制漏电电流补偿单元通过输出端向读位线充电，其中上述第一预定值小于或等于上述第二预定值。在该方案中，在被选中的存储单元的存储信息为高电平时，读位线会保持高电平，反馈电路确定读位线的电平高于第二预定值时，向漏电电流补偿单元的控制端输出反馈信号，该反馈信号可以控制漏电电流补偿单元通过输出端向读位线充电，补偿读位线上其他存储单元产生的漏电电流。由于该反馈电路输出的反馈信号也能控制漏电电流补偿单元及时开启，从而也能保证该单端存储器读取存储信息为高电平的读取性能。
可选的，上述反馈电路包括：反相器。反相器的输入端连接读位线，反相器的输出端连接漏电电流补偿单元的控制端，其中反相器用于根据读位线的电平生成反馈信号。
可选的，本申请的实施例还提供了反相器的具体结构。反相器包括：第一晶体管和第二晶体管。第一晶体管的第一端连接电源，第一晶体管的第二端连接第二晶体管的第一端，第二晶体管的第二端连接地，第一晶体管的控制端与第二晶体管的控制端连接反相器的输入端，第一晶体管的第二端还连接反相器的输出端，并且，第一晶体管与第二晶体管的类型不同。
可选的，本申请的实施例还提供了另一种反相器的具体结构，反相器包括：第三晶体管、第四晶体管、第五晶体管和第六晶体管；第三晶体管的第一端连接电源，第三晶体管的第二端连接第四晶体管的第一端，第四晶体管的第二端连接第五晶体管的第一端；第五晶体管的第二端连接地；第六晶体管的第一端连接第四晶体管的第二端，第六晶体管的控制端连接第三晶体管的第二端，第六晶体管的第二端连接电源；第三晶体管的控制端、第四晶体管的控制端以及第五晶体管的控制端连接反相器的输入端； 第三晶体管的第二端还连接反相器的输出端；第四晶体管、第五晶体管以及第六晶体管的类型相同，第三晶体管与第四晶体管的类型不同。
可选的，上述反馈电路也可以通过设置逻辑门电路实现根据读位线的电平生成反馈信号。则该反馈电路包括：第一或非门以及第一非门。其中，第一非门的输入端连接列选择单元的控制端，第一非门的输出端连接第一或非门的第一输入端，第一或非门的第二输入端连接读位线；第一或非门的输出端连接漏电电流补偿单元的控制端。
可选的，当预充电单元通过列选择单元向读位线充电后，若读字线将存储单元选中，则存储单元向读位线输出存储信息。
可选的，反馈电路连接于存储单元与列选择单元之间的传输路径上。
可选的，单端存储器还包括：第一开关单元，漏电电流补偿单元通过第一开关单元连接读位线，第一开关单元的控制端连接列选择单元的控制端。在该方案中，确保在列选择单元被其控制端的信号开启以选中读位线时，能够同时将第一开关单元开启以将漏电电流补偿单元接入读位线，使得漏电电流补偿单元能够在读位线被选中时，及时对读位线的电平进行补偿或停止补偿，实现了漏电电流补偿单元同读位线被选中自适应地工作。
可选的，为了使得上述单端存储器读取存储信息为低电平的速度更快，上述的单端存储器还包括：放电单元。放电单元的控制端连接漏电电流补偿单元的控制端，放电单元的第一端通过列选择单元连接读位线，放电单元的第二端连接地。在该方案中，在存储信息为低电平时，放电单元在接收到反馈信号以后，能将读位线通过列选择单元和放电单元连接地，使得读位线的电平降低速度加快，保证读位线的电平能尽快降低至低电平，提升了单端存储器的读取速度。
可选的，上述放电单元可以包括第七晶体管和第八晶体管；第七晶体管的控制端连接漏电电流补偿单元的控制端，第七晶体管的第一端通过列选择单元连接读位线；第七晶体管的第二端连接第八晶体管的控制端，第七晶体管的第二端还连接第八晶体管的第一端，第八晶体管的第二端连接地。在该方案中，第七晶体管和第八晶体管这样的连接方式会使得当前放电单元的等效电阻变高，那么放电单元的放电速度会变缓。如果当前读位线的电平是因为漏电电流的存在而降低的，这样设置的放电单元就不会直接将读位线的连接地，造成存储信息读取出错的问题，使得该单端存储器的读取性能更稳定。
可选的，上述放电单元还可以包括：第九晶体管。漏电电流补偿单元的控制端通过第二非门连接第九晶体管的控制端，第九晶体管的第一端通过列选择单元连接读位线；第九晶体管的第二端连接地。在该方案中，第九晶体管为P型晶体管，P型晶体管传递电平时会存在阈值损失，由此也使得放电单元的放电速度变缓。
可选的，上述放电单元的第一端与列选择单元之间还设置有第二开关单元。在该方案中，第二开关单元的存在是为了控制放电单元根据需要自适应地工作或不工作。
可选的，上述单端存储器还包括：第二或非门以及第三非门。其中第三非门的输入端连接列选择单元的控制端，第三非门的输出端连接第二或非门的第一输入端；第二或非门的第二输入端连接读位线；第二或非门的输出端连接放电单元的控制端。
附图说明
图1为现有技术提供的单端存储器的结构示意图；
图2为本申请的实施例一提供的单端存储器的结构示意图；
图3为图2中的存储单元的典型结构示意图；
图4为本申请的实施例二提供的单端存储器的电流流向示意图一；
图5为本申请的实施例二提供的单端存储器的电流流向示意图二；
图6为本申请的实施例三提供的单端存储器的结构示意图；
图7为本申请的实施例四提供的单端存储器的结构示意图；
图8为本申请的实施例五提供的单端存储器的结构示意图；
图9为本申请的实施例六提供的单端存储器的结构示意图；
图10为本申请的实施例七提供的单端存储器的结构示意图；
图11为本申请的实施例八提供的单端存储器的结构示意图；
图12为本申请的实施例九提供的单端存储器的结构示意图；
图13为本申请的实施例十提供的单端存储器的结构示意图；
图14为本申请的实施例十一提供的单端存储器的结构示意图；
图15为本申请的实施例十二提供的单端存储器的结构示意图；
图16为本申请的实施例提供的单端存储器的性能仿真图一；
图17为本申请的实施例提供的单端存储器的性能仿真图二。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
除非另有定义，否则本文所用的所有科技术语都具有与本领域普通技术人员公知的含义相同的含义。在本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a和b，a和c，b和c或a、b和c，其中a、b和c可以是单个，也可以是多个。另外，在本申请的实施例中，“第一”、“第二”等字样并不对数量和次序进行限定。
此外，本申请中，“上”、“下”等方位术语是相对于附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件所放置的方位的变化而相应地发生变化。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
以下对本申请的实施例中的技术术语说明如下：
在本申请的实施例中，晶体管可以采用金属-氧化物半导体场效应晶体管(metal-oxide-semiconductor field effect transistor,MOSFET)，晶体管分为N (negative，负)型晶体管和P(positive，正)型晶体管两种类型。晶体管包括源极(source)、漏极(drain)以及栅极(gate)，通过控制输入晶体管栅极的电平可以控制晶体管的开启或关闭。晶体管在开启时，源极和漏极导通，产生开启电流；晶体管在关闭时，源极和漏极虽然不会导通，但是由于晶体管的结构特性，源极和漏极之间会产生微小漏电电流。在本申请的实施例中，晶体管的栅极也被称为控制端，源极被称为第一端，漏极被称为第二端；或者，栅极被称为控制端，漏极被称为第一端，源极被称为第二端。此外，N型晶体管在控制端的电平为高电平时开启，第一端和第二端导通，第一端和第二端之间产生开启电流；N型晶体管在控制端的电平为低电平时关闭，第一端和第二端不导通，第一端和第二端之间存在漏电电流。P型晶体管在控制端的电平为低电平时开启，第一端和第二端导通，产生开启电流；P型晶体管在控制端的电平为高电平时关闭，第一端和第二端不导通，存在漏电电流。
本申请的实施例中，存储单元的存储信息为高电平代表当前存储单元中存储的数据为“1”(也被称为逻辑“1”)；存储单元的存储信息为低电平代表当前存储单元中存储的数据为“0”(也被称为逻辑“0”)。另外，高电平也代表当前电压高于预定值；低电平也代表当前电压低于预定值(预定值可以根据电路的变化而发生改变)。还有，信号为高电平表示当前信号为逻辑高(有时也被称为HIGH)；信号为低电平表示当前信号为逻辑低(有时也被称为LOW)。
参照图2所示，本申请的实施例提供的提供了一种单端存储器的结构示意图，该单端存储器包括存储器阵列20，以及分别与存储器阵列20耦合的输入/输出(inpit/output，I/O)电路21、参考电路22以及解码器23，还有与输入/输出电路21以及解码器23耦合的控制逻辑电路24。
参照图2所示，存储器阵列20包括多个存储单元，该多个存储单元在存储器阵列20中阵列分布，并且每一存储单元中均包括多个晶体管。如图2所示，存储单元201和存储单元202排列于a行，存储单元203和存储单元204排列于b行；存储单元201和存储单元203排列于A列，存储单元202和存储单元204排列于B列。每一个存储单元用来存储一位数据，即数据“1”或数据“0”，存储单元中存储的数据为“1”时也可以说该存储单元的存储信息为高电平(后续本申请的实施例中用存储单元的存储信息为高电平表示存储单元存储的数据是“1”)，存储单元存储的数据为“0”时也可以说该存储单元的存储信息为低电平(后续本申请的实施例中用存储单元的存储信息为低电平表示存储单元存储的数据是“0”)。此外，存储器阵列20还包括沿相应列排列的多个位线(bit line，BL)(可以是读位线(read bit line，RBL)或写位线(write bit line,WBL))和/或位条线(可以是写位条线(write bit bar line，WBBL))、以及沿相应行排列的多个字线(word line，WL)(可以是读字线(read word line，RWL)或写字线(write word line，WWL))。为清晰起见，图2中的每一列仅示出一条读位线，如图2所示的A列的读位线RBL-A和B列的读位线RBL-B。
输入/输出电路21包括多个灵敏放大器(sense amplifier,SA)(如图2所示的的灵敏放大器SA-A和灵敏放大器SA-B)，参考电路(reference circuit，RC)22包括多个子参考电路(如图2所示的子参考电路RC-A和子参考电路RC-B)。上述的存储器阵列20的每一列存储单元均通过一条读位线RBL耦合至对应的灵敏放大器以及 子参考电路。如图2所示，A列的存储单元201和存储单元203等经由读位线RBL-A耦合至灵敏放大器SA-A以及子参考电路RC-A；B列的存储单元202和存储单元204等经由读位线RBL-B耦合至灵敏放大器SA-B以及子参考电路RC-B。示例性的，在存储器阵列20增加相应的列时，输入/输出电路21会增加与存储器阵列20中的列对应的灵敏放大器，参考电路22会增加与存储器阵列20中的列对应的子参考电路。
其中，存储器阵列20所耦合的解码器23可用于接收到由控制逻辑电路24提供的地址信息(例如，行地址)来将存储器阵列20的一个或多个字线置位(assert)。此外，控制逻辑电路24可耦合至输入/输出电路21以撷取在读取操作期间由灵敏放大器(例如，灵敏放大器SA-A、灵敏放大器SA-B等)读出的数据。
其中，图2所示的单端存储器中也可以包括其他存储器阵列和/或其他的一个或多个功能电路(例如缓冲电路、时序电路等)，每一个存储器阵列中可以包括更多或更少的存储单元。
参照图3所示，为本申请的实施例提供的一种图2中的存储单元201的典型结构示意图，其中，存储单元201包括8个晶体管(该8个晶体管构成的存储单元也被称为八晶体管静态随机存取存储器单元)，8个晶体管分别为晶体管M1、晶体管M2、晶体管M3、晶体管M4、晶体管M5、晶体管M6、晶体管M7、以及晶体管M8。如图3所示，晶体管M1和晶体管M3为P型晶体管，其他的晶体管为N型晶体管。并且，存储单元201还包括写字线WWL、写位线WBL、写位条线WBBL、读位线RBL-A以及读字线RWL。
如图3所示，晶体管M1的第一端连接至电源Vdd，晶体管M1的第二端连接至晶体管M2的第一端，晶体管M2的第二端连接地GND。晶体管M3的第一端连接至电源Vdd，晶体管M3的第二端连接至晶体管M4的第一端，晶体管M4的第二端连接地GND，晶体管M3的第二端还连接于晶体管M1的控制端，晶体管M1的控制端还连接于晶体管M2的控制端。写位线WBL连接晶体管M5的第一端，晶体管M5的第二端连接于晶体管M1的第二端，晶体管M5的第二端还连接于晶体管M3的控制端，晶体管M3的控制端还连接于晶体管M4的控制端。写字线WWL连接晶体管M5的控制端，写字线WWL还连接于晶体管M6的控制端，晶体管M6的第一端连接于晶体管M3的第二端，晶体管M6的第二端连接于写位条线WBBL。其中，晶体管M3的第二端还连接于晶体管M7的控制端，晶体管M7的第二端连接地，晶体管M7的第一端连接于晶体管M8的第一端，晶体管M8的第二端连接于读位线RBL-A，晶体管M8的控制端连接于读字线RWL。晶体管M1的第二端还耦合于该存储单元201的第一节点2011，晶体管M3的第二端还耦合于该存储单元201的第二节点2012。
其中，晶体管M1-M6构成存储单元201的核心，该核心主要用于执行写入操作(即，核心中包括写入接口)。晶体管M1和晶体管M2连接形成为第一反相器，而晶体管M3和晶体管M4连接形成为第二反相器，第一反相器与第二反相器彼此交叉耦合(如图3所示)。更具体来说，第一反相器与第二反相器各自耦合于电源Vdd与地GND之间。此外，第一反相器耦合至晶体管M5，第二反相器耦合至晶体管M6。晶体管M5和晶体管M6还耦合至存储单元的写字线WWL，晶体管M5也耦合至写位线WBL，晶体管M6也耦合至写位条线WBBL。晶体管M5和晶体管M6的开启与关闭是由写字线WWL进行控制的。存储单元201的核心使得存储单元201的存储功能更稳定。晶体管M7及晶体管M8构 成存储单元201的读取缓冲器，该读取缓冲器主要用以执行读取操作(即，该读取缓冲器提供了读取接口)。其中，读字线RWL控制晶体管M8开启或关闭，读字线RWL为高电平代表当前的存储单元201被选中进行存储信息输出，读字线RWL为低电平代表当前的存储单元201未被选中。存储单元201的存储信息控制晶体管M7开启或关闭，在存储单元201的存储信息为高电平时，该高电平的存储信息控制晶体管M7关闭，在存储单元201的存储信息为低电平时，该低电平的存储信息控制晶体管M7开启。
下面结合图2所示的单端存储器以及图3所示的存储单元，对单端存储器向存储单元201中写入存储信息以及读取存储单元201的存储信息的过程进行说明。
在向存储单元201中写入存储信息时，参照图2所示，首先输入/输出电路21接收到当前的写入指令，输入/输出电路21通过控制逻辑电路24获取到写入指令中对应需要写入存储信息的存储单元的地址信息(例如行地址)，然后通过解码器23将存储器阵列20中对应需要写入存储信息的存储单元的一个或多个字线置位(assert)。参照图3所示，也就是将写字线WWL置于高电平，此时，晶体管M5以及晶体管M6开启。写位线WBL将相应的低电平/高电平的存储信息传输至存储单元201，与此同时，位条线WBBL接收到存储信息的反向信号(例如当WBL接收的存储信息为高电平时，位条线接收到低电平；当WBL接收的存储信息为低电平时，位条线接收到高电平)。假设，当前写位线WBL传输的存储信息为低电平，则对应的存储单元201中的晶体管M3以及晶体管M2开启，晶体管M1以及晶体管M4关闭，存储单元201内的第一节点2011为低电平，第二节点2012为高电平，写位线WBL传输的低电平的存储信息准确写入到该存储单元201的核心中。假设，当前写位线WBL传输的存储信息为高电平，则对应的存储单元201中的晶体管M3以及晶体管M2关闭，晶体管M1以及晶体管M4开启，存储单元201内的第一节点2011为高电平，第二节点2012为低电平，写位线WBL传输的高电平的存储信息准确写入到该存储单元201的核心中。换言之，存储单元201内的第一节点2011为高电平，第二节点2012为低电平，代表当前存储单元201的存储信息为高电平；存储单元201内的第一节点2011为低电平，第二节点2012为高电平，代表存储单元201的存储信息为低电平。
在读取存储单元201的存储信息时，参照图2所示，首先输入/输出电路21接收到当前的读取指令，输入/输出电路21通过控制逻辑电路24获取到读取指令中对应需要读取存储信息的存储单元的地址信息(例如行地址)，然后通过解码器23将存储器阵列20中对应需要读取存储信息的存储单元的一个或多个字线置位(assert)，并且还需要将读位线设置为高电平。参照图3所示，也就是将读字线RWL以及读位线RBL-A置于高电平。读字线RWL置于高电平使得存储单元201被选中，存储单元201中的晶体管M8开启，此时晶体管M8以及读位线RBL-A之间形成电流I1。假设，当前存储单元201的存储信息为高电平，则存储单元201内的第一节点2011为高电平，第二节点2012为低电平，晶体管M7关闭，读位线RBL-A不会通过晶体管M7以及晶体管M8连接地GND，不会产生流经晶体管M7和晶体管M8的电流I2，因此存储单元201向读位线RBL-A输出高电平，读位线RBL-A的电平保持初始的高电平。参照图2，输入/输出电路21接收到读位线RBL-A的电平以及子参考电路RC-A的电平，判断出读位线RBL-A的电平大于子参考电路RC-A的电平，则确定此时存储单元201中存储信息为高电平。 参照图3，假设，当前存储单元201的存储信息为低电平，则存储单元201内的第一节点2011为低电平，第二节点2012为高电平，晶体管M7开启，读位线RBL-A会通过晶体管M7以及晶体管M8连接地GND，产生流经晶体管M7和晶体管M8的电流I2，因此存储单元201向读位线RBL-A输出低电平，读位线RBL-A的电平开始降低。参照图2，输入/输出电流21接收到读位线RBL-A的电平以及子参考电路RC-A的电平，判断出读位线RBL-A的电平小于子参考电路RC-A的电平，则确定此时存储单元201中存储信息为低电平。
需要说明的是，根据实际的单端存储器的需要，可以设置参考电路21，也可以不设置参考电路21。在不设置参考电路21时，输入/输出电路22仅接收读位线上的电平，根据读位线上的电平确定当前存储单元的存储信息为高电平还是低电平。
在读取上述的单端存储器中被选中的存储单元的存储信息时，被选中的存储单元向读位线输出存储信息，该存储信息会影响读位线的电平。此时，与被选中的存储单元处于同一列的其他存储单元，会产生漏电电流，漏电电流也会影响读位线的电平，导致读位线的电平变化出现异常，为此，单端存储器中大多会设置漏电电流补偿单元。
具体的，参考图4所示，本申请的实施例提供了一种单端存储器的结构示意图，该单端存储器包括读位线RBL-1和其他读位线RBL-n，每一条读位线上均包括多个存储单元，以读位线RBL-1为示例，该读位线RBL-1连接有3个存储单元(分别为存储单元c1、存储单元c2、存储单元c3)，通过读位线RBL-1可以读取这3个存储单元中的存储信息。其中，存储单元c1还连接于读字线RWL-1，存储单元c2还连接于读字线RWL-2，存储单元c3还连接于读字线RWL-3。读位线RBL-1还通过预充电单元连接至电源Vdd(图4中预充电单元以晶体管M41为例，晶体管M41的第一端连接电源Vdd，晶体管M41的第二端连接读位线RBL-1)，读位线RBL-1通过漏电电流补偿单元连接至电源Vdd(图4中漏电电流补偿单元以晶体管M42为例，晶体管M42的第一端连接电源Vdd，晶体管M42的第二端连接读位线RBL-1)。并且读位线RBL-1耦合于与非门401的第一输入端，其他列的存储单元通过其他读位线RBL-n耦合于与非门401的第二输入端，与非门401的输出端耦合于晶体管M45的控制端，晶体管M45的第一端连接地GND，晶体管M45的第二端连接全局位线(global bit line，GBL)，与非门401的输出端也耦合于晶体管M42的控制端。其中，上述的晶体管M41和晶体管M42以P型晶体管为例，晶体管M45以N型晶体管为例。
另外，图4所示的单端存储器中的3个存储单元的结构可以参照图3所示的存储单元201的结构示意图，其中图4中的存储单元内的核心cc相当于图3中的存储单元201中的晶体管M1-M6，该核心cc用于保存存储信息和执行写入操作。其中图4中的晶体管M44相当于图3中的存储单元201中的晶体管M7，每个存储单元中的核心cc均耦合至晶体管M44，在存储单元的核心cc保存的存储信息为高电平时，晶体管M44关闭，在存储单元的核心cc保存的存储信息为低电平时，晶体管M44开启。图4中的存储单元内的晶体管M43相当于图3中的存储单元201中的晶体管M8，读字线RWL为高电平控制存储单元内的晶体管M43开启，读字线RWL为低电平控制存储单元内的晶体管M43关闭。
参照图4所示，该单端存储器在读取存储信息时，首先，预充信号(precharge) S1由高电平切换为低电平，以此控制的晶体管M41的控制端电平为低电平，晶体管M41开启，电源Vdd与读位线RBL-1导通，电源Vdd对读位线RBL-1充电，使得读位线RBL-1的电平为高电平，然后预充信号S1由低电平变为高电平，控制晶体管M41的控制端电平为高电平，晶体管M41关闭，电源Vdd停止对读位线RBL-1充电，读位线RBL-1保持高电平。其中，其他列的存储单元连接的其他读位线RBL-n通过开关1连接至电源Vdd,全局位线GBL通过开关2也连接至电源Vdd，并且在预充信号(precharge)S1由高电平切换为低电平控制读位线RBL-1的电平变为高电平时，开关1和开关2也会被打开，使得其他读位线RBL-n与全局位线GBL连接至电源Vdd，因此其他读位线RBL-n与全局位线GBL也会被设置于高电平，并且由于晶体管M45被关闭(因为读位线RBL-1与其他读位线RBL-n上的高电平被与非门401与非操作就输出低电平，控制M45关闭)，全局位线GBL保持高电平。
以读取存储单元c1的存储信息为例对该单端存储器的读取过程进行说明。存储单元c1连接的读字线RWL-1为高电平控制晶体管M43的控制端电平为高电平，使得存储单元c1被选中，存储单元c1向读位线RBL-1输出存储信息。存储单元c2连接的读字线RWL-2为低电平控制晶体管M43的控制端电平为低电平，存储单元c2未被选中。存储单元c3连接的读字线RWL-3为低电平控制晶体管M43的控制端电平为低电平，存储单元c3未被选中。
参照图4所示，如果该存储单元c1的存储信息为高电平，则存储单元c1中的存储信息控制的晶体管M44关闭，读位线RBL-1不会因为存储单元c1中的晶体管M43和晶体管M44而连接地GND，读位线RBL-1的电平保持高电平，也就相当于存储单元c1向读位线RBL-1输出高电平。其中,由于其他读位线RBL-n被置于高电平，那么读位线RBL-1与其他读位线RBL-n上的高电平被与非门401执行与非操作就输出低电平，该低电平传输至漏电电流补偿单元(也就是晶体管M42)的控制端，使得晶体管M42打开，读位线RBL-1通过晶体管M42连接电源Vdd，电源Vdd为读位线RBL-1充电，并且与非门401的输出端输出低电平，也控制晶体管M45关闭，全局位线GBL不会通过晶体管M45连接地，因此与该全局位线GBL耦合的输入/输出电路可以确定全局位线GBL的电平为高电平，也可以确定当前被选中的存储单元c1中的存储信息为高电平。虽然，存储单元c2中的晶体管M43和晶体管M44会产生漏电，即如图4所示读位线RBL-1通过存储单元c2中的晶体管M43和晶体管M44连接地GND，存储单元c2产生流经晶体管M43和晶体管M44的漏电电流Ic2。读位线RBL-1也通过存储单元c3中的晶体管M43和晶体管M44连接地GND，存储单元c3产生流经晶体管M43和晶体管M44的漏电电流Ic3。漏电电流Ic2和漏电电流Ic3会导致读位线RBL-1的电平降低。但是，由于单端存储器中设置有漏电电流补偿单元(也就是晶体管M42)，晶体管M42开启使得读位线RBL-1通过晶体管M42连接电源Vdd，读位线RBL-1的电平升高，补偿了读位线RBL-1上由于漏电电流Ic2和漏电电流Ic3的产生而降低的电平。
参照图5所示，如果该存储单元c1的存储信息为低电平，则存储单元c1中的存储信息控制的晶体管M44开启，读位线RBL-1会因为存储单元c1中的晶体管M43和晶体管M44的开启而连接地GND，存储单元c1中产生流经晶体管M43和晶体管M44的开启电流Ic1，因此，存储单元c1向读位线RBL-1输出低电平，读位线RBL-1的电平开 始降低。当读位线RBL-1的电平降低为低电平时，与非门401将读位线RBL-1与其他读位线RBL-n的电平进行与非操作，向晶体管M45输出高电平，晶体管M45开启，这样全局位线GBL通过晶体管M45连接地GND，全局位线GBL的电平开始降低，当全局位线GBL的电平逐渐降低至低电平，与该全局位线GBL耦合的输入/输出电路可以确定存储单元c1的存储信息为低电平。同时，在与非门401输出高电平时，晶体管M42的控制端也能接收到高电平，晶体管M42关闭，电源Vdd停止向读位线RBL-1充电。但是，在读位线RBL-1的电平开始降低到读位线RBL-1的电平降低为低电平的期间，晶体管M42一直开启，电源Vdd向读位线RBL-1充电，影响了读位线RBL-1的电平下降速度，导致该单端存储器的读取速度变慢。
需要说明的是，在单端存储器中，还可以包括与其他读位线RBL-n一一对应的漏电电流补偿单元、预充电单元和与非门，在读取一条读位线上连接的存储单元中的存储信息时，该一条读位线对应的漏电电流补偿单元、预充电单元和与非门工作。或者，单端存储器还可以包括与其他读位线RBL-n一一对应的漏电电流补偿单元和预充电单元，每一个漏电电流补偿单元的控制端通过一个开关连接至与非门401的输出端，在读取一条读位线上连接的存储单元中的存储信息时，该一条读位线上对应的漏电电流补偿单元连接的开关打开，该一条读位线上对应的漏电电流补偿单元工作。
为了解决单端存储器的读取速度慢的问题，本申请的实施例提供了一种单端存储器，该单端存储器可以应用于图2所示的存储器阵列20中。参照图6所示，图6为本申请的实施例提供的单端存储器的结构示意图，该单端存储器包括阵列分布的存储单元601，存储单元601连接读位线RBL-1以及读字线；读位线RBL-1通过列选择单元(图6中的列选择单元以晶体管M61为例)连接预充电单元(图6中的预充电单元以晶体管M62为例)；读位线RBL-1通过列选择单元连接漏电电流补偿单元(图6中的漏电电流补偿单元以晶体管M63为例)的输出端；读位线RBL-1还通过反馈电路602连接漏电电流补偿单元的控制端；反馈电路602在确定读位线的电平低于第一预定值时，向漏电电流补偿单元的控制端输出反馈信号(feedback)，以停止漏电电流补偿单元通过输出端向读位线RBL-1充电。
在一种示例中，参照图6所示，该单端存储器的列选择单元包括晶体管M61，预充电单元包括晶体管M62，漏电电流补偿单元包括晶体管M63。其中，读位线RBL-1连接存储单元601。电源Vdd连接于晶体管M62的第一端，晶体管M62的第二端连接晶体管M61的第二端，晶体管M61的第一端连接于读位线RBL-1。读位线RBL-1通过反馈电路602连接至晶体管M63的控制端，反馈电路602连接于存储单元601与晶体管M61之间的传输路径上，晶体管M63的第一端连接电源Vdd，晶体管M63的第二端连接晶体管M61的第二端。读位线RBL-1还连接于与非门603的第一输入端，其他列的存储单元通过其他读位线RBL-n连接于与非门603的第二输入端，与非门603的输出端连接于晶体管M64的控制端，晶体管M64的第一端连接地GND，晶体管M64的第二端连接全局位线GBL。
需要说明的是，上述的列选择单元、预充电单元以及漏电电流补偿单元也可以包含其他更多或更少的电子元器件，其连接关系也可以更简单或更复杂。读位线RBL-1也可以连接更多的存储单元。
参照图6所示，该单端存储器读取存储单元601的存储信息时，由于存储单元601连接在读位线RBL-1上，因此，需要先让列选择信号S2从低电平变为高电平，控制晶体管M61开启，表示选中读位线RBL-1。然后，预充信号S3从高电平变为低电平，控制晶体管M62开启，读位线RBL-1通过晶体管M61和晶体管M62连接至电源Vdd，电源Vdd为读位线RBL-1充电，使得读位线RBL-1为高电平。随后，预充信号S3由低电平变为高电平，控制晶体管M62关闭，电源Vdd停止对读位线RBL-1充电，读位线RBL-1保持高电平。其中，其他列的存储单元连接的其他读位线RBL-n会被置为高电平，全局位线GBL也会被提前设置于高电平(具体参见图4所示的其他读位线RBL-n与全局位线GBL被置于高电平的步骤)，并且由于晶体管M64被关闭(因为读位线RBL-1与其他读位线RBL-n上的高电平被与非门603与非操作就输出低电平，控制M64关闭)，全局位线GBL保持高电平。
接着，读字线选中存储单元601，存储单元601向读位线RBL-1输出存储信息。
当存储单元601中的存储信息为低电平(例如可以参考图5所示，存储单元c1中的晶体管M44开启，存储单元c1向读位线RBL-1输出低电平，存储单元601和存储单元c1相同)时，读位线RBL-1的电平会开始下降，此时，反馈电路602，在确定读位线RBL-1的电平降低至第一预定值后，向晶体管M63的控制端输出反馈信号S4，控制晶体管M63关闭(示例性的，晶体管M63为P型晶体管时，反馈信号S4为高电平；晶体管M63为N型晶体管时，反馈信号S4为低电平)，晶体管M63将读位线RBL-1与电源Vdd断开，电源Vdd停止为读位线RBL-1充电，读位线RBL-1的电平会降低至低电平。其中读位线RBL-1的电平为低电平，其他读位线RBL-n一直保持高电平，则经与非门603的与非处理，与非门603的输出端输出高电平，以此控制晶体管M64开启，全局位线GBL通过晶体管M64连接地GND，全局位线GBL的电平会逐渐降低至低电平，与该全局位线GBL耦合的输入/输出电路可以确定全局位线GBL的电平为低电平，也可以确定当前被选中的存储单元601中的存储信息为低电平。
在上述的单端存储器中，当列选择单元选中读位线，预充电单元通过列选择单元向该读位线充电，读位线保持高电平，若此时读字线将某一个存储单元选中，则该存储单元向该读位线输出存储信息。在存储信息为低电平时，读位线的电平也开始降低，反馈电路在确定读位线的电平低于某一预定值后，向漏电电流补偿单元的控制端输出反馈信号，该反馈信号可以停止漏电电流补偿单元通过输出端向读位线充电。由于单端存储器的漏电电流补偿单元是通过反馈电路输出的反馈信号控制的，而且反馈电路输出的反馈信号是根据读位线的电平变化而及时改变，这样使得漏电电流补偿单元能更及时地关闭，由于及时地停止了电流补偿单元向读位线充电，因此读位线的电平能够在存储信息为低电平的作用下更快的降低，从而使得该单端存储器能够更快的在读位线上读取该存储信息，因此单端存储器的读取速度变快。
依然参照图6所示，当存储单元601中的存储信息为高电平(例如可以参考图4所示，存储单元c1中的晶体管M44关闭，存储单元c1向读位线RBL-1输出高电平，存储单元601和存储单元c1相同)时，读位线RBL-1保持高电平，但是，当前读位线RBL-1上连接的其他未被选中的存储单元，会发生漏电情况，产生漏电电流。此时，与读位线RBL-1连接的反馈电路602，在确定读位线RBL-1的电平高于第二预定值时， 向晶体管M63的控制端输出反馈信号S4，控制晶体管M63开启(示例性的，晶体管M63为P型晶体管时，反馈信号S4为低电平；晶体管M63为N型晶体管时，反馈信号S4为高电平)，读位线RBL-1通过晶体管M63和晶体管M61连接至电源Vdd，电源Vdd为读位线RBL-1充电，补偿读位线RBL-1上未被选中的存储单元产生的漏电电流，使得读位线RBL-1保持高电平。由于其他读位线RBL-n一直保持高电平，则经与非门603的与非处理，与非门603的输出端输出低电平，以此控制晶体管M64关闭，全局位线GBL不会通过晶体管M64连接地GND，全局位线GBL的电平保持初始的高电平，与该全局位线GBL耦合的输入/输出电路可以确定全局位线GBL的电平为高电平，也可以确定当前被选中的存储单元601中的存储信息为高电平。
其中，上述的第一预定值小于或等于上述第二预定值。具体的，第一预定值还需要大于低电平，只有第一预定值大于低电平时，反馈电路602才能在读位线RBL-1的电平在降低至低电平之前，就能向晶体管M63输出反馈信号，停止电源Vdd通过晶体管M63向读位线RBL-1充电。第二预定值还需要小于高电平，只有第二预定值小于高电平时，那么在读位线RBL-1的电平因为漏电电流的产生而降低时，反馈电路602能向晶体管M63输出反馈信号，控制电源Vdd通过晶体管M63向读位线RBL-1充电。
上述的单端存储器，在被选中的存储单元的存储信息为高电平时，读位线会保持高电平，反馈电路确定读位线的电平高于第二预定值时，向漏电电流补偿单元的控制端输出反馈信号，该反馈信号可以控制漏电电流补偿单元通过输出端向读位线充电，补偿读位线上其他存储单元产生的漏电电流。由于该反馈电路输出的反馈信号也能控制漏电电流补偿单元及时开启，从而也能保证该单端存储器读取存储信息为高电平的读取性能。
示例性的，上述的反馈电路包括：反相器。反相器的输入端连接读位线，反相器的输出端连接漏电电流补偿单元的控制端；其中反相器用于根据所述读位线的电平生成反馈信号，以控制漏电电流补偿单元及时地开启或关闭。
具体的，反馈电路602中的反相器包括：第一晶体管和第二晶体管(这样的反相器也被称为拉偏反相器)。
参照图7所示，本申请的实施例提供了一种单端存储器的结构示意图，在图7所示的单端存储器中，详细示出了反馈电路602中的反相器的具体结构，其中，图7所示的反馈电路602中的反相器包括晶体管Mf1(也就是上述的第一晶体管，该晶体管Mf1以P型晶体管为例)和晶体管Mf2(也就是上述的第二晶体管，该晶体管Mf2以N型晶体管为例)。晶体管Mf1的第一端连接电源Vdd，晶体管Mf1的第二端连接晶体管Mf2的第一端，晶体管Mf2的第二端连接地GND，晶体管Mf1的控制端与晶体管Mf2的控制端连接反馈电路602包括的反相器的输入端；晶体管Mf1的第二端还连接反馈电路602包括的反相器的输出端。
在该单端存储器读取存储单元601中的存储信息时，该存储信息为高电平，存储单元601向读位线RBL-1输出高电平，尽管此时读位线RBL-1的电平会因为漏电电流的存在而降低，但是在读位线RBL-1的电平处于第二预定值和高电平之间时，反馈电路602包括的反相器的输入端电平都被认为是高电平，使得晶体管Mf1的控制端电平为高电平，晶体管Mf1关闭，而晶体管Mf2的控制端电平为高电平，晶体管Mf2开启。 由于晶体管Mf1关闭，晶体管Mf2开启，反相器的输出端连接地GND，则反相器的输出端输出电平为低电平，此时反馈电路602向漏电电流补偿单元(也就是晶体管M63，该晶体管M63以P型晶体管为例)的控制端输出的反馈信号S4为低电平，以此控制晶体管M63开启，读位线RBL-1通过晶体管M63连接至电源Vdd，电源Vdd为读位线RBL-1充电，读位线RBL-1保持高电平。
在该单端存储器读取存储单元601的存储信息时，该存储信息为低电平，存储单元601向读位线RBL-1输出低电平，则读位线RBL-1的电平开始降低，在读位线RBL-1的电平降低至第一预定值时，反馈电路602包括的反相器的输入端电平被认为是低电平，使得晶体管Mf1的控制端电平为低电平，晶体管Mf1开启，而晶体管Mf2的控制端电平为低电平，晶体管Mf2关闭。由于晶体管Mf1开启，晶体管Mf2关闭，反相器的输出端连接电源Vdd，则反相器的输出端输出电平为高电平，此时反馈电路602向漏电电流补偿单元(也就是晶体管M63，该晶体管M63以P型晶体管为例)的控制端输出的反馈信号S4为高电平，以此控制晶体管M63关闭，读位线RBL-1不会通过晶体管M63连接至电源Vdd，电源Vdd不会为读位线RBL-1充电，读位线RBL-1的电平持续降低至低电平。
在一些实施例中，参照图8所示，本申请的实施例提供了一种单端存储器的结构示意图，在图8所示的单端存储器中，详细示出了反馈电路602中的反相器的另一种具体结构，反馈电路602中的反相器包括：第三晶体管、第四晶体管、第五晶体管和第六晶体管(这样的反相器也被称为半斯密特反相器)。
具体的，如图8所示，反馈电路602中的反相器包括晶体管Mf3(也就是上述的第三晶体管，该晶体管Mf3以P型晶体管为例)、晶体管Mf4(也就是上述的第四晶体管，该晶体管Mf4以N型晶体管为例)、晶体管Mf5(也就是上述的第五晶体管，该晶体管Mf5以N型晶体管为例)以及晶体管Mf6(也就是上述的第六晶体管，该晶体管Mf6以N型晶体管为例)。晶体管Mf3的第一端连接电源Vdd，晶体管Mf3的第二端连接晶体管Mf4的第一端，晶体管Mf4的第二端连接晶体管Mf5的第一端；晶体管Mf5的第二端连接地GND；晶体管Mf6的第一端连接晶体管Mf4的第二端，晶体管Mf6的控制端连接晶体管Mf3的第二端，晶体管Mf6的第二端连接电源Vdd；晶体管Mf3的控制端、晶体管Mf4的控制端以及晶体管Mf5的控制端连接反馈电路602包括的反相器的输入端；晶体管Mf3的第二端还连接反馈电路602包括的反相器的输出端。
在该单端存储器读取存储单元601中的存储信息时，该存储信息为高电平，存储单元601向读位线RBL-1输出高电平，尽管此时读位线RBL-1的电平会因为漏电电流的存在而降低，但是在读位线RBL-1的电平处于第二预定值(该第二预定值可以是半斯密特反相器的正向阈值电压)和高电平之间时，反馈电路602包括的反相器的输入端电平都被认为是高电平，使得晶体管Mf3的控制端电平为高电平，晶体管Mf3关闭，而晶体管Mf4和晶体管Mf5的控制端电平为高电平，晶体管Mf4和晶体管Mf5开启。由于晶体管Mf3关闭，晶体管Mf4和晶体管Mf5开启，使得晶体管Mf3的第二端连接地GND，晶体管Mf3的第二端的电平为低电平，晶体管Mf3的第二端所连接的晶体管Mf6的控制端电平也为低电平，晶体管Mf6关闭。则该反相器的输出端输出电平为低电平，此时反馈电路602向漏电电流补偿单元(也就是晶体管M63，该晶体管M63以P 型晶体管为例)的控制端输出的反馈信号S4为低电平，以此控制晶体管M63开启，读位线RBL-1通过晶体管M63连接至电源Vdd，电源Vdd为读位线RBL-1充电，读位线RBL-1保持高电平。
在该单端存储器读取存储单元601的存储信息时，该存储信息为低电平，存储单元601向读位线RBL-1输出低电平，则读位线RBL-1的电平开始降低，在读位线RBL-1的电平降低至第一预定值时(该第一预定值可以是半斯密特反相器的负向阈值电压)，反馈电路602包括的反相器的输入端电平被认为是低电平，使得晶体管Mf3的控制端电平为低电平，晶体管Mf3开启，而晶体管Mf4和晶体管Mf5的控制端电平为低电平时，晶体管Mf4和晶体管Mf5关闭。由于晶体管Mf3开启，晶体管Mf4和晶体管Mf5关闭，使得晶体管Mf3的第二端连接电源Vdd，晶体管Mf3的第二端的电平为高电平，晶体管Mf3的第二端所连接的晶体管Mf6的控制端电平为高电平，晶体管Mf6开启，晶体管Mf4的第二端通过晶体管Mf6也连接至电源Vdd，使得晶体管Mf3的第二端维持高电平。因此，反相器的输出端输出电平为高电平，此时反馈电路602向漏电电流补偿单元(也就是晶体管M63，该晶体管M63以P型晶体管为例)的控制端输出的反馈信号S4为高电平，以此控制晶体管M63关闭，读位线RBL-1不能通过晶体管M63连接至电源Vdd，电源Vdd不会为读位线RBL-1充电，读位线RBL-1的电平持续降低至低电平。
其中，反馈电路602也可以通过设置逻辑门电路实现根据读位线的电平生成反馈信号，参照图9所示，本申请的实施例提供了一种单端存储器的结构示意图，在图9所示的单端存储器中，反馈电路602包括：第一或非门以及第一非门。
具体的，如图9所示，该单端存储器的反馈电路602包括非门6020(也就是上述的第一非门)和或非门6021(也就是上述的第一或非门)，非门6020的输入端连接晶体管M61(也就是上述的列选择单元，该晶体管M61以N型晶体管为例)的控制端，非门6020的输出端连接或非门6021的第一输入端；或非门6021的第二输入端连接读位线RBL-1；或非门6021的输出端连接漏电电流补偿单元(也就是晶体管M63,该晶体管M63以P型晶体管为例)的控制端。
示例性的，参照图9所示，非门6020的输入端连接列选择单元的控制端，具体表示晶体管M61的控制端输入的是列选择信号S2，非门6020的输入端输入的也是列选择信号S2。
在该单端存储器读取存储单元601中的存储信息时，该存储信息为高电平，存储单元601向读位线RBL-1输出高电平，尽管此时读位线RBL-1的电平会因为漏电电流的存在而降低，但是在读位线RBL-1的电平处于第二预定值和高电平之间时，反馈电路602包括的或非门6021的第二输入端输入的电平被认为是高电平。由于在读取数据发生时列选择信号S2就会是高电平，使得列选择信号S2通过非门6020输出至或非门6021的第一输入端的电平为低电平，或非门6021执行或非操作，使得或非门6021的输出端为低电平，此时反馈电路602向晶体管M63的控制端输出的反馈信号S4为低电平，晶体管M63开启，读位线RBL-1通过晶体管M63连接至电源Vdd，电源Vdd为读位线RBL-1充电，读位线RBL-1保持高电平。
在该单端存储器读取存储单元601的存储信息时，该存储信息为低电平，存储单 元601向读位线RBL-1输出低电平，则读位线RBL-1的电平开始降低，在读位线RBL-1的电平降低至第一预定值时，反馈电路602包括的或非门6021的第二输入端输入的电平被认为是低电平。由于在读取数据发生时列选择信号S2就会是高电平，使得列选择信号S2通过非门6020输出至或非门6021的第一输入端的电平为低电平，或非门6021执行或非操作，使得或非门6021的输出端为高电平，此时反馈电路602向晶体管M63的控制端输出的反馈信号S4为高电平，晶体管M63关闭，读位线RBL-1不会通过晶体管M63连接至电源Vdd，电源Vdd不再为读位线RBL-1充电，读位线RBL-1的电平持续降低至低电平。
在另一些实施例中，单端存储器的漏电电流补偿单元可以通过第一开关单元连接读位线，第一开关单元的控制端连接列选择单元的控制端。
具体的，参照图10所示，本申请的实施例提供了一种单端存储器的结构示意图，该单端存储器还包括晶体管M65(也就是上述的第一开关单元,该晶体管M65以N型晶体管为例)。其中，晶体管M65的第一端连接晶体管M63(也就是上述的漏电电流补偿单元,该晶体管M63以P型晶体管为例)的第二端，晶体管M63的第一端连接电源Vdd,晶体管M65的第二端连接晶体管M61(也就是上述的列选择单元,该晶体管M61以N型晶体管为例)的第二端，晶体管M61的第一端连接于读位线RBL-1。上述的第一开关单元的控制端连接列选择单元的控制端代表列选择单元的控制端输入的是列选择信号S2，晶体管M65的控制端输入的也是列选择信号S2。在该单端存储器读取存储单元601中的存储信息时，列选择信号S2会设置为高电平，因此晶体管M61和晶体管M65的控制端的电平为高电平，晶体管M61和晶体管M65开启，电源Vdd通过晶体管M61、晶体管M65和晶体管M63连接至读位线RBL-1。由于列选择单端的控制端信号也同时控制第一开关单元的开启或关闭，因此确保在列选择单元被其控制端的信号开启以选中读位线时，能够同时将第一开关单元开启以将漏电电流补偿单元接入读位线，使得漏电电流补偿单元能够在读位线被选中时，及时对读位线的电平进行补偿或停止补偿，实现了漏电电流补偿单元同读位线被选中自适应地工作。
示例性的，为了使得该单端存储器读取存储信息为低电平的速度更快，本申请的实施例提供了一种单端存储器。该单端存储器还包括：放电单元，放电单元的控制端连接漏电电流补偿单元的控制端；放电单元的第一端通过列选择单元连接读位线；放电单元的第二端连接地。
具体的，参照图11所示，本申请的实施例提供了一种单端存储器的结构示意图。该单端存储器还包括放电单元604，放电单元604包括晶体管Md1(该晶体管Md1以N型晶体管为例)。晶体管Md1的控制端连接漏电电流补偿单元(也就是晶体管M63，该晶体管M63以P型晶体管为例)的控制端，晶体管Md1的第二端连接地GND，晶体管Md1的第一端连接通过晶体管M61(也就是上述的列选择单元，该晶体管M61以N型晶体管为例)的第二端，晶体管M61的第一端连接于读位线RBL-1。
在该单端存储器读取存储单元601中的存储信息时，该存储信息为高电平，存储单元601向读位线RBL-1输出高电平，反馈电路602在确定读位线RBL-1的电平高于第二预定值时，向晶体管M63的控制端输出反馈信号S4，该反馈信号S4为低电平，晶体管M63开启，以控制电源Vdd通过晶体管M63向读位线RBL-1充电，使得读位线 RBL-1保持高电平。与此同时，晶体管Md1的控制端也接收到反馈信号S4，因为反馈信号S4为低电平，所以晶体管Md1关闭，读位线RBL-1不会通过晶体管Md1而连接地GND，以确保读位线RBL-1保持高电平。
在该单端存储器读取存储单元601的存储信息时，该存储信息为低电平，存储单元601向读位线RBL-1输出低电平，则读位线RBL-1的电平开始降低，在读位线RBL-1的电平降低至第一预定值时，反馈电路602向晶体管M63的控制端输出反馈信号S4，该反馈信号S4为高电平，晶体管M63关闭，以停止电源Vdd通过晶体管M63向读位线RBL-1充电，使得读位线RBL-1的电平持续降低至低电平。与此同时，晶体管Md1的控制端也接收到反馈信号S4，因为反馈信号S4为高电平，所以晶体管Md1开启，读位线RBL-1会通过晶体管Md1而连接地GND，读位线RBL-1的电平降低，晶体管Md1使得读位线RBL-1的电平降低速度变快。这样的单端存储器通过晶体管M63和晶体管Md1的协同作用，保证在存储信息为低电平时读位线RBL-1的电平能尽快降低至低电平，提升单端存储器的读取速度。
在一些实施例中，为了避免放电单元反应过于灵敏，出现在读位线的电平由于漏电电流的产生而降低，放电单元就将读位线连接地进行放电，造成读取数据出错的问题，本申请的实施例还提供了一种单端存储器的放电单元，该单端存储器的放电单元包括第七晶体管和第八晶体管。
具体的，参照图12所示，本申请的实施例提供了一种单端存储器的结构示意图，在图12所示的单端存储器中，示出了放电单元604的一种具体结构，该放电单元604包括晶体管Md2(也就是上述的第七晶体管，该晶体管Md2以N型晶体管为例)和晶体管Md3(也就是上述的第八晶体管，该晶体管Md3以N型晶体管为例)。晶体管Md2的控制端连接晶体管M63的控制端(也就是上述的连接漏电电流补偿单元,该晶体管M63以P型晶体管为例)，晶体管Md2的第一端连接晶体管M61的第二端(也就是上述的列选择单元，该晶体管M61以N型晶体管为例)，晶体管M61的第一端连接读位线RBL-1，晶体管Md2的第二端连接晶体管Md3的控制端，晶体管Md2的第二端还连接晶体管Md3的第一端，晶体管Md3的第二端连接地。
在该单端存储器读取存储单元601中的存储信息时，该存储信息为高电平，存储单元601向读位线RBL-1输出高电平，反馈电路602在确定读位线RBL-1的电平高于第二预定值时，向晶体管M63的控制端输出反馈信号S4，该反馈信号S4为低电平，晶体管M63开启，以控制电源Vdd通过晶体管M63向读位线RBL-1充电，使得读位线RBL-1保持高电平。与此同时，晶体管Md2的控制端也接收到反馈信号S4，因为反馈信号S4为低电平，所以晶体管Md2关闭，由于晶体管Md2的第二端连接晶体管Md3的控制端，因此晶体管Md3也关闭，读位线RBL-1不会通过晶体管Md2和晶体管Md3而连接地GND，以确保读位线RBL-1保持高电平。
在该单端存储器读取存储单元601的存储信息时，该存储信息为低电平，存储单元601向读位线RBL-1输出低电平，则读位线RBL-1的电平开始降低，在读位线RBL-1的电平降低至第一预定值时，反馈电路602向晶体管M63的控制端输出反馈信号S4，该反馈信号S4为高电平，晶体管M63关闭，以停止电源Vdd通过晶体管M63向读位线RBL-1充电，使得读位线RBL-1的电平持续降低至低电平。与此同时，晶体管Md2的 控制端也接收到反馈信号S4，因为反馈信号S4为高电平，所以晶体管Md2开启，由于晶体管Md2的第二端连接晶体管Md3的控制端和第一端，晶体管Md3的第二端连接地GND，也就证明此时的放电单元604是通过晶体管Md2和晶体管Md3而连接地GND，晶体管Md2和晶体管Md3这样的连接方式会使得当前放电单元604的等效电阻变大，那么放电单元604的放电速度会变缓。如果当前读位线RBL-1的电平是因为漏电电流的存在而降低的，这样设置的放电单元604就不会直接将读位线RBL-1的连接地，造成存储信息读取出错的问题，使得该单端存储器的读取性能更稳定。
在另一些实施例中，该单端存储器包括第二非门，放电单元包括：第九晶体管。
具体的，参照图13所示，本申请的实施例提供了一种单端存储器的结构示意图，在图13所示的单端存储器中，详细示出了放电单元604的另一种具体结构，该放电单元604包括晶体管Md4(也就是上述的第九晶体管，该晶体管Md4以P型晶体管为例)，。该单端存储器还包括非门605(也就是上述的第二非门)，晶体管M63(也就是上述的漏电电流补偿单元，该晶体管M63以P型晶体管为例)的控制端连接于非门605的输入端，非门605的输出端连接至晶体管Md4的控制端，晶体管Md4的第二端连接地GND，晶体管Md4的第一端连接晶体管M61的第二端(也就是上述的列选择单元，该晶体管M61以N型晶体管为例)，晶体管M61的第一端连接读位线RBL-1。
在该单端存储器读取存储单元601中的存储信息时，该存储信息为高电平，存储单元601向读位线RBL-1输出高电平，反馈电路602在确定读位线RBL-1的电平高于第二预定值时，向晶体管M63的控制端输出反馈信号S4，该反馈信号S4为低电平，晶体管M63开启，以控制电源Vdd通过晶体管M63向读位线RBL-1充电，使得读位线RBL-1保持高电平。与此同时，反馈信号S4通过非门605取非操作变成高电平，并输入到晶体管Md4的控制端，晶体管Md4关闭，读位线RBL-1不会通过晶体管Md4而连接地GND，以确保读位线RBL-1保持高电平。
在该单端存储器读取存储单元601的存储信息时，该存储信息为低电平，存储单元601向读位线RBL-1输出低电平，则读位线RBL-1的电平开始降低，在读位线RBL-1的电平降低至第一预定值时，反馈电路602向晶体管M63的控制端输出反馈信号S4，该反馈信号S4为高电平，晶体管M63关闭，以停止电源Vdd通过晶体管M63向读位线RBL-1充电，使得读位线RBL-1的电平持续降低至低电平。与此同时，反馈信号S4通过非门605变成低电平，并输入到晶体管Md4的控制端，晶体管Md4开启，读位线RBL-1通过晶体管Md4而连接地GND，但是，由于晶体管Md4为P型晶体管，P型晶体管传递电平时会存在阈值损失，由此也使得放电单元604的放电速度变缓。如果当前读位线RBL-1的电平是因为漏电电流的存在而降低的，这样设置的放电单元604不会直接将读位线RBL-1的电平降低至低电平，使得该单端存储器的读取性能更稳定。
本申请的实施例还提供了一种单端存储器，该单端存储器在放电单元的第一端与列选择单元之间还设置有第二开关单元。
具体的，参照图14所示，本申请的实施例提供了一种单端存储器的结构示意图，该单端存储器还包括晶体管M66(也就是上述的第二开关单元，该晶体管M66以N型晶体管为例)。放电单元604的第一端连接晶体管M66的第二端，晶体管M66的第一端连接至晶体管M61的第二端(也就是上述的列选择单元，该晶体管M61以N型晶体 管为例)，晶体管M61的第一端连接读位线RBL-1。其中，晶体管M66的控制端可以连接至该单端存储器的跟踪电路(tracking)，其中该跟踪电路可以跟踪全局位线GBL上的电平变化，在全局位线GBL读取低电平之前，将晶体管M66开启；在全局位线GBL读取高电平之前，将晶体管M66关闭。具体的，可以在全局位线GBL读取低电平之前提前δt1的时间量向M66的控制端输出高电平，以控制晶体管M66开启，放电单元604通过晶体管M66和晶体管M61连接读位线RBL-1，放电单元604将加速对读位线RBL-1放电，以使得读位线RBL-1更快降低至低电平。另一方面，可以在全局位线GBL读取高电平之前提前δt2的时间量向晶体管M66的控制端输出低电平，以控制晶体管M66关闭，放电单元604不能通过晶体管M66和晶体管M61连接读位线RBL-1，如果当前的读位线RBL-1的电平由于漏电电流的产生而降低时，放电单元604不会将读位线RBL-1连接地进行放电，确保该单端存储器读取存储信息为高电平的性能。其中，上述的δt1的时间量以及上述的δt2的时间量可以默认配置或自适应调整。
或者，晶体管M66的控制端可以连接至该单端存储器的外部测试管脚。具体的，在读取存储单元601的存储信息时，可以选择通过外部测试管传输低电平控制晶体管M66关闭，使得放电单元604不能通过晶体管M66和晶体管M61接入读位线RBL-1，如果当前的读位线RBL-1的电平由于漏电电流的产生而降低时，放电单元604不会将读位线RBL-1连接地进行放电，确保该单端存储器读取存储信息为高电平的性能。另一方面，在读取存储单元601的存储信息时，可以选择通过外部测试管传输高电平控制晶体管M66开启，使得放电单元604通过晶体管M66和晶体管M61接入读位线RBL-1，放电单元604将加速对读位线RBL-1放电，以使得读位线RBL-1更快降低至低电平。
在其他的实施例中，放电单元的控制端可以通过类似于反馈电路602的电路连接结构来控制其开启或关闭。示例性的，该单端存储器还包括：第二或非门以及第三非门。
具体的，参照图15所示，图15为本申请的实施例提供的单端存储器的结构示意图，该单端存储器还包括非门606(也就是上述的第三非门)和或非门607(也就是上述的第二或非门)，非门606的输入端连接晶体管M61(也就是上述的列选择单元，该晶体管M61以N型晶体管为例)的控制端，非门606的输出端连接至或非门607的第一输入端，读位线RBL-1连接至或非门607的第二输入端，或非门607的输出端连接至放电单元604的控制端。
示例性的，参照图15所示，非门606的输入端连接列选择单元的控制端，具体表示晶体管M61的控制端输入的是列选择信号S2，非门606的输入端输入的也是列选择信号S2。
在该单端存储器读取存储单元601中的存储信息时，该存储信息为高电平，存储单元601向读位线RBL-1输出高电平，尽管此时读位线RBL-1的电平会因为漏电电流的存在而降低，但是在读位线RBL-1的电平处于第二预定值和高电平之间时，或非门607的第二输入端输入的电平被认为是高电平。由于在读取发生时列选择信号S2就会是高电平，使得列选择信号S2通过非门606输出至或非门607的第一输入端的电平为低电平，或非门607执行或非操作，使得或非门607传输至放电单元604的控制端的电平为低电平。
在该单端存储器读取存储单元601的存储信息时，该存储信息为低电平，存储单元601向读位线RBL-1输出低电平，则读位线RBL-1的电平开始降低，在读位线RBL-1的电平降低至第一预定值时，或非门607的第二输入端输入的电平被认为是低电平。由于在读取发生时列选择信号S2就会是高电平，使得列选择信号S2通过非门606输出至或非门607的第一输入端的电平为低电平，或非门607执行或非操作，使得或非门607传输至放电单元604的控制端的电平为高电平。
需要说明的是，或非门607传输至放电单元604的控制端的低电平，可以是控制放电单元604内的晶体管开启(放电单元604中设置P型晶体管)进行放电，也可以是控制放电单元604内的晶体管关闭(放电单元604中设置N型晶体管)不进行放电。或非门607传输至放电单元604的控制端的高电平，可以是控制放电单元604内的晶体管开启(放电单元604中设置N型晶体管)进行放电，也可以是控制放电单元604内的晶体管关闭(放电单元604中设置P型晶体管)不进行放电。
示例性的，当单端存储器的反馈电路602包括反相器，并且设置放电单元604时，通过选取慢的N型晶体管和快的P型晶体管工艺角(slow NMOS fast PMOS concer,SNFP concer)，电平设置为0.6伏，温度设置为-40摄氏度。或者选取典型工艺角(tipical concer，TT concer)，电平设置为1.2伏，温度设置为25摄氏度，对单端存储器的反馈信号以及读取时间进行仿真，仿真图如图16和图17所示。
需要说明的是，上述实施例所描述的电平升高至高电平或者电平降低至低电平，其变化过程都是逐渐改变的，在仿真图中由于设置的时间间隔非常短，所以该逐渐变化的过程会很明显。
以读取的存储单元的存储信息为低电平进行仿真，得到图16所示的现有的单端存储器中全局位线GBL的电平变化情况(曲线一)，本申请的实施例提供的单端存储器中全局位线GBL的电平变化情况(曲线二)。具体结合曲线一以及图5对现有的单端存储器的存储单元的存储信息(低电平)的读取过程说明如下。其中CLK时钟的上升沿(也就是CLK时钟刚开始为高电平)到来时，读位线RBL-1被选通，在t1时刻，预充电单元M41开启，预充电单元M41向读位线RBL-1充电，同时其他读位线RBL-n和全局位线GBL的电平也不断升高。也就是曲线一的t1时刻至t2时刻，全局位线GBL的电平不断升高至高电平。然后，读字线将存储单元c1选中，存储单元c1向读位线RBL-1输出低电平的存储信息，该低电平的存储信息为低电平使得读位线RBL-1的电平不断降低。但是，在读位线RBL-1的电平没有降低至低电平之前，与非门401的第一端接收的读位线RBL-1的电平为高电平，与非门401的第二端接收的其他读位线RBL-n的电平为高电平，与非门401执行与非操作输出低电平，使得晶体管M42的控制端电平为低电平，晶体管M42开启，读位线RBL-1通过晶体管M42连接至电源Vdd，电源Vdd为读位线RBL-1充电，读位线RBL-1的电平降低速度缓慢。对应于曲线一的t2时刻至t3时刻，由于读位线的电平降低速度缓慢，没有降低至低电平，因此与非门401输出的电平为低电平，晶体管M45关闭，全局位线GBL不能通过晶体管M45连接地，因此全局位线GBL的电平在t2时刻至t3时刻保持一段高电平。在读位线RBL-1的电平降低至低电平时，与非门401执行与非操作输出高电平，晶体管M42关闭，并且晶体管M45开启，全局位线GBL通过晶体管M45连接地，使得全局位线GBL的电平 不断降低，也就是在t3时刻至t6时刻，全局位线GBL不断降低至低电平。与该全局位线GBL耦合的输入/输出电路可以确定当前全局位线GBL的电平为低电平，也可以确定当前存储单元c1的存储信息为低电平。
其次，结合曲线二以及图15对本申请的实施例提供的单端存储器的存储单元的存储信息(低电平)的读取过程说明如下。参照图16的曲线二以及图15所示的单端存储器，其中CLK时钟的上升沿(也就是CLK时钟刚开始为高电平)到来时，列选择单元M61开启，读位线RBL-1被选通，在t1时刻，预充电单元M62开启，预充电单元M62向读位线RBL-1充电，读位线RBL-1的电平不断升高，同时其他读位线RBL-n和全局位线GBL的电平也不断升高，也就是曲线一的t1时刻至t3时刻，全局位线GBL的电平不断升高至高电平。其中，反馈电路602确定读位线RBL-1的电平高于第二预定值时，向漏电电流补偿单元M63的控制端输出反馈信号，以控制漏电电流补偿单元M63通过输出端向读位线RBL-1充电，使得读位线RBL-1的保持高电平。在t3时刻，读字线RWL将存储单元601选中，存储单元601向读位线RBL-1输出存储信息，该存储信息为低电平使得读位线RBL-1的电平开始降低，由于此时的漏电电流补偿单元M63并没有关闭，漏电电流补偿单元M63还在为读位线RBL-1充电，使得读位线RBL-1的电平降低速度缓慢。反馈电路602在确定读位线RBL-1的电平低于第一预定值时，向漏电电流补偿单元M63的控制端输出反馈信号，以停止漏电电流补偿单元M63通过输出端向读位线RBL-1充电，此时读位线RBL-1的电平降低速度变快，在读位线RBL-1的电平降低至低电平时，与非门603执行与非操作，晶体管M64开启，全局位线GBL通过晶体管M64连接地，使得全局位线GBL的电平不断降低，也就是在t3时刻至t5时刻，全局位线GBL不断降低。其中到t4时刻，由于放电单元604打开，读位线RBL-1的电平开始快速降低，反映到全局位线GBL上则可以看到全局位线GBL(也就是曲线二)在t4时刻电平降低速度也明显地加快。与该全局位线GBL耦合的输入/输出电路在t5时刻可以确定全局位线GBL的电平为低电平，也可以确定当前存储单元601的存储信息为低电平。
参照图16可以得知现有的单端存储器从CLK时钟上升沿到来，到全局位线GBL读取到存储信息为低电平，消耗的时长为t6-t1，是1.4纳秒(该时长是读取时间)；而本申请的实施例提供的单端存储器从CLK时钟上升沿到来，到全局位线GBL读取到存储信息为低电平，消耗的时长为t5-t1，是0.8纳秒(该时长是读取时间)。本申请的实施例提供的单端存储器的读取时间相较于现有的单端存储器提升了40％。
图17示出了现有的单端存储器中漏电电流补偿单元接收到的反馈信号的电平变化情况(曲线三)，本申请的实施例提供的单端存储器中漏电电流补偿单元接收到的反馈信号的电平变化情况(曲线四)。具体结合曲线三以及图5对现有的单端存储器的存储单元的存储信息(低电平)的读取过程说明如下。其中CLK时钟的上升沿(也就是CLK时钟刚开始为高电平)到来时，读位线RBL-1被选通，在t1时刻，预充电单元M41开启，预充电单元M41向读位线RBL-1充电，读位线RBL-1的电平不断升高，同时其他读位线RBL-n和全局位线GBL的电平也不断升高，与非门401的第一端接收的读位线RBL-1的电平为高电平，与非门401的第二端接收的其他读位线RBL-n的电平为高电平，与非门401执行与非操作输出低电平，使得晶体管M42的控制端电平(也 就是晶体管M42收到的反馈信号)为低电平，晶体管M42开启，也就是在t2’时刻，与非门401向晶体管M42的控制端输出的反馈信号为低电平，控制晶体管M42开启，电源Vdd通过晶体管M42向读位线RBL-1充电，所以曲线三所示的反馈信号的电平在t2’时刻迅速降低。到t5’时刻时，读位线RBL-1的电平降低至低电平，与非门401的第一端接收的读位线RBL-1的电平为低电平，与非门401的第二端接收的其他读位线RBL-n的电平为高电平，与非门401执行与非操作输出高电平，也就是在t5’时刻，参照曲线三，与非门401向晶体管M42的控制端输出反馈信号，该反馈信号为高电平，控制晶体管M42关闭。同时，与非门401输出的高电平也使得晶体管M45开启，全局位线GBL通过晶体管M45开始放电，全局位线GBL的电平变低，在全局位线GBL的电平降低至低电平时，与该全局位线GBL耦合的输入/输出电路确定存储单元c1的存储信息为低电平。
其次，结合曲线四以及图15对本申请的实施例提供的单端存储器的存储单元的存储信息(低电平)的读取过程说明如下。参照图17的曲线四以及图15所示的单端存储器，其中CLK时钟的上升沿(也就是CLK时钟刚开始为高电平)到来时，列选择单元M61开启，读位线RBL-1被选通，在t1时刻，预充电单元M62开启，预充电单元M62向读位线RBL-1充电，在读位线RBL-1被充电的过程中，反馈电路602确定读位线RBL-1的电平高于第二预定值时，向漏电电流补偿单元M63的控制端输出反馈信号，该反馈信号为低电平，参照曲线四，也就是在t3’时刻，反馈信号变为低电平控制漏电电流补偿单元M63通过输出端向读位线RBL-1充电。在读字线RWL将存储单元601选中，存储单元601向读位线RBL-1输出存储信息，该存储信息为低电平使得读位线RBL-1的电平开始降低，反馈电路602在确定读位线RBL-1的电平低于第一预定值时，向漏电电流补偿单元M63的控制端输出反馈信号，该反馈信号为高电平，参照曲线四，也就是在t4’时刻，反馈信号变为高电平以停止漏电电流补偿单元M63通过输出端向读位线RBL-1充电，此时读位线RBL-1的电平降低速度变快，并且由于放电单元604的存在，读位线RBL-1的电平快速降低至低电平。与非门603执行与非操作输出高电平，则晶体管M64开启，全局位线GBL通过晶体管M64连接地，全局位线GBL的电平变低，与该全局位线GBL耦合的输入/输出电路读取存储单元601的存储信息为低电平。
参照图17可以得知现有的单端存储器从CLK时钟上升沿到来，反馈信号从高电平变为低电平再变为高电平，消耗的时长为t5’-t1，是1.47纳秒；而本申请的实施例提供的单端存储器从列选择信号的时钟上升沿到来，反馈信号从高电平变为低电平再变为高电平，消耗的时长为t4’-t1，是1.01纳秒。本申请的实施例提供的单端存储器的反馈信号变化时间相较于现有的单端存储器提升了46％。本申请的实施例提供的单端存储器的反馈信号相比于现有的单端存储器的反馈信号可以更早地变为高电平。
需要说明的是，为了清楚描述本申请提供的各个实施例，本申请的实施例中使用的晶体管的类型均示出，可以理解的是，在本领域技术人员不脱离本申请的思想的前提下，本申请的实施例所提供的晶体管的类型可以适应性的改变，对应的该晶体管的控制端的电平也可以适应性地改变，这种改变被认为是符合本申请所要保护的范围内。
尽管结合具体特征及其实施例对本申请进行了描述，显而易见的，在不脱离本申请的精神和范围的情况下，可对其进行各种修改和组合。相应地，本说明书和附图仅 仅是所附权利要求所界定的本申请的示例性说明，且视为已覆盖本申请范围内的任意和所有修改、变化、组合或等同物。显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包括这些改动和变型在内。

Claims (14)

  1. 一种单端存储器，其特征在于，包括阵列分布的存储单元，所述存储单元连接读位线以及读字线；所述读位线通过列选择单元连接预充电单元；所述读位线通过所述列选择单元连接漏电电流补偿单元的输出端；所述读位线还通过反馈电路连接所述漏电电流补偿单元的控制端；
    所述反馈电路在确定所述读位线的电平低于第一预定值时，向所述漏电电流补偿单元的控制端输出反馈信号，以停止所述漏电电流补偿单元通过输出端向所述读位线充电。
  2. 根据权利要求1所述的单端存储器，其特征在于，
    所述反馈电路确定所述读位线的电平高于第二预定值时，向所述漏电电流补偿单元的控制端输出反馈信号，以控制所述漏电电流补偿单元通过输出端向所述读位线充电，其中所述第一预定值小于或等于所述第二预定值。
  3. 根据权利要求1或2所述的单端存储器，其特征在于，所述反馈电路包括：反相器；
    所述反相器的输入端连接所述读位线，所述反相器的输出端连接所述漏电电流补偿单元的控制端；
    其中所述反相器用于根据所述读位线的电平生成所述反馈信号。
  4. 根据权利要求3所述的单端存储器，其特征在于，所述反相器包括：第一晶体管和第二晶体管；
    所述第一晶体管的第一端连接电源，所述第一晶体管的第二端连接所述第二晶体管的第一端，所述第二晶体管的第二端连接地，所述第一晶体管的控制端与所述第二晶体管的控制端连接所述反相器的输入端；所述第一晶体管的第二端还连接所述反相器的输出端；
    所述第一晶体管与所述第二晶体管的类型不同。
  5. 根据权利要求3所述的单端存储器，其特征在于，所述反相器包括：第三晶体管、第四晶体管、第五晶体管和第六晶体管；
    所述第三晶体管的第一端连接电源，所述第三晶体管的第二端连接所述第四晶体管的第一端，所述第四晶体管的第二端连接所述第五晶体管的第一端；所述第五晶体管的第二端连接地；所述第六晶体管的第一端连接所述第四晶体管的第二端，所述第六晶体管的控制端连接所述第三晶体管的第二端，所述第六晶体管的第二端连接电源；
    所述第三晶体管的控制端、所述第四晶体管的控制端以及所述第五晶体管的控制端连接所述反相器的输入端；所述第三晶体管的第二端还连接所述反相器的输出端；
    所述第四晶体管、所述第五晶体管以及所述第六晶体管的类型相同，所述第三晶体管与所述第四晶体管的类型不同。
  6. 根据权利要求1或2所述的单端存储器，其特征在于，所述反馈电路包括：第一或非门以及第一非门；
    其中，所述第一非门的输入端连接所述列选择单元的控制端，所述第一非门的输出端连接所述第一或非门的第一输入端；
    所述第一或非门的第二输入端连接所述读位线；所述第一或非门的输出端连接所 述漏电电流补偿单元的控制端。
  7. 根据权利要求1-6任一项所述的单端存储器，其特征在于，
    当所述预充电单元通过所述列选择单元向所述读位线充电后，若所述读字线将所述存储单元选中，则所述存储单元向所述读位线输出存储信息。
  8. 根据权利要求1-6任一项所述的单端存储器，其特征在于，
    所述反馈电路连接于所述存储单元与所述列选择单元之间的传输路径上。
  9. 根据权利要求1-8任一项所述的单端存储器，其特征在于，所述单端存储器还包括：第一开关单元，所述漏电电流补偿单元通过所述第一开关单元连接所述读位线，所述第一开关单元的控制端连接所述列选择单元的控制端。
  10. 根据权利要求1-8任一项所述的单端存储器，其特征在于，
    所述单端存储器还包括：放电单元，所述放电单元的控制端连接所述漏电电流补偿单元的控制端；
    所述放电单元的第一端通过所述列选择单元连接所述读位线；所述放电单元的第二端连接地。
  11. 根据权利要求10所述的单端存储器，其特征在于，所述放电单元，包括第七晶体管和第八晶体管；
    所述第七晶体管的控制端连接所述漏电电流补偿单元的控制端，所述第七晶体管的第一端通过所述列选择单元连接所述读位线；所述第七晶体管的第二端连接所述第八晶体管的控制端，所述第七晶体管的第二端还连接所述第八晶体管的第一端，所述第八晶体管的第二端连接地。
  12. 根据权利要求10所述的单端存储器，其特征在于，所述放电单元包括：第九晶体管，所述漏电电流补偿单元的控制端通过第二非门连接所述第九晶体管的控制端，所述第九晶体管的第一端通过所述列选择单元连接所述读位线；所述第九晶体管的第二端连接地。
  13. 根据权利要求10-12任一项所述的单端存储器，其特征在于，所述放电单元的第一端与所述列选择单元之间还设置有第二开关单元。
  14. 根据权利要求10所述的单端存储器，其特征在于，所述单端存储器还包括：第二或非门以及第三非门；
    其中所述第三非门的输入端连接所述列选择单元的控制端，所述第三非门的输出端连接所述第二或非门的第一输入端；
    所述第二或非门的第二输入端连接所述读位线；所述第二或非门的输出端连接所述放电单元的控制端。
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