WO2023069916A1

WO2023069916A1 - Buried photodetector with hetero structure as a gate

Info

Publication number: WO2023069916A1
Application number: PCT/US2022/078250
Authority: WO
Inventors: Martin Ettenberg; Michael Ettenberg
Original assignee: Princeton Infrared Technologies, Inc.
Priority date: 2021-10-20
Filing date: 2022-10-18
Publication date: 2023-04-27

Abstract

Disclosed herein are device and method embodiments for photodetectors photo-detection. For example, a photodetector includes one or more pixels region of semiconductor material configured to accumulate photocurrent, one or more sense regions of semiconductor material (each sense region associated with a corresponding pixel region) a hetero junction interposed between at least one sense region and its corresponding pixel region (wherein the hetero junction is operable, in a first state, to maintain the photocurrent in the pixel region, and operable, in a second state, to allow the photocurrent to move from the pixel region to its corresponding sense region) and readout electronics configured to operate the hetero junction, causing the accumulated photocurrent to move from pixel regions to corresponding sense regions, the readout electronics further configured to measure the photocurrent at the corresponding sense regions.

Description

BURIED PHOTODETECTOR WITH HETERO STRUCTURE AS A GATE

TECHNICAL FIELD

[0001] The present disclosure generally relates to semiconductor photon detectors.

BACKGROUND

[0002] A focal plane array is a detector array (e.g., 1-dimensional (1-D) or 2-Dimensional (2- D)) that includes multiple pixels (picture elements). The pixels are typically connected to a Read Out Integrated Circuit (ROIC). Photodetector arrays made from Indium Gallium Arsenide (InGaAs) alloys In_xGai-_xAs alloy have been used in telecommunications, spectroscopy, and imaging. Depending on the composition of the InGaAs alloy, the detector can detect photons in the range from 400 nm to 2700 nm. A common composition is an InGaAs alloy including 53% InAs and 47% GaAs (Ino.53Gao.47As) which is lattice-matched to Indium phosphide (InP), enabling detection of photons from 400 nm to 1700 nm. These detector arrays (either 1-D or 2- D) are interfaced with an ROIC, which converts accumulated charge to a voltage through an amplification circuit associated with each pixel. This enables measurement of the amount of light that strikes the detector in a given amount of time.

[0003] Focal plane arrays may be monolithic p-i-n or p-n photodetector arrays. The array may have a high bandgap semiconductor, e.g., a InP, Indium Arsenide Phosphide (InAsP), _or Indium Aluminum Arsenide (InAlAs) cap layer above the InGaAs to minimize the dark current and surface recombination from electron hole pairs that are formed in the detector material. The pixel may be formed by diffusing or implanting a p-type dopant such as Zn, Be, or Cd into the structure from the surface down to the InGaAs layer through the higher bandgap cap layer. An ohmic contact (or near ohmic contact) may be made on top of the p-type area to allow the pixel to be biased and to remove the charge collected (both dark charge as well as charge from photons that are converted to electron hole pairs). A second contact may be made elsewhere to the n-side (e.g., Indium Phosphide (InP) or Aluminum Indium Arsenide (InAlAs)) cathode to allow the circuit to be completed. A recurring problem in this filed is reducing dark current and noise. Prior technologies addressed this problem by intentionally doping the intrinsic region of a p-i-n photodiode to reduce the dark current in planar structures, for example. This has been effective but has limits. It still requires the photodiode to be biased which is a source of dark current. There is also the lower bandgap material having a conductive path to the surface where defects occur being a source of dark current.

[0004] This document describes structures methods and systems that are directed to addressing reducing dark current and noise in these hybridized systems as well as similar devices and systems, and/or other issues.

SUMMARY

[0005] At least some of the problems associated with the existing solutions will be shown solved by the subject matter of the independent claims that are included in this document. Additional advantageous aspects are discussed in the dependent claims.

[0006] This disclosure general relates to photodetectors and methods of measuring photon flux. [0007] In an embodiment, a photodetector includes one or more pixels region of semiconductor material configured to accumulate photocurrent, one or more sense regions of semiconductor material (each sense region associated with a corresponding pixel region), a heterojunction interposed between at least one sense region and its corresponding pixel region (wherein the heterojunction is operable, in a first state, to maintain the photocurrent in the pixel region and operable, in a second state, to allow the photocurrent to move from the pixel regions to corresponding sense regions) and readout electronics configured to operate the heterojunction, causing the accumulated photocurrent to move from pixel regions to corresponding sense regions, the readout electronics further configured to measure the photocurrent at the corresponding sense regions.

[0008] Implementations of the disclosure may include one or more of the following optional features. In some examples, the pixel regions are disposed in the interior of a semiconductor device. The pixel regions may include p-type indium gallium arsenide. The heterojunction may include an n-type indium alloy that is lattice matched to the indium gallium arsenide detector. In some examples, the readout electronics operate the heterojunction by applying a voltage across the heterojunction. The readout electronics may be configured to measure the photocurrent at the corresponding sense regions by subtracting a first measurement, taken before the accumulated photocurrent moves to the corresponding sense regions, from a second measurement, taken after the accumulated photocurrent moves to the corresponding sense regions. The pixel regions may be configured to be sensitive to visible and short wavelength infrared light.

[0009] In an embodiment, a method of making a semiconductor photodetector includes forming a cathode layer, growing a detector layer of a first conductivity type adjacent to the cathode layer, doping a plurality of pixel regions of the detector layer to form regions of a second conductivity type (the second conductivity type different than the first conductivity type), growing a cap layer adjacent to the detector layer and the same dopant type as the cathode layer, doping sense regions in the cap layer of the same type of material as the detector region, doping a plurality of sense regions in the cap layer to form regions of the second conductivity type (the plurality of sense regions corresponding to the plurality of pixel regions), and electrically interfacing readout electronics to the cathode layer and the sense regions.

[0010] Implementations of the disclosure may include one or more of the following optional features. The method may further include forming the cathode layer on a substrate layer or using the substrate as the cathode layer. In some examples, the detector layer is grown by epitaxial deposition, and the plurality of pixel regions are doped using Zn, Be, or another p-type dopant before the cap layer is grown on top of the plurality of pixels. In some examples, the method includes etching visible markers in the detector layer before growing the cap layer, the visible markers indicating positions of the plurality of pixel regions. The detector layer and the cap layer may include indium alloys. The cathode layer may be lattice-matched to the detector layer. The cap layer may include a higher bandgap material than the detector layer. The detector layer may include n-type or intrinsic indium gallium arsenide. The cap layer may include indium phosphide or indium aluminum arsenide. The pixel regions may form a one-dimensional line of pixels or two-dimensional grid.

[0011] In an embodiment, a method of measuring photon flux includes accumulating photocurrent in one or more pixel regions disposed in the interior of a semiconductor device and separated from corresponding sense regions by a heterojunction, applying a voltage to the anode sense nodes of the semiconductor device, causing the accumulated photocurrent to move across the heterojunction to corresponding sense regions, removing the applied voltage, and measuring the charge at the corresponding sense regions while the voltage is removed. Removing the charge from the sense region using a different voltage then measuring the sense region again after the removal of the charge to allow corelated double sampling.

[0012] Implementations of the disclosure may include one or more of the following optional features. In some examples, the method further includes measuring the charge at the corresponding sense regions before applying the voltage to the cathode to obtain an offset measurement and subtracting the offset measurement from the measured charge. The one or more pixel regions may be configured to generate photocurrent in response to visible or short wavelength infrared light.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG. 1 is a cross-sectional view of an example semiconductor structure.

[0014] FIG. 2 is a cross-sectional view of the example semiconductor structure showing additional structure.

[0015] FIG. 3 is a cross-sectional view of the example semiconductor structure with readout electronics.

DETAILED DESCRIPTION

[0016] This disclosure relates to a device structure that allows for detection of visible and/or short wavelength infrared light with semiconductor detector arrays of III-V material. In particular, the disclosure relates to detector arrays having photodiodes (e.g., an array or grid of photodiodes) buried within the detector structure (either p-n or p-i-n). e.g., a p-type region formed into an Indium Gallium Arsenide (InGaAs) detector region of the structure. The disclosed structures have lower dark current and lower effective readnoise when reading out accumulated charge as compared to conventional detector structures (i.e., detectors in which the photodiodes are connected directly to readout electronics). While the descriptions below pertain to lattice matched InGaAs detectors used for (e.g., sensitive to) visible and short wavelength infrared (SWIR) radiation, the subject matter of the disclosure can be employed for many other III-V or II- VI semiconductor materials that detect photons in arrays or individual detectors that are integrated to amplification circuits.

[0017] A focal plane array is a detector array, 1-dimensional (ID) or 2-Dimensional (2-D), made of pixels (picture elements) which are connected to a Read Out Integrated Circuit (ROIC). Arrays of photodetectors made of InAs_yPi-_y/In_xGai-_xAs/ InAs_yPi-_y/InP (InGaAs) (or In_xAh-_xAs being substituted for InAs_yPi-_y) will have reduced dark current and will enable low-read-noise ROICs to be manufactured if the photodiode is buried in the structure instead of being connected directly to the ROIC through the surface of the detector array. Burying the p-i-n or p-n detector enables lower dark current from the detector and decouples the capacitance of the buried detector from the ROIC. A heterojunction structure enables removing charge from that buried photodiode by applying a voltage to a contact node to deplete the heterojunction to allow the flow of charge. The heterojunction acts like a normally closed switch preventing charge from leaving the buried photodiode until voltage is applied and a depletion region is formed between a top p-region and the buried p-region which is separated by an n-type region. The voltage creates a depletion region in the n-type material between the p-regions allowing charge to flow from the p-i-n or p-n junction in the detector region to the upper p-junction node in the cap layer. This new active pixel in InGaAs detectors enables the movement of charge noiselessly and enables in pixel correlated double sampling to reduce the noise when attached to a CMOS circuit while also enabling a significantly lower dark current detector pixel. The descriptions below pertain to InGaAs detectors used for visible and short wavelength infrared (SWIR) radiation, but the subject matter of the disclosure can be employed for any III-V or II- VI semiconductor material that detect photons in arrays or individual detectors that are integrated to amplification circuits.

[0018] Referring to FIG. 1, a cross-sectional view of an example semiconductor structure 100 is illustrated. The lowest layer of the structure is a substrate layer 102 that provide support for the higher layers, e.g., the layers that comprise the photodetector. In some examples, subsequent layers are grown epitaxially on the substrate layer 102. As shown in FIG. 1, the substrate layer 102 consists primarily of InP (e.g., n-type or semi-insulating). Above the substrate layer 102 is a cathode layer 104 which may be electrically connected to the readout electronics (150, FIG. 3). The cathode layer 104 may be composed of a semiconductor material that is lattice-matched to the substrate 102 or the material of the detector layer 106. For example, the cathode layer 104 may consist primarily of n-type InP. Alternatively, the cathode layer 104 may consist primarily of In.52Al.4sAs followed by any InAs_yPi-_y or In_xAh-_xAs that modifies its lattice constant to enable a lattice match to the In_xGai-_xAs alloy of the detector layer 106. One or more pixels 110 (e.g., 110a, 110b) may be embedded in the detector layer 106 at or near the surface of the detector layer 106. The pixels 110 are where charge is accumulated as photons interact with the detector 106. The amount of charge that can be accumulated in each pixel 110 depends on the volume of each pixel 110 and properties of the semiconductor materials (e.g., the degree of doping of each region). The width of each pixel 110 is constrained by the presence of adjacent pixels 110 in the detector layer 106.

[0019] The InGaAs detector layer 106 may have a conductivity type of intrinsic or n-type except for the pixels 110, which may have a p-type conductivity type and may occupy a volume at or near the surface of the detector region 106. Alternatively, the conductivity type of the detector layer 106 may be p-type and then layer 104 and pixels 110 would be n-type, respectively. The pixels 110 may be manufactured on a specific pitch and the volumes must be small enough so it does not reach deep enough to contact what is known as the cathode layer 104 contact nor should they be wide enough that one pixel 110 overlaps another pixel. On top of the InGaAs detector layer 106 is a cap layer 108 of Indium Phosphide (InP), Indium Aluminum Arsenide (InAlAs), or other higher bandgap material, doped to be n-type (if the pixel 110 is p- type otherwise doped p-type if pixel 110 is n-type), and the cap layer should be lattice-matched to the InGaAs material used for the detection layer 106. An exposed region of this cap layer 108 has a volume of p-type material 120 that extends into the cap layer 108 from the surface. The size of this volume is dependent on the pixel size and pitch as well as doping density of the cap layer 108. The volume and doping determine the amount of charge that each region (e.g., 120a, 120b) can store. A larger volume with larger capacitance can increase the amount of charge stored, however, a smaller volume reducing the capacitance will allow for reduced read noise but less charge that can be stored but will improve the accuracy of the measurement. The structure may include a thin ohmic contact layer 122 of In_xGai-_xAs which is lattice matched to detector material in layer 106. The p-type volume of 120 would be extended through the thin ohmic contact layer 122 of In_xGai-_xAs which is lattice matched to detector material in layer 106, if the ohmic contact layer is chosen to be used. This lower bandgap material allows for simpler ohmic contact to be formed (140, FIG. 2) when metal is placed on top of the semiconductor.

[0020] The p-type region 120 in this higher bandgap cap layer 108 makes electrical contact to the Read Out Integrated Circuit (150, FIG. 3), through the use of an ohmic or near ohmic contact (e.g., 140b, 140c, FIG. 2) on the exposed p-type region 120 and an indium bump or other metal contact connection (152b and 152c, FIG. 3). This p-type region 120 is aligned with the p-type region (i.e., pixel 110) in the InGaAs detector material layer (i.e., detector layer 106) but the two p-regions 120, 110 (in the cap 108 and the detector layer 106, respectively) are separated by an amount of n-type material (of the cap layer 108). The material in between the two p-type materials is n-type and the space should be thicker than 0.05 pm and less than 10 pm. Above the p-type region in the higher bandgap material 120 another volume exists for an ohmic contact 142a, 124b in the lower bandgap material. To make the ohmic contact a metal layer 140 is placed in hole 130 that forms an ohmic contact in volume 142a, 142b material between the sense region 120 and the electrical contact 152 to the ROIC. 142a, 142b is the volume retained from layer 122 (in FIG. 1). Much of layer 122 is removed during processing except the material above 120. The p-type region 120 in the higher bandgap material may be smaller in diameter and volume than the p-region 110 in the detector material. However, the charge capacity of the p- type region 120 in the higher bandgap material may be configured to be sufficient to store charge accumulated in the p-type region 110 of the detector layer. The amount of charge that can be stored in either region is based on the volume and the degree of doping of each region.

[0021] The disclosed buried detector structure can be formed in many ways. For example, the structure can be grown, e.g., using epitaxial deposition, up to the InGaAs detector layer 106. The p-type regions 110 that form the pixels can then be diffused, or ion implanted, into the n-type (or intrinsic) InGaAs layer using Zn, Be, or another p-type dopant. The diffusion or ion implant material can be processed to limit how wide and deep the regions are in layer 106. The diffused p-type region 110 will become the buried photodiode for an individual pixel. Regrowth can then occur by growing the higher bandgap cap material 108 as n-type on top of the InGaAs detector layer 106. Visible markers 126 (e.g., areas of etched material) may be formed on the surface of the detector layer 106 before regrowth to indicate where the buried pixels are located so that the upper p-type region 120 which contacts the ROIC 150 can be formed directly above the buried p- type region 110, since the buried p-type regions will not be visible once the higher bandgap material is grown on top of the buried photodiodes. The other parts of the structure like the ohmic contact layer 122 can also be grown when the cap layer is grown. The upper p-type region 120 in the higher bandgap n-type material of layer 122 and 108 may be formed through diffusion or ion implantation. It does not have to be the same technique as the formation of the first p-type region 110, but it should be aligned with the original p-type buried photodiode 110. As stated earlier the second p-type region 120 should not be so deep a region as to contact the already buried p-type volume 110. The cap region 108 thickness could vary from .075 pm to 3 pm.

[0022] There are other ways to form this buried photodiode including growing the entire structure in one growth. The entire growth could be done making the InGaAs detector region 106 n-type as well as the higher bandgap material of the cap layer 108. The p-type dopant can then be diffused from the top of the structure all the way down to the InGaAs detector region. Ion implantation can be done of an n-type dopant to separate the p-type region into two to form and upper and lower region (110, 120) essentially two volumes. The ion implant can be conducted to create an n-type region in the higher bandgap material below the p-type region 120 near the surface and above the p-type region 110 in the detector material 106. This recreates an n-type region in 108 to separate the two p-type regions, one p-type region 110 in the detector and the other p-type region 120 in the higher bandgap cap region 108 at the surface and in the contact layer 122.

[0023] One can also grow the structure shown in FIG. 1 without regrowth. The buried photodiode may be formed by using ion implantation. Using a very deep doping with high energy ions the dopant can be placed in layer 106 with minimal dopant being placed in layer 108 and 122. A shallow second ion implant of p-type dopant can be conducted to form the upper p- region 120. A third ion implant can be conducted of n-type dopant. The energy of this implant would be high enough to place n-dopant between volumes 120 and 110 in layer 108. This would allow one to create separation between the two p-type regions (110, 120).

[0024] Referring to FIG. 1, The detector structure may be grown epitaxially on InP substrates 102, e.g., n-type or semi-insulating. The detector structure may be grown first with a cathode layer 104 which is InP n-type or In.52Al.4sAs followed by any InAs_yPi-_y or In_xAh-_xAs that modifies its lattice constant to enable a lattice match to the In_xGai-_xAs alloy used as the detector layer 106. For lattice-matched In_xGai-_xAs the detector layer 106 may be In.53Ga.47As (InGaAs, for short) on an InP cathode layer 104 on top of the InP substrate 102. Alternatively, In.52Al.4sAs can be used for cathode layer 104. The thickness of the InP or InAlAs cathode 104 may be from 0.1 to 10 pm thick and may be doped n-type from 5xl0¹⁹/cm³ to 5xl0¹⁶/cm³. One way of forming the buried photodiodes is to diffuse or ion implant p-type dopants (e.g., Be or Zn) into the detector materials before the higher bandgap cap 108 is grown on the detector layer. The doping of the p-type layer 110 may be >lel5/cm³. The p-type layer 110 may be 0.1 to 4pm deep and less deep than the thickness of the detection layer 106. There should be more than lum between the bottom of 110 and the cathode 104 In addition, a marker 126 may be etched into the material (or deposited onto the material) to allow alignment of later structures to the buried photodiodes 110. The buried photodiode 110 may not touch the surface of the detector material. [0025] After the buried photodiodes or p-type inserts 110 are formed in the detector material 106, the cap layer(s) 108 may be grown. On top of the In_xGai-_xAs an InAs_yPi-_y or In_xAh-_xAs higher bandgap cap layer 108 may be grown. This cap layer 108 may be n-type with a doping >5xl0¹⁶/cm³ and 0.075-3pm thickness. An In_xGai-_xAs or lower bandgap layer 122 may be grown on top on the cap layer 108 to allow for ohmic contacts. This layer 122 may be .01 to 0.5 pm thick. The ohmic contact layer 122 may be undoped or p-type. Most of layer 122 will be removed during later processing except for the portion above volume 120.

[0026] A Silicon Nitride (SiN_x) or other passivation layer 124 may be applied to the surface. Holes (e.g., 130a, 130b) may be opened in the SiNx to diffuse or ion-implant the p-type constituents into the cap layer 108 and/or place metal for the contacts 140. The holes 130 may be placed above the buried photodiodes 110. The p-type transfer zone 120 may be formed in the InGaAs contact layer 122 and the cap layer 108. In general, the p-type transfer zone 120 does not contact the InGaAs detector layer 106. In an embodiment, there is some space approximately >0.1 pm between the upper volume 120 and the edge of the lower p-type zone 120. The doping of this transfer zone 120 may type-convert the cap layer 108 in the zone from n-type to p-type approximately >lxl0¹⁵/cm³. This structure allows the buried photodiode 110 to be separated from the transfer zone 120 by a n-type cap layer 108 with a higher band gap.

[0027] Referring to FIG. 2, following the manufacture of the buried photodiode 110 and the transfer zone 120 the InGaAs layer not used as a contact for the upper p-type volume is removed from the structure. In addition, a trench 160 may be created to contact the cathode 104 from the surface. The trench may be created by etching through cap layer 108 and detector layer 106 to the cathode layer 104. Metal 140a may be deposited in the trench 160, on the cathode layer 104 as well as on the transfer zone 120 (e.g., 140b, 140c) to form metal contacts. These metals 140 are then sintered to form ohmic contacts on the cathode 104 and transfer zone 120. The metal contact 140a to the cathode 104 may be a contact to the n-type layer to allow the completion of the circuit to the ROIC 150. The electrical connection(s) (e.g., 140b, 140c) between the ROIC 150 and detector is done through indium bumps or other metal type contacts (e.g., 152a, 152b, 152c, FIG. 3) The photodiode array can be attached to the ROIC through various techniques available for hybridization.

[0028] The ROIC controls the voltages applied to the transfer zone 120 to create a depletion region in between the transfer zone 120 and the buried photodiode 110 to allow charge to be pulled from the buried photodiode 110 that was accumulated during the integration time. This setup allows for near zero bias on the photodiode and minimizes dark current from surface defects while charge is being collected. Charge can then be moved from the buried photodiode 110 to the transfer zone 120 by applying a voltage to create a depletion region between the two p-type regions. The charge transfer is similar to a CMOS imager with charge transfer in a pinned photodiode. This charge transfer allows for correlated double sampling and other techniques to reduce the read-out noise in the ROIC by measuring the transfer zone before the charge transfer and then after the charge transfer. This method minimizes dark charge from the photodetector by creating a true near zero bias device with no surface defects from the photodiode while also reducing the read noise of the ROIC by reducing the capacitance the ROIC will “see” on the end of its amplification circuit as the transfer zone 120 has a significantly smaller capacitance than a standard p-n or p-i-n photodiode.

[0029] In an operational device, short wavelength infrared (SWIR) light will create electronhole pairs in the InGaAs detector layer. The charge from the holes will be collected in the p-type buried region 110 of the detector. The charge will collect in this region during the given exposure time, or time between reading the collected charge by the ROIC 150. The charge is trapped in that region because of the n-type material surrounding the p-region in the detector and the higher bandgap material above 108 is also n-type material. The p-type region 120 in the higher bandgap material is connected to the Read Out Integrated Circuit (ROIC) 150 through an ohmic contact 140b or 140c. During charge collection, the exposure time of an image frame, no bias is applied to the p-type material 120 in the high bandgap cap region 108 and no bias is placed on the lower p-type region 110. To move the charge noiselessly from the buried p-type region 110 in the detector material to the second p-region 120 in the high-band-gap material, the ROIC 150 applies a reverse bias to the ohmic contact 140b and 140c through the metal contacts at 152. The level of reverse bias, based on properties of the materials, creates a depletion region in the n-type material 108 between the two p-type regions 110, 120. This depletion region will allow charge to flow from the buried p-type region 110 to the top p-type region 120 connected to the ohmic contact 140. This will allow removal of the charge from the buried photodiode 110. This application of voltage can be done, e.g., in less than 10 ns, thus minimizing the amount of dark charge from the bias voltage. The readout speed may depend on factors such as the level of reverse bias applied and properties of the materials. Once the charge has moved from the lower p-region 110 to the upper 120, the charge can now be measured by the (e.g., CMOS) ROIC 150, e.g., via an amplifier circuit. In between charge transfers the upper p-region 120 can have a short small bias, e.g., 20 mV, applied to measure the charge that sits at that contact point. This will allow for correlated double sampling on the contact node reducing the noise measurement of that node. The advantage of this scheme is the contact node to the ROIC 150 will also have a significantly lower capacitance between the readout electronics 150 and the detector compared to other designs, as there is not a large volume of p-diode material 110 in the detector region 106. The disclosed design moves charge from a relatively large p-type buried photodiode 110 to a relatively smaller p-type region 120 in the upper part of the photodiode. The ROIC 150 can then read the charge on the relatively smaller capacitance node 120 thus reducing the noise in the measurement.

[0030] It will be appreciated that the various above-disclosed and other features and functions, or alternatives thereof, may be desirably combined into many other different systems or applications or combinations of systems and applications. Also, that various presently unforeseen or unanticipated alternatives, modifications, variations or improvements therein may be subsequently made by those skilled in the art which are also intended to be encompassed by the following claims. For example, the methods and structures disclosed in this application may be applicable to other detector wavelengths and materials.

Claims

What is claimed is:

1. A photodetector compri sing : one or more pixels regions of semiconductor material configured to accumulate photocurrent; one or more sense regions of semiconductor material, each sense region associated with a corresponding pixel region; a heterojunction interposed between at least one sense region and its corresponding pixel region such that the one or more pixel regions are not in contact with the surface directly, wherein the heterojunction is operable, in a first state, to maintain the photocurrent in the pixel region, and operable, in a second state, to allow the photocurrent to move from the pixel region to its corresponding sense region; and readout electronics configured to operate the heterojunction, causing the accumulated photocurrent to move from pixel regions to corresponding sense regions, the readout electronics further configured to measure the photocurrent at the corresponding sense regions.

2. The photodetector of claim 1, wherein the pixel regions are disposed in the interior of a semiconductor device where the detector material is either intrinsic or n-type.

3. The photodetector of claim 1, wherein the pixel regions comprise a region of p-type detector material.

4. The photodetector of claim 3, wherein the heterojunction comprises an n-type higher bandgap alloy versus the pixel regions.

5. The photodetector of claim 4, wherein a sense region of p-type material is in alignment with the pixel regions disposed in the interior of the semiconductor device, but the sense region is on the surface of the photodetector and is in direct contact with readout electronics and there is n-type material in a cap layer between the sense region and pixel regions disposed in the interior of the semiconductor device.

6. The photodetector of claim 5, wherein the readout electronics operate the photodetector by applying a voltage across the heterojunction to deplete it to allow charge to move from the one or more pixel regions to the one or more sense regions.

7. The photodetector of claim 6, wherein the readout electronics are configured to measure the photocurrent at the corresponding sense regions twice first before the charged is moved to the sense region from the pixel region and then after the charge is moved from the pixel region to the sense region, the two are subtracted from one another to achieve low noise.

8. A method of making a semiconductor photodetector comprising: forming a cathode layer; growing a detector layer of a first conductivity type adjacent to the cathode layer; doping a plurality of pixel regions of the detector layer to form regions of a second conductivity type, the second conductivity type different than the first conductivity type; growing a cap layer adjacent to the detector layer and opposite to the cathode layer but the same conductivity type as the cathode layer ; growing a contact layer adjacent to the cap layer; doping a plurality of sense regions in the sense and contact layers to form regions of the second conductivity type matching the conductivity of the pixel regions, the plurality of sense regions corresponding to the plurality of pixel regions; and electrically interfacing readout electronics to the cathode layer and the plurality of sense regions.

9. The method of claim 8, further comprising forming the cathode layer on a substrate layer.

10. The method of claim 8, wherein the detector layer is grown by epitaxial deposition, and the plurality of pixel regions are doped using Zn, Be, or another p-type dopant before the cap layer is grown.

11. The method of claim 8, further comprising etching visible markers in the detector layer before growing the cap layer, the visible markers indicating positions of the plurality of pixel regions which will not be visible following regrowth.

12. The method of claim 8, wherein the cap layer comprises a higher bandgap material than the detector layer.

13. The method of claim 8, wherein the detector layer comprises intrinsic or n-type detector material. .

14. The method of claim 8, wherein the cap layer comprises a higher bandgap material than the detector layer.

15. The method of claim 8, wherein the pixel regions form a two dimensional grid.

16. A method of measuring photon flux, comprising: accumulating photocurrent in one or more pixel regions disposed in the interior of a semiconductor device and separated from corresponding sense regions by a heterojunction; applying a voltage to one or more anodes of the semiconductor device, causing the accumulated photocurrent to move across the heterojunction to corresponding sense regions; removing the applied voltage; and measuring charge at the corresponding sense regions while the voltage is removed to obtain a charge measurement.

17. The method of claim 16, further comprising: measuring the charge at the corresponding sense regions before applying the voltage to the one or more anodes to obtain one or more offset measurements; and subtracting the offset measurement from the corresponding charge measurement.

18. The method of claim 16, wherein the one or more pixel regions are configured to generate photocurrent in response to visible or short wavelength infrared light.

15