WO2023055351A1

WO2023055351A1 - Secure page retrieval

Info

Publication number: WO2023055351A1
Application number: PCT/US2021/052559
Authority: WO
Inventors: Marvin Nelson; Gary T. Brown
Original assignee: Hewlett-Packard Development Company, L.P.
Priority date: 2021-09-29
Filing date: 2021-09-29
Publication date: 2023-04-06

Abstract

In some examples, a computing device can include a memory, a processor to execute an instruction by attempting to load a page into the memory, in response to the page not being loaded in the memory, transmit a request to a secure microcontroller, a secure memory associated with the secure microcontroller, and the secure microcontroller to retrieve, in response to receiving the request from the processor, the page, decrypt the page, validate the page via a validation operation, and place the page in the memory at an address in the memory.

Description

SECURE PAGE RETRIEVAL Background [0001] Computing devices can allow a user to utilize computing device operations for work, education, gaming, multimedia, and/or other uses. Computing devices can be portable to allow a user to carry or otherwise bring the computing device with while in a mobile setting. A computing device can allow a user to utilize computing device operations for work, education, gaming, multimedia, and/or other general use in a mobile setting. Brief Description of the Drawings [0002] Figure 1 is an example of a system for secure page retrieval consistent with the disclosure. [0003] Figure 2 is an example of a computing device for secure page retrieval consistent with the disclosure. [0004] Figure 3 is an example of a method for secure page retrieval consistent with the disclosure. Detailed Description [0005] A user may utilize a computing device for various purposes, such as for business and/or recreational use. As used herein, the term “computing device” refers to an electronic system having a processing resource and a memory resource. Examples of computing devices can include, for instance, a laptop computer, a notebook computer, an all-in-one (AIO) computer, an imaging device (e.g., a printer), among other types of computing devices. [0006] When executing computing processes, a computing device can utilize virtual memory techniques. Utilizing virtual memory can free computing processes, such as applications, from having to manage a shared memory space, share memory used by libraries between processes, increase security due to memory isolation, and utilize more memory than may be physically available by utilizing paging techniques. For example, a computing device may utilize demand paging techniques for memory management. As used herein, the term “demand paging” refers to a method of memory management in which when an attempt is made to access a page that is not in memory, the page is copied into memory for execution. That is, demand paging allows for pages that are brought into memory (e.g., random-access memory) from a secondary storage location (e.g., a hard disk drive) when the executing process demands them. [0007] A processor of the computing device can fetch the pages when demanded by the executing process. While such pages can be monitored by a secure microcontroller, the processor is not able to be trusted to monitor such pages. Further, the secure microcontroller does not know which pages are to be fetched and loaded into memory at any given time. Accordingly, an unauthorized user may alter such pages prior to being fetched by the processor, allowing the unauthorized user to carry out malicious actions when altered pages are executed by the computing device. [0008] Secure page retrieval, according to the disclosure, can allow for a secure microcontroller to work in parallel with the processor to ensure secure page retrieval for an executing process. When a page is demanded, the processor can request the secure microcontroller to retrieve the page, validate the page, and place the validated page into memory for execution by an executing process. Such an approach can ensure pages are not altered prior to being paged, allowing for an increase in security as compared with previous approaches. [0009] Figure 1 is an example of a system 100 for secure page retrieval consistent with the disclosure. The system 100 can include computing device 102. [0010] As illustrated in Figure 1, the system 100 can include a computing device 102. As described above, the computing device 102 can be a laptop computer, a notebook computer, an all-in-one (AIO) computer, an imaging device, among other types of computing devices. The computing device 102 can include a processor 104 and a memory 106 that can be utilized by the computing device 102 to perform computing operations. [0011] As mentioned above, computing operations may include executing processes. For instance, an application being run on the computing device 102 executes instructions in order to perform (e.g., execute) processes. Certain instructions may be included as a page 112. As used herein, the term “page” refers to a fixed length contiguous block of virtual memory. The computing device 102 may utilize demand paging in order to enable the processor 104 to validate the page 112 of the computing device 102 (e.g., upon boot or during normal runtime), which can prevent an unauthorized user from altering the page 112 without discovery, as is further described herein. [0012] The page 112 is illustrated in Figure 1 as including dashed lines. The dashed lines of the page 112 indicate the page 112 may be accessed in a different memory 105 of the computing device 102 by the secure microcontroller 108 and placed in the memory 106, as is further described herein. The memory 105 can be, for instance, non-executable memory, executable memory, among other examples. [0013] During the demand paging process, the processor 104 executes an instruction associated with a process by attempting to load the page 112 from the memory 105 into the memory 106 for execution by the process. Since the page 112 is not yet located (e.g., loaded) in the memory 106, a page fault error is generated. If the page 112 is not loaded in the memory 106, the processor stalls the process until the page 112 is retrieved. If the page 112 is mapped to the memory 106 (e.g., but not loaded in the memory 106), the processor 104 transmits a request to the secure microcontroller 108 to retrieve and place the page 112 in the memory 106, as is further described herein. As used herein, the term “microcontroller” refers to an integrated circuit designed to perform a specific operation. For example, the secure microcontroller 108 can perform secure page retrieval operations, as is further described herein. [0014] As illustrated in Figure 1, the computing device 102 can include memory 106. In some examples, the memory 106 is dynamic random-access memory (DRAM). However, examples of the disclosure are not so limited. For example, the memory 106 can be any other type of memory. [0015] If the page 112 is not mapped to the memory 106, the processor 104 finds a page to free (e.g., eject) from the memory 106 and loads the page 112 to the memory 106. To facilitate the page 112 being loaded to the memory 106, the processor 104 finds a free frame in the memory 106. As used herein, the term “frame” refers to a block of memory. The free frame in the memory 106 can include an address in the memory 106. Additionally, the processor 104 schedules a read in order to load the page 112 to the memory 106. [0016] To load the page 112 to the memory 106, the processor 104 transmits a request to the secure microcontroller 108. The request transmitted to the secure microcontroller 108 can include the page 112 to be received and the address in the memory 106 to place the page 112. [0017] As illustrated in Figure 1, the computing device 102 includes the secure microcontroller 108 and the secure memory 110. The secure memory 110 can be, for example, flash memory. For example, the secure memory 110 can be non- volatile solid-state memory (e.g., NAND flash). However, examples of the disclosure are not so limited. For example, the secure memory 110 can be any other type of memory (e.g., static random-access memory (SRAM)). [0018] The secure memory 110 can be associated with the secure microcontroller 108 and is not accessible to the processor 104. That is, the processor 104 is not able to access the secure memory 110. In such a way, the secure microcontroller 108 and the secure memory 110 associated with the secure microcontroller 108 can operate within a secure perimeter 115, as illustrated in Figure 1, to avoid outside intrusions by unauthorized users. [0019] The secure microcontroller 108 can receive the request from the processor 104 that includes the page 112 to be retrieved and an address in the memory 106 to place the page 112. In response to receiving the request from the processor 104, the secure microcontroller 108 retrieves the page 112 from the memory 105. The memory 105 can be memory external to the secure perimeter 115. The memory 105 can be flash memory, in some examples, and the page 112 located in the memory 105 may be encrypted. [0020] In an example in which the page 112 is encrypted, the secure microcontroller 108 decrypts the page 112. For example, the secure microcontroller utilizes a key to decrypt the page 112 in order for the page 112 to be utilized by the executing process/processor 104. [0021] The secure microcontroller 108 validates the page 112. For example, the secure microcontroller 108 performs a validation operation on the page 112 to ensure the page 112 is unaltered (e.g., by an unauthorized user). The validation operation can include utilizing a validation table, error correction, message authentication, and/or other mathematical operations in order to validate the page 112, as is further described herein. Additionally, in some examples the validation utilizes a combination of a validation table, error correction, message authentication, and/or other mathematical operations in order to validate the page 112. [0022] In some examples, the secure microcontroller 108 validates the page via the validation operation using a hash of the page 112 according to a validation table 114 saved in the secure memory 110. As used herein, the term “hash” refers to a function to map data of arbitrary size to a bit array of a fixed size. As used herein, the term “validation table” refers to a data structure that maps keys to values. For example, the secure microcontroller 108 compares a hash associated with the page 112 with the validation table 114. [0023] The secure microcontroller 108 places the page 112 in the memory 106 at the address in the memory 106. That is, in response to the hash of the page 112 matching the hash in the validation table 114, the secure microcontroller 108 places the page 112 in the memory 106 at the address in the memory 106 included in the request received from the processor 104. When the hash of the page 112 matches the hash in the validation table 114, the match is indicative that the page 112 has not been altered by an unauthorized user. In other words, the secure microcontroller 108 validates the page 112 using the hash of the page 112 in order to ensure the page 112 has not been altered while residing in the secure memory 110. The secure microcontroller 108 then updates the validation table 114 with the address in the memory 106 at which the page 112 is placed. The validation table 114 can accordingly track valid pages located in the memory 106 and can be utilized to periodically interrogate the pages in the memory 106 to ensure the pages loaded in the memory 106 are not altered, as is further described herein. [0024] In an example in which the hash of the page 112 does not match the hash in the validation table 114, the secure microcontroller 108 performs a recovery action. The recovery action can be, for example, going back to an established root of trust in the secure memory 110 by, for instance, rebooting the computing device 102 in order to rebuild the validation table 114, as is further described herein. [0025] When pages included in the secure memory 110 are written (e.g., when the computing device instructions (e.g., code) are written), they are signed with a private key that does not exist in the computing device 102. Such pages are then encrypted with signatures included in the encryption. In some examples, such pages may be encrypted on a per device basis (e.g., uniquely encrypted for computing device 102). In such an example, pages associated with other computing devices may be encrypted differently than computing device 102. [0026] As mentioned above, the secure microcontroller 108 generates the validation table 114. In an example in which the pages 112 are not encrypted, a hash for each page can be created and placed in the validation table 114 during a boot sequence of the computing device 102. In an example in which the pages are encrypted, during a boot sequence of the computing device 102, the pages in the secure memory 110 can be decrypted (a page at a time) by the secure microcontroller 108, a hash for each page can be created and placed in the validation table 114. The validation table 114 correlates a plurality of pages (e.g., not illustrated in Figure 1) stored in the secure memory 110 with corresponding hashes in the validation table 114. [0027] Additionally, in order to create a root of trust in the secure memory 110, during the boot procedure of the computing device 102 the secure microcontroller 108 signature validates the decrypted plurality of pages stored in the secure memory 110. For example, the signatures of each page are validated with a public key corresponding to the private key mentioned above. If a signature fails, the validation table 114 is not trusted. However, if the signatures pass, the validation table 114 is trusted. When the validation table 114 is created and trusted, demand paging operations as described above can begin. That is, the validation table 114 can be utilized during runtime of the computing device 102 to ensure pages don’t change over time. [0028] In some examples, the secure microcontroller 108 validates the page via the validation operation using error correction techniques. For example, the secure microcontroller 108 utilizes Cyclic Redundancy Checks (CRCs), checksums, and/or parity checks of the page 112 to validate the page 112. [0029] The secure microcontroller 108 then places the page 112 in the memory 106 at the address in the memory 106. That is, in response to the error correction determining the page 112 has not been altered while residing in the secure memory 110, the secure microcontroller 108 places the page 112 in the memory 106 at the address in the memory 106 included in the request received from the processor 104. The secure microcontroller 108 then updates the validation table 114 with the address in the memory 106 at which the page 112 is placed. [0030] In some examples, the secure microcontroller 108 validates the page 112 via the validation operation using message authentication techniques. For example, the secure microcontroller 108 utilizes message authentication techniques included as part of the Advanced Encryption Standard (AES) Galois/Counter Mode (GCM) block cipher mode of operation to validate the page 112. [0031] The secure microcontroller 108 then places the page 112 in the memory 106 at the address in the memory 106. That is, in response to the message authentication techniques determining the page 112 has not been altered while residing in the secure memory 110, the secure microcontroller 108 places the page 112 in the memory 106 at the address in the memory 106 included in the request received from the processor 104. The secure microcontroller 108 then updates the validation table 114 with the address in the memory 106 at which the page 112 is placed. [0032] In some examples, the secure microcontroller 108 validates the page via the validation operation using a mathematical operation. Such mathematical operations may include CRC’s, checksums, signature operations, hashes, and/or other mathematical operations. [0033] The secure microcontroller 108 then places the page 112 in the memory 106 at the address in the memory 106. That is, in response to the mathematical operation determining the page 112 has not been altered while residing in the secure memory 110, the secure microcontroller 108 places the page 112 in the memory 106 at the address in the memory 106 included in the request received from the processor 104. The secure microcontroller 108 then updates the validation table 114 with the address in the memory 106 at which the page 112 is placed. [0034] During the scheduled read (e.g., as mentioned above), the secure microcontroller 108 places the page 112 in the free frame in the memory 106 at the address. When the read is complete, the processor 104 restarts the executing process in order to execute the instruction that previously generated the page fault error. The instruction associated with the process can then proceed utilizing the page 112 located in the memory 106. [0035] The process described above can be repeated for other pages located in the secure memory 110 as processes execute via the processor 104. Such an approach can allow for pages stored in the secure memory 110 to be retrieved, decrypted, validated, and placed in memory 106 by the secure microcontroller 108 to ensure pages stored in the secure memory 110 are not altered before being placed in the memory 106 for execution, increasing security over previous approaches. During runtime operation of the computing device 102, the secure microcontroller can interrogate pages located in the memory 106 to ensure such pages have not been altered while residing in the memory 106, as is further described herein. [0036] As mentioned above, the secure microcontroller 108 can interrogate the page 112 located in the memory 106 by running a hash check on the page 112. For example, the secure microcontroller 108 can compare a hash of the page 112 located in the memory against the validation table 114 stored in the secure memory 110. In response to the hash check being passed (e.g., the hash of the page 112 in the memory 106 matches a hash included in the validation table 114), the secure microprocessor 108 can check other hashes of other pages included in the memory 106 (e.g., not illustrated in Figure 1). In such an example, the secure microcontroller 108 ensures that pages stored in the memory 106 are not altered by an unauthorized user. [0037] In an example in which the hash check of a page 112 located in the memory 106, the secure microcontroller 108 performs a recovery measure. For example, the secure microcontroller 108 can compare a hash of the page 112 located in the memory against the validation table 114 stored in the secure memory 110. In response to the hash check not being passed (e.g., the hash of the page 112 in the memory 106 does not match a hash included in the validation table 114), the secure microcontroller 108 performs a recovery measure to reestablish the root of trust in the secure memory 110. For example, the secure microcontroller 108 causes the computing device 102 to reboot, allowing the secure microcontroller 108 to regenerate the validation table 114 by again decrypting pages in the secure memory 110 and signature validating the decrypted pages in the secure memory 110. [0038] Although the recovery measure is described above as rebooting the computing device 102, examples of the disclosure are not so limited. For example, the secure microcontroller 108 can take any other recovery action to reestablish the root of trust with the pages in the secure memory 110. [0039] The secure microcontroller 108 interrogates the page 112 located in the memory 106 to ensure the page 112 has not been altered by an unauthorized user. The secure microcontroller 108 interrogates the page 112 in the memory 106 in response to an interrogation-criterion being met. The interrogation-criterion can be, for example, a criterion that causes the secure microcontroller 108 to interrogate the page 112, and can include utilizing a predetermined time interval, a counter exceeding a threshold amount, etc. In some examples, the secure microcontroller 108 can interrogate the page 112 (e.g., and other pages in the memory 106) according to a predetermined time interval (e.g., every minute, every five minutes, every hour, etc.). In some examples, the secure microcontroller 108 can interrogate the page 112 (e.g., and other pages in the memory 106) according to an access counter exceeding a threshold count level (e.g., every time the secure microcontroller 108 places a page in the memory 106, interrogate other pages in the memory 106; every fifth time (e.g., threshold of four) the secure microcontroller 108 places a page in the memory 106, interrogate other pages in the memory 106; after every page retrieval request received by the secure microcontroller 108 from the processor 104 to retrieve a page from the memory 105, interrogate other pages in the memory 106; after five page retrieval requests received by the secure microcontroller 108 from the processor 104 to retrieve pages from the memory 105, interrogate other pages in the memory 106; etc.). [0040] Secure page retrieval, according to the disclosure, can allow for a secure microcontroller to ensure secure page retrieval for an executing process when a page is demanded from secure memory, as well as when a page is located in unsecure memory. Such an approach can ensure pages are not altered prior to being paged or while the pages are in memory for execution by a process, allowing for an increase in security as compared with previous approaches. [0041] Figure 2 is an example of a computing device 202 for secure page retrieval consistent with the disclosure. As described herein, the computing device 202 may perform functions related to secure page retrieval. Although not illustrated in Figure 2, the computing device 202 may include a processor and a machine- readable storage medium. Although the following descriptions refer to a single processor and a single machine-readable storage medium, the descriptions may also apply to a system with multiple processors and multiple machine-readable storage mediums. In such examples, the computing device 202 may be distributed across multiple machine-readable storage mediums and across multiple processors. Put another way, the instructions executed by the computing device 202 may be stored across multiple machine-readable storage mediums and executed across multiple processors, such as in a distributed or virtual computing environment. [0042] Processor 204 may be a central processing unit (CPU), a semiconductor-based microprocessor, and/or other hardware devices suitable for retrieval and execution of machine-readable instructions 216, 218 stored in memory 206. Processor 204 may fetch, decode, and execute instructions 216, 218. As an alternative or in addition to retrieving and executing instructions 216, 218, processor 204 may include a plurality of electronic circuits that include electronic components for performing the functionality of instructions 216, 218. [0043] Memory 206 may be any electronic, magnetic, optical, or other physical storage device that stores executable instructions 216, 218, and/or data. Thus, memory 206 may be, for example, Random Access Memory (RAM), an Electrically- Erasable Programmable Read-Only Memory (EEPROM), a storage drive, an optical disc, and the like. Memory 206 may be disposed within computing device 202, as shown in Figure 2. Additionally, memory 206 may be a portable, external or remote storage medium, for example, that causes computing device 202 to download the instructions 216, 218 from the portable/external/remote storage medium. [0044] Additionally, secure microcontroller 208 may include a processor (e.g., not illustrated in Figure 2) that may be a central processing unit (CPU), a semiconductor-based microprocessor, and/or other hardware devices suitable for retrieval and execution of machine-readable instructions 220, 222, 224, 226 stored in secure memory 210. The processor of the secure microcontroller 208 may fetch, decode, and execute instructions 220, 222, 224, 226. As an alternative or in addition to retrieving and executing instructions 220, 222, 224, 226, the processor of the secure microcontroller 208 may include a plurality of electronic circuits that include electronic components for performing the functionality of instructions 220, 222, 224, 226. [0045] Further, secure memory 210 may be any electronic, magnetic, optical, or other physical storage device that stores executable instructions 220, 222, 224, 226, and/or data. Thus, secure memory 210 may be, for example, Random Access Memory (RAM), an Electrically-Erasable Programmable Read-Only Memory (EEPROM), a storage drive, flash memory, an optical disc, and the like. Secure memory 210 may be disposed within computing device 202, as shown in Figure 2. [0046] The computing device 202 may include instructions 216 stored in the memory 206 and executable by the processor 204 to execute an instruction by attempting to load a page into the memory 206. The processor 204 can attempt to load a page into the memory 206 during a demand paging process. [0047] The computing device 202 may include instructions 218 stored in the memory 206 and executable by the processor 204 to transmit, in response to the page not being loaded in the memory 206, a page retrieval request to the secure microcontroller 208. The page retrieval request includes a page to be retrieved and an address in the memory 206 to place the page. [0048] The computing device 202 may include instructions 220 stored in the secure memory 210 and executable by the secure microcontroller 208 to retrieve the page from a different memory (e.g., different from the memory 206). The secure microcontroller 208 retrieves the page from the different memory in response to receiving the request from the processor 204. [0049] The computing device 202 may include instructions 222 stored in the secure memory 210 and executable by the secure microcontroller 208 to decrypt the page. The secure microcontroller 208 decrypts the page via a key. [0050] The computing device 202 may include instructions 224 stored in the secure memory 210 and executable by the secure microcontroller 208 to validate a hash of the page according to a validation operation. The validation operation can include, for example, utilizing a validation table stored in the secure memory. The secure microcontroller 208 can compare the hash of the page against a hash for the page included in the validation table. However, examples of the disclosure are not so limited. For example, the validation operation can include error correction (e.g., CRCs, checksums, and/or parity checks), message authentication, etc. in order to validate the page. [0051] The computing device 202 may include instructions 226 stored in the secure memory 210 and executable by the secure microcontroller 208 to place the page in the memory 206 at the address in the memory 206. For example, if the page stored in the secure memory 210 is validated (e.g., has not been altered while residing in the secure memory 210), the secure microcontroller 208 places the page in the memory 206 for use by a process that is executing an instruction. [0052] Figure 3 is an example of a method 330 for secure page retrieval consistent with the disclosure. The method 330 can be performed by a computing device (e.g., computing device 102, 202, previously described in connection with Figures 1 and 2, respectively). [0053] At 332, the method 330 includes executing, by a processor, an instruction by attempting to load a page into memory. The processor can attempt to load the page into the memory during a demand paging process. [0054] At 334, the method 330 includes transmitting, by the processor, a page retrieval request to a secure microcontroller in response to the page not being loaded in the memory. The page retrieval request includes the page to be retrieved and an address in the memory to place the page. [0055] At 336, the method 330 includes retrieving, by the secure microcontroller in response to receiving the request from the processor, the page from a different memory. [0056] At 338, the method 330 includes decrypting, by the secure microcontroller, the page. The secure microcontroller decrypts the page according to a key. [0057] At 340, the method 330 includes validating a hash of the page according to a validation table stored in the secure memory. The secure microcontroller compares the hash of the page against a hash for the page included in the validation table to validate the hash. [0058] At 342, the method 330 includes placing, by the secure microcontroller in response to the hash being validated, the page in the memory at the address. For example, if the page stored in the secure memory is validated (e.g., has not been altered while residing in the secure memory), the secure microcontroller places the page in the memory. [0059] At 344, the method 330 includes executing the instruction. For example, the page can be loaded in the memory for use by a process that is executing an instruction. [0060] In the foregoing detailed description of the disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how examples of the disclosure may be practiced. These examples are described in sufficient detail to enable those of ordinary skill in the art to practice the examples of this disclosure, and it is to be understood that other examples may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the disclosure. Further, as used herein, “a” can refer to one such thing or more than one such thing. [0061] The figures herein follow a numbering convention in which the first digit corresponds to the drawing figure number and the remaining digits identify an element or component in the drawing. For example, reference numeral 100 may refer to element 102 in Figure 1 and an analogous element may be identified by reference numeral 202 in Figure 2. Elements shown in the various figures herein can be added, exchanged, and/or eliminated to provide additional examples of the disclosure. In addition, the proportion and the relative scale of the elements provided in the figures are intended to illustrate the examples of the disclosure, and should not be taken in a limiting sense. [0062] It can be understood that when an element is referred to as being "on," "connected to", “coupled to”, or "coupled with" another element, it can be directly on, connected, or coupled with the other element or intervening elements may be present. In contrast, when an object is “directly coupled to” or “directly coupled with” another element it is understood that are no intervening elements (adhesives, screws, other elements) etc. [0063] The above specification, examples and data provide a description of the method and applications, and use of the system and method of the disclosure. Since many examples can be made without departing from the spirit and scope of the system and method of the disclosure, this specification merely sets forth some of the many possible example configurations and implementations.

Claims

What is claimed is: 1. A computing device, comprising: a memory; a processor to: execute an instruction by attempting to load a page into the memory; in response to the page not being loaded in the memory, transmit a request to a secure microcontroller; a secure memory associated with the secure microcontroller; and the secure microcontroller to: retrieve, in response to receiving the request from the processor, the page from a different memory; validate the page via a validation operation; and place the page in the memory at an address in the memory.

2. The computing device of claim 1, wherein the secure microcontroller is to: validate the page via the validation operation using a hash of the page according to a validation table stored in the secure memory; and update the validation table with the address of the page in the memory.

3. The computing device of claim 1, wherein the secure microcontroller is to validate the page via the validation operation using at least one of: error correction; message authentication; and a mathematical operation.

4. The computing device of claim 1, wherein the secure microcontroller is to interrogate the page in the memory by running a hash check on the page.

5. The computing device of claim 4, wherein: the memory includes a plurality of pages; and in response to the hash check on the page being passed, the secure microcontroller is to perform a hash check on another page of the plurality of pages in the memory.

6. The computing device of claim 4, wherein in response to the hash check on the page not being passed, the secure microcontroller is to cause the computing device to perform a recovery measure.

7. The computing device of claim 1, wherein the processor is to execute the page located in the memory.

8. The computing device of claim 1, wherein the memory is dynamic random- access memory (DRAM).

9. A computing device, comprising: a memory; a processor to execute instructions stored in the memory to: execute an instruction by attempting to load a page into the memory; in response to the page not being loaded in the memory, transmit a page retrieval request to a secure microcontroller, the page retrieval request including a page to be retrieved and an address in the memory to place the page; a secure memory associated with the secure microcontroller; and the secure microcontroller to execute instructions stored in the secure memory to: retrieve, in response to receiving the request from the processor, the page from a different memory of the computing device; decrypt the page; validate a hash of the page according to a validation table stored in the secure memory; and place the page in the memory at the address in the memory.

10. The computing device of claim 9, wherein the secure microcontroller is to generate the validation table by decrypting, during a boot sequence of the computing device, pages in flash memory, wherein the validation table correlates pages with hashes.

11. The computing device of claim 10, wherein the secure microcontroller is to signature validate the decrypted pages to create a root of trust in the flash memory.

12. A method, comprising: executing, by a processor, an instruction by attempting to load a page into a memory; transmitting, by the processor, a page retrieval request to a secure microcontroller in response to the page not being loaded in the memory, wherein the page retrieval request includes the page to be retrieved and an address in the memory to place the page; retrieving, by the secure microcontroller in response to receiving the request from the processor, the page from a different memory; decrypting, by the secure microcontroller, the page according to a key; validating, by the secure microcontroller, a hash of the page according to a validation table stored in the secure memory; placing, by the secure microcontroller in response to the hash being validated, the page in the memory at the address; and executing, by the processor, the instruction by loading the page in the memory.

13. The method of claim 12, wherein: validating the hash includes comparing the hash of the page to the validation table; and the method includes: placing, in response to the hash of the page matching a hash in the validation table, the page in the memory at the address; and performing, in response to the hash of the page not matching the hash in the validation table, a recovery action.

14. The method of claim 12, wherein the method includes: determining, by the processor, a free frame in the memory; and placing, by the secure microcontroller, the page in the free frame in the memory at the address.

15. The method of claim 12, wherein the method includes interrogating the page in the memory in response to an interrogation criterion being met.