WO2023051591A1 - 一种进程间通信方法及相关装置 - Google Patents

一种进程间通信方法及相关装置 Download PDF

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Publication number
WO2023051591A1
WO2023051591A1 PCT/CN2022/122061 CN2022122061W WO2023051591A1 WO 2023051591 A1 WO2023051591 A1 WO 2023051591A1 CN 2022122061 W CN2022122061 W CN 2022122061W WO 2023051591 A1 WO2023051591 A1 WO 2023051591A1
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Prior art keywords
address
instruction
shared memory
memory
descriptor
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PCT/CN2022/122061
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English (en)
French (fr)
Inventor
缪晴朗
蔡卫光
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华为技术有限公司
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Publication of WO2023051591A1 publication Critical patent/WO2023051591A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication

Definitions

  • the present application relates to the field of computer technology, and in particular to an inter-process communication method and related devices.
  • the vehicle market has ushered in an unprecedented opportunity - intelligence.
  • the sensor process transmits the image to different processing processes. After the processing process performs the corresponding recognition processing, it sends control signals to the corresponding components in the vehicle.
  • intelligent driving scenarios have high requirements on the efficiency and safety of inter-process communication. Efficiency affects the speed at which vehicles respond to emergencies, while safety is directly related to the safety of passengers.
  • inter-process communication is usually implemented based on socket technology and message queue (Message Queue) technology.
  • socket technology and Message Queue technology involve data copying, and the communication efficiency is poor. Therefore, at present, the method of shared memory is mainly used to realize inter-process communication. Communication is based on shared memory, without involving data copying, and the communication efficiency is high.
  • the embodiment of the present application provides an inter-process communication method, which can ensure that when a software error occurs, the process in communication cannot access the memory segment being used by other processes, thereby avoiding the data in the shared memory being damaged and causing the system to go down phenomenon, to ensure the normal operation of the system.
  • the first aspect of the present application provides an inter-process communication method, which is applied to an electronic device running multiple processes, such as a wireless electronic device in a smart driving scenario.
  • the method includes: the processor acquires a first instruction from a first process, and the first instruction is used to request an address of a shared memory, so that the first process writes data into the shared memory or reads an address in the shared memory. data.
  • the shared memory is used for inter-process communication.
  • the first process is, for example, a sensor process, responsible for acquiring sensor data and sending the sensor data to a processing process; the first process may also be a processing process, responsible for receiving sensor data transmitted by the The sensor data performs corresponding processing operations.
  • the processor returns the first address to the first process according to the first instruction, and adds the first address to a filter table corresponding to the first process.
  • the first address may be an address range, which is used to indicate an address segment corresponding to a memory segment in the shared memory.
  • the memory segment corresponding to the first address is the memory used for inter-process communication by the first process.
  • the filter table is used to store the addresses of the shared memory that the first process can access, and the addresses recorded in the filter table are all addresses in the shared memory.
  • the processor acquires a second instruction from the first process, the second instruction includes the first address, and the second instruction is used to request to use the storage space corresponding to the first address, based on the The storage space corresponding to the first address implements inter-process communication.
  • the processor triggers to query the filter table based on the first address in the second instruction being an address of the shared memory, and executes the second instruction according to the fact that the first address is located in the filter table. That is to say, when the processor acquires an instruction to access a certain address and determines that the address is an address in the shared memory, the processor triggers a query filter table to determine whether the address is in the filter table. If the address is in the filtering table, it means that the process has the right to access the address; if the address is not in the filtering table, it means that the process does not have the right to access the address.
  • the processor executes the second instruction, it deletes the first address from the filter table, so that the first process no longer has the right to access the first address.
  • the first process that needs to communicate based on the shared memory obtains the address of the shared memory through an instruction, and is triggered by the instruction to add the obtained address of the shared memory to the filter table; when the first process accesses the address of the shared memory , triggering to query the filter table to determine whether the first process has the permission to access the shared memory. Moreover, after the first process successfully accesses the shared memory, the access right of the first process is released in the filter table, thereby ensuring that the process will not trample on the shared memory being used by another process due to software errors or attacks.
  • the first process is a sender process
  • the second instruction further includes first data
  • the second instruction is used to instruct writing to the storage space corresponding to the first address
  • the first data, the first data is data to be transmitted to the second process.
  • a process in which the processor executes the second instruction includes: the processor writes the first data into a storage space corresponding to the first address.
  • the first process is a receiver process
  • the second instruction is used to instruct to read second data in the storage space corresponding to the first address
  • the second data is Data transmitted by the second process to the first process.
  • the process of the processor executing the second instruction includes: the processor reads the second data in the storage space corresponding to the first address, and returns the second data to the first process.
  • the processor acquires a third instruction from the first process, the third instruction includes the second address, and the third The instruction is used to request to use the storage space corresponding to the second address.
  • the second address is an address in the shared memory, and the second address is not located in the filtering table. That is, the processor may not trigger adding the second address to the filter table; the processor may also delete the second address from the filter table after the first process loses the access right to the second address.
  • the processor triggers to query the filter table based on the second address in the third instruction being an address of the shared memory, and refuses to execute the third instruction according to the fact that the second address is not in the filter table.
  • the processor may refuse to execute the process that the first process requests to access the second address. instruction, so as to ensure that the first process cannot use the storage space corresponding to the second address, and avoid the phenomenon that the first process tramples on the storage space being used by other processes.
  • the processor after allocating the shared memory for the first process or obtaining the first instruction from the first process, the processor adds a mark to the page table entry corresponding to the first process .
  • the mark is used to indicate that the first address is an address used for inter-process communication
  • the page table entry is used to indicate a mapping relationship between the first address and a physical address corresponding to the first address , the first address is a virtual address.
  • the processor may search the page table entry based on the first address in the second instruction, and determine the first address in the second instruction according to the flag in the page table entry. Address is the address of the shared memory.
  • a mark is added to the page table entry to indicate an address belonging to the shared memory, so that the processor can recognize that the first address in the second instruction is an address of the shared memory, which improves the feasibility of the solution.
  • the first instruction generated by the first process includes the identifier of the shared memory, and the first instruction is used to request to acquire the shared memory. address of shared memory.
  • the processor acquires the descriptor corresponding to the shared memory according to the identifier in the first instruction.
  • the descriptor may be established by the processor after allocating the shared memory for the first process, and the descriptor is used to record usage of the shared memory. That is, after each time the processor allocates shared memory for two processes that need to communicate, it creates a descriptor for the allocated shared memory to record the usage of the shared memory.
  • the processor determines the first address according to the content of the descriptor, and returns the first address to the first process, and the storage space corresponding to the first address is to be written or to be written in the shared memory.
  • the storage space to read.
  • the processor can know the usage of the shared memory when it obtains the instruction requesting the address in the shared memory, so as to return the valid memory to the process segment address.
  • the processor may generate a descriptor table for the first process.
  • the processor obtains the first instruction including the identifier of the shared memory
  • the processor acquires the address of the descriptor corresponding to the identifier in the descriptor table corresponding to the first process according to the identifier in the first instruction
  • the descriptor table is used to store addresses of one or more descriptors corresponding to the first process.
  • the processor then acquires the descriptor according to the address of the descriptor.
  • the descriptor table is used to record the address of the descriptor, which can effectively manage multiple descriptors corresponding to the same process and ensure the feasibility of the solution.
  • the shared memory allocated by the processor to the first process includes multiple memory blocks, and the multiple memory blocks form a ring queue for reading and writing by the process.
  • the descriptor corresponding to the shared memory records and manages the state of each memory block in the plurality of memory blocks.
  • the descriptor includes a write pointer and a read pointer, the write pointer is used to indicate the position of the memory block to be written among the plurality of memory blocks in the circular queue, and the read The pointer is used to indicate the position of the to-be-read memory block in the circular queue among the plurality of memory blocks.
  • the processor can quickly determine the address of the memory block for writing data and the address of the memory block for reading data.
  • the two processes in the communication can work asynchronously, that is, the sender process and the receiver process Processes access different memory blocks in the shared memory at the same time, improving communication efficiency.
  • the sender process can write data in the ring queue cyclically, thereby realizing the recycling of the shared memory and saving communication overhead.
  • the processor after executing the second instruction, updates the write pointer in the descriptor, so as to update the location of the memory block to be written in the plurality of memory blocks. position in the circular queue;
  • the processor updates the read pointer in the descriptor, so as to update the position of the memory block to be read among the plurality of memory blocks in the circular queue.
  • the processor acquires a fourth instruction from the first process, where the fourth instruction is used to request allocation for inter-process communication of memory.
  • the processor allocates the shared memory for the first process according to the fourth instruction, and returns an identifier of the shared memory to the first process.
  • the processor after obtaining the fourth instruction from the first process, the processor also generates a descriptor corresponding to the shared memory according to the fourth instruction, and stores the address of the descriptor Add to the descriptor table corresponding to the first process.
  • the processor may also add the identifier of the shared memory to the descriptor table, so as to establish the relationship between the address of the descriptor and the identifier of the shared memory The corresponding relationship is convenient for subsequent processors to determine the corresponding descriptor according to the identifier of the shared memory.
  • the processor after executing the second instruction, acquires a fifth instruction from the first process, and the fifth instruction is used to indicate the Out of storage space.
  • the processor deletes the first address in the filtering table according to the fifth instruction.
  • Triggering the processor to revoke the access right of the first process to the shared memory by the second instruction sent by the first process can make the behavior of the process accessing the shared memory controllable, ensuring that the process in communication cannot access the memory being used by other processes segment, so as to avoid the phenomenon that the data in the shared memory is damaged and cause the system to go down.
  • the second aspect of the present application provides an electronic device, including an acquisition unit, a processing unit, and a sending unit; the acquisition unit is configured to acquire a first instruction from a first process, and the first instruction is used to request acquisition of a shared memory The address of the shared memory is used for inter-process communication; the sending unit is configured to return a first address to the first process according to the first instruction, and add the first address to the first In the filtering table corresponding to the process, the first address is an address in the shared memory, and the filtering table is used to store the address of the shared memory that the first process can access; the obtaining unit is also used to obtain the address from A second instruction of the first process, the second instruction includes the first address, and the second instruction is used to request to use the storage space corresponding to the first address; the processing unit is configured to The first address in the second instruction is the address of the shared memory, triggering the query of the filter table, and executing the second instruction according to the location of the first address in the filter table; the processing unit also uses After executing the second instruction
  • the second instruction further includes first data, and the second instruction is used to instruct to write the first data into the storage space corresponding to the first address, and the first The data is data to be transmitted to the second process; the processing unit is specifically configured to write the first data into the storage space corresponding to the first address.
  • the second instruction is used to instruct to read the second data in the storage space corresponding to the first address, and the second data is transmitted from the second process to the first process the data;
  • the processing unit is specifically configured to read the second data in the storage space corresponding to the first address, and return the second data to the first process.
  • the acquiring unit is further configured to acquire a third instruction from the first process, the third instruction includes the second address, and the third instruction is used to request to use the The storage space corresponding to the second address, the second address is an address in the shared memory; the processing unit is specifically configured to trigger the query based on the second address in the third instruction being an address in the shared memory the filter table, and refuse to execute the third instruction according to that the second address is not in the filter table.
  • the processing unit is further configured to add a mark to the page table entry corresponding to the first process, and the mark is used to indicate that the first address is used for inter-process communication.
  • the page table entry is used to indicate the mapping relationship between the first address and the physical address corresponding to the first address, the first address is a virtual address;
  • the processing unit is specifically configured to: based on The first address in the second instruction searches the page table entry; and according to the flag in the page table entry, it is determined that the first address in the second instruction is the address of the shared memory.
  • the first instruction includes an identifier of the shared memory; the processing unit is specifically configured to obtain a descriptor according to the identifier, and the descriptor is used to record the identifier of the shared memory Usage: the sending unit is specifically configured to determine the first address according to the descriptor, and return the first address to the first process, and the storage space corresponding to the first address is the shared The storage space to be written or read in the memory.
  • the processing unit is specifically configured to: acquire the address of the descriptor corresponding to the identifier in the descriptor table corresponding to the first process according to the identifier, and the descriptor table uses for storing the addresses of one or more descriptors corresponding to the first process; acquiring the descriptors according to the addresses of the descriptors.
  • the shared memory includes a plurality of memory blocks, and the plurality of memory blocks constitute a circular queue for processes to read and write;
  • the descriptor includes a write pointer and a read pointer, so The write pointer is used to indicate the position of the memory block to be written in the circular queue in the plurality of memory blocks, and the read pointer is used to indicate the memory block to be read in the plurality of memory blocks position in the circular queue.
  • the processing unit is specifically configured to: after executing the second instruction, update the write pointer in the descriptor, so as to update the pending The position of the written memory block in the ring queue; or, after executing the second instruction, update the read pointer in the descriptor, so as to update the multiple memory blocks to be read The memory block's position in the ring queue.
  • the obtaining unit is further configured to obtain a fourth instruction from the first process, where the fourth instruction is used to request memory allocation for inter-process communication; the The processing unit is further configured to allocate the shared memory for the first process according to the fourth instruction, and return an identifier of the shared memory to the first process.
  • the processing unit is further configured to generate a descriptor corresponding to the shared memory according to the fourth instruction, and add the address of the descriptor to the address corresponding to the first process. in the descriptor table.
  • the acquiring unit is further configured to acquire a fifth instruction from the first process, where the fifth instruction is used to indicate that the storage space corresponding to the first address is used up;
  • the processing unit is further configured to delete the first address in the filtering table according to the fifth instruction.
  • the third aspect of the present application provides an electronic device, which includes: a memory and a processor; the memory stores codes, the processor is configured to execute the codes, and when the codes are executed, the The electronic device executes the method in any one implementation manner in the first aspect.
  • the fourth aspect of the present application provides a smart car, the smart car includes: a memory and a processor; the memory stores codes, the processor is configured to execute the codes, and when the codes are executed, the The smart car executes the method in any one of the implementation manners in the first aspect.
  • the fifth aspect of the present application provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when it is run on a computer, the computer executes any one of the implementations in the first aspect or the second aspect. way of way.
  • the sixth aspect of the present application provides a computer program product, which, when running on a computer, causes the computer to execute the method in any one of the implementation manners of the first aspect or the second aspect.
  • the seventh aspect of the present application provides a chip, including one or more processors. Part or all of the processor is used to read and execute the computer program stored in the memory, so as to execute the method in any possible implementation manner of any aspect above.
  • the chip includes a memory, and the memory and the processor are connected to the memory through a circuit or wires.
  • the chip further includes a communication interface, and the processor is connected to the communication interface.
  • the communication interface is used to receive data and/or information to be processed, and the processor obtains the data and/or information from the communication interface, processes the data and/or information, and outputs the processing result through the communication interface.
  • the communication interface may be an input-output interface.
  • Fig. 1 is a kind of communication diagram based on socket technology that the embodiment of the present application provides;
  • Fig. 2 is a kind of communication diagram based on Message Queue technology that the embodiment of the present application provides;
  • FIG. 3 is a schematic structural diagram of a vehicle 100 provided in an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a computer system 101 in a vehicle provided by an embodiment of the present application.
  • FIG. 5 is a schematic flowchart of an inter-process communication method 500 provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a page table entry provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a descriptor provided by an embodiment of the present application.
  • FIG. 8 is a schematic flowchart of an inter-process communication method 800 provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a state change of a memory block in a shared memory provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a system architecture for inter-process communication provided by an embodiment of the present application.
  • FIG. 11A is a schematic structural diagram of a descriptor table provided by the embodiment of the present application.
  • Fig. 11B is a schematic structural diagram of a descriptor provided by the embodiment of the present application.
  • FIG. 12 is a schematic diagram of a system architecture in an intelligent driving scenario provided by an embodiment of the present application.
  • FIG. 13 is a schematic flowchart of an inter-process communication method 1300 provided in an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of an electronic device 1400 provided in an embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of a computer-readable storage medium 1500 provided by an embodiment of the present application.
  • the vehicle market has ushered in an unprecedented opportunity - intelligence.
  • the sensor process transmits the image to different processing processes. After the processing process performs the corresponding recognition processing, it sends control signals to the corresponding components in the vehicle.
  • intelligent driving scenarios have high requirements on the efficiency and safety of inter-process communication. Efficiency affects the speed at which vehicles respond to emergencies, while safety is directly related to the safety of passengers.
  • inter-process communication in intelligent driving scenarios is usually also called inter-core communication.
  • inter-process communication is usually implemented based on socket technology and message queue (Message Queue) technology.
  • FIG. 1 is a schematic diagram of communication based on socket technology provided by an embodiment of the present application.
  • TCP Transmission Control Protocol
  • the TCP client and the TCP server respectively establish a socket object.
  • the TCP server does not locate the socket of the specific client, but is always in the listening state.
  • the socket of the TCP client needs to describe the socket of the server to be connected by the TCP client, and provide the address and port number; then, the TCP client makes a connection request to the socket of the TCP server.
  • the socket on the TCP server side receives the connection request from the socket on the TCP client side, it responds to the request from the socket on the TCP client side, and creates a new thread to send the description of the socket on the TCP server side to client.
  • the TCP client confirms the description returned by the TCP server, the connection is formally established.
  • the socket on the TCP server side continues to be in the listening state, and continues to receive connection requests from other client sockets.
  • Message Queue is one of the more commonly used communication technologies in Linux.
  • the Message Queue technology establishes a message queue in the kernel, copies the data in the message buffer of the process in the user mode space to the kernel mode, and then copies it to the message buffer of another process, thereby completing the communication between processes.
  • Figure 2 is a schematic diagram of communication based on the Message Queue technology provided by the embodiment of the present application.
  • Shared memory is currently the most efficient inter-process communication method.
  • communication based on shared memory the same physical address in the memory is mapped to the address space of different processes, and the two processes in the communication asynchronously read and write the same physical address in the memory, thereby realizing data copy-free communication .
  • the receiver process will first check the validity of the data. If the data is legal, the receiver process then processes the data. However, when the receiver process processes the data, if the sender modifies the data again, the receiver process can no longer check the legality of the data, thus introducing a security hole.
  • the attacker can attack the sender process by using the Time of check to time of use (TOCTTOU) attack. After the sender process is controlled by the attack, the sender process will first send a legal data; the receiver process will start processing after verifying that the data is legal. At this point, the sender process can attack by modifying the content of the data.
  • TOCTTOU Time of check to time of use
  • the embodiment of the present application provides an inter-process communication method, in which the process that needs to communicate based on the shared memory obtains the address of the shared memory through an instruction, and is triggered by the instruction to add the obtained address of the shared memory to the filter table;
  • the process accesses the address of the shared memory, it triggers to query the filter table to determine whether the process has the permission to access the shared memory.
  • the access right of the process is released in the filter table, so as to ensure that the process will not step on the shared memory being used by another process due to software errors or attacks.
  • the inter-process communication method provided by the embodiment of the present application can be applied to electronic devices.
  • the electronic device may be, for example, a wireless electronic device in intelligent driving, a server, a smart phone (mobile phone), a personal computer (personal computer, PC), a notebook computer, a tablet computer, a smart TV, a mobile Internet device (mobile Internet device, MID), wearable devices, virtual reality (virtual reality, VR) equipment, augmented reality (augmented reality, AR) equipment, wireless electronic equipment in industrial control (industrial control), remote surgery (remote medical surgery) wireless electronic devices in smart grid, wireless electronic devices in transportation safety, wireless electronic devices in smart city, wireless in smart home electronic equipment, etc.
  • a wireless electronic device in intelligent driving a server
  • a smart phone mobile phone
  • personal computer personal computer
  • PC notebook computer
  • tablet computer tablet computer
  • smart TV a mobile Internet device
  • mobile Internet device mobile Internet device
  • MID mobile Internet device
  • wearable devices virtual reality (virtual reality, VR) equipment, augmented reality (augmented reality, AR
  • the method provided in the embodiment of the present application will be introduced below by taking the method provided in the embodiment of the present application applied to a wireless electronic device in intelligent driving as an example.
  • FIG. 3 is a schematic structural diagram of a vehicle 100 provided in an embodiment of the present application.
  • vehicle 100 may be configured in a fully or partially autonomous driving mode.
  • the vehicle 100 can control itself while in the automatic driving mode, and can determine the current state of the vehicle and its surrounding environment through human operation, determine the likely behavior of at least one other vehicle in the surrounding environment, and determine the behavior of the other vehicle.
  • a confidence level corresponding to the likelihood of performing the possible action is used to control the vehicle 100 based on the determined information.
  • the vehicle 100 While the vehicle 100 is in the autonomous driving mode, the vehicle 100 may be set to operate without human interaction.
  • Vehicle 100 may include various subsystems such as travel system 102 , sensor system 104 , control system 106 , one or more peripheral devices 108 as well as power supply 110 , computer system 112 and user interface 116 .
  • the vehicle 100 may include more or fewer subsystems, and each subsystem may include multiple elements, for example, each subsystem includes multiple ECUs.
  • each subsystem and element of the vehicle 100 may be interconnected by wire or wirelessly.
  • the propulsion system 102 may include components that provide powered motion for the vehicle 100 .
  • propulsion system 102 may include engine 118 , energy source 119 , transmission 120 , and wheels/tyres 121 .
  • the engine 118 may be an internal combustion engine, an electric motor, an air compression engine or other types of engine combinations, such as a hybrid engine composed of a gasoline engine and an electric motor, or a hybrid engine composed of an internal combustion engine and an air compression engine.
  • Engine 118 converts energy source 119 into mechanical energy.
  • Examples of energy source 119 include gasoline, diesel, other petroleum-based fuels, propane, other compressed gas-based fuels, ethanol, solar panels, batteries, and other sources of electrical power. Energy source 119 may also provide energy to other systems of vehicle 100 .
  • Transmission 120 may transmit mechanical power from engine 118 to wheels 121 .
  • Transmission 120 may include a gearbox, a differential, and drive shafts.
  • the transmission 120 may also include other devices, such as clutches.
  • drive shafts may include one or more axles that may be coupled to one or more wheels 121 .
  • the sensor system 104 may include a number of sensors that sense information about the environment surrounding the vehicle 100 .
  • the sensor system 104 may include a positioning system 122 (the positioning system may be a GPS system, or a Beidou system or other positioning systems), an inertial measurement unit (inertial measurement unit, IMU) 124, a radar 126, a laser range finder 128 and camera 130 .
  • the sensor system 104 may also include sensors of the interior systems of the monitored vehicle 100 (eg, interior air quality monitor, fuel gauge, oil temperature gauge, etc.). Sensor data from one or more of these sensors can be used to detect objects and their corresponding properties (position, shape, orientation, velocity, etc.). Such detection and identification are critical functions for safe operation of autonomous vehicle 100 .
  • the positioning system 122 may be used to estimate the geographic location of the vehicle 100 .
  • the IMU 124 is used to sense changes in position and orientation of the vehicle 100 based on inertial acceleration.
  • IMU 124 may be a combination accelerometer and gyroscope.
  • the radar 126 may utilize radio signals to sense objects within the surrounding environment of the vehicle 100 .
  • radar 126 may be used to sense the velocity and/or heading of objects.
  • the laser rangefinder 128 may utilize laser light to sense objects in the environment in which the vehicle 100 is located.
  • laser rangefinder 128 may include one or more laser sources, a laser scanner, and one or more detectors, among other system components.
  • Camera 130 may be used to capture multiple images of the surrounding environment of vehicle 100 .
  • Camera 130 may be a still camera or a video camera.
  • Control system 106 controls the operation of the vehicle 100 and its components.
  • Control system 106 may include various elements including steering system 132 , accelerator 134 , braking unit 136 , computer vision system 140 , route control system 142 , and obstacle avoidance system 144 .
  • the steering system 132 is operable to adjust the heading of the vehicle 100 .
  • it could be a steering wheel system.
  • the throttle 134 is used to control the operating speed of the engine 118 and thus the speed of the vehicle 100 .
  • the braking unit 136 is used to control the deceleration of the vehicle 100 .
  • the braking unit 136 may use friction to slow the wheels 121 .
  • the brake unit 136 can convert the kinetic energy of the wheel 121 into electric current.
  • the braking unit 136 may also take other forms to slow down the wheels 121 to control the speed of the vehicle 100 .
  • Computer vision system 140 is operable to process and analyze images captured by camera 130 in order to identify objects and/or features in the environment surrounding vehicle 100 .
  • the objects and/or features may include traffic signals, road boundaries and obstacles.
  • the computer vision system 140 may use object recognition algorithms, Structure from Motion (SFM) algorithms, video tracking, and other computer vision techniques.
  • SFM Structure from Motion
  • computer vision system 140 may be used to map the environment, track objects, estimate the velocity of objects, and the like.
  • the route control system 142 is used to determine the travel route of the vehicle 100 .
  • route control system 142 may combine data from sensors 138, GPS 122, and one or more predetermined maps to determine a travel route for vehicle 100.
  • the obstacle avoidance system 144 is used to identify, evaluate, and avoid or otherwise overcome potential obstacles in the environment of the vehicle 100 .
  • control system 106 may additionally or alternatively include components other than those shown and described. Alternatively, some of the components shown above may be reduced.
  • Vehicle 100 interacts with external sensors, other vehicles, other computer systems, or users via peripherals 108 .
  • Peripherals 108 may include wireless communication system 146 , on-board computer 148 , microphone 150 and/or speaker 152 .
  • peripheral device 108 provides a means for a user of vehicle 100 to interact with user interface 116 .
  • on-board computer 148 may provide information to a user of vehicle 100 .
  • the user interface 116 may also operate the on-board computer 148 to receive user input.
  • the on-board computer 148 can be operated through a touch screen.
  • peripheral devices 108 may provide a means for vehicle 100 to communicate with other devices located within the vehicle.
  • microphone 150 may receive audio (eg, voice commands or other audio input) from a user of vehicle 100 .
  • speaker 152 may output audio to a user of vehicle 100 .
  • Wireless communication system 146 may communicate wirelessly with one or more devices, either directly or via a communication network.
  • wireless communication system 146 may use 3G cellular communications, such as CDMA, EVDO, GSM/GPRS, or 4G cellular communications, such as LTE. Or 5G cellular communications.
  • the wireless communication system 146 can use WiFi to communicate with a wireless local area network (wireless local area network, WLAN).
  • wireless communication system 146 may communicate directly with the device using an infrared link, Bluetooth, or ZigBee.
  • Other wireless protocols, such as various vehicle communication systems, for example, wireless communication system 146 may include one or more dedicated short range communications (DSRC) devices, which may include public and/or private data communications.
  • DSRC dedicated short range communications
  • the power supply 110 may provide power to various components of the vehicle 100 .
  • the power source 110 may be a rechargeable lithium-ion or lead-acid battery.
  • One or more battery packs of such batteries may be configured as a power source to provide power to various components of the vehicle 100 .
  • power source 110 and energy source 119 may be implemented together, such as in some all-electric vehicles.
  • Computer system 112 may include at least one controller 113 that executes instructions 115 stored in a non-transitory computer-readable medium such as memory 114 .
  • the computer system 112 may also be a plurality of computing devices that control individual components or subsystems of the vehicle 100 in a distributed manner.
  • Controller 113 may be any conventional processor, such as a commercially available CPU.
  • the processor may be a special purpose device such as an ASIC or other hardware based processor.
  • FIG. 1 functionally illustrates the processor, memory, and other elements of computer 110 in the same block, those of ordinary skill in the art will understand that the processor, computer, or memory may actually include Multiple processors, computers, or memories stored within the same physical enclosure.
  • the memory may be a hard drive or other storage medium located in a different housing than the computer 110 .
  • references to a processor or computer are to be understood to include references to collections of processors or computers or memories that may or may not operate in parallel.
  • some components such as the steering and deceleration components, may each have their own processor that only performs calculations related to component-specific functions .
  • the processor may be located remotely from the vehicle and be in wireless communication with the vehicle. In other aspects, some of the processes described herein are executed on a processor disposed within the vehicle while others are executed by a remote processor, including taking the necessary steps to perform a single maneuver.
  • the data storage device 114 may contain instructions 115 (eg, program logic) executable by the processor to perform various functions of the vehicle 100 , including those described above.
  • Memory 114 may also contain additional instructions, including instructions for sending data to, receiving data from, interacting with, and/or controlling one or more of propulsion system 102, sensor system 104, control system 106, and peripherals 108. instruction.
  • data storage device 114 may also store data such as road maps, route information, the vehicle's position, direction, speed, and other such vehicle data, among other information. Such information may be used by the vehicle 100 and the computer system 112 during operation of the vehicle 100 in autonomous, semi-autonomous, and/or manual modes.
  • a user interface 116 for providing information to or receiving information from a user of the vehicle 100 .
  • user interface 116 may include one or more input/output devices within set of peripheral devices 108 , such as wireless communication system 146 , in-vehicle computer 148 , microphone 150 , and speaker 152 .
  • the computer system 112 may control functions of the vehicle 100 based on input received from various subsystems (eg, the travel system 102 , the sensor system 104 , and the control system 106 ) and from the user interface 116 .
  • computer system 112 may utilize input from control system 106 in order to control steering unit 132 to avoid obstacles detected by sensor system 104 and obstacle avoidance system 144 .
  • the computer system 112 is operable to provide control over many aspects of the vehicle 100 and its subsystems.
  • one or more of these components described above may be installed separately from or associated with the vehicle 100 .
  • data storage device 114 may exist partially or completely separate from vehicle 1100 .
  • the components described above may be communicatively coupled together in a wired and/or wireless manner.
  • FIG. 1 should not be construed as limiting the embodiment of the present application.
  • An autonomous vehicle traveling on a road can identify objects within its surroundings to determine adjustments to the current speed.
  • the objects may be other vehicles, traffic control devices, or other types of objects.
  • each identified object may be considered independently and based on the object's respective characteristics, such as its current speed, acceleration, distance to the vehicle, etc., may be used to determine the speed at which the autonomous vehicle is to adjust.
  • the autonomous vehicle 100 or a computing device associated with the autonomous vehicle 100 (such as the computer system 112, the computer vision system 140, the data storage device 114 of FIG. state (eg, traffic, rain, ice on the road, etc.) to predict the behavior of the identified objects.
  • each recognized object is dependent on the behavior of the other, so it is also possible to predict the behavior of a single recognized object by considering all recognized objects together.
  • the vehicle 100 is able to adjust its speed based on the predicted behavior of the identified object.
  • the self-driving car is able to determine what steady state the vehicle will need to adjust to (eg, accelerate, decelerate, or stop) based on the predicted behavior of the object.
  • other factors may also be considered to determine the speed of the vehicle 100 , such as the lateral position of the vehicle 100 in the traveling road, the curvature of the road, the proximity of static and dynamic objects, and the like.
  • the computing device may also provide instructions to modify the steering angle of the vehicle 100 such that the self-driving car follows a given trajectory and/or maintains contact with objects in the vicinity of the self-driving car (e.g., , the safe lateral and longitudinal distances of cars in adjacent lanes on the road.
  • objects in the vicinity of the self-driving car e.g., , the safe lateral and longitudinal distances of cars in adjacent lanes on the road.
  • the aforementioned vehicle 100 may be a car, truck, motorcycle, bus, recreational vehicle, playground vehicle, construction equipment, tram, golf cart, train, etc., which is not specifically limited in this embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a computer system 101 in a vehicle provided by an embodiment of the present application.
  • the computer system 101 shown in FIG. 4 is configured to execute the inter-process communication method provided by the embodiment of the present application.
  • Computer system 101 includes processor 103 coupled to system bus 105 .
  • the processor 103 may be used to implement the functions of the controller described in FIG. 2 .
  • the processor 103 may be one or more processors, each of which may include one or more processor cores.
  • a display adapter (video adapter) 107 which can drive a display 109, and the display 109 is coupled to the system bus 105.
  • the system bus 105 is coupled to an input-output (I/O) bus 113 through a bus bridge 111 .
  • I/O input-output
  • the I/O interface 115 is coupled to the I/O bus.
  • the I/O interface 115 communicates with various I/O devices, such as an input device 117 (such as a keyboard, a mouse, a touch screen, etc.), a multimedia tray (media tray) 121, (such as a CD-ROM, a multimedia interface, etc.).
  • Transceiver 123 which can send and/or receive radio communication signals
  • camera 155 which can capture dynamic digital video images
  • external USB port 125 external USB port 125 .
  • the interface connected to the I/O interface 115 may be a USB interface.
  • the processor 103 may be any conventional processor, including a Reduced Instruction Set Computing (“RISC”) processor, a Complex Instruction Set Computing (“CISC”) processor, or a combination thereof.
  • RISC Reduced Instruction Set Computing
  • CISC Complex Instruction Set Computing
  • a processor may be a special purpose device such as an application specific integrated circuit (“ASIC").
  • ASIC application specific integrated circuit
  • the processor 103 may be a neural network processor or a combination of a neural network processor and the above traditional processors.
  • computer system 101 may be located remotely from the autonomous vehicle and may communicate wirelessly with the autonomous vehicle.
  • some of the processes described herein are performed on a processor disposed within the self-driving vehicle and others are performed by a remote processor, including taking the actions required to perform a single maneuver.
  • Computer system 101 can communicate with software deployment server 149 through network interface 129 .
  • the network interface 129 is a hardware network interface, such as a network card.
  • the network 127 can be an external network, such as the Internet, or an internal network, such as Ethernet or a virtual private network (VPN).
  • the network 127 may also be a wireless network, such as a WiFi network, a cellular network, and the like.
  • a hard disk drive interface is coupled to the system bus 105 .
  • the hardware drive interface is connected with the hard disk drive.
  • System memory 135 is coupled to system bus 105 .
  • Data running in system memory 135 may include operating system 137 and application programs 143 of computer 101 .
  • the operating system includes a Shell 139 and a kernel (kernel) 141.
  • Shell 139 is an interface between the user and the kernel of the operating system.
  • the shell is the outermost layer of the operating system. The shell manages the interaction between the user and the operating system: waiting for user input, interpreting user input to the operating system, and processing various operating system output.
  • Kernel 141 consists of those parts of the operating system that manage memory, files, peripherals, and system resources. Directly interacting with hardware, the operating system kernel usually runs processes and provides communication between processes, providing CPU time slice management, interrupts, memory management, IO management, and so on.
  • the application program 143 includes a program 147 related to data processing and a program related to controlling the automatic driving of the vehicle.
  • the data processing-related program 147 is used to manage the data of multiple ECUs respectively.
  • the computer system 101 can realize the function of the controller described in FIG. 2 by executing the program 147 related to data processing, that is, to manage the data of multiple ECUs, for example, to delete the data stored in a certain ECU.
  • Programs related to controlling the automatic driving of the car may include, for example, programs that manage the interaction between the self-driving car and obstacles on the road, programs that control the route or speed of the self-driving car, and programs that control the interaction between the self-driving car and other self-driving cars on the road.
  • Application 143 also exists on the system of deploying server 149.
  • Sensor 153 is associated with computer system 101 .
  • Sensors 153 are used to detect the environment around computer system 101 .
  • the sensor 153 can detect animals, automobiles, obstacles and crosswalks, etc., and further sensors can also detect the surrounding environment of objects such as the above-mentioned animals, automobiles, obstacles and crosswalks, such as: the environment around the animals, for example, around the animals other animals, weather conditions, the brightness of the surrounding environment, etc.
  • FIG. 5 is a schematic flowchart of an inter-process communication method 500 provided in an embodiment of the present application. As shown in FIG. 5, the inter-process communication method 500 includes the following steps 501-505.
  • Step 501 acquire a first instruction from a first process, where the first instruction is used to request to acquire an address of a shared memory, and the shared memory is used for inter-process communication.
  • the first process may be any process that needs to implement inter-process communication through shared memory. Moreover, the first process may also be any party of the inter-process communication.
  • the first process can be the sender process of inter-process communication, and the first process needs to send communication data to the receiver process; the first process can also be the receiver process of inter-process communication, and the first process needs to receive Communication data sent.
  • the first process may be a sensor process, responsible for acquiring sensor data and sending the sensor data to a processing process; the first process may also be a processing process, responsible for receiving sensor data transmitted by shared memory data, and perform corresponding processing operations based on the sensor data.
  • the processor may obtain a first instruction from the first process, and the first instruction is used to request to obtain the address of the shared memory, so that the first process can go to the Write data in shared memory or read data in shared memory.
  • the first process may request to allocate shared memory and obtain information about the allocated shared memory.
  • the first process may generate a first instruction based on the information of the allocated shared memory to request to acquire the address of the shared memory used for communication.
  • the processor may acquire a fourth instruction from the first process, where the fourth instruction is used to request memory allocation for inter-process communication. Then, the processor allocates the shared memory for the first process according to the fourth instruction, and returns the identifier of the shared memory to the first process. Specifically, the processor may designate a memory segment in the memory as a shared memory according to the fourth instruction, and assign a unique identifier to the shared memory, and then return the identifier of the shared memory to the first process and the second process . In this way, the first process may generate a first instruction based on the identifier of the shared memory returned by the processor, where the first instruction includes the identifier of the shared memory to request to acquire the address of the shared memory.
  • Step 502 return a first address to the first process according to the first instruction, and add the first address to the filter table corresponding to the first process, the first address is the shared memory
  • the address in the filter table is used to store the address of the shared memory that the first process can access.
  • the processor After obtaining the first instruction from the first process, the processor obtains the first address in the shared memory according to the first instruction, and returns the first address to the first process for the first
  • the process uses the memory segment corresponding to the first address to perform inter-process communication.
  • the first address may be an address range, which is used to indicate an address segment corresponding to a memory segment in the shared memory.
  • the memory segment corresponding to the first address is the memory used for inter-process communication by the first process.
  • the first address may include a start address and an end address, the start address is used to indicate the start address of the memory segment corresponding to the first address, and the end address is used to indicate the first corresponding memory segment
  • the end address of the segment; the first address may also include a start address and an address offset, and the address offset is used to represent the address length between the start address and the end address of the memory segment corresponding to the first address.
  • the processor after the processor obtains the first address, the processor also adds the first address to the filter table corresponding to the first process.
  • the filter table is established by the processor when the first process needs to perform inter-process communication, and the filter table is used to record addresses that the first process can access, and the addresses recorded in the filter table are all is an address in shared memory. That is, for the addresses recorded in the filtering table, the first process has the right to access the addresses recorded in the filtering table; for the addresses of the shared memory not recorded in the filtering table, the first process has no access right.
  • the shared memory allocated by the processor for the first process and the second process is usually divided into multiple memory segments for the first process and the second process Simultaneous access to different memory segments in shared memory. Therefore, by establishing a filter table and adding the address in the shared memory requested by the first process to the filter table, the address of the shared memory to which the first process has access rights can be recorded.
  • Step 503 acquire a second instruction from the first process, the second instruction includes the first address, and the second instruction is used to request to use the storage space corresponding to the first address.
  • the first process After the first process obtains the first address returned by the processor, the first process generates a second instruction according to communication requirements.
  • the second instruction includes the address, and the second instruction is used to request to use the storage space corresponding to the first address, so as to implement inter-process communication based on the storage space corresponding to the first address.
  • the second instruction may be an instruction with different functions.
  • the first process when the first process is a sender process and the second process is a receiver process, the first process needs to transmit data to the second process, so the second instruction also includes the first data, and the second The second instruction is used to instruct to write the first data into the storage space corresponding to the first address, and the first data is data to be transmitted to the second process. That is to say, after the first process obtains the first address, it generates a second instruction based on the first address and the first data to be transmitted to the second process, so as to request to write the first address into the shared memory. a data.
  • the first process when the first process is the receiver process and the second process is the sender process, the first process needs to receive the data transmitted by the second process, so the second instruction is specifically used to instruct the read Fetch second data in the storage space corresponding to the first address, where the second data is data transmitted by the second process to the first process. That is to say, after the first process obtains the first address, based on the first address, it generates a second instruction for requesting access to the storage space corresponding to the first address, so as to read the second process through the storage space corresponding to the first address. The transmitted second data.
  • Step 504 based on the fact that the first address in the second instruction is an address of the shared memory, trigger querying the filter table, and execute the second instruction according to the fact that the first address is in the filter table.
  • the processor may recognize that the first address in the second instruction is an address in the shared memory used for inter-process communication. Therefore, in order to prevent the first process from stepping on the memory segment being used by other processes, the processor triggers to query the filter table, and confirms whether the first process has access to the first address by judging whether the first address in the second instruction is located in the filter table. The authority of an address.
  • the processor when the processor acquires an instruction to access a certain address and determines that the address is an address in the shared memory, the processor triggers a query filter table to determine whether the address is in the filter table. If the address is in the filtering table, it means that the process has the right to access the address; if the address is not in the filtering table, it means that the process does not have the right to access the address.
  • the processor can determine that the first process has permission to access the first address, and the processor executes a second instruction from the first process.
  • the second instruction further includes the first data
  • the processor sends the first data to the first address according to the second instruction
  • the corresponding storage space writes the first data, so that the second process obtains the first data transmitted by the first process from the storage space corresponding to the first address.
  • the processor reads the second data in the storage space corresponding to the first address according to the second instruction , and return the second data to the first process, so that the first process can obtain the second data transmitted by the second process.
  • Step 505 after executing the second instruction, delete the first address in the filtering table.
  • the processor After the processor executes the second instruction, the processor has implemented writing the first data into the storage space corresponding to the first address or reading the second data in the storage space corresponding to the first address, that is, the first process has completed After successfully transmitting the first data or reading the second data, the first process no longer needs to access the storage space corresponding to the first address. Therefore, after the processor finishes executing the second instruction, it deletes the first address in the filter table, so that the first process no longer has the right to access the first address.
  • the processor may also acquire a fifth instruction from the first process, where the fifth instruction is used to indicate that the storage space corresponding to the first address is used up.
  • the processor deletes the first address in the filtering table according to the fifth instruction.
  • the processor can reject the request based on the absence of the first address in the filter table.
  • the request of the first process thereby effectively preventing the first process from stepping on the storage space corresponding to the first address being used by other processes.
  • the first process that needs to communicate based on the shared memory obtains the address of the shared memory through an instruction, and is triggered by the instruction to add the address of the obtained shared memory to the filter table; when the first process accesses the address of the shared memory , triggering to query the filtering table to determine whether the first process has the permission to access the shared memory. Moreover, after the first process successfully accesses the shared memory, the access right of the first process is released in the filter table, thereby ensuring that the process will not trample on the shared memory being used by another process due to software errors or attacks.
  • the processor can deny access to the address of the shared memory that the process does not have the access right to, thereby preventing the process from stepping on the memory segment in the shared memory being used by other processes.
  • the processor obtains a third instruction from the first process, the third instruction includes the second address, and the third instruction is used to request the use of The storage space corresponding to the second address.
  • the second address is an address in the shared memory
  • the second address and the first address may be the same address
  • the second address and the first address may also be different addresses .
  • the second address is not located in the filtering table. That is, the processor may not trigger adding the second address to the filter table; the processor may also delete the second address from the filter table after the first process loses the access right to the second address.
  • the processor Based on the fact that the second address in the third instruction is an address of the shared memory, the processor triggers to query the filter table, and refuses to execute the third instruction according to that the second address is not in the filter table.
  • the processor may refuse to execute the process that the first process requests to access the second address. instruction, so as to ensure that the first process cannot use the storage space corresponding to the second address, and avoid the phenomenon that the first process tramples on the storage space being used by other processes.
  • this embodiment in order to enable the processor to recognize that the first address in the second instruction is an address of the shared memory, this embodiment indicates that the address belongs to the shared memory by adding a mark to the page table entry .
  • the addresses used by the process are all virtual addresses, it is usually necessary to search the page table to convert the virtual address into a physical address in the memory space, so as to determine the real memory address corresponding to the virtual address.
  • the page table is a special data structure, which is placed in the page table area of the system space, and stores the corresponding relationship between the virtual address and the physical address.
  • Each process has a corresponding page table.
  • a virtual address and its corresponding physical address are called a page table entry. By adding a flag to the page table entry, you can indicate that the virtual address in the page table entry belongs to the address in the shared memory.
  • FIG. 6 is a schematic structural diagram of a page table entry provided in an embodiment of the present application.
  • the page table entry includes a reserved bit (reserved), and the length of the reserved bit is 10 bits.
  • the page table entry also includes other bits, which are respectively used to indicate information such as the virtual address, the physical address, and the read and write permission of the physical address in the page table entry.
  • the processor can add a mark by setting one or more bits of the reserved bits of the page table entry. That is to say, for a certain virtual address, if one or more reserved bits in the page table entry of the virtual address are set, the processor can determine that the virtual address belongs to an address of the shared memory.
  • the processor may add a mark to the page table entry corresponding to the first process, and the mark is used to indicate that the first address is an address of a shared memory used for inter-process communication , the page table entry is used to indicate a mapping relationship between the first address and a physical address corresponding to the first address, where the first address is a virtual address.
  • the processor may add a mark to page table entries corresponding to all addresses included in the shared memory to indicate that the addresses in the shared memory are used A specific address for inter-process communication.
  • the processor may also add a mark to the page table entry corresponding to the first address after obtaining the first instruction from the first process, to indicate that the first address is a specific address for inter-process communication.
  • the processor may search the page table entry based on the first address in the second instruction, and determine the first address in the second instruction according to the flag in the page table entry. Address is the address of the shared memory.
  • the processor can look up the page table entry of the address, and determine whether the address is the address of the shared memory by confirming whether the reserved bit in the page table entry of the address is set. . If the reserved bit in the page table entry of the address is set, the processor can determine that the address belongs to the address of shared memory; if the reserved bit in the page table entry of the address is not set, the processor can determine that the The address does not belong to the address of shared memory.
  • the processor allocates a shared memory for communication between the first process and the second process.
  • the first process is the sender process
  • the first process requests the processor for the address of a memory segment in the shared memory, based on the requested memory segment to realize data transmission.
  • the first process is the receiver process
  • the first process needs to request the address of a memory segment in the shared memory from the processor, so as to read the data written into the memory segment by the second process.
  • a method for recording the usage of the shared memory is introduced in this embodiment.
  • Descriptor By using the descriptor to record the usage of the shared memory in real time, the processor can know the usage of the shared memory when it gets an instruction requesting to acquire the address in the shared memory, so as to return the address of a valid memory segment to the process.
  • the first instruction generated by the first process includes the identifier of the shared memory, and the first instruction is used to request to acquire the address of the shared memory .
  • the processor may acquire the descriptor corresponding to the shared memory according to the identifier in the first instruction.
  • the descriptor may be established by the processor after allocating the shared memory for the first process, and the descriptor is used to record usage of the shared memory. To put it simply, each time the processor allocates shared memory for two processes that need to communicate, it creates a descriptor for the allocated shared memory to record the usage of the shared memory.
  • the processor may determine the first address according to content of the descriptor, and return the first address to the first process.
  • the storage space corresponding to the first address is the storage space to be written or read in the shared memory.
  • the processor when the first process is the sender process, the processor returns the first address to the first process, and the storage space corresponding to the first address is the storage space of data to be written in the shared memory.
  • the processor returns the first address to the first process, and the storage space corresponding to the first address is the storage space of the data to be read in the shared memory.
  • the shared memory allocated by the processor to the first process includes a plurality of memory blocks, and the plurality of memory blocks are organized into a circular queue for reading and writing by processes.
  • the descriptor corresponding to the shared memory records and manages the state of each memory block in the plurality of memory blocks.
  • the descriptor includes a write pointer and a read pointer, the write pointer is used to indicate the position of the memory block to be written among the plurality of memory blocks in the circular queue, and the read The pointer is used to indicate the position of the to-be-read memory block in the circular queue among the plurality of memory blocks.
  • the processor can quickly determine the address of the memory block for writing data and the address of the memory block for reading data.
  • FIG. 7 is a schematic structural diagram of a descriptor provided by an embodiment of the present application.
  • the shared memory allocated by the processor is divided into 16 memory blocks, and the 16 memory blocks are respectively memory block 0-memory block 15 .
  • the 16 memory blocks are organized into a circular queue for the process to write data or read data cyclically.
  • the descriptor corresponding to the shared memory includes memory block size, memory block quantity, sender virtual address, receiver virtual address, write pointer, read pointer, and the like.
  • the size of the 16 memory blocks divided by the shared memory is the same, and the size of the memory block recorded in the descriptor may be, for example, 4 kilobytes (Kilobyte, kB).
  • the number of memory blocks indicates the number of memory blocks divided in the shared memory corresponding to the descriptor, for example, 16.
  • the virtual address of the sender corresponds to the write pointer.
  • the write pointer indicates the position of the memory block to be written in the ring queue, and the virtual address of the sender indicates the address of the memory block to be written.
  • the sender virtual address indicates the virtual address the processor needs to return to the sender process.
  • the virtual address of the receiver corresponds to the read pointer.
  • the read pointer indicates the position of the memory block of the current data to be read in the circular queue, and the virtual address of the receiver indicates the address of the memory block of the data to be read.
  • the fetcher virtual address indicates the virtual address that the processor needs to return to the reader process.
  • the write pointer points to the location of memory block 3, which indicates that the memory block currently to be written in the ring queue is memory block 3; when the sender process requests to obtain the address of the shared memory, The processor can return the virtual address of the memory block 3 to the sender.
  • the read pointer points to the location of memory block 0, that is, it indicates that the memory block currently to be read in the ring queue is memory block 0.
  • the two processes in the communication can work asynchronously, that is, the sender process and the receiver process access the shared memory at the same time. Different blocks of memory in memory.
  • the sender process may first sequentially write data to be transmitted to the receiver process in memory block 0, memory block 1, and memory block 2. Then, while the sender process writes data to memory block 3, the receiver process can access memory block 0 to obtain the data written into memory block 0 by the sender process. In this way, the sender process writes data sequentially according to the order of the memory blocks in the ring queue, and the receiver process also reads data sequentially according to the order of the memory blocks in the ring queue, so that the sender process and the receiver process work asynchronously and improve communication s efficiency. In addition, since multiple memory blocks in the shared memory are organized into a ring queue, the sender process can write data in the ring queue cyclically, thereby realizing the recycling of the shared memory and saving communication overhead.
  • the processor can update the write pointer or read pointer in the descriptor, so as to process when the process requests the address of the shared memory
  • the device can return a valid address to the process.
  • the processor updates the write pointer in the descriptor, so as to update the multiple The position of the memory block to be written in the memory block in the circular queue.
  • the write pointer is updated, the virtual address of the sender corresponding to the write pointer is also updated accordingly.
  • the processor updates the read pointer in the descriptor, so as to update the The position of the memory block to be read in the circular queue.
  • the receiver virtual address corresponding to the read pointer is also updated accordingly.
  • the sender process requests to obtain the address of the shared memory, and the processor returns the address of memory block 3 to the sender process according to the content of the descriptor; then, the processor obtains the data write instruction from the sender process , and write data into memory block 3 according to the data write instruction. After the processor executes the data write instruction, the processor updates the write pointer in the descriptor, and points the write pointer to the location of the memory block 4, which indicates the memory block currently to be written in the ring queue It is memory block 4.
  • the receiver process requests to obtain the address of the shared memory, and the processor returns the address of memory block 0 to the receiver process according to the content of the descriptor; then, the processor obtains the data read instruction from the receiver process, and according to This data read instruction reads the data in memory block 0.
  • the processor updates the read pointer in the descriptor, and points the read pointer to the location of memory block 1, which indicates the memory block of the current data to be read in the ring queue For memory block 1.
  • the processor when the process requests the address of the shared memory, the processor returns the corresponding address according to the write pointer or read pointer in the descriptor, and after executing the data write instruction or data read instruction, updates the description If the write pointer or read pointer in the symbol can ensure that the process writes data or reads data in multiple memory blocks of the ring queue in an orderly manner.
  • this embodiment may use a descriptor table to store addresses of multiple descriptors corresponding to the same process.
  • the processor may generate a descriptor table for the first process.
  • the processor adds the address of the descriptor of the shared memory corresponding to the first process and the process to the descriptor table.
  • the descriptor table may also include a correspondence between descriptors and identifiers of the shared memory, so that subsequent processors can determine corresponding descriptors according to the identifier of the shared memory.
  • the processor when the processor obtains the fourth instruction from the first process, the processor generates the descriptor corresponding to the shared memory according to the fourth instruction, and adds the address of the descriptor to the first process.
  • the descriptor table corresponding to a process. Among them, it is used to request the allocation of memory for inter-process communication.
  • the processor may also add the identifier of the shared memory to the descriptor table, so as to establish the relationship between the address of the descriptor and the identifier of the shared memory corresponding relationship.
  • the processor may acquire the address of the descriptor corresponding to the identifier in the descriptor table corresponding to the first process according to the identifier in the first instruction , the descriptor table is used to store addresses of one or more descriptors corresponding to the first process. Then, the processor acquires the descriptor according to the address of the descriptor.
  • the descriptor table corresponding to the first process includes four descriptors, which are descriptor 0, descriptor 1, descriptor 2, and descriptor 3; among them, descriptor 0, descriptor 1, descriptor 2, and
  • the identifiers of the shared memory corresponding to descriptor 3 are identifier 0, identifier 1, identifier 2, and identifier 3, respectively. Then, when the processor obtains the first instruction including the identifier 2 from the first process, the processor can determine the address of the descriptor 2 in the descriptor table according to the identifier 2, thereby obtaining the descriptor 2.
  • four new instructions are introduced in the process of process communication to support inter-process communication, and the behavior of process access to shared memory can be controlled to ensure that the process in communication cannot access the memory being used by other processes segment, so as to avoid the phenomenon that the data in the shared memory is damaged and cause the system to go down.
  • FIG. 8 is a schematic flowchart of an inter-process communication method 800 provided in an embodiment of the present application. As shown in FIG. 8, the inter-process communication method 800 includes the following steps 801-806.
  • Step 801 the sender process generates an Acquire instruction.
  • the sender process After the processor allocates the shared memory for the sender process and the receiver process, the sender process generates an Acquire instruction to request the address of the shared memory.
  • the processor After the processor acquires the Acquire instruction, the processor returns the address of the free memory block in the shared memory to the sender process, and adds the address of the memory block to the filter table corresponding to the sender process. That is to say, the sender process generates an Acquire command to trigger adding the address of the memory block to be accessed by the sender into the filter table, thereby granting the sender process the right to access the address of the memory block.
  • the Acquire instruction may be, for example, the first instruction described in the above embodiment.
  • Step 802 the sender process generates a data write instruction.
  • the sender process After obtaining the address of the memory block returned by the processor, the sender process generates a data write instruction including the address of the memory block, so as to instruct writing data to be transmitted to the receiver process into the memory block.
  • the processor After the processor obtains the data writing instruction, the processor triggers the query filter table according to the address in the data writing instruction being the address of the shared memory. In addition, the processor executes the data write instruction according to the address in the data write instruction located in the filter table, so as to write the data into the memory block.
  • the data writing instruction may be, for example, the second instruction described in the above embodiment.
  • Step 803 the sender process generates a Push instruction.
  • the data transmitted by the sender process is successfully written into the memory block of the shared memory, so the sender process generates a Push instruction to instruct to revoke the access right of the sender process to the memory block.
  • the processor deletes the address of the memory block in the filter table corresponding to the sender process according to the Push instruction, thereby revoking the access right of the sender process to the memory block.
  • the Push instruction may be, for example, the fifth instruction described in the above embodiment.
  • Step 804 the receiver process generates a Pop command.
  • the receiver process After the sender process writes data to the memory block of the shared memory, the receiver process generates a Pop instruction to request the address of the shared memory.
  • the processor After the processor obtains the Pop instruction, the processor returns the address of the memory block in the shared memory to which the data has been written to the receiver process, and adds the address of the memory block to the filter table corresponding to the receiver process. That is to say, the address of the memory block to be accessed by the receiver is triggered to be added into the filter table by generating a Pop instruction by the receiver process, thereby granting the receiver process the right to access the address of the memory block.
  • the Pop instruction may be, for example, the first instruction described in the above embodiment.
  • Step 805 the receiver process generates a data read command.
  • the receiver process After obtaining the address of the memory block returned by the processor, the receiver process generates a data read instruction including the address of the memory block to instruct to read the data written by the sender process in the memory block.
  • the processor After the processor obtains the data read instruction, the processor triggers the query filter table according to the address in the data read instruction being the address of the shared memory. Moreover, the processor executes the data reading instruction according to the address in the data reading instruction located in the filter table, thereby reading the data in the memory block and returning the read data to the receiver process.
  • the data reading instruction may be, for example, the second instruction described in the above embodiment.
  • Step 806 the receiver process generates a release (Release) command.
  • the receiver process After the execution of the data reading instruction is completed, the receiver process successfully reads the data in the memory block of the shared memory, so the receiver process generates a Release instruction to indicate that the access right of the receiver process to the memory block is revoked.
  • the processor deletes the address of the memory block in the filter table corresponding to the receiver process according to the Release command, thereby revoking the access right of the receiver process to the memory block.
  • the Release instruction may be, for example, the fifth instruction described in the above embodiment.
  • an Acquire command is used to grant the sender process the right to access a memory block in the shared memory
  • a Push command is used to revoke the sender process' access right.
  • the recipient process is given the permission to access the memory block in the shared memory through the Pop instruction, and the access permission of the recipient process is revoked through the Release instruction.
  • FIG. 9 is a schematic diagram of state changes of memory blocks in a shared memory provided by an embodiment of the present application. As shown in FIG. 9 , for a memory block in the shared memory, when data is not written, the state of the memory block is an idle (Free) state.
  • the sender process After the sender process generates the Acquire command, it means that the sender process will write data into the memory block, so the state of the memory block changes to the TxActive state.
  • the sender process When the sender process generates a Push command, it means that the sender process has successfully written the data into the memory block, which stores the data that the sender process needs to transmit to the receiver process, so the state of the memory block changes to Busy state.
  • the receiver process When the receiver process generates the Pop command, it means that the receiver process wants to read the data in the memory block, so the state of the memory block changes to the receiving active (RxActive) state.
  • the receiver process When the receiver process generates a Release command, it means that the receiver process has successfully read the data in the memory block, and the data stored in the memory block has been successfully transmitted to the receiver process, so the state of the memory block changes to the free state .
  • the sender process can continue to write the data to be transmitted into the memory block, and the receiver process reads the data in the memory block, so as to achieve Communication between processes.
  • FIG. 10 is a schematic diagram of a system architecture for inter-process communication provided by an embodiment of the present application.
  • the processor used to process the process includes two registers and a memory management unit (Memory Management Unit, MMU), and the MMU includes a filter.
  • MMU memory Management Unit
  • One register in the processor is used to store the address of the descriptor table in the memory, and the processor can obtain the descriptor table stored in the memory based on the value of the register; the other register is used to store the address of the filter table in the memory address, the processor can obtain the filter table stored in memory based on the value of this register.
  • the MMU is the piece of computer hardware responsible for handling memory access requests from the processor.
  • the function of the MMU mainly includes the translation from virtual address to physical address, that is, to convert the virtual address requested by the process to the physical address in the memory.
  • the filter in the MMU is used to determine whether the process has the right to access the address in the shared memory according to the address in the filter table when the shared memory access request from the process is obtained. If the process has the permission to access the address in the shared memory, execute the shared memory access request of the process; if the process does not have the permission to access the address in the shared memory, then refuse to execute the shared memory access request of the process, and report an exception.
  • each process corresponds to a descriptor table, which is used to store the addresses of all descriptors corresponding to the process; each process can establish one or more communications, and each communication has a corresponding descriptor , that is, each process corresponds to one or more descriptors. And, two processes in communication correspond to the same descriptor.
  • Each process also corresponds to a filter table, which records addresses of shared memory that the process can access.
  • FIG. 11A is a schematic structural diagram of a descriptor table provided by an embodiment of the present application.
  • the address of the descriptor table of process A is stored in descriptor table register 1 , and the processor can obtain the descriptor table of process A based on the value of descriptor table register 1 .
  • the address of the descriptor table of process B is stored in the descriptor table register 2, and the processor can obtain the descriptor table of process B based on the value of the descriptor table register 2.
  • addresses of multiple descriptors corresponding to process A are recorded.
  • the process may be the sender process in the communication, or the receiver process in the communication.
  • the 0th descriptor address in the descriptor table of process A indicates the descriptor corresponding to the communication between process A and process B.
  • addresses of multiple descriptors corresponding to process B are also recorded.
  • the process may be the sender process in the communication, or the receiver process in the communication.
  • the second descriptor address in the descriptor table of process B indicates the descriptor corresponding to the communication between process A and process B.
  • FIG. 11B is a schematic structural diagram of a descriptor provided by an embodiment of the present application.
  • multiple virtual addresses are recorded in the filter table, such as virtual address 1 , virtual address 2 and virtual address 3 .
  • each virtual address indicates a space range of a virtual address, that is, indicates an address range corresponding to a memory segment.
  • FIG. 12 is a schematic diagram of a system architecture in an intelligent driving scenario provided by an embodiment of the present application.
  • the system architecture of an intelligent driving scenario includes a sender processor, a receiver processor, and physical memory.
  • the sender processor refers to the processor running the sender process
  • the receiver processor refers to the processor running the receiver process.
  • MMU1 is responsible for converting the virtual address in the data write request from the sender process into a physical address.
  • the register 1 stores the address of the descriptor table 1 corresponding to the sender process in the physical memory.
  • Register 2 stores the address of the filter table 1 corresponding to the sender process in the physical memory.
  • MMU2 is responsible for converting the virtual address in the data read request from the receiver process into a physical address.
  • the register 3 stores the address of the descriptor table 2 corresponding to the receiver process in the physical memory.
  • the register 4 stores the address of the filter table 2 corresponding to the receiver process in the physical memory.
  • Descriptor Table 1 and filter table 1 corresponding to the sender process
  • descriptor table 2 and filter table 2 corresponding to the receiver process
  • shared memory and Descriptor the shared memory and Descriptor.
  • Descriptor Table 1 and Descriptor Table 2 both indicate the address of the descriptor. The usage of multiple memory blocks in the shared memory is recorded in the descriptor.
  • FIG. 13 is a schematic flowchart of an inter-process communication method 1300 provided in an embodiment of the present application. As shown in FIG. 13 , the inter-process communication method 1300 includes the following steps 1301-1316.
  • Step 1301 the sender processor acquires the Acquire command from the sender process.
  • the sender processor After the sender processor allocates the shared memory for the sender process, the sender processor stores the identifier of the shared memory in source register 1.
  • the sender process may generate an Acquire instruction based on the identification of the shared memory in source register 1 .
  • the Acquire command includes an identifier of the shared memory, and the Acquire command is used to request to acquire an address in the shared memory.
  • Step 1302 the sender processor returns the address of the target memory block in the shared memory to the sender process.
  • the sender processor obtains the physical address of the descriptor table according to the descriptor table register, thereby obtaining the descriptor table corresponding to the sender process. Then, the sender process determines the address of the corresponding descriptor in the descriptor table according to the identifier of the shared memory in the Acquire instruction, so as to obtain the descriptor corresponding to the sender process. The sender process then determines the address of the target memory block according to the write pointer in the descriptor, and stores the address of the target memory block in the target register, so as to return the address of the target memory block in the shared memory to the sender process. Wherein, the target memory block is a memory block in the shared memory to which data is to be written.
  • Step 1303 the sender processor adds the address of the target memory block to the filter table 1 .
  • the sender processor obtains the physical address of the filter table 1 according to the filter table register, thereby obtaining the filter table 1 corresponding to the sender process. Then, the sender processor adds the address of the target memory block to filter table 1 .
  • Step 1304 the sender processor acquires a data write instruction from the sender process, and the data write instruction includes the address of the target memory block and the data to be written.
  • Step 1305 the processor at the sender side triggers querying the filtering table 1 according to the address in the data writing instruction as the address of the shared memory, and confirms that the address in the data writing instruction is in the filtering table 1.
  • the sender processor When the sender processor allocates shared memory for the sender process, the sender processor sets the reserved bit in the page table entry corresponding to the address of the shared memory in the sender process to indicate that the address of the shared memory is dedicated to inter-process communication. Therefore, the sender processor can determine that the address in the data write instruction is the address of the shared memory according to the page table entry corresponding to the address in the data write instruction is set, thereby triggering query filter table 1 . And, the sender processor can confirm that the address in the data write command is located in the filter table 1 .
  • Step 1306 the sender's processor executes the data writing instruction to write data to the target memory block in the shared memory.
  • Step 1307 the sender processor obtains the Push instruction from the sender process.
  • the data transmitted by the sender process is successfully written into the memory block of the shared memory, so the sender process generates a Push instruction to instruct to revoke the access right of the sender process to the target memory block.
  • the sender processor updates the write pointer in the descriptor so that the write pointer points to the memory block next to the target memory block.
  • Step 1309 the receiver processor obtains the Pop instruction from the receiver process.
  • the receiver processor After allocating the shared memory for the sender process and the receiver process, the receiver processor stores the identifier of the shared memory in the source register 2 .
  • the receiver process can generate a Pop instruction based on the identification of the shared memory in the source register 2 .
  • the Pop instruction includes an identifier of the shared memory, and the Pop instruction is used to request to obtain an address in the shared memory.
  • Step 1310 the receiver processor returns the address of the target memory block in the shared memory to the receiver process.
  • the receiver processor obtains the physical address of the descriptor table according to the descriptor table register, thereby obtaining the descriptor table corresponding to the receiver process. Then, the receiver process determines the address of the corresponding descriptor in the descriptor table according to the identifier of the shared memory in the Pop instruction, so as to obtain the descriptor corresponding to the receiver process. The receiver process then determines the address of the target memory block according to the read pointer in the descriptor, and stores the address of the target memory block in the target register, so as to return the address of the target memory block in the shared memory to the receiver process.
  • the target memory block is a memory block of data to be read in the shared memory.
  • Step 1311 the receiver processor adds the address of the target memory block to the filtering table 2 .
  • the receiver processor obtains the physical address of the filter table 2 according to the filter table register, thereby obtaining the filter table 2 corresponding to the receiver process. Then, the receiver processor adds the address of the target memory block to the filtering table 2 .
  • Step 1312 the receiving processor obtains the data reading instruction from the receiving process, and the data writing instruction includes the address of the target memory block.
  • Step 1313 the receiver processor triggers to query the filter table 2 according to the address in the data read instruction is the address of the shared memory, and confirms that the address in the data read instruction is in the filter table 2 .
  • the recipient processor allocates shared memory for the recipient process
  • the recipient processor sets the reserved bit in the page table entry corresponding to the address of the shared memory in the recipient process to indicate that the address of the shared memory is dedicated to inter-process communication. Therefore, according to the page table entry corresponding to the address in the data write instruction is set, the receiving processor can determine that the address in the data read instruction is the address of the shared memory, thereby triggering the query filter table 2 . And, the recipient processor can confirm that the address in the data read instruction is in the filtering table 2 .
  • Step 1314 the receiver processor executes the data read instruction to read the data in the target memory block in the shared memory.
  • Step 1315 the receiving processor obtains the Release command from the receiving process.
  • the receiver process After the execution of the data reading instruction, the receiver process has successfully read the data in the memory block of the shared memory, so the receiver process generates a Push instruction to indicate the revocation of the receiver process's access right to the target memory block.
  • Step 1316 the receiver processor deletes the address of the target memory block in the filtering table 2.
  • the receiver processor updates the read pointer in the descriptor so that the read pointer points to the memory block next to the target memory block.
  • FIG. 14 is a schematic structural diagram of an electronic device 1400 provided in an embodiment of the present application.
  • the electronic device 1400 includes: an acquisition unit 1401, a processing unit 1402, and a sending unit 1403; Obtaining a first instruction from a first process, the first instruction is used to request to obtain an address of a shared memory, and the shared memory is used for inter-process communication; the sending unit 1403 is configured to send the The first process returns a first address, and adds the first address to a filter table corresponding to the first process, the first address is an address in the shared memory, and the filter table is used for Store the address of the shared memory that the first process can access; the acquisition unit 1401 is also used to acquire a second instruction from the first process, the second instruction includes the first address, the second The instruction is used to request to use the storage space corresponding to the first address; the processing unit 1402 is configured to trigger querying the filter table based on the first address in the second instruction being an address of the shared memory, and according to the The first
  • the second instruction further includes first data, and the second instruction is used to instruct to write the first data into the storage space corresponding to the first address, and the first The data is data to be transmitted to the second process; the processing unit 1402 is specifically configured to write the first data into the storage space corresponding to the first address.
  • the second instruction is used to instruct to read the second data in the storage space corresponding to the first address, and the second data is transmitted from the second process to the first process the data;
  • the processing unit 1402 is specifically configured to read the second data in the storage space corresponding to the first address, and return the second data to the first process.
  • the acquiring unit 1401 is further configured to acquire a third instruction from the first process, the third instruction includes the second address, and the third instruction is used to request to use The storage space corresponding to the second address, where the second address is an address in the shared memory; the processing unit 1402 is specifically configured to, based on the second address in the third instruction being an address in the shared memory, Triggering to query the filter table, and refusing to execute the third instruction according to the fact that the second address is not in the filter table.
  • the processing unit 1402 is further configured to add a mark to the page table entry corresponding to the first process, and the mark is used to indicate that the first address is used for inter-process communication address, the page table entry is used to indicate the mapping relationship between the first address and the physical address corresponding to the first address, the first address is a virtual address; the processing unit 1402 is specifically used to : Finding the page table entry based on the first address in the second instruction; determining that the first address in the second instruction is an address of a shared memory according to a flag in the page table entry.
  • the first instruction includes an identifier of the shared memory; the processing unit 1402 is specifically configured to obtain a descriptor according to the identifier, and the descriptor is used to record the identifier of the shared memory The usage of the application; the sending unit 1403 is specifically configured to determine the first address according to the descriptor, and return the first address to the first process, and the storage space corresponding to the first address is the The storage space to be written or read in the shared memory.
  • the processing unit 1402 is specifically configured to: acquire the address of the descriptor corresponding to the identifier in the descriptor table corresponding to the first process according to the identifier, and the descriptor table It is used to store the addresses of one or more descriptors corresponding to the first process; and obtain the descriptors according to the addresses of the descriptors.
  • the shared memory includes a plurality of memory blocks, and the plurality of memory blocks constitute a circular queue for processes to read and write;
  • the descriptor includes a write pointer and a read pointer, so The write pointer is used to indicate the position of the memory block to be written in the circular queue in the plurality of memory blocks, and the read pointer is used to indicate the memory block to be read in the plurality of memory blocks position in the circular queue.
  • the processing unit 1402 is specifically configured to: after executing the second instruction, update the write pointer in the descriptor, so as to update the The position of the memory block to be written in the circular queue; or, after executing the second instruction, updating the read pointer in the descriptor, so as to update the memory blocks to be read in the plurality of memory blocks The position of the fetched memory block in the circular queue.
  • the obtaining unit 1401 is further configured to obtain a fourth instruction from the first process, where the fourth instruction is used to request memory allocation for inter-process communication;
  • the processing unit 1402 is further configured to allocate the shared memory for the first process according to the fourth instruction, and return an identifier of the shared memory to the first process.
  • the processing unit 1402 is further configured to generate a descriptor corresponding to the shared memory according to the fourth instruction, and add the address of the descriptor to the address corresponding to the first process. in the descriptor table.
  • the acquiring unit 1401 is further configured to acquire a fifth instruction from the first process, where the fifth instruction is used to indicate that the storage space corresponding to the first address is used up ;
  • the processing unit 1402 is further configured to delete the first address in the filtering table according to the fifth instruction.
  • the inter-process communication method provided by the embodiment of the present application can be specifically implemented by a chip in an electronic device, and the chip includes: a processing unit and a communication unit.
  • the processing unit can be, for example, a processor.
  • the communication unit can be, for example, an input/output interface, a pipe pins or circuits etc.
  • the processing unit may execute the computer-executable instructions stored in the storage unit, so that the chip in the electronic device executes the inter-process communication method described in the embodiments shown in FIGS. 1 to 13 above.
  • the storage unit is a storage unit in the chip, such as a register, a cache, etc.
  • the storage unit can also be a storage unit located outside the chip in the wireless access device end, such as a read-only memory (read-only memory, ROM) Or other types of static storage devices that can store static information and instructions, random access memory (random access memory, RAM), etc.
  • ROM read-only memory
  • RAM random access memory
  • the present application also provides a computer-readable storage medium.
  • the method disclosed in FIG. Computer program instructions encoded on other non-transitory media or articles of manufacture.
  • Figure 15 schematically illustrates a conceptual partial view of an example computer-readable storage medium comprising a computer program for executing a computer process on a computing device, arranged in accordance with at least some embodiments presented herein.
  • computer readable storage medium 1500 is provided using signal bearing medium 1501 .
  • the signal-bearing medium 1501 may include one or more program instructions 1502 which, when executed by one or more processors, may provide the functions or portions of the functions described above with respect to FIG. 5 .
  • program instructions 1502 in FIG. 15 also describe example instructions.
  • signal bearing medium 1501 may include computer readable medium 1503 such as, but not limited to, a hard drive, compact disc (CD), digital video disc (DVD), digital tape, memory, ROM or RAM, and the like.
  • computer readable medium 1503 such as, but not limited to, a hard drive, compact disc (CD), digital video disc (DVD), digital tape, memory, ROM or RAM, and the like.
  • signal bearing media 1501 may comprise computer recordable media 1504 such as, but not limited to, memory, read/write (R/W) CDs, R/W DVDs, and the like.
  • signal bearing media 1501 may include communication media 1505, such as, but not limited to, digital and/or analog communication media (eg, fiber optic cables, waveguides, wired communication links, wireless communication links, etc.).
  • signal bearing medium 1501 may be conveyed by a wireless form of communication medium 1505 (eg, a wireless communication medium that complies with the IEEE 802.15 standard or other transmission protocol).
  • One or more program instructions 1502 may be, for example, computer-executable instructions or logic-implemented instructions.
  • the computing device of the computing device may be configured to respond to program instructions 1502 communicated to the computing device via one or more of computer-readable media 1503 , computer-recordable media 1504 , and/or communication media 1505 , providing various operations, functions, or actions.
  • the disclosed system, device and method can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.
  • the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or part of the contribution to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium includes: various media capable of storing program codes such as U disk, mobile hard disk, read-only memory, random access memory, magnetic disk or optical disk.

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Abstract

本申请公开了一种进程间通信方法，应用于运行多个进程的电子设备。该方法包括：获取用于请求获取共享内存的地址的第一指令；根据第一指令向第一进程返回第一地址，并将第一地址添加至用于存放第一进程能够访问的共享内存的地址的过滤表中；获取来自于第一进程的第二指令，第二指令包括第一地址，第二指令用于请求使用第一地址对应的存储空间；基于第二指令中的第一地址为共享内存的地址，触发查询过滤表，并根据第一地址位于过滤表中，执行第二指令；在执行第二指令后，在过滤表中删除第一地址。基于本方法，能够保证在软件发生错误时，通信中的进程无法访问其他进程正在使用的内存段，从而避免共享内存中数据受到破坏而导致系统宕机。

Description

一种进程间通信方法及相关装置
本申请要求于2021年9月29日提交中国专利局、申请号为202111155635.5、发明名称为“一种进程间通信方法及相关装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机技术领域，尤其涉及一种进程间通信方法及相关装置。
背景技术
近年来，随着人们生活品质的提高和技术水平的飞跃，车载市场迎来前所未有的机遇--智能化。智能驾驶场景中会存在大量的进程间通信，例如，传感器进程把图像传输给不同的处理进程，处理进程执行相应的识别处理后，再给车辆内相应的部件发出控制信号。由实际应用可知，智能驾驶场景对进程间通信的效率和安全性都有很高的要求，效率影响车辆对紧急情况做出反应的速度，而安全性直接与乘客的生命安全息息相关。
在传统方法中，通常是基于套接字(socket)技术以及消息队列(Message Queue)技术来实现进程间通信。然而，socket技术以及Message Queue技术均涉及到数据的拷贝，通信效率差。因此，目前主要采用共享内存的方式来实现进程间通信。基于共享内存的方式来进行通信，无需涉及数据的拷贝，通信效率高。
在通过共享内存进行通信的场景，通信中的多个进程在任意时刻访问的是共享内存中不同的内存段。但是，当软件在运行过程中发生错误时，通信中的一个进程可能会访问另一个进程正在使用的内存段，这就有可能破坏共享内存中的数据，从而导致系统宕机。在智能驾驶场景下，一旦出现这种情况，有可能会危害到人身安全。
发明内容
本申请实施例提供了一种进程间通信方法，能够保证在软件发生错误时，通信中的进程无法访问其他进程正在使用的内存段，从而避免出现共享内存中数据受到破坏而导致系统宕机的现象，保证了系统的正常运行。
本申请第一方面提供一种进程间通信方法，应用于运行有多个进程的电子设备，例如智能驾驶场景下的无线电子设备。该方法包括：处理器获取来自于第一进程的第一指令，所述第一指令用于请求获取共享内存的地址，以便于第一进程往共享内存中写入数据或者读取共享内存中的数据。所述共享内存用于进程间通信。在智能驾驶场景中，第一进程例如为传感器进程，负责获取传感器数据并将传感器数据发送给处理进程；第一进程也可以为处理进程，负责接收传感器数据通过共享内存传输的传感器数据，并根据传感器数据执行相应的处理操作。
处理器根据所述第一指令向所述第一进程返回第一地址，并将所述第一地址添加至所述第一进程对应的过滤表中。所述第一地址可以为一个地址范围，用于指示共享内存中的一个内存段所对应的地址段。所述第一地址对应的内存段即为用于供第一进程进行进程间通信的内存。所述过滤表用于存放第一进程能够访问的共享内存的地址，且所述过滤表中 所记录的地址均为共享内存中的地址。
处理器获取来自于所述第一进程的第二指令，所述第二指令包括所述第一地址，所述第二指令用于请求使用所述第一地址对应的存储空间，以基于所述第一地址对应的存储空间来实现进程间通信。
处理器基于所述第二指令中的第一地址为共享内存的地址，触发查询所述过滤表，并根据所述第一地址位于所述过滤表中，执行所述第二指令。也就是说，在处理器在获取到访问某一个地址的指令并确定该地址为共享内存中的地址时，处理器则触发查询过滤表，以确定该地址是否位于过滤表中。如果该地址位于过滤表中，则代表进程具有访问该地址的权限；如果该地址不位于过滤表中，则代表进程不具有访问该地址的权限。
处理器在执行所述第二指令后，在所述过滤表中删除所述第一地址，从而使得第一进程不再具有访问第一地址的权限。
本方案中，需要基于共享内存进行通信的第一进程通过指令来获取共享内存的地址，并由该指令触发将获取的共享内存的地址加入过滤表中；在第一进程访问共享内存的地址时，触发查询过滤表，以确定第一进程是否具有访问共享内存的权限。并且，在第一进程成功访问共享内存后，在过滤表中释放第一进程的访问权限，从而保证进程不会因为软件错误或受到攻击而踩踏另一个进程正在使用的共享内存。基于本方案，能够保证在软件发生错误或受到恶意攻击时，通信中的进程无法访问其他进程正在使用的内存段，从而避免出现共享内存中数据受到破坏而导致系统宕机的现象，保证了系统的正常运行。
在一种可能的实现方式中，所述第一进程为发送方进程，所述第二指令还包括第一数据，所述第二指令用于指示向所述第一地址对应的存储空间写入所述第一数据，所述第一数据为待传输给第二进程的数据。所述处理器执行所述第二指令的过程包括：处理器向所述第一地址对应的存储空间写入所述第一数据。
在一种可能的实现方式中，所述第一进程为接收方进程，所述第二指令用于指示读取所述第一地址对应的存储空间中的第二数据，所述第二数据为第二进程向所述第一进程传输的数据。所述处理器执行所述第二指令的过程包括：处理器读取所述第一地址对应的存储空间中的第二数据，并向所述第一进程返回所述第二数据。
在一种可能的实现方式中，在第一进程出现bug或者受到恶意攻击时，处理器获取来自于所述第一进程的第三指令，所述第三指令包括第二地址，所述第三指令用于请求使用所述第二地址对应的存储空间。所述第二地址为所述共享内存中的地址，且所述第二地址并不位于过滤表中。即，处理器可以是并没有触发将第二地址添加至过滤表中；处理器也可以是在第一进程失去访问第二地址的访问权限之后，将第二地址从过滤表中删除。
处理器基于所述第三指令中的第二地址为共享内存的地址，触发查询所述过滤表，并根据所述第二地址不位于所述过滤表中，拒绝执行所述第三指令。
本方案中，在第一进程所请求访问的第二地址属于共享内存中的地址，且所述第二地址不位于所述过滤表时，处理器可以拒绝执行第一进程请求访问第二地址的指令，从而保证第一进程无法使用第二地址对应的存储空间，避免出现第一进程踩踏其他进程正在使用 的存储空间的现象。
在一种可能的实现方式中，在为第一进程分配了所述共享内存或获取到来自于第一进程的第一指令之后，处理器在所述第一进程对应的页表项中添加标记。其中，所述标记用于指示所述第一地址为用于进程间通信的地址，所述页表项用于指示所述第一地址与所述第一地址对应的物理地址之间的映射关系，所述第一地址为虚拟地址。
在获取到第二指令之后，处理器可以基于所述第二指令中的第一地址查找所述页表项，并根据所述页表项中的标记，确定所述第二指令中的第一地址为共享内存的地址。
本方案中，通过在页表项中添加标记，来指示属于共享内存中的地址，使得处理器能够识别到第二指令中的第一地址为共享内存的地址，提高了方案的可行性。
在一种可能的实现方式中，在处理器为第一进程分配共享内存之后，第一进程生成的所述第一指令中包括所述共享内存的标识，所述第一指令用于请求获取所述共享内存的地址。
处理器根据所述第一指令中的所述标识获取所述共享内存对应的描述符。其中，所述描述符可以是处理器在为所述第一进程分配所述共享内存之后建立的，所述描述符用于记录所述共享内存的使用情况。即，处理器每次为需要进行通信的两个进程分配共享内存之后，则为所分配的共享内存建立一个描述符，以记录该共享内存的使用情况。
处理器根据所述描述符的内容确定所述第一地址，并向所述第一进程返回所述第一地址，所述第一地址对应的存储空间为所述共享内存中待写入或待读取的存储空间。
本方案中，通过采用描述符来实时记录共享内存的使用情况，可以使得处理器能够在获取到请求获取共享内存中的地址的指令时，获知共享内存的使用情况，从而向进程返回有效的内存段的地址。
在一种可能的实现方式中，在第一进程第一次与其他进程建立通信时，处理器可以为第一进程生成描述符表。在处理器获取到包括有共享内存的标识的第一指令时，处理器根据所述第一指令中的标识，在第一进程对应的描述符表中获取所述标识对应的描述符的地址，所述描述符表用于存储所述第一进程对应的一个或多个描述符的地址。处理器再根据所述描述符的地址获取所述描述符。
本方案中，通过描述符表来记录描述符的地址，可以有效管理同一个进程对应的多个描述符，保证方案的可实现性。
在一种可能的实现方式中，处理器为第一进程所分配的共享内存包括多个内存块，所述多个内存块构成用于供进程读写的环形队列。其中，所述共享内存对应的描述符对所述多个内存块中的每个内存块的状态进行记录与管理。具体地，所述描述符包括写入指针和读取指针，所述写入指针用于指示所述多个内存块中待写入的内存块在所述环形队列中的位置，所述读取指针用于指示所述多个内存块中待读取的内存块在所述环形队列中的位置。 基于所述描述符中的写入指针以及读取指针，处理器可以快速确定用于供写入数据的内存块的地址以及用于供读取数据的内存块的地址。
本方案中，通过将共享内存中的多个内存块组织成环形队列，采用描述符记录环形队列中的内存块的状态，可以使得通信中的双方进程能够异步工作，即发送方进程和接收方进程同时访问共享内存中不同的内存块，提高通信的效率。
此外，由于共享内存中的多个内存块被组织成环形队列，发送方进程可以循环地在环形队列中写入数据，从而实现共享内存的循环利用，节省通信开销。
在一种可能的实现方式中，在执行所述第二指令后，处理器更新所述描述符中的所述写入指针，以更新所述多个内存块中待写入的内存块在所述环形队列中的位置；
或，在执行所述第二指令后，处理器更新所述描述符中的所述读取指针，以更新所述多个内存块中待读取的内存块在所述环形队列中的位置。
在一种可能的实现方式中，在第一进程与其他进程建立通信之前，处理器获取来自于所述第一进程的第四指令，所述第四指令用于请求分配用于进行进程间通信的内存。处理器根据所述第四指令为所述第一进程分配所述共享内存，并向所述第一进程返回所述共享内存的标识。
在一种可能的实现方式中，在获取到来自于第一进程的第四指令之后，处理器还根据所述第四指令生成所述共享内存对应的描述符，并将所述描述符的地址添加至所述第一进程对应的描述符表中。在处理器根据第四指令为第一进程分配共享内存之后，处理器还可以将该共享内存的标识添加至描述符表中，以建立所述描述符的地址与所述共享内存的标识之间的对应关系，便于后续处理器能够根据共享内存的标识确定相应的描述符。
在一种可能的实现方式中，所述在执行所述第二指令后，处理器获取来自于所述第一进程的第五指令，所述第五指令用于指示所述第一地址对应的存储空间使用完毕。处理器根据所述第五指令，将所述过滤表中的第一地址删除。
通过由第一进程发送的第二指令来触发处理器撤销第一进程对共享内存的访问权限，能够使得进程访问共享内存的行为能够得到控制，保证通信中的进程无法访问其他进程正在使用的内存段，从而避免出现共享内存中数据受到破坏而导致系统宕机的现象。
本申请第二方面提供一种电子设备，包括获取单元、处理单元和发送单元；所述获取单元，用于获取来自于第一进程的第一指令，所述第一指令用于请求获取共享内存的地址，所述共享内存用于进程间通信；所述发送单元，用于根据所述第一指令向所述第一进程返回第一地址，并将所述第一地址添加至所述第一进程对应的过滤表中，所述第一地址为所述共享内存中的地址，所述过滤表用于存放第一进程能够访问的共享内存的地址；所述获取单元，还用于获取来自于所述第一进程的第二指令，所述第二指令包括所述第一地址，所述第二指令用于请求使用所述第一地址对应的存储空间；所述处理单元，用于基于所述 第二指令中的第一地址为共享内存的地址，触发查询所述过滤表，并根据所述第一地址位于所述过滤表中，执行所述第二指令；所述处理单元，还用于在执行所述第二指令后，在所述过滤表中删除所述第一地址。
在一种可能的实现方式中，所述第二指令还包括第一数据，所述第二指令用于指示向所述第一地址对应的存储空间写入所述第一数据，所述第一数据为待传输给第二进程的数据；所述处理单元，具体用于向所述第一地址对应的存储空间写入所述第一数据。
在一种可能的实现方式中，所述第二指令用于指示读取所述第一地址对应的存储空间中的第二数据，所述第二数据为第二进程向所述第一进程传输的数据；所述处理单元，具体用于读取所述第一地址对应的存储空间中的第二数据，并向所述第一进程返回所述第二数据。
在一种可能的实现方式中，所述获取单元，还用于获取来自于所述第一进程的第三指令，所述第三指令包括第二地址，所述第三指令用于请求使用所述第二地址对应的存储空间，所述第二地址为所述共享内存中的地址；所述处理单元，具体用于基于所述第三指令中的第二地址为共享内存的地址，触发查询所述过滤表，并根据所述第二地址不位于所述过滤表中，拒绝执行所述第三指令。
在一种可能的实现方式中，所述处理单元，还用于在所述第一进程对应的页表项中添加标记，所述标记用于指示所述第一地址为用于进程间通信的地址，所述页表项用于指示所述第一地址与所述第一地址对应的物理地址之间的映射关系，所述第一地址为虚拟地址；所述处理单元，具体用于：基于所述第二指令中的第一地址查找所述页表项；根据所述页表项中的标记，确定所述第二指令中的第一地址为共享内存的地址。
在一种可能的实现方式中，所述第一指令包括所述共享内存的标识；所述处理单元，具体用于根据所述标识获取描述符，所述描述符用于记录所述共享内存的使用情况；所述发送单元，具体用于根据所述描述符确定所述第一地址，并向所述第一进程返回所述第一地址，所述第一地址对应的存储空间为所述共享内存中待写入或待读取的存储空间。
在一种可能的实现方式中，所述处理单元，具体用于：根据所述标识，在第一进程对应的描述符表中获取所述标识对应的描述符的地址，所述描述符表用于存储所述第一进程对应的一个或多个描述符的地址；根据所述描述符的地址获取所述描述符。
在一种可能的实现方式中，所述共享内存包括多个内存块，所述多个内存块构成用于供进程读写的环形队列；所述描述符包括写入指针和读取指针，所述写入指针用于指示所述多个内存块中待写入的内存块在所述环形队列中的位置，所述读取指针用于指示所述多个内存块中待读取的内存块在所述环形队列中的位置。
在一种可能的实现方式中，所述处理单元，具体用于：在执行所述第二指令后，更新所述描述符中的所述写入指针，以更新所述多个内存块中待写入的内存块在所述环形队列中的位置；或，在执行所述第二指令后，更新所述描述符中的所述读取指针，以更新所述多个内存块中待读取的内存块在所述环形队列中的位置。
在一种可能的实现方式中，所述获取单元，还用于获取来自于所述第一进程的第四指令，所述第四指令用于请求分配用于进行进程间通信的内存；所述处理单元，还用于根据 所述第四指令为所述第一进程分配所述共享内存，并向所述第一进程返回所述共享内存的标识。
在一种可能的实现方式中，所述处理单元，还用于根据所述第四指令生成所述共享内存对应的描述符，并将所述描述符的地址添加至所述第一进程对应的描述符表中。
在一种可能的实现方式中，所述获取单元，还用于获取来自于所述第一进程的第五指令，所述第五指令用于指示所述第一地址对应的存储空间使用完毕；所述处理单元，还用于根据所述第五指令，将所述过滤表中的第一地址删除。
本申请第三方面提供一种电子设备，该电子设备包括：存储器和处理器；所述存储器存储有代码，所述处理器被配置为执行所述代码，当所述代码被执行时，所述电子设备执行如第一方面中的任意一种实现方式的方法。
本申请第四方面提供一种智能汽车，该智能汽车包括：存储器和处理器；所述存储器存储有代码，所述处理器被配置为执行所述代码，当所述代码被执行时，所述智能汽车执行如第一方面中的任意一种实现方式的方法。
本申请第五方面提供一种计算机可读存储介质，计算机可读存储介质中存储有计算机程序，当其在计算机上运行时，使得计算机执行如第一方面或第二方面中的任意一种实现方式的方法。
本申请第六方面提供一种计算机程序产品，当其在计算机上运行时，使得计算机执行如第一方面或第二方面中的任意一种实现方式的方法。
本申请第七方面提供一种芯片，包括一个或多个处理器。处理器中的部分或全部用于读取并执行存储器中存储的计算机程序，以执行上述任一方面任意可能的实现方式中的方法。
可选地，该芯片该包括存储器，该存储器与该处理器通过电路或电线与存储器连接。可选地，该芯片还包括通信接口，处理器与该通信接口连接。通信接口用于接收需要处理的数据和/或信息，处理器从该通信接口获取该数据和/或信息，并对该数据和/或信息进行处理，并通过该通信接口输出处理结果。该通信接口可以是输入输出接口。本申请提供的方法可以由一个芯片实现，也可以由多个芯片协同实现。
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图1为本申请实施例提供的一种基于socket技术的通信示意图；
图2为本申请实施例提供的一种基于Message Queue技术的通信示意图；
图3为本申请实施例提供的车辆100的一种结构示意图；
图4为本申请实施例提供的一种车辆内的计算机系统101的结构示意图；
图5为本申请实施例提供的一种进程间通信方法500的流程示意图；
图6为本申请实施例提供的一种页表项的结构示意图；
图7为本申请实施例提供的一种描述符的结构示意图；
图8为本申请实施例提供的一种进程间通信方法800的流程示意图；
图9为本申请实施例提供的一种共享内存中的内存块的状态变化示意图；
图10为本申请实施例提供的一种进程间通信的系统架构示意图；
图11A为本申请实施例提供的一种描述符表的结构示意图；
图11B为本申请实施例提供的一种描述符的结构示意图；
图12为本申请实施例提供的一种智能驾驶场景下的系统架构示意图；
图13为本申请实施例提供的一种进程间通信方法1300的流程示意图；
图14为本申请实施例提供的一种电子设备1400的结构示意图；
图15为本申请实施例提供的一种计算机可读存储介质1500的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
下面结合附图，对本申请的实施例进行描述。本领域普通技术人员可知，随着技术的发展和新场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
近年来，随着人们生活品质的提高和技术水平的飞跃，车载市场迎来前所未有的机遇--智能化。智能驾驶场景中会存在大量的进程间通信，例如，传感器进程把图像传输给不同的处理进程，处理进程执行相应的识别处理后，再给车辆内相应的部件发出控制信号。由实际应用可知，智能驾驶场景对进程间通信的效率和安全性都有很高的要求，效率影响车辆对紧急情况做出反应的速度，而安全性直接与乘客的生命安全息息相关。
此外，在智能驾驶场景中，需要进行通信的两个进程通常位于不同的处理器上。因此，智能驾驶场景下的进程间通信通常又称为核间通信。
在传统方法中，通常是基于套接字(socket)技术以及消息队列(Message Queue)技术来实现进程间通信。
其中，socket技术是网络中进程通信的常用方式，也能应用于同一个计算机系统中的进程间通信。如图1所示，图1为本申请实施例提供的一种基于socket技术的通信示意图。对于待通信的传输控制协议(Transmission Control Protocol，TCP)客户端以及TCP服务器端，TCP客户端和TCP服务器端分别建立一个socket对象。
TCP服务器端并不定位具体客户端的套接字，而是时刻处于监听状态。TCP客户端的套接字则需要描述TCP客户端所要连接的服务器的套接字，并提供地址和端口号；然后，TCP客户端向TCP服务器端的套接字提出连接请求。当TCP服务器端的套接字收到TCP客户端的套接字发来的连接请求后，响应TCP客户端的套接字的请求，并建立一个新的线程，把TCP服务器端的套接字的描述发给客户端。一旦TCP客户端确认TCP服务器端返回的描述，就正式建立连接。而TCP服务器端的套接字继续处于监听状态，继续接收其他客户端套接字的连接请求。
Message Queue是Linux中较为常用的通信技术之一。Message Queue技术通过在内核 建立一个消息队列，把进程放在用户态空间中消息缓冲区的数据拷贝到内核态，再拷贝到另一个进程的消息缓冲区，从而完成进程间的通信。如图2所示，图2为本申请实施例提供的一种基于Message Queue技术的通信示意图。
然而，socket技术以及Message Queue技术在通信过程中均涉及到数据的拷贝，通信效率较低。因此，目前主要采用共享内存的方式来实现进程间通信。基于共享内存的方式来进行通信，无需涉及数据的拷贝，通信效率高。
共享内存是当前效率最高的进程间通信方式。在基于共享内存进行通信的情况下，内存中的同一个物理地址被映射到不同进程的地址空间，通信中的两个进程异步读写该内存中相同的物理地址，从而实现数据的免拷贝通信。
一般来说，在通过共享内存进行通信的场景，通信中的多个进程在任意时刻访问的是共享内存中不同的内存段。但是，当软件在运行过程中发生错误时(例如软件发生了BUG)，通信中的一个进程可能会访问另一个进程正在使用的内存段，这就有可能破坏共享内存中的数据，从而导致系统宕机。在智能驾驶场景下，一旦出现这种情况，有可能会危害到人身安全。
此外，在大部分的进程间通信业务中，发送方进程所发送的数据被接收后，接收方进程会先进行数据的合法性检查。如果数据是合法的，则接收方进程再对数据进行处理。但是，在接收方进程对数据进行处理的过程中，如果发送方再次修改数据，则接收方进程无法再对数据的合法性进行检查，从而引入安全漏洞。在智能驾驶场景下，攻击方可以通过检查时间至使用时间(Time of check to time of use，TOCTTOU)攻击方式来攻击发送方进程。在发送方进程被攻击控制后，发送方进程会先发送一个合法的数据；接收方进程校验该数据为合法后，便会开始处理。此时，发送方进程可以通过修改数据的内容来进行攻击。
有鉴于此，本申请实施例提供一种进程间通信方法，需要基于共享内存进行通信的进程通过指令来获取共享内存的地址，并由该指令触发将获取的共享内存的地址加入过滤表中；在进程访问共享内存的地址时，触发查询过滤表，以确定进程是否具有访问共享内存的权限。并且，在进程成功访问共享内存后，在过滤表中释放进程的访问权限，从而保证进程不会因为软件错误或受到攻击而踩踏另一个进程正在使用的共享内存。
基于本实施例的方案，能够保证在软件发生错误或受到恶意攻击时，通信中的进程无法访问其他进程正在使用的内存段，从而避免出现共享内存中数据受到破坏而导致系统宕机的现象，保证了系统的正常运行。
具体地，本申请实施例所提供的进程间通信方法可以应用于电子设备上。示例性地，该电子设备例如可以是智能驾驶中的无线电子设备、服务器、智能手机(mobile phone)、个人电脑(personal computer，PC)、笔记本电脑、平板电脑、智慧电视、移动互联网设备(mobile internet device，MID)、可穿戴设备，虚拟现实(virtual reality，VR)设备、增强现实(augmented reality，AR)设备、工业控制(industrial control)中的无线电子设备、远程手术(remote medical surgery)中的无线电子设备、智能电网(smart grid)中的无线电子设备、运输安全(transportation safety)中的无线电子设备、智慧城市(smart city)中的无 线电子设备、智慧家庭(smart home)中的无线电子设备等。
为了便于叙述，以下将以本申请实施例提供的方法应用于智能驾驶中的无线电子设备上为例，对本申请实施例所提供的方法进行介绍。
为了便于理解本方案，本申请实施例中首先结合图3对本申请提供的智能驾驶场景下的车辆的结构进行介绍。请参阅图3，图3为本申请实施例提供的车辆100的一种结构示意图。
在一个实施例中，车辆100可以配置为完全或部分地自动驾驶模式。例如，车辆100可以在处于自动驾驶模式中的同时控制自身，并且可通过人为操作来确定车辆及其周边环境的当前状态，确定周边环境中的至少一个其他车辆的可能行为，并确定该其他车辆执行可能行为的可能性相对应的置信水平，基于所确定的信息来控制车辆100。在车辆100处于自动驾驶模式中时，可以将车辆100置为在没有和人交互的情况下操作。
车辆100可包括各种子系统，例如行进系统102、传感器系统104、控制系统106、一个或多个外围设备108以及电源110、计算机系统112和用户接口116。可选地，车辆100可包括更多或更少的子系统，并且每个子系统可包括多个元件，例如每个子系统包括多个ECU。另外，车辆100的每个子系统和元件可以通过有线或者无线互连。
行进系统102可包括为车辆100提供动力运动的组件。在一个实施例中，推进系统102可包括引擎118、能量源119、传动装置120和车轮/轮胎121。引擎118可以是内燃引擎、电动机、空气压缩引擎或其他类型的引擎组合，例如汽油发动机和电动机组成的混动引擎，内燃引擎和空气压缩引擎组成的混动引擎。引擎118将能量源119转换成机械能量。
能量源119的示例包括汽油、柴油、其他基于石油的燃料、丙烷、其他基于压缩气体的燃料、乙醇、太阳能电池板、电池和其他电力来源。能量源119也可以为车辆100的其他系统提供能量。
传动装置120可以将来自引擎118的机械动力传送到车轮121。传动装置120可包括变速箱、差速器和驱动轴。在一个实施例中，传动装置120还可以包括其他器件，比如离合器。其中，驱动轴可包括可耦合到一个或多个车轮121的一个或多个轴。
传感器系统104可包括感测关于车辆100周边的环境的信息的若干个传感器。例如，传感器系统104可包括定位系统122(定位系统可以是GPS系统，也可以是北斗系统或者其他定位系统)、惯性测量单元(inertial measurement unit，IMU)124、雷达126、激光测距仪128以及相机130。传感器系统104还可包括被监视车辆100的内部系统的传感器(例如，车内空气质量监测器、燃油量表、机油温度表等)。来自这些传感器中的一个或多个的传感器数据可用于检测对象及其相应特性(位置、形状、方向、速度等)。这种检测和识别是自主车辆100的安全操作的关键功能。
定位系统122可用于估计车辆100的地理位置。IMU 124用于基于惯性加速度来感测车辆100的位置和朝向变化。在一个实施例中，IMU 124可以是加速度计和陀螺仪的组合。
雷达126可利用无线电信号来感测车辆100的周边环境内的物体。在一些实施例中，除了感测物体以外，雷达126还可用于感测物体的速度和/或前进方向。
激光测距仪128可利用激光来感测车辆100所位于的环境中的物体。在一些实施例中，激光测距仪128可包括一个或多个激光源、激光扫描器以及一个或多个检测器，以及其他系统组件。
相机130可用于捕捉车辆100的周边环境的多个图像。相机130可以是静态相机或视频相机。
控制系统106为控制车辆100及其组件的操作。控制系统106可包括各种元件，其中包括转向系统132、油门134、制动单元136、计算机视觉系统140、路线控制系统142以及障碍物避免系统144。
转向系统132可操作来调整车辆100的前进方向。例如在一个实施例中可以为方向盘系统。
油门134用于控制引擎118的操作速度并进而控制车辆100的速度。
制动单元136用于控制车辆100减速。制动单元136可使用摩擦力来减慢车轮121。在其他实施例中，制动单元136可将车轮121的动能转换为电流。制动单元136也可采取其他形式来减慢车轮121转速从而控制车辆100的速度。
计算机视觉系统140可以操作来处理和分析由相机130捕捉的图像以便识别车辆100周边环境中的物体和/或特征。所述物体和/或特征可包括交通信号、道路边界和障碍物。计算机视觉系统140可使用物体识别算法、运动中恢复结构(Structure from Motion，SFM)算法、视频跟踪和其他计算机视觉技术。在一些实施例中，计算机视觉系统140可以用于为环境绘制地图、跟踪物体、估计物体的速度等等。
路线控制系统142用于确定车辆100的行驶路线。在一些实施例中，路线控制系统142可结合来自传感器138、GPS 122和一个或多个预定地图的数据以为车辆100确定行驶路线。
障碍物避免系统144用于识别、评估和避免或者以其他方式越过车辆100的环境中的潜在障碍物。
当然，在一个实例中，控制系统106可以增加或替换地包括除了所示出和描述的那些以外的组件。或者也可以减少一部分上述示出的组件。
车辆100通过外围设备108与外部传感器、其他车辆、其他计算机系统或用户之间进行交互。外围设备108可包括无线通信系统146、车载电脑148、麦克风150和/或扬声器152。
在一些实施例中，外围设备108提供车辆100的用户与用户接口116交互的手段。例如，车载电脑148可向车辆100的用户提供信息。用户接口116还可操作车载电脑148来接收用户的输入。车载电脑148可以通过触摸屏进行操作。在其他情况中，外围设备108可提供用于车辆100与位于车内的其它设备通信的手段。例如，麦克风150可从车辆100的用户接收音频(例如，语音命令或其他音频输入)。类似地，扬声器152可向车辆100的用户输出音频。
无线通信系统146可以直接地或者经由通信网络来与一个或多个设备无线通信。例如，无线通信系统146可使用3G蜂窝通信，例如CDMA、EVD0、GSM/GPRS，或者4G蜂窝 通信，例如LTE。或者5G蜂窝通信。无线通信系统146可利用WiFi与无线局域网(wireless local area network，WLAN)通信。在一些实施例中，无线通信系统146可利用红外链路、蓝牙或ZigBee与设备直接通信。其他无线协议，例如各种车辆通信系统，例如，无线通信系统146可包括一个或多个专用短程通信(dedicated short range communications，DSRC)设备，这些设备可包括车辆和/或路边台站之间的公共和/或私有数据通信。
电源110可向车辆100的各种组件提供电力。在一个实施例中，电源110可以为可再充电锂离子或铅酸电池。这种电池的一个或多个电池组可被配置为电源为车辆100的各种组件提供电力。在一些实施例中，电源110和能量源119可一起实现，例如一些全电动车中那样。
车辆100的部分或所有功能受计算机系统112控制。计算机系统112可包括至少一个控制器113，控制器113执行存储在例如存储器114这样的非暂态计算机可读介质中的指令115。计算机系统112还可以是采用分布式方式控制车辆100的个体组件或子系统的多个计算设备。
控制器113可以是任何常规的处理器，诸如商业可获得的CPU。替选地，该处理器可以是诸如ASIC或其它基于硬件的处理器的专用设备。尽管图1功能性地图示了处理器、存储器、和在相同块中的计算机110的其它元件，但是本领域的普通技术人员应该理解该处理器、计算机、或存储器实际上可以包括可以或者可以不存储在相同的物理外壳内的多个处理器、计算机、或存储器。
例如，存储器可以是硬盘驱动器或位于不同于计算机110的外壳内的其它存储介质。因此，对处理器或计算机的引用将被理解为包括对可以或者可以不并行操作的处理器或计算机或存储器的集合的引用。不同于使用单一的处理器来执行此处所描述的步骤，诸如转向组件和减速组件的一些组件每个都可以具有其自己的处理器，所述处理器只执行与特定于组件的功能相关的计算。
在此处所描述的各个方面中，处理器可以位于远离该车辆并且与该车辆进行无线通信。在其它方面中，此处所描述的过程中的一些在布置于车辆内的处理器上执行而其它则由远程处理器执行，包括采取执行单一操纵的必要步骤。
在一些实施例中，数据存储装置114可包含指令115(例如，程序逻辑)，指令115可被处理器执行来执行车辆100的各种功能，包括以上描述的那些功能。存储器114也可包含额外的指令，包括向推进系统102、传感器系统104、控制系统106和外围设备108中的一个或多个发送数据、从其接收数据、与其交互和/或对其进行控制的指令。
除了指令115以外，数据存储装置114还可存储数据，例如道路地图、路线信息，车辆的位置、方向、速度以及其它这样的车辆数据，以及其他信息。这种信息可在车辆100在自主、半自主和/或手动模式中操作期间被车辆100和计算机系统112使用。
用户接口116，用于向车辆100的用户提供信息或从其接收信息。可选地，用户接口116可包括在外围设备108的集合内的一个或多个输入/输出设备，例如无线通信系统146、车车在电脑148、麦克风150和扬声器152。
计算机系统112可基于从各种子系统(例如，行进系统102、传感器系统104和控制系 统106)以及从用户接口116接收的输入来控制车辆100的功能。例如，计算机系统112可利用来自控制系统106的输入以便控制转向单元132来避免由传感器系统104和障碍物避免系统144检测到的障碍物。在一些实施例中，计算机系统112可操作来对车辆100及其子系统的许多方面提供控制。
可选地，上述这些组件中的一个或多个可与车辆100分开安装或关联。例如，数据存储装置114可以部分或完全地与车辆1100分开存在。上述组件可以按有线和/或无线方式来通信地耦合在一起。
可选地，上述组件只是一个示例，实际应用中，上述各个模块中的组件有可能根据实际需要增添或者删除，图1不应理解为对本申请实施例的限制。
在道路行进的自动驾驶汽车，如上面的车辆100，可以识别其周围环境内的物体以确定对当前速度的调整。所述物体可以是其它车辆、交通控制设备、或者其它类型的物体。在一些示例中，可以独立地考虑每个识别的物体，并且基于物体的各自的特性，诸如它的当前速度、加速度、与车辆的间距等，可以用来确定自动驾驶汽车所要调整的速度。
可选地，自动驾驶汽车车辆100或者与自动驾驶车辆100相关联的计算设备(如图1的计算机系统112、计算机视觉系统140、数据存储装置114)可以基于所识别的物体的特性和周围环境的状态(例如，交通、雨、道路上的冰、等等)来预测所述识别的物体的行为。可选地，每一个所识别的物体都依赖于彼此的行为，因此还可以将所识别的所有物体全部一起考虑来预测单个识别的物体的行为。车辆100能够基于预测的所述识别的物体的行为来调整它的速度。
换句话说，自动驾驶汽车能够基于所预测的物体的行为来确定车辆将需要调整到(例如，加速、减速、或者停止)什么稳定状态。在这个过程中，也可以考虑其它因素来确定车辆100的速度，诸如，车辆100在行驶的道路中的横向位置、道路的曲率、静态和动态物体的接近度等等。
除了提供调整自动驾驶汽车的速度的指令之外，计算设备还可以提供修改车辆100的转向角的指令，以使得自动驾驶汽车遵循给定的轨迹和/或维持与自动驾驶汽车附近的物体(例如，道路上的相邻车道中的轿车)的安全横向和纵向距离。
上述车辆100可以为轿车、卡车、摩托车、公共汽车、娱乐车、游乐场车辆、施工设备、电车、高尔夫球车以及火车等，本申请实施例不做特别的限定。
可以参阅图4，图4为本申请实施例提供的一种车辆内的计算机系统101的结构示意图。图4所示的计算机系统101用于执行本申请实施例所提供的进程间通信方法。计算机系统101包括处理器103，处理器103和系统总线105耦合。其中，处理器103可以用于实现图2所述的控制器的功能。处理器103可以是一个或者多个处理器，其中每个处理器都可以包括一个或多个处理器核。显示适配器(video adapter)107，显示适配器可以驱动显示器109，显示器109和系统总线105耦合。系统总线105通过总线桥111和输入输出(I/O)总线113耦合。I/O接口115和I/O总线耦合。I/O接口115和多种I/O设备进行通信，比如输入设备117(如：键盘，鼠标，触摸屏等)，多媒体盘(media tray)121,(例如，CD-ROM， 多媒体接口等)。收发器123(可以发送和/或接受无线电通信信号)，摄像头155(可以捕捉动态数字视频图像)和外部USB端口125。其中，可选地，和I/O接口115相连接的接口可以是USB接口。
其中，处理器103可以是任何传统处理器，包括精简指令集计算(“RISC”)处理器、复杂指令集计算(“CISC”)处理器或上述的组合。可选地，处理器可以是诸如专用集成电路(“ASIC”)的专用装置。可选地，处理器103可以是神经网络处理器或者是神经网络处理器和上述传统处理器的组合。
可选地，在本文所述的各种实施例中，计算机系统101可位于远离自动驾驶车辆的地方，并且可与自动驾驶车辆无线通信。在其它方面，本文所述的一些过程在设置在自动驾驶车辆内的处理器上执行，其它由远程处理器执行，包括采取执行单个操纵所需的动作。
计算机系统101可以通过网络接口129和软件部署服务器149通信。网络接口129是硬件网络接口，比如，网卡。网络127可以是外部网络，比如因特网，也可以是内部网络，比如以太网或者虚拟私人网络(VPN)。可选地，网络127还尅是无线网络，比如WiFi网络，蜂窝网络等。
硬盘驱动接口和系统总线105耦合。硬件驱动接口和硬盘驱动器相连接。系统内存135和系统总线105耦合。运行在系统内存135的数据可以包括计算机101的操作系统137和应用程序143。
操作系统包括Shell 139和内核(kernel)141。Shell 139是介于使用者和操作系统之内核(kernel)间的一个接口。shell是操作系统最外面的一层。shell管理使用者与操作系统之间的交互:等待使用者的输入,向操作系统解释使用者的输入,并且处理各种各样的操作系统的输出结果。
内核141由操作系统中用于管理存储器、文件、外设和系统资源的那些部分组成。直接与硬件交互，操作系统内核通常运行进程，并提供进程间的通信，提供CPU时间片管理、中断、内存管理、IO管理等等。
应用程序143包括数据处理相关程序147以及控制汽车自动驾驶相关的程序。其中，数据处理相关程序147用于分别对多个ECU的数据进行管理。计算机系统101通过执行数据处理相关程序147，可以实现图2所述的控制器的功能，即对多个ECU的数据进行管理，例如删除某个ECU中所存储的数据。
控制汽车自动驾驶相关的程序例如可以包括管理自动驾驶的汽车和路上障碍物交互的程序，控制自动驾驶汽车路线或者速度的程序，控制自动驾驶汽车和路上其他自动驾驶汽车交互的程序。应用程序143也存在于deploying server 149的系统上。
传感器153和计算机系统101关联。传感器153用于探测计算机系统101周围的环境。举例来说，传感器153可以探测动物，汽车，障碍物和人行横道等，进一步传感器还可以探测上述动物，汽车，障碍物和人行横道等物体周围的环境，比如：动物周围的环境，例如，动物周围出现的其他动物，天气条件，周围环境的光亮度等。
以上介绍了本申请实施例提供的进程间通信方法的应用场景，以下将详细介绍本申请 实施例提供的进程间通信方法的执行流程。可以参阅图5，图5为本申请实施例提供的一种进程间通信方法500的流程示意图。如图5所示，该进程间通信方法500包括以下的步骤501-505。
步骤501，获取来自于第一进程的第一指令，所述第一指令用于请求获取共享内存的地址，所述共享内存用于进程间通信。
本实施例中，第一进程可以是需要通过共享内存来实现进程间通信的任意一个进程。并且，第一进程也可以是进程间通信的任意一方。例如，第一进程可以为进程间通信的发送方进程，第一进程需要向接收方进程发送通信数据；第一进程也可以为进程间通信的接收方进程，第一进程需要接收发送方进程所发送的通信数据。
示例性地，在智能驾驶场景中，第一进程可以是传感器进程，负责获取传感器数据并将传感器数据发送给处理进程；第一进程也可以是处理进程，负责接收传感器数据通过共享内存传输的传感器数据，并根据传感器数据执行相应的处理操作。
在处理器为第一进程分配通信用的共享内存之后，处理器可以获取到来自于第一进程的第一指令，所述第一指令用于请求获取共享内存的地址，以便于第一进程往共享内存中写入数据或者读取共享内存中的数据。
可选的，在第一进程生成第一指令之前，第一进程可以请求分配共享内存，并且获得所分配的共享内存的信息。这样，第一进程可以基于所分配的共享内存的信息生成第一指令，以请求获取用于通信的共享内存的地址。
示例性地，假设第一进程需要与第二进程进行通信，处理器可以获取来自于所述第一进程的第四指令，所述第四指令用于请求分配用于进行进程间通信的内存。然后，处理器根据所述第四指令为所述第一进程分配所述共享内存，并向所述第一进程返回所述共享内存的标识。具体地，处理器可以根据所述第四指令在内存中指定一个内存段为共享内存，并为该共享内存分配一个唯一的标识，再将该共享内存的标识返回给第一进程和第二进程。这样，第一进程可以基于处理器所返回的共享内存的标识，生成第一指令，所述第一指令包括所述共享内存的标识，以请求获取所述共享内存的地址。
步骤502，根据所述第一指令向所述第一进程返回第一地址，并将所述第一地址添加至所述第一进程对应的过滤表中，所述第一地址为所述共享内存中的地址，所述过滤表用于存放第一进程能够访问的共享内存的地址。
在获取到来自于第一进程的第一指令之后，处理器则根据所述第一指令获取共享内存中的第一地址，并向所述第一进程返回所述第一地址，以供第一进程使用所述第一地址所对应的内存段来进行进程间通信。其中，所述第一地址可以为一个地址范围，用于指示共享内存中的一个内存段所对应的地址段。所述第一地址对应的内存段即为用于供第一进程进行进程间通信的内存。
示例性地，所述第一地址可以包括起始地址和结束地址，所述起始地址用于表示第一地址对应的内存段的起始地址，所述结束地址用于表示第一对应的内存段的结束地址；所述第一地址也可以是包括起始地址和地址偏移，所述地址偏移用于表示第一地址对应的内 存段的起始地址和结束地址之间的地址长度。
此外，处理器在获取到第一地址之后，处理器还将所述第一地址添加至第一进程对应的过滤表中。其中，所述过滤表是由处理器在第一进程需要进行进程间通信时所建立的，所述过滤表用于记录第一进程能够访问的地址，且所述过滤表中所记录的地址均为共享内存中的地址。即，对于过滤表中所记录的地址，第一进程具有访问过滤表中所记录的地址的权限；对于过滤表中没有记录的共享内存的地址，第一进程则不具有访问权限。
一般来说，假设第一进程与第二进程进行进程间通信，处理器为第一进程和第二进程所分配的共享内存通常会分为多个内存段，以供第一进程和第二进程同时访问共享内存中不同的内存段。因此，通过建立过滤表，并在过滤表中添加第一进程所请求的共享内存中的地址，可以记录第一进程具有访问权限的共享内存的地址。
步骤503，获取来自于所述第一进程的第二指令，所述第二指令包括所述第一地址，所述第二指令用于请求使用所述第一地址对应的存储空间。
在第一进程获取到处理器所返回的第一地址之后，第一进程则根据通信需要，生成第二指令。其中，所述第二指令包括所述地址，所述第二指令用于请求使用所述第一地址对应的存储空间，以基于所述第一地址对应的存储空间来实现进程间通信。
具体地，在第一进程为进程间通信的不同角色时，所述第二指令可以是具有不同作用的指令。
示例性地，在第一进程为发送方进程，第二进程为接收方进程的情况下，第一进程需要向第二进程传输数据，因此所述第二指令还包括第一数据，所述第二指令用于指示向所述第一地址对应的存储空间写入所述第一数据，所述第一数据为待传输给第二进程的数据。也就是说，第一进程在获取到第一地址之后，则基于所述第一地址和待传输给第二进程的第一数据，生成第二指令，以请求向共享内存中写入所述第一数据。
示例性地，在第一进程为接收方进程，第二进程为发送方进程的情况下，所述第一进程需要接收第二进程所传输的数据，因此所述第二指令具体用于指示读取所述第一地址对应的存储空间中的第二数据，所述第二数据为第二进程向所述第一进程传输的数据。也就是说，第一进程在获取到第一地址之后，基于第一地址生成用于请求访问第一地址对应的存储空间的第二指令，以读取第二进程通过第一地址对应的存储空间所传输的第二数据。
步骤504，基于所述第二指令中的第一地址为共享内存的地址，触发查询所述过滤表，并根据所述第一地址位于所述过滤表中，执行所述第二指令。
在处理器获取到第二指令之后，处理器可以识别到第二指令中的第一地址为用于进程间通信的共享内存中的地址。因此，为了避免第一进程踩踏到其他进程正在使用的内存段，处理器触发查询所述过滤表，通过判断第二指令中的第一地址是否位于过滤表中来确认第一进程是否具有访问第一地址的权限。
也就是说，在处理器在获取到访问某一个地址的指令并确定该地址为共享内存中的地址时，处理器则触发查询过滤表，以确定该地址是否位于过滤表中。如果该地址位于过滤 表中，则代表进程具有访问该地址的权限；如果该地址不位于过滤表中，则代表进程不具有访问该地址的权限。
由于所述第一地址位于所述过滤表中，因此处理器可以确定所述第一进程具有访问所述第一地址的权限，处理器执行来自于所述第一进程的第二指令。
示例性地，在第一进程为发送方进程，第二进程为接收方进程的情况下，所述第二指令中还包括第一数据，处理器根据所述第二指令向所述第一地址对应的存储空间写入所述第一数据，以便于第二进程从所述第一地址对应的存储空间获取第一进程所传输的第一数据。
示例性地，在第一进程为接收方进程，第二进程为发送方进程的情况下，所述处理器根据所述第二指令读取所述第一地址对应的存储空间中的第二数据，并向所述第一进程返回所述第二数据，以使得第一进程能够获取到第二进程所传输的第二数据。
步骤505，在执行所述第二指令后，在所述过滤表中删除所述第一地址。
在处理器执行完所述第二指令之后，处理器已经实现向第一地址对应的存储空间写入第一数据或者读取第一地址对应的存储空间中的第二数据，即第一进程已成功传输第一数据或读取第二数据，第一进程不需要再访问第一地址对应的存储空间。因此，处理器在执行完第二指令之后，将过滤表中的所述第一地址删除，从而使得第一进程不再具有访问第一地址的权限。
示例性地，处理器也可以是获取来自于所述第一进程的第五指令，所述第五指令用于指示所述第一地址对应的存储空间使用完毕。处理器根据所述第五指令，将所述过滤表中的第一地址删除。
这样一来，在过滤表中的第一地址被删除之后，如果第一进程由于bug或者受到攻击的原因而继续请求访问第一地址时，处理器可以根据过滤表中不具有第一地址而拒绝第一进程的请求，从而有效地避免第一进程踩踏其他进程正在使用的第一地址对应的存储空间。
本实施例中，需要基于共享内存进行通信的第一进程通过指令来获取共享内存的地址，并由该指令触发将获取的共享内存的地址加入过滤表中；在第一进程访问共享内存的地址时，触发查询过滤表，以确定第一进程是否具有访问共享内存的权限。并且，在第一进程成功访问共享内存后，在过滤表中释放第一进程的访问权限，从而保证进程不会因为软件错误或受到攻击而踩踏另一个进程正在使用的共享内存。
基于本实施例的方案，能够保证在软件发生错误或受到恶意攻击时，通信中的进程无法访问其他进程正在使用的内存段，从而避免出现共享内存中数据受到破坏而导致系统宕机的现象，保证了系统的正常运行。
简单来说，基于本实施例中所提供的过滤表过滤机制，处理器能够拒绝访问进程不具有访问权限的共享内存的地址，从而避免进程踩踏其他进程正在使用的共享内存中的内存段。
示例性地，在第一进程出现bug或者受到恶意攻击时，处理器获取来自于所述第一进程的第三指令，所述第三指令包括第二地址，所述第三指令用于请求使用所述第二地址对 应的存储空间。其中，所述第二地址为所述共享内存中的地址，所述第二地址与所述第一地址可以为相同的地址，所述第二地址与所述第一地址也可以为不同的地址。并且，所述第二地址并不位于过滤表中。即，处理器可以是并没有触发将第二地址添加至过滤表中；处理器也可以是在第一进程失去访问第二地址的访问权限之后，将第二地址从过滤表中删除。
基于所述第三指令中的第二地址为共享内存的地址，处理器触发查询所述过滤表，并根据所述第二地址不位于所述过滤表中，拒绝执行所述第三指令。
也就是说，在第一进程所请求访问的第二地址属于共享内存中的地址，且所述第二地址不位于所述过滤表时，处理器可以拒绝执行第一进程请求访问第二地址的指令，从而保证第一进程无法使用第二地址对应的存储空间，避免出现第一进程踩踏其他进程正在使用的存储空间的现象。
可选的，在步骤504中，为了使得处理器能够识别到第二指令中的第一地址为共享内存的地址，本实施例通过在页表项中添加标记，来指示属于共享内存中的地址。
由于进程所使用的地址均为虚拟地址，因此通常需要通过查找页表来将虚拟地址转换为内存空间中的物理地址，才能够确定虚拟地址所对应的真实的内存地址。其中，页表是一种特殊的数据结构，放在系统空间的页表区，存放虚拟地址与物理地址的对应关系。每一个进程都拥有一个对应的页表。在页表中，一段虚拟地址与其对应的物理地址称为一个页表项。通过在页表项中添加标记，可以指示页表项中的虚拟地址属于共享内存中的地址。
示例性地，可以参阅图6，图6为本申请实施例提供的一种页表项的结构示意图。如图6所示，页表项中包括保留位(reserved)，该保留位的长度为10位。此外，页表项中还包括其他的位，分别用于指示页表项中的虚拟地址、物理地址以及物理地址的读写权限等信息。在实际应用中，处理器可以通过将页表项的保留位中的某一位或者多位置位，来实现标记的添加。也就是说，对于某一个虚拟地址来说，如果该虚拟地址的页表项中的保留位的一位或多位被置位，则处理器可以确定该虚拟地址属于共享内存的地址。
具体地，在上述的方法500中，处理器可以在所述第一进程对应的页表项中添加标记，所述标记用于指示所述第一地址为用于进程间通信的共享内存的地址，所述页表项用于指示所述第一地址与所述第一地址对应的物理地址之间的映射关系，所述第一地址为虚拟地址。
其中，处理器可以是在为第一进程分配了所述共享内存之后，则在所述共享内存所包括的所有地址对应的页表项上添加标记，以指示所述共享内存中的地址是用于进程间通信的特定地址。处理器也可以是在获取到来自于第一进程的第一指令后，再在第一地址对应的页表项中添加标记，以指示第一地址是用于进程间通信的特定地址。
在获取到第二指令之后，处理器可以基于所述第二指令中的第一地址查找所述页表项，并根据所述页表项中的标记，确定所述第二指令中的第一地址为共享内存的地址。
也就是说，处理器在获取到一个地址之后，可以查找该地址的页表项，并通过确认该地址的页表项中的保留位是否被置位，来判断该地址是否为共享内存的地址。如果该地址 的页表项中的保留位被置位，则处理器可以确定该地址属于共享内存的地址；如果该地址的页表项中的保留位没有被置位，则处理器可以确定该地址不属于共享内存的地址。
可以理解的是，在第一进程与第二进程建立通信时，处理器会为第一进程和第二进程分配通信用的共享内存。在第一进程为发送方进程的情况下，在第一进程需要向第二进程传输数据时，第一进程则向处理器请求共享内存中的一段内存段的地址，以基于所请求的内存段来实现数据的传输。在第一进程为接收方进程的情况下，第一进程则需要向处理器请求共享内存中的一段内存段的地址，以读取第二进程写入至该内存段中的数据。
因此，为了使得处理器在获取到请求获取共享内存中的地址的指令时，处理器能够向进程返回共享内存中空闲的内存段的地址，本实施例中引入了用于记录共享内存使用情况的描述符。通过采用描述符来实时记录共享内存的使用情况，可以使得处理器能够在获取到请求获取共享内存中的地址的指令时，获知共享内存的使用情况，从而向进程返回有效的内存段的地址。
示例性地，在处理器为第一进程分配共享内存之后，第一进程生成的所述第一指令中包括所述共享内存的标识，所述第一指令用于请求获取所述共享内存的地址。处理器可以根据所述第一指令中的所述标识获取所述共享内存对应的描述符。其中，所述描述符可以是处理器在为所述第一进程分配所述共享内存之后建立的，所述描述符用于记录所述共享内存的使用情况。简单来说，处理器每次为需要进行通信的两个进程分配共享内存之后，则为所分配的共享内存建立一个描述符，以记录该共享内存的使用情况。
在获取到所述共享内存对应的描述符之后，处理器可以根据所述描述符的内容确定所述第一地址，并向所述第一进程返回所述第一地址。所述第一地址对应的存储空间为所述共享内存中待写入或待读取的存储空间。
也就是说，在第一进程为发送方进程时，处理器向第一进程返回第一地址，所述第一地址对应的存储空间为所述共享内存中待写入数据的存储空间。在第一进程为接收方进程时，处理器向第一进程返回第一地址，所述第一地址对应的存储空间则为所述共享内存中待读取数据的存储空间。
为了便于理解，以下将结合附图详细介绍描述符所记录的内容。
本实施例中，处理器为第一进程所分配的所述共享内存包括多个内存块，所述多个内存块被组织成用于供进程读写的环形队列。其中，所述共享内存对应的描述符对所述多个内存块中的每个内存块的状态进行记录与管理。具体地，所述描述符包括写入指针和读取指针，所述写入指针用于指示所述多个内存块中待写入的内存块在所述环形队列中的位置，所述读取指针用于指示所述多个内存块中待读取的内存块在所述环形队列中的位置。基于所述描述符中的写入指针以及读取指针，处理器可以快速确定用于供写入数据的内存块的地址以及用于供读取数据的内存块的地址。
示例性地，可以参阅图7，图7为本申请实施例提供的一种描述符的结构示意图。如图7所示，处理器所分配的共享内存被分为16个内存块，该16个内存块分别为内存块0- 内存块15。并且，该16个内存块被组织成环形队列，以供进程循环地写入数据或读取数据。
该共享内存对应的描述符中包括内存块大小、内存块数量、发送方虚拟地址、接收方虚拟地址、写入指针以及读取指针等内容。其中，共享内存所划分的16个内存块的大小是一样的，描述符中所记录的内存块大小例如可以为4千字节(Kilobyte，kB)。内存块数量则指示描述符对应的共享内存中所划分的内存块的数量，例如16。发送方虚拟地址与写入指针对应，写入指针指示了当前待写入数据的内存块在环形队列中的位置，发送方虚拟地址则指示了该待写入数据的内存块的地址，即发送方虚拟地址指示了处理器需要向发送方进程返回的虚拟地址。接收方虚拟地址与读取指针对应，读取指针指示了当前待读取数据的内存块在环形队列中的位置，接收方虚拟地址则指示了该待读取数据的内存块的地址，即读取方虚拟地址指示了处理器需要向读取方进程返回的虚拟地址。
例如，在图7中，写入指针指向了内存块3所在的位置，即指示了环形队列中当前待写入数据的内存块为内存块3；当发送方进程请求获取共享内存的地址时，处理器则可以向发送方进行返回内存块3的虚拟地址。此外，读取指针指向了内存块0所在的位置，即指示了环形队列中当前待读取数据的内存块为内存块0。
通过将共享内存中的多个内存块组织成环形队列，采用描述符记录环形队列中的内存块的状态，可以使得通信中的双方进程能够异步工作，即发送方进程和接收方进程同时访问共享内存中不同的内存块。
例如，发送方进程可以先依次往内存块0、内存块1和内存块2中写入需要传输给接收方进程的数据。然后，在发送方进程往内存块3写入数据的同时，接收方进程可以访问内存块0，以获取发送方进程写入至内存块0中的数据。这样，发送方进程按照环形队列中内存块的顺序依次写入数据，接收方进程则同样按照环形队列中内存块的顺序依次读取数据，从而实现发送方进程和接收方进程异步工作，提高通信的效率。此外，由于共享内存中的多个内存块被组织成环形队列，发送方进程可以循环地在环形队列中写入数据，从而实现共享内存的循环利用，节省通信开销。
可选的，在处理器执行完进程请求写入数据或读取数据的指令之后，处理器可以是更新描述符中的写入指针或读取指针，以便于在进程请求共享内存的地址时处理器能够向进程返回有效的地址。
示例性地，在第一进程为发送方进程的情况下，处理器在执行请求写入数据的所述第二指令后，更新所述描述符中的所述写入指针，以更新所述多个内存块中待写入的内存块在所述环形队列中的位置。同时，在写入指针更新的情况下，与写入指针对应的发送方虚拟地址也相应地进行更新。
在第一进程为接收方进程的情况下，处理器在执行请求读取数据的所述第二指令后，更新所述描述符中的所述读取指针，以更新所述多个内存块中待读取的内存块在所述环形队列中的位置。同时，在读取指针更新的情况下，与读取指针对应的接收方虚拟地址也相应地进行更新。
以图7为例，发送方进程请求获取共享内存的地址，处理器根据描述符的内容向发送方进程返回内存块3的地址；然后，处理器获取到来自于发送方进程的数据写入指令，并根据该数据写入指令向内存块3中写入数据。在处理器执行完该数据写入指令之后，处理器则更新描述符中的写入指针，将写入指针指向内存块4所在的位置，即指示了环形队列中当前待写入数据的内存块为内存块4。
又例如，接收方进程请求获取共享内存的地址，处理器根据描述符的内容向接收方进程返回内存块0的地址；然后，处理器获取到来自于接收方进程的数据读取指令，并根据该数据读取指令读取内存块0中的数据。在处理器执行完该数据读取指令之后，处理器则更新描述符中的读取指针，将读取指针指向内存块1所在的位置，即指示了环形队列中当前待读取数据的内存块为内存块1。
这样一来，处理器通过在进程请求共享内存的地址时，根据描述符中的写入指针或读取指针返回相应的地址，并且在执行完数据写入指令或数据读取指令之后，更新描述符中的写入指针或读取指针，则能够保证进程有序地在环形队列的多个内存块中写入数据或读取数据。
可选的，由于一个进程可能同时与多个其他的进程建立通信，因此该进程被分配有多个不同的共享内存，且每个共享内存均有对应的描述符。因此，为了便于对同一个进程对应的多个描述符进行管理，本实施例可以通过描述符表来存放同一个进程所对应的多个描述符的地址。
示例性地，在第一进程第一次与其他进程建立通信时，处理器可以为第一进程生成描述符表。这样，在第一进程与任意一个进程建立通信时，处理器则将第一进程与该进程对应的共享内存的描述符的地址添加至描述符表中。此外，描述符表中还可以包括描述符与共享内存的标识之间的对应关系，以便于后续处理器能够根据共享内存的标识确定相应的描述符。
例如，在处理器获取到来自于第一进程的第四指令时，处理器则根据所述第四指令生成所述共享内存对应的描述符，并将所述描述符的地址添加至所述第一进程对应的描述符表中。其中，用于请求分配用于进行进程间通信的内存。在处理器根据第四指令为第一进程分配共享内存之后，处理器还可以将该共享内存的标识添加至描述符表中，以建立所述描述符的地址与所述共享内存的标识之间的对应关系。
在处理器获取到包括有共享内存的标识的第一指令时，处理器可以根据所述第一指令中的标识，在第一进程对应的描述符表中获取所述标识对应的描述符的地址，所述描述符表用于存储所述第一进程对应的一个或多个描述符的地址。然后，处理器根据所述描述符的地址获取所述描述符。
例如，在第一进程对应的描述符表中包括4个描述符，分别为描述符0、描述符1、描述符2和描述符3；其中，描述符0、描述符1、描述符2和描述符3对应的共享内存的标识分别为标识0、标识1、标识2和标识3。那么，在处理器从第一进程获取到包括标识2的第一指令时，处理器则可以根据标识2在描述符表中确定描述符2的地址，从而获取到 描述符2。
以上详细介绍了通过将进程所请求的共享内存的地址加入过滤表，并在进程访问完共享内存后在过滤表中删除该共享内存的地址来实现对进程的访问控制。为了便于理解，以下将从发送方进程和接收方进程的角度，详细介绍如何通过指令来触发将共享内存的地址加入过滤表以及从过滤表中删除共享内存的地址。
本实施例中，通过在进程通信的过程中引入了新的四条指令来支持进程间的通信，并使得进程访问共享内存的行为能够得到控制，保证通信中的进程无法访问其他进程正在使用的内存段，从而避免出现共享内存中数据受到破坏而导致系统宕机的现象。
可以参阅图8，图8为本申请实施例提供的一种进程间通信方法800的流程示意图。如图8所示，该进程间通信方法800包括以下的步骤801-806。
步骤801，发送方进程生成请求(Acquire)指令。
在处理器为发送方进程和接收方进程分配了共享内存之后，发送方进程生成Acquire指令，以请求获取共享内存的地址。
在处理器获取到Acquire指令之后，处理器则向发送方进程返回共享内存中空闲的内存块的地址，并将该内存块的地址添加至发送方进程对应的过滤表中。也就是说，通过由发送方进程生成Acquire指令，来触发将发送方要访问的内存块的地址加入过滤表中，从而赋予发送方进程访问该内存块的地址的权限。
其中，在上述实施例中的第一进程为发送方进程的情况下，Acquire指令例如可以为上述实施例所述的第一指令。
步骤802，发送方进程生成数据写入指令。
在获取到处理器所返回的内存块的地址之后，发送方进程则生成包括该内存块的地址的数据写入指令，以指示向该内存块写入待传输给接收方进程的数据。
在处理器获取到数据写入指令之后，处理器根据数据写入指令中的地址为共享内存的地址，触发查询过滤表。并且，处理器根据数据写入指令中的地址位于过滤表中，执行该数据写入指令，从而将数据写入至内存块中。
其中，在上述实施例中的第一进程为发送方进程的情况下，数据写入指令例如可以为上述实施例所述的第二指令。
步骤803，发送方进程生成推进(Push)指令。
在数据写入指令执行完毕之后，发送方进程所传输的数据成功写入至共享内存的内存块中，因此发送方进程生成Push指令，以指示撤销发送方进程对该内存块的访问权限。
处理器根据Push指令，将发送方进程对应的过滤表中的所述内存块的地址删除，从而撤销发送方进程对该内存块的访问权限。
其中，在上述实施例中的第一进程为发送方进程的情况下，Push指令例如可以为上述实施例所述的第五指令。
步骤804，接收方进程生成弹出(Pop)指令。
在发送方进程将数据写入至共享内存的内存块之后，接收方进程生成Pop指令，以请 求获取共享内存的地址。
在处理器获取到Pop指令之后，处理器则向接收方进程返回共享内存中已写入数据的内存块的地址，并将该内存块的地址添加至接收方进程对应的过滤表中。也就是说，通过由接收方进程生成Pop指令，来触发将接收方要访问的内存块的地址加入过滤表中，从而赋予接收方进程访问该内存块的地址的权限。
其中，在上述实施例中的第一进程为接收方进程的情况下，Pop指令例如可以为上述实施例所述的第一指令。
步骤805，接收方进程生成数据读取指令。
在获取到处理器所返回的内存块的地址之后，接收方进程则生成包括该内存块的地址的数据读取指令，以指示向读取该内存块中由发送方进程所写入的数据。
在处理器获取到数据读取指令之后，处理器根据数据读取指令中的地址为共享内存的地址，触发查询过滤表。并且，处理器根据数据读取指令中的地址位于过滤表中，执行该数据读取指令，从而读取内存块中的数据并将所读取的数据返回给接收方进程。
其中，在上述实施例中的第一进程为接收方进程的情况下，数据读取指令例如可以为上述实施例所述的第二指令。
步骤806，接收方进程生成释放(Release)指令。
在数据读取指令执行完毕之后，接收方进程成功读取共享内存的内存块中的数据，因此接收方进程生成Release指令，以指示撤销接收方进程对该内存块的访问权限。
处理器根据Release指令，将接收方进程对应的过滤表中的所述内存块的地址删除，从而撤销接收方进程对该内存块的访问权限。
其中，在上述实施例中的第一进程为接收方进程的情况下，Release指令例如可以为上述实施例所述的第五指令。
总的来说，对于发送方进程，本实施例中通过Acquire指令来赋予发送方进程访问共享内存中内存块的权限，并通过Push指令来撤销发送方进程的访问权限。对于接收方进程，本实施例中通过Pop指令来赋予接收方进程访问共享内存中内存块的权限，并通过Release指令来撤销接收方进程的访问权限。
可以参阅图9，图9为本申请实施例提供的一种共享内存中的内存块的状态变化示意图。如图9所示，对于共享内存中的内存块，在数据未写入的情况下，内存块的状态为空闲(Free)状态。
在发送方进程生成Acquire指令之后，表示发送方进程要往内存块中写入数据，因此内存块的状态变化为发送活跃(TxActive)状态。
在发送方进程生成Push指令时，表示发送方进程已经成功将数据写入内存块，内存块中存储了发送方进程需要传输给接收方进程的数据，因此内存块的状态变化为忙碌(Busy)状态。
在接收方进程生成Pop指令时，表示接收方进程要读取内存块中的数据，因此内存块的状态变化为接收活跃(RxActive)状态。
在接收方进程生成Release指令时，表示接收方进程已经成功读取内存块中的数据，内存块中所存储的数据已经成功传输给接收方进程，因此内存块的状态变化为空闲(Free)状态。
也就是说，在内存块的状态再次变化为空闲状态之后，发送方进程可以继续往内存块中写入待传输的数据，并由接收方进程读取内存块中的数据，以此循环，实现进程间的通信。
为了便于理解，以下将结合具体例子详细介绍本申请实施例提供的进程间通信方法。
可以参阅图10，图10为本申请实施例提供的一种进程间通信的系统架构示意图。
在硬件设置上，用于处理进程的处理器上包括两个寄存器以及内存管理单元(Memory Management Unit，MMU)，且MMU中包括过滤器。
处理器中的一个寄存器用于存储描述符表在内存中的地址，处理器可以基于该寄存器的值获取到存储于内存中的描述符表；另一个寄存器则用于存储过滤表在内存中的地址，处理器可以基于该寄存器的值获取到存储于内存中的过滤表。
MMU是负责处理处理器的内存访问请求的计算机硬件。MMU的功能主要包括虚拟地址到物理地址的转换，即将进程请求访问的虚拟地址转换为内存中的物理地址。MMU中的过滤器则用于在获取到来自于进程的共享内存访问请求时，根据过滤表中的地址来确定进程是否具有访问共享内存中的地址的权限。如果进程具有访问共享内存中的地址的权限，则执行该进程的共享内存访问请求；如果进程不具有访问共享内存中的地址的权限，则拒绝执行该进程的共享内存访问请求，并上报异常。
在内存中，存储有每个进程对应的描述符表、过滤表以及描述符，并分配有供进程通信用的共享内存。其中，每个进程对应有一个描述符表，该描述符表用于存储该进程对应的所有描述符的地址；每个进程可以建立有一个或多个通信，每个通信均有对应的描述符，即每个进程对应有一个或多个描述符。并且，通信中的两个进程对应于同一个描述符。每个进程还对应有一个过滤表，该过滤表记录了该进程能够访问的共享内存的地址。
示例性地，可以参阅图11A，图11A为本申请实施例提供的一种描述符表的结构示意图。如图11A所示，描述符表寄存器1中存储了进程A的描述符表的地址，处理器基于描述符表寄存器1的值可以获取到进程A的描述符表。描述符表寄存器2中存储了进程B的描述符表的地址，处理器基于描述符表寄存器2的值可以获取到进程B的描述符表。
在进程A的描述符表中，记录了进程A对应的多个描述符的地址。并且，在进程A对应的多个描述符中，进程可以是作为通信中的发送方进程，也可以是作为通信中的接收方进程。例如，在进程A的描述符表中第0个描述符地址指示了进程A与进程B之间的通信所对应的描述符。
在进程B的描述符表中，同样记录了进程B对应的多个描述符的地址。并且，在进程B对应的多个描述符中，进程可以是作为通信中的发送方进程，也可以是作为通信中的接收方进程。例如，在进程B的描述符表中第2个描述符地址指示了进程A与进程B之间的通信所对应的描述符。
可以参阅图11B，图11B为本申请实施例提供的一种描述符的结构示意图。如图11A所示，过滤表中记录了多个虚拟地址，例如虚拟地址1、虚拟地址2和虚拟地址3。其中，每个虚拟地址均指示了一个虚拟地址的空间范围，即指示了一段内存段所对应的地址范围。
具体地，以下将介绍智能驾驶场景下的系统架构。可以参阅图12，图12为本申请实施例提供的一种智能驾驶场景下的系统架构示意图。
如图12所示，智能驾驶场景的系统架构包括发送方处理器、接收方处理器和物理内存。其中，发送方处理器是指运行发送方进程的处理器，接收方处理器是指运行接收方进程的处理器。
在发送方处理器中，包括MMU1、寄存器1和寄存器2。MMU1负责将来自于发送方进程的数据写入请求中的虚拟地址转换为物理地址。寄存器1中存储了发送方进程对应的描述符表1在物理内存中的地址。寄存器2中存储了发送方进程对应的过滤表1在物理内存中的地址。
在接收方处理器中，包括MMU2、寄存器3和寄存器4。MMU2负责将来自于接收方进程的数据读取请求中的虚拟地址转换为物理地址。寄存器3中存储了接收方进程对应的描述符表2在物理内存中的地址。寄存器4中存储了接收方进程对应的过滤表2在物理内存中的地址。
在物理内存中，分别存储了发送方进程对应的描述符表1和过滤表1，接收方进程对应的描述符表2和过滤表2，以及发送方进程和接收方进程共同对应的共享内存和描述符。其中，描述符表1和描述符表2中均指示了描述符的地址。描述符中则记录了共享内存中的多个内存块的使用情况。
可以参阅图13，图13为本申请实施例提供的一种进程间通信方法1300的流程示意图。如图13所示，该进程间通信方法1300包括以下的步骤1301-1316。
步骤1301，发送方处理器获取来自于发送方进程的Acquire指令。
在发送方处理器为发送方进程分配共享内存之后，发送方处理器将共享内存的标识存放于源寄存器1中。发送方进程可以基于源寄存器1中的共享内存的标识生成Acquire指令。该Acquire指令中包括共享内存的标识，该Acquire指令用于请求获取共享内存中的地址。
步骤1302，发送方处理器向发送方进程返回共享内存中目标内存块的地址。
发送方处理器根据描述符表寄存器获取到描述符表的物理地址，从而获取到发送方进程对应的描述符表。然后，发送方进程根据Acquire指令中共享内存的标识，确定描述符表中相应的描述符的地址，以获取到发送方进程对应的描述符。发送方进程再根据描述符中的写入指针确定目标内存块的地址，并将目标内存块的地址存放于目标寄存器中，以实现向发送方进程返回共享内存中目标内存块的地址。其中，该目标内存块即为共享内存中待写入数据的内存块。
步骤1303，发送方处理器将目标内存块的地址添加至过滤表1中。
发送方处理器根据过滤表寄存器获取到过滤表1的物理地址，从而获取到发送方进程对应的过滤表1。然后，发送方处理器将目标内存块的地址添加至过滤表1中。
步骤1304，发送方处理器获取来自于发送方进程的数据写入指令，该数据写入指令中包括目标内存块的地址以及待写入的数据。
步骤1305，发送方处理器根据数据写入指令中的地址为共享内存的地址，触发查询过滤表1，并且确认数据写入指令中的地址位于过滤表1中。
由于在发送方处理器为发送方进程分配共享内存时，发送方处理器将发送方进程中共享内存的地址所对应的页表项中的保留位置位，以指示共享内存的地址是专门用于进程间通信的。因此，发送方处理器根据数据写入指令中的地址对应的页表项被置位，即可确定数据写入指令中的地址为共享内存的地址，从而触发查询过滤表1。并且，发送方处理器可以确认数据写入指令中的地址位于过滤表1中。
步骤1306，发送方处理器执行数据写入指令，向共享内存中的目标内存块写入数据。
步骤1307，发送方处理器获取来自于发送方进程的Push指令。
在数据写入指令执行完毕之后，发送方进程所传输的数据成功写入至共享内存的内存块中，因此发送方进程生成Push指令，以指示撤销发送方进程对目标内存块的访问权限。
步骤1308，发送方处理器删除过滤表1中的目标内存块的地址。
此外，发送方处理器更新描述符中的写入指针，以使得写入指针指向目标内存块的下一个内存块。
步骤1309，接收方处理器获取来自于接收方进程的Pop指令。
在为发送方进程和接收方进程分配共享内存之后，接收方处理器将共享内存的标识存放于源寄存器2中。接收方进程可以基于源寄存器2中的共享内存的标识生成Pop指令。该Pop指令中包括共享内存的标识，该Pop指令用于请求获取共享内存中的地址。
步骤1310，接收方处理器向接收方进程返回共享内存中目标内存块的地址。
接收方处理器根据描述符表寄存器获取到描述符表的物理地址，从而获取到接收方进程对应的描述符表。然后，接收方进程根据Pop指令中共享内存的标识，确定描述符表中相应的描述符的地址，以获取到接收方进程对应的描述符。接收方进程再根据描述符中的读取指针确定目标内存块的地址，并将目标内存块的地址存放于目标寄存器中，以实现向接收方进程返回共享内存中目标内存块的地址。其中，该目标内存块即为共享内存中待读取数据的内存块。
步骤1311，接收方处理器将目标内存块的地址添加至过滤表2中。
接收方处理器根据过滤表寄存器获取到过滤表2的物理地址，从而获取到接收方进程对应的过滤表2。然后，接收方处理器将目标内存块的地址添加至过滤表2中。
步骤1312，接收方处理器获取来自于接收方进程的数据读取指令，该数据写入指令中包括目标内存块的地址。
步骤1313，接收方处理器根据数据读取指令中的地址为共享内存的地址，触发查询过滤表2，并且确认数据读取指令中的地址位于过滤表2中。
由于在接收方处理器为接收方进程分配共享内存时，接收方处理器将接收方进程中共享内存的地址所对应的页表项中的保留位置位，以指示共享内存的地址是专门用于进程间通信的。因此，接收方处理器根据数据写入指令中的地址对应的页表项被置位，即可确定数据读取指令中的地址为共享内存的地址，从而触发查询过滤表2。并且，接收方处理器可以确认数据读取指令中的地址位于过滤表2中。
步骤1314，接收方处理器执行数据读取指令，读取共享内存中的目标内存块中的数据。
步骤1315，接收方处理器获取来自于接收方进程的Release指令。
在数据读取指令执行完毕之后，接收方进程已经成功读取共享内存的内存块中的数据，因此接收方进程生成Push指令，以指示撤销接收方进程对目标内存块的访问权限。
步骤1316，接收方处理器删除过滤表2中的目标内存块的地址。
此外，接收方处理器更新描述符中的读取指针，以使得读取指针指向目标内存块的下一个内存块。
在图1至图13所对应的实施例的基础上，为了更好的实施本申请实施例的上述方案，下面还提供用于实施上述方案的相关设备。
具体可以参阅图14，图14为本申请实施例提供的一种电子设备1400的结构示意图，该电子设备1400包括：获取单元1401、处理单元1402和发送单元1403；所述获取单元1401，用于获取来自于第一进程的第一指令，所述第一指令用于请求获取共享内存的地址，所述共享内存用于进程间通信；所述发送单元1403，用于根据所述第一指令向所述第一进程返回第一地址，并将所述第一地址添加至所述第一进程对应的过滤表中，所述第一地址为所述共享内存中的地址，所述过滤表用于存放第一进程能够访问的共享内存的地址；所述获取单元1401，还用于获取来自于所述第一进程的第二指令，所述第二指令包括所述第一地址，所述第二指令用于请求使用所述第一地址对应的存储空间；所述处理单元1402，用于基于所述第二指令中的第一地址为共享内存的地址，触发查询所述过滤表，并根据所述第一地址位于所述过滤表中，执行所述第二指令；所述处理单元1402，还用于在执行所述第二指令后，在所述过滤表中删除所述第一地址。
在一种可能的实现方式中，所述第二指令还包括第一数据，所述第二指令用于指示向所述第一地址对应的存储空间写入所述第一数据，所述第一数据为待传输给第二进程的数据；所述处理单元1402，具体用于向所述第一地址对应的存储空间写入所述第一数据。
在一种可能的实现方式中，所述第二指令用于指示读取所述第一地址对应的存储空间中的第二数据，所述第二数据为第二进程向所述第一进程传输的数据；所述处理单元1402，具体用于读取所述第一地址对应的存储空间中的第二数据，并向所述第一进程返回所述第二数据。
在一种可能的实现方式中，所述获取单元1401，还用于获取来自于所述第一进程的第三指令，所述第三指令包括第二地址，所述第三指令用于请求使用所述第二地址对应的存储空间，所述第二地址为所述共享内存中的地址；所述处理单元1402，具体用于基于所述第三指令中的第二地址为共享内存的地址，触发查询所述过滤表，并根据所述第二地址不 位于所述过滤表中，拒绝执行所述第三指令。
在一种可能的实现方式中，所述处理单元1402，还用于在所述第一进程对应的页表项中添加标记，所述标记用于指示所述第一地址为用于进程间通信的地址，所述页表项用于指示所述第一地址与所述第一地址对应的物理地址之间的映射关系，所述第一地址为虚拟地址；所述处理单元1402，具体用于：基于所述第二指令中的第一地址查找所述页表项；根据所述页表项中的标记，确定所述第二指令中的第一地址为共享内存的地址。
在一种可能的实现方式中，所述第一指令包括所述共享内存的标识；所述处理单元1402，具体用于根据所述标识获取描述符，所述描述符用于记录所述共享内存的使用情况；所述发送单元1403，具体用于根据所述描述符确定所述第一地址，并向所述第一进程返回所述第一地址，所述第一地址对应的存储空间为所述共享内存中待写入或待读取的存储空间。
在一种可能的实现方式中，所述处理单元1402，具体用于：根据所述标识，在第一进程对应的描述符表中获取所述标识对应的描述符的地址，所述描述符表用于存储所述第一进程对应的一个或多个描述符的地址；根据所述描述符的地址获取所述描述符。
在一种可能的实现方式中，所述共享内存包括多个内存块，所述多个内存块构成用于供进程读写的环形队列；所述描述符包括写入指针和读取指针，所述写入指针用于指示所述多个内存块中待写入的内存块在所述环形队列中的位置，所述读取指针用于指示所述多个内存块中待读取的内存块在所述环形队列中的位置。
在一种可能的实现方式中，所述处理单元1402，具体用于：在执行所述第二指令后，更新所述描述符中的所述写入指针，以更新所述多个内存块中待写入的内存块在所述环形队列中的位置；或，在执行所述第二指令后，更新所述描述符中的所述读取指针，以更新所述多个内存块中待读取的内存块在所述环形队列中的位置。
在一种可能的实现方式中，所述获取单元1401，还用于获取来自于所述第一进程的第四指令，所述第四指令用于请求分配用于进行进程间通信的内存；所述处理单元1402，还用于根据所述第四指令为所述第一进程分配所述共享内存，并向所述第一进程返回所述共享内存的标识。
在一种可能的实现方式中，所述处理单元1402，还用于根据所述第四指令生成所述共享内存对应的描述符，并将所述描述符的地址添加至所述第一进程对应的描述符表中。
在一种可能的实现方式中，所述获取单元1401，还用于获取来自于所述第一进程的第五指令，所述第五指令用于指示所述第一地址对应的存储空间使用完毕；所述处理单元1402，还用于根据所述第五指令，将所述过滤表中的第一地址删除。
本申请实施例提供的进程间通信方法具体可以由电子设备中的芯片来执行，该芯片包括：处理单元和通信单元，处理单元例如可以是处理器，通信单元例如可以是输入/输出接口、管脚或电路等。该处理单元可执行存储单元存储的计算机执行指令，以使电子设备内的芯片执行上述图1至图13所示实施例描述的进程间通信方法。可选的，存储单元为芯片内的存储单元，如寄存器、缓存等，存储单元还可以是无线接入设备端内的位于芯片外部的存储单元，如只读存储器(read-only memory，ROM)或可存储静态信息和指令的其他类 型的静态存储设备，随机存取存储器(random access memory，RAM)等。
可以参阅图15，本申请还提供了一种计算机可读存储介质，在一些实施例中，上述图5所公开的方法可以实施为以机器可读格式被编码在计算机可读存储介质上或者被编码在其它非瞬时性介质或者制品上的计算机程序指令。
图15示意性地示出根据这里展示的至少一些实施例而布置的示例计算机可读存储介质的概念性局部视图，示例计算机可读存储介质包括用于在计算设备上执行计算机进程的计算机程序。
在一个实施例中，计算机可读存储介质1500是使用信号承载介质1501来提供的。信号承载介质1501可以包括一个或多个程序指令1502，其当被一个或多个处理器运行时可以提供以上针对图5描述的功能或者部分功能。因此，例如，参考图5中所示的实施例，步骤501-505的一个或多个特征可以由与信号承载介质1501相关联的一个或多个指令来承担。此外，图15中的程序指令1502也描述示例指令。
在一些示例中，信号承载介质1501可以包含计算机可读介质1503，诸如但不限于，硬盘驱动器、紧密盘(CD)、数字视频光盘(DVD)、数字磁带、存储器、ROM或RAM等等。
在一些实施方式中，信号承载介质1501可以包含计算机可记录介质1504，诸如但不限于，存储器、读/写(R/W)CD、R/W DVD、等等。在一些实施方式中，信号承载介质1501可以包含通信介质1505,诸如但不限于，数字和/或模拟通信介质(例如，光纤电缆、波导、有线通信链路、无线通信链路、等等)。因此，例如，信号承载介质1501可以由无线形式的通信介质1505(例如，遵守IEEE 802.15标准或者其它传输协议的无线通信介质)来传达。
一个或多个程序指令1502可以是，例如，计算机可执行指令或者逻辑实施指令。在一些示例中，计算设备的计算设备可以被配置为，响应于通过计算机可读介质1503、计算机可记录介质1504、和/或通信介质1505中的一个或多个传达到计算设备的程序指令1502，提供各种操作、功能、或者动作。
应该理解，这里描述的布置仅仅是用于示例的目的。因而，本领域技术人员将理解，其它布置和其它元素(例如，机器、接口、功能、顺序、和功能组等等)能够被取而代之地使用，并且一些元素可以根据所期望的结果而一并省略。另外，所描述的元素中的许多是可以被实现为离散的或者分布式的组件的、或者以任何适当的组合和位置来结合其它组件实施的功能实体。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显 示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器、随机存取存储器、磁碟或者光盘等各种可以存储程序代码的介质。

Claims (15)

  1. 一种进程间通信方法，其特征在于，包括：
    获取来自于第一进程的第一指令，所述第一指令用于请求获取共享内存的地址，所述共享内存用于进程间通信；
    根据所述第一指令向所述第一进程返回第一地址，并将所述第一地址添加至所述第一进程对应的过滤表中，所述第一地址为所述共享内存中的地址，所述过滤表用于存放第一进程能够访问的共享内存的地址；
    获取来自于所述第一进程的第二指令，所述第二指令包括所述第一地址，所述第二指令用于请求使用所述第一地址对应的存储空间；
    基于所述第二指令中的第一地址为共享内存的地址，触发查询所述过滤表，并根据所述第一地址位于所述过滤表中，执行所述第二指令；
    在执行所述第二指令后，在所述过滤表中删除所述第一地址。
  2. 根据权利要求1所述的方法，其特征在于，所述第二指令还包括第一数据，所述第二指令用于指示向所述第一地址对应的存储空间写入所述第一数据，所述第一数据为待传输给第二进程的数据；
    所述执行所述第二指令，包括：
    向所述第一地址对应的存储空间写入所述第一数据。
  3. 根据权利要求1所述的方法，其特征在于，所述第二指令用于指示读取所述第一地址对应的存储空间中的第二数据，所述第二数据为第二进程向所述第一进程传输的数据；
    所述执行所述第二指令，包括：
    读取所述第一地址对应的存储空间中的第二数据，并向所述第一进程返回所述第二数据。
  4. 根据权利要求1-3任意一项所述的方法，其特征在于，所述方法还包括：
    获取来自于所述第一进程的第三指令，所述第三指令包括第二地址，所述第三指令用于请求使用所述第二地址对应的存储空间，所述第二地址为所述共享内存中的地址；
    基于所述第三指令中的第二地址为共享内存的地址，触发查询所述过滤表，并根据所述第二地址不位于所述过滤表中，拒绝执行所述第三指令。
  5. 根据权利要求1-4任意一项所述的方法，其特征在于，所述方法还包括：
    在所述第一进程对应的页表项中添加标记，所述标记用于指示所述第一地址为用于进程间通信的地址，所述页表项用于指示所述第一地址与所述第一地址对应的物理地址之间的映射关系，所述第一地址为虚拟地址；
    所述基于所述第二指令中的第一地址为共享内存的地址，包括：
    基于所述第二指令中的第一地址查找所述页表项；
    根据所述页表项中的标记，确定所述第二指令中的第一地址为共享内存的地址。
  6. 根据权利要求1-5任意一项所述的方法，其特征在于，所述第一指令包括所述共享内存的标识；
    所述根据所述第一指令向所述第一进程返回第一地址，包括：
    根据所述标识获取描述符，所述描述符用于记录所述共享内存的使用情况；
    根据所述描述符确定所述第一地址，并向所述第一进程返回所述第一地址，所述第一地址对应的存储空间为所述共享内存中待写入或待读取的存储空间。
  7. 根据权利要求6所述的方法，其特征在于，所述根据所述标识获取描述符，包括：
    根据所述标识，在第一进程对应的描述符表中获取所述标识对应的描述符的地址，所述描述符表用于存储所述第一进程对应的一个或多个描述符的地址；
    根据所述描述符的地址获取所述描述符。
  8. 根据权利要求6或7所述的方法，其特征在于，所述共享内存包括多个内存块，所述多个内存块构成用于供进程读写的环形队列；
    所述描述符包括写入指针和读取指针，所述写入指针用于指示所述多个内存块中待写入的内存块在所述环形队列中的位置，所述读取指针用于指示所述多个内存块中待读取的内存块在所述环形队列中的位置。
  9. 根据权利要求8所述的方法，其特征在于，所述方法还包括：
    在执行所述第二指令后，更新所述描述符中的所述写入指针，以更新所述多个内存块中待写入的内存块在所述环形队列中的位置；
    或，在执行所述第二指令后，更新所述描述符中的所述读取指针，以更新所述多个内存块中待读取的内存块在所述环形队列中的位置。
  10. 根据权利要求6-9任意一项所述的方法，其特征在于，所述方法还包括：
    获取来自于所述第一进程的第四指令，所述第四指令用于请求分配用于进行进程间通信的内存；
    根据所述第四指令为所述第一进程分配所述共享内存，并向所述第一进程返回所述共享内存的标识。
  11. 根据权利要求10所述的方法，其特征在于，所述方法还包括：根据所述第四指令生成所述共享内存对应的描述符，并将所述描述符的地址添加至所述第一进程对应的描述符表中。
  12. 根据权利要求1-11任意一项所述的方法，其特征在于，所述在执行所述第二指令后， 在所述过滤表中删除所述第一地址，包括：
    获取来自于所述第一进程的第五指令，所述第五指令用于指示所述第一地址对应的存储空间使用完毕；
    根据所述第五指令，将所述过滤表中的第一地址删除。
  13. 一种电子设备，其特征在于，包括存储器和处理器；所述存储器存储有代码，所述处理器被配置为执行所述代码，当所述代码被执行时，所述电子设备执行如权利要求1至12任一项所述的方法。
  14. 一种计算机可读存储介质，其特征在于，包括计算机可读指令，当所述计算机可读指令在计算机上运行时，使得所述计算机执行如权利要求1至12中任一项所述的方法。
  15. 一种计算机程序产品，其特征在于，包括计算机可读指令，当所述计算机可读指令在计算机上运行时，使得所述计算机执行如权利要求1至12任一项所述的方法。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116107762A (zh) * 2023-04-11 2023-05-12 远江盛邦（北京）网络安全科技股份有限公司 内存分配方法、装置、电子设备和存储介质
CN116233520A (zh) * 2023-05-06 2023-06-06 海马云（天津）信息技术有限公司 传递和获取视频数据的方法及装置、服务器设备和存储介质

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107704325A (zh) * 2016-08-08 2018-02-16 北京百度网讯科技有限公司 用于进程间传输消息的方法和装置
CN110858162A (zh) * 2018-08-24 2020-03-03 华为技术有限公司 内存管理方法及装置、服务器
CN111914284A (zh) * 2020-09-30 2020-11-10 杭州未名信科科技有限公司 操作系统中进程地址空间隔离保护方法、装置及设备
US20200364100A1 (en) * 2019-05-14 2020-11-19 Microsoft Technology Licensing, Llc Memory abstraction for lock-free inter-process communication
CN112035272A (zh) * 2019-06-03 2020-12-04 华为技术有限公司 进程间通信的方法、装置以及计算机设备

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107704325A (zh) * 2016-08-08 2018-02-16 北京百度网讯科技有限公司 用于进程间传输消息的方法和装置
CN110858162A (zh) * 2018-08-24 2020-03-03 华为技术有限公司 内存管理方法及装置、服务器
US20200364100A1 (en) * 2019-05-14 2020-11-19 Microsoft Technology Licensing, Llc Memory abstraction for lock-free inter-process communication
CN112035272A (zh) * 2019-06-03 2020-12-04 华为技术有限公司 进程间通信的方法、装置以及计算机设备
CN111914284A (zh) * 2020-09-30 2020-11-10 杭州未名信科科技有限公司 操作系统中进程地址空间隔离保护方法、装置及设备

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116107762A (zh) * 2023-04-11 2023-05-12 远江盛邦（北京）网络安全科技股份有限公司 内存分配方法、装置、电子设备和存储介质
CN116233520A (zh) * 2023-05-06 2023-06-06 海马云（天津）信息技术有限公司 传递和获取视频数据的方法及装置、服务器设备和存储介质

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