WO2023051256A1

WO2023051256A1 - Dynamic latch, semiconductor chip, computing power board, and computing device

Info

Publication number: WO2023051256A1
Application number: PCT/CN2022/118830
Authority: WO
Inventors: 闫浩; 王磊; 赵安
Original assignee: 北京比特大陆科技有限公司
Priority date: 2021-09-30
Filing date: 2022-09-14
Publication date: 2023-04-06
Also published as: CN115911026A

Abstract

The present application provides a dynamic latch, a semiconductor chip, a computing power board, and a computing device. The dynamic latch comprises: a substrate; a transmission gate, disposed in a first region of the substrate; and a data output unit, disposed in a second region of the substrate and comprising a first inverter, an input end of the first inverter being connected to an output end of the transmission gate, wherein the first region is adjacent to the second region and oxide diffusion regions within the two regions are continuous. A source region of the first inverter is located on the side close to the first region in the second region, and a drain region of the first inverter is located on the side away from the first region in the second region. In a manufacturing manner for the semiconductor device, by means of the configuration that the source region of the first inverter in the dynamic latch is close to the transmission gate and the drain region is away from the transmission gate, the electric leakage caused by a parasitic transistor can be effectively reduced, so that it is ensured that the logic of the dynamic latch is correct.

Description

Dynamic latches, semiconductor chips, hashboards and computing equipment

technical field

The present application relates to the technical field of integrated circuits, and in particular to a dynamic latch, a semiconductor chip, a computing power board and a computing device.

Background technique

At present, in the field of integrated circuit technology, semiconductor devices (such as semiconductor chips) can be realized by CNOD (Continuous Oxide Diffusion, continuous oxide diffusion region), that is, the OD (Oxide Diffusion, oxide diffusion region) of each functional unit in the semiconductor device Diffusion zone) is continuous.

Dynamic latches can be used as registers for digital signals, and thus can be applied to semiconductor devices, such as semiconductor chips. However, in the aforementioned CNOD implementation, the dynamic latch will have a leakage problem, resulting in an abnormality of the dynamic latch.

application content

Based on this, the present application provides a dynamic latch, a semiconductor chip, a computing power board, and a computing device to solve the leakage problem of the dynamic latch.

In a first aspect, the present application provides a dynamic latch, and the dynamic latch includes:

Substrate;

a transmission gate disposed on the first region of the substrate;

The data output unit is arranged in the second area of the substrate and includes a first inverter; the input end of the first inverter is connected to the output end of the transmission gate; wherein, the first area adjacent to the second region and the oxide diffusion region in both regions is continuous;

Wherein, the source region of the first inverter is located on a side close to the first region in the second region, and the drain region of the first inverter is located in the second region away from the side of the first region.

In a second aspect, the present application provides a semiconductor chip, which includes one or more dynamic latches as described above.

In a third aspect, the present application also provides a hash board, which includes one or more semiconductor chips as described above.

In a fourth aspect, the present application also provides a computing device, which includes a power board, a control board, a connection board, a heat sink, and a plurality of computing power boards as described above; the power board is respectively connected to the control board, The connecting board, the radiator and each of the computing power boards; the control board is connected to the computing power board through the connecting board, and the radiator is arranged close to the computing power board.

In this application, the source region of the first inverter is designed to be located on the side close to the first region in the second region, and the drain region of the first inverter is located on the side far from the first region in the second region , which can effectively reduce the leakage caused by the parasitic transistor of the CNOD process.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present application more clearly, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application. Ordinary technicians can also obtain other drawings based on these drawings on the premise of not paying creative work.

Fig. 1 is a schematic diagram of a circuit structure of a dynamic latch in the prior art;

FIG. 2 is a schematic structural diagram of a dynamic latch in the prior art;

FIG. 3 is a schematic structural diagram of a dynamic latch provided by an embodiment of the present application;

FIG. 4 is a schematic structural diagram of a dynamic latch provided by another embodiment of the present application;

FIG. 5 is a schematic structural diagram of a dynamic latch provided by another embodiment of the present application;

FIG. 6 is a schematic structural diagram of a dynamic latch provided in another embodiment of the present application;

FIG. 7 is a schematic structural diagram of a dynamic latch provided by another embodiment of the present application;

FIG. 8 is a schematic structural diagram of a dynamic latch provided by another embodiment of the present application;

FIG. 9 is a schematic structural diagram of a semiconductor chip provided by an embodiment of the present application;

Fig. 10 is a schematic structural diagram of a computing power board provided by an embodiment of the present application;

FIG. 11 is a schematic structural diagram of a computing device provided by an embodiment of the present application.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

It should be understood that the terms used in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit the application. As used in this specification and the appended claims, the singular forms "a", "an" and "the" are intended to include plural referents unless the context clearly dictates otherwise.

It should also be understood that the terms "first", "second", "third", "fourth", etc. (if any) in the specification, claims or above drawings of the present application are used to distinguish similar objects , and are not necessarily used to describe a specific sequence or sequence, and cannot be interpreted as indicating or implying their relative importance or implicitly indicating the number of indicated technical features.

It should also be further understood that the term "and/or" (if present) used in the description of the present application and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, And includes these combinations.

FIG. 1 is a schematic diagram of a circuit structure of a dynamic latch in the prior art, and the dynamic latch includes a transmission gate and an inverter.

The transmission gate includes a parallel PMOS tube (ie, MTG1 in the figure) and an NMOS tube (ie, MTG2 in the figure). Specifically, the drain of the PMOS transistor is connected to the drain of the NMOS transistor, and the connection of the two drains is used as a data input node (ie, D in the figure); the source of the PMOS transistor is connected to the source of the NMOS transistor, and The connection of the two sources is used as a data storage node (that is, DYN in the figure); the gate of the PMOS transistor is connected to the clock signal (that is, CPN in the figure), and the gate of the NMOS transistor is connected to the clock signal (that is, CPP in the figure). ) connection, and the two clock signals are mutually inverse signals.

The inverter includes a PMOS transistor (ie, MDR1 in the figure) and an NMOS transistor (ie, MDR2 in the figure) connected in series. Specifically, both the gate of the PMOS transistor and the gate of the NMOS transistor are connected to the data storage node; the source of the PMOS transistor is connected to VDD (Voltage Drain Drain, drain voltage source), and the source of the NMOS transistor is connected to VSS (Voltage Source Source , source voltage source); the drain of the PMOS transistor is connected to the drain of the NMOS transistor, and the junction of the two drains is used as an inverting data output node (that is, QN in the figure).

Based on the aforementioned dynamic latch, when the D node has data input, when CPN is logic low level and CPP is logic high level, the data of D node is transmitted to QN node through DYN node for output; and when CPN is When the logic level is high and the CPP is logic low level, the DYN node can save the current data and transmit the saved data to the QN node for output, and this stage can be called the data holding stage. In addition, it can be understood that the data output by the QN node is opposite to the data output by the QYN node.

It can be seen from the foregoing discussion that dynamic latches are often applied to semiconductor devices, such as semiconductor chips, and current semiconductor devices often use CNOD implementations. Therefore, Figure 2 is a dynamic latch in the prior art. Schematic. It should be noted that MTG1-D in the figure represents the drain region of the PMOS transistor in the transmission gate, MTG1-S represents the source region of the PMOS transistor in the transmission gate, and MTG1-G represents the gate region of the PMOS transistor in the transmission gate. Others are similar and will not be described in detail; it still needs to be explained, and some connection relationships are shown in the figure, for example, the drain of the PMOS transistor in the transmission gate is connected to the drain of the NMOS transistor in the transmission gate through a connection point and a metal sheet, and the two The connection of the two drains is used as the data input node D, and other similarities are not described in detail, but all the connection relationships are not shown in the figure.

It can be seen from the figure that the two functional units of the transmission gate and the inverter are respectively arranged in two adjacent unit areas on the substrate (not shown), and the ODs of the two unit areas are continuous, that is, corresponding to the PMOS transistor OD (that is, the upper OD in the figure) is continuous, and the OD of the corresponding NMOS tube (that is, the lower OD in the figure) is also continuous. However, due to the implementation of CNOD, the functional unit is usually provided with pseudo polysilicon (poly in the figure) on the edge of the OD, that is, poly on Diffusion Edge (PODE) on the edge of the oxide, so PODE can also be Understand it as a pseudo gate.

Since the PODE will parasitic transistors, there are two parasitic transistors in the dynamic latch, as shown in the dotted box in the figure. For the convenience of discussion, the embodiment of the present application refers to the parasitic transistors described here as MPODE. Based on this, the inventors found that the MPODE has a leakage problem. When the dynamic latch is working in the data holding stage, the leakage of the MPODE will affect the data holding node DYN, resulting in an abnormality of the dynamic latch.

For this, please refer to FIG. 3 , which is a schematic structural diagram of a dynamic latch 10 provided by an embodiment of the present application. The dynamic latch 10 includes: a substrate (not shown); The transmission gate 11 of the first region A of the bottom; the data output unit (not completely shown in the figure) that is located at the second region B of the substrate, the data output unit includes the first inverter 12, the input of the first inverter 12 The terminal is connected to the output terminal of the transmission gate (not shown in the figure); wherein, the first region A is adjacent to the second region B and the oxide diffusion region (OD) in the two regions is continuous, wherein the first reverse The source regions (MDR1-S, MDR2-S) of the phasers 12 are located on the side close to the first region A in the second region B, and the drain regions (MDR1-D, MDR2-D) of the first inverters 12 ) is located on the side away from the first area A in the second area B.

Exemplarily, as mentioned above, the drain regions (MTG1-D, MTG2-D) of the transmission gates 11 are connected to the data input node D, and the source regions (MTG1-S, MTG2-S) of the transmission gates are provided with There is data storage node DYN.

Exemplarily, the drain regions (MDR1-D, MDR2-D) of the first inverter 12 in the data output unit are set on the side away from the first region A, and the source of the first inverter 12 The pole regions (MDR1-S, MDR2-S) are arranged on one side close to the first region A to separate the QN node from the DYN node, thereby reducing leakage from the QN node to the DYN node through the parasitic transistor MPODE.

It can be understood that in this case, MPODE still exists between the source region (MDR1-S, MDR2-S) of the first inverter 12 and the DYN node, which is the same as the principle of leakage from the QN node to the DYN node. Only when the data in the source regions (MDR1-S, MDR2-S) of the first inverter 12 and the data in the DYN node are reversed, the leakage will be caused, wherein the source regions of the first inverter 12 ( MDR1-S, MDR2-S) include the source (MDR1-S) of the PMOS transistor connected to VDD (Voltage Drain Drain, drain voltage source), and the NMOS connected to VSS (Voltage Source Source, source voltage source) The source of the tube (MDR2-S), VDD and VSS are always inverting during data storage and output, so only when VDD and DYN nodes are inverting or when VSS and DYN nodes are inverting Leakage is caused, for example, at a certain working moment, VDD=1, VSS=0, DYN=1, at this moment, the MPODE on the same side as the source (MDR2-S) of the NMOS transistor in the first inverter 12 will Leakage is performed, and the MPODE on the same side as the source (MDR1-S) of the PMOS tube in the first inverter 12 will not leak electricity. Only one MPODE will leak electricity during operation, thereby reducing the number of first inverters. 12 Leakage to transmission gate 11.

Please refer to FIG. 4 . FIG. 4 is a schematic structural diagram of a dynamic latch provided by another embodiment of the present application.

In some embodiments, at least one empty unit (FILL) for filling is provided between the transmission gate 11 and the data output unit.

Exemplarily, the empty unit (FILL) is used to indicate a functional unit without actual circuit function. It can be understood that the empty unit (FILL) in the embodiment of the present application is also set on the substrate. Therefore, in FIG. 4, the empty unit (FILL) ) is located between the pseudo polysilicon (that is, poly in the figure) and there is no electronic component or part of the electronic component in the empty cell (FILL).

Exemplarily, the empty cell (FILL) may be set in the first area on the side close to the second area, or in the second area on the side close to the first area, or in the first area and in the third area between the second area.

It can be understood that there is no element in the empty cell (FILL), so there is no leakage to the DYN node of the adjacent transmission gate, and the source regions (MDR1-S, MDR2-S) of the first inverter 12 are still It will leak to the DYN node, but because there is an empty cell (FILL) between the first inverter 12 and the DYN node, the leakage path changes from one MPODE leakage to two MPODE cascaded leakage, and the inversion signal is farther apart, And the resistance of the cascaded MPODE is larger, so as to reduce the leakage rate of the first inverter 12 to the DYN node.

It can be understood that, according to the above principle, the number of empty cells (FILL) provided between the transmission gate 11 and the data output unit is negatively correlated with the leakage rate.

Please refer to FIG. 5 in conjunction with the foregoing embodiments. FIG. 5 is a schematic structural diagram of a dynamic latch provided by another embodiment of the present application.

In some embodiments, the oxide diffusion region in the empty cell is connected to a predetermined voltage.

Exemplarily, a preset voltage can be added to an empty unit provided between the transmission gate 11 and the data output unit, and the preset voltage can effectively reduce leakage.

It is understandable that the MPODE will leak when the data on both sides is reversed, that is, a voltage difference is generated on both sides of the MPODE, resulting in the leakage of the MPODE, and the voltage difference is positively correlated with the leakage rate and the leakage power.

Exemplarily, a preset bias voltage is connected to the empty cell (FILL) to reduce the voltage difference between the two sides of the MPODE, thereby reducing the leakage power and reducing the leakage rate.

Exemplarily, at least two PN transistors may be used to form a bias circuit (not shown in the figure), so as to input the bias voltage output by the bias circuit into the empty unit (FILL). It can be understood that the bias voltage generated by the bias circuit is VDD/2, which can effectively reduce the voltage difference between the two sides of the MPODE, so as to achieve the purpose of reducing the leakage power and the leakage rate.

In some embodiments, the dynamic latch 10 further includes a diode unit 13; the diode unit 13 is disposed in a third region C of the substrate, and the third region C is located in the first region A and Between the second area B.

Exemplarily, a third area C is provided between the first area A and the second area B, and a diode unit 13 is provided in the third area C, and the diode unit 13 is used to reduce the transmission gate of the first inverter 12 through MPODE 11 leakage.

Exemplarily, regardless of whether the diode unit 13 is set forward or reverse, there will be a voltage drop in at least one working state, thus reducing the leakage of the first inverter 12 or the transmission gate 11 . Wherein, the forward setting may be, for example, that the first region A conducts to the second region B.

Please refer to FIG. 6 . FIG. 6 is a schematic structural diagram of a dynamic latch provided in another embodiment of the present application.

In some embodiments, the diode unit 13 includes a PMOS transistor and an NMOS transistor; the gate of the PMOS transistor is connected to the source of the PMOS transistor (not shown in the figure), and the gate of the NMOS transistor ( MDR4-G) is connected to the source (MDR4-S) of the NMOS transistor, and the source (MDR3-S) of the PMOS transistor is connected to the source (MDR4-S) of the NMOS transistor.

Exemplarily, the function of the diode unit 13 can be realized by two transistors, for example, the function of the diode unit 13 can be realized by the aforementioned PMOS transistor and NMOS transistor.

It can be understood that the diode unit 13 composed of PMOS transistors and NMOS transistors is not connected to the circuit of the dynamic latch 10, but is added on the substrate when the dynamic latch 10 is fabricated on the substrate, so as to Make at least one voltage drop between the two MPODEs to reduce the leakage of the first inverter 12 .

In some implementations, the drain of the PMOS transistor (MDR3-D) and the drain of the NMOS transistor (MDR4-D) of the diode unit 13 can be connected in idling.

In other embodiments, the drain of the PMOS transistor (MDR3-D) and the drain of the NMOS transistor (MDR4-D) of the diode unit may be connected to each other. Figure 6 only shows the case of empty connection, and the case of mutual connection is not shown in the figure.

In some embodiments, the drain region of the PMOS transistor and the drain region of the NMOS transistor are located on a side close to the first region in the third region; the source region of the PMOS transistor and the The source region of the NMOS transistor is located on a side close to the second region in the third region.

Exemplarily, as shown in FIG. 6, the drain (MDR3-D) of the PMOS transistor and the drain (MDR4-D) of the NMOS transistor of the diode unit 13 can be close to the first region A (such as the first region in FIG. 3 One side of A) is set, the source (MDR3-S) of the PMOS transistor of the diode unit is connected to the source (MDR4-S) of the NMOS transistor, and is arranged close to the second area B (as shown in the second area in Figure 3 On one side of B), it can be understood that the gates (MDR3-G, MDR4-G) of the PMOS transistor and the NMOS transistor are located at the source (MDR3-S, MDR4-S) and the drain (MDR3-D, MDR4-D ), by setting the diode unit 13, the leakage current from the first inverter 12 to the transmission gate 11 can be effectively reduced.

In some other implementation manners, the drain (MDR3-D) of the PMOS transistor and the drain (MDR4-D) of the NMOS transistor of the diode unit 13 can be arranged close to one side of the second region B, and the source of the PMOS transistor of the diode unit Pole (MDR3-S) is connected to the source (MDR4-S) of the NMOS transistor, and is arranged on the side close to the first region A. It can be understood that on the substrate, the source region (MDR3-S) of the diode unit 13 S, MDR4-S) and drain regions (MDR3-D, MDR4-D) are interchanged with the above-mentioned embodiments, and the functions realized by the diode unit 13 remain unchanged.

Please refer to FIG. 7 . FIG. 7 is a schematic structural diagram of a dynamic latch provided by another embodiment of the present application.

In some embodiments, the data output unit also includes a second inverter 14; the input of the second inverter 14 is connected to the output of the first inverter 12.

It can be understood that the connection between the input terminal of the second inverter 14 and the output terminal of the first inverter 12 is a circuit connection, and the corresponding connection relationship is not shown in FIG. 7 .

Exemplarily, after the data is output from the output terminal (QN node) of the first inverter 12, it enters the second inverter 14 for inversion processing, and the processed data can be latched at the output terminal of the second inverter 14 (Q node) or output the data through the output terminal (Q node). It can be understood that the data output by the second inverter 14 is inverted from the data output by the first inverter 12. Based on this, the second inverter The data at the output terminal (Q node) of the phaser 14 is in phase with the data latched at the DYN node.

For example, the data in the DYN node is 1, which is processed by the first inverter 12 and output to obtain data 0, and the output of the first inverter 12 is processed by the second inverter 14 to obtain data 1.

It can be understood that since the data in the QN node and the data in the DYN node are reversed, there is a voltage difference that causes leakage. After adding the second inverter 14 as shown in FIG. 7, the data in the Q node and the data in the DYN node In the same phase, the voltage difference is not much different or equal to 0, which can reduce the leakage of the first inverter 12 to the DYN node, thereby ensuring the correct logic of the DYN node.

Exemplarily, the second inverter 14 is added after the first inverter 12, and the data output by the first inverter 12 can be inverted, so as to meet the usage requirements in specific situations.

Exemplarily, the structure of the second inverter 14 is the same as that of the first inverter 12 .

It can be understood that, as shown in FIG. 7, in the design of the substrate, the second inverter 14 can be arranged between the transmission gate 11 and the first inverter 12, so as to reduce the transmission gate input from the first inverter 12. 11 leakage.

Please refer to FIG. 8 in conjunction with the foregoing embodiments. FIG. 8 is a schematic structural diagram of a dynamic latch provided by another embodiment of the present application. It can be understood that not all connection structures are shown in the figure.

In some embodiments, the source of the PMOS transistor in the first inverter 12 and the source of the PMOS transistor in the second inverter 14 are connected to the same drain voltage source; The source of the NMOS transistor in 12 and the source of the NMOS transistor in the second inverter 14 are connected to the same source voltage source.

It can be understood that, as shown in FIG. 7, the source (MDR1-S) of the PMOS transistor in the first inverter 12 and the source (MDR5-S) of the PMOS transistor in the second inverter 14 can be connected to the same A drain voltage source (VDD); and the source (MDR2-S) of the NMOS transistor in the first inverter 12 and the source (MDR6-S) of the NMOS transistor in the second inverter 14 are connected to the same Source Voltage Source (VSS). Through the above design, the manufacturing difficulty of the dynamic latch 10 can be effectively reduced.

Please refer to FIG. 8 in conjunction with the foregoing embodiments. FIG. 8 is a schematic structural diagram of a dynamic latch provided by another embodiment of the present application.

In some embodiments, the first inverter 12 and the second inverter 14 share a source region (MDR1-S, MDR2-S in the figure); the drain of the second inverter 14 The pole region is located on a side close to the first region in the second region, and the drain region of the first inverter 12 is located on a side away from the first region in the second region, The source region shared between the first inverter 12 and the second inverter 14 is located between the drain region of the first inverter and the drain region of the second inverter .

It can be understood that, as shown in FIG. 3 and FIG. 8 , the shared source region shown in FIG. 8 follows the source region of the first inverter 12 (MDR1-S, MDR2-S in the figure). In some other implementation manners, the source region of the second inverter 14 (such as MDR5-S and MDR6-S in FIG. 7 ) can be used to achieve the same effect, and will not be repeated here.

Exemplarily, in the design of the chip corresponding to the dynamic latch 10, the second inverter 14 may be located in the second area, and for the sake of size reduction, the second inverter 14 and the first inverter 12 can share one source region (MDR1-S, MDR2-S in the figure).

Exemplarily, the shared source region (MDR1-S, MDR2-S) may be located in the drain region (MDR1-D, MDR2-D) of the first inverter 12 and the drain region of the second inverter 14 (MDR5-D, MDR6-D), in order to reduce the difficulty of making the chip corresponding to the dynamic latch 10.

It can be understood that the drain regions (MDR5-D, MDR6-D) of the second inverter 14 can be connected to the data output interface for outputting data, and the Q node in the figure is used to indicate the data output of the second inverter port.

Exemplarily, the QN node is set on the side away from the first area in the second area, and in the case of sharing the source region, the Q node is set on the side close to the first area in the second area, understandably , the data in the QN node and the data in the DYN node are reversed, so there will be leakage, but the data in the Q node is reversed with the data in the QN node, that is, the data in the Q node and the data in the DYN node are in phase, It can effectively reduce the occurrence of electric leakage.

In some embodiments, the transmission gate includes a first clock signal input terminal and a second clock signal input terminal; the first clock signal input terminal is used for connecting the first clock signal, and the second clock signal input terminal is used for connected to the second clock signal, wherein the first clock signal and the second clock signal are opposite signals.

It can be understood that the transmission gate 11 is obtained by connecting two MOS transistors in parallel, and an input terminal of a clock signal is provided on each MOS transistor. Specifically, the transmission gate 11 includes a PMOS transistor and an NMOS transistor, wherein the PMOS transistor A first clock signal input terminal for receiving the first clock signal CPN is provided, and a second clock signal input terminal for receiving the second clock signal CPP is provided on the NMOS tube, and the first clock signal CPN and the second clock signal CPP are inverted For example, when the first clock signal CPN=1, the second clock signal CPP=0.

Exemplarily, the dynamic latch 10 can latch or output data through an input clock signal.

Please refer to FIG. 9 . FIG. 9 is a schematic structural diagram of a semiconductor chip 100 provided by an embodiment of the present application.

The present application also provides a semiconductor chip 100, wherein the semiconductor chip 100 includes one or more dynamic memories 10 as provided in the above-mentioned embodiments.

As shown in Figure 9, the semiconductor chip 100 also includes a control unit 110, one or more data operation units 120, wherein, the data operation unit 120 includes a control circuit 121, an operation circuit 122 and one or more dynamic memories 10, and the control circuit 121 Connected with the dynamic memory 10 and the operation circuit 122, the control circuit 121 is used to update the data in the dynamic memory 10, and obtain data from the dynamic memory 10, the operation circuit 122 can perform operations on the acquired data, and output to the control circuit 121 for output .

Please refer to FIG. 10 . FIG. 10 is a schematic structural diagram of a computing power board 200 provided by an embodiment of the present application.

As shown in FIG. 10 , the computing power board 200 includes one or more mounting portions of semiconductor chips 100 , and at least one mounting portion is installed with a semiconductor chip 100 to complete calculations on data.

Please refer to FIG. 11 , which is a schematic structural diagram of a computing device 300 provided by an embodiment of the present application.

The computing device 300 includes a power board 301, a connection board 302, a heat sink 303, a control board 304, and a plurality of computing power boards 200, wherein the power board 301 is respectively connected to the connection board 302, the control board 304, and the heat sink 303 and each of the computing power boards 200, the control board 304 is connected to the computing power board 200 through the connecting board 302, and the heat sink 303 is set close to the computing power board 200.

The above is only a specific embodiment of the application, but the scope of protection of the application is not limited thereto. Any person familiar with the technical field can easily think of various equivalents within the scope of the technology disclosed in the application. Modifications or replacements, these modifications or replacements shall be covered within the scope of protection of this application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

A kind of dynamic latch is characterized in that, comprises:

Substrate;

a transmission gate disposed on the first region of the substrate;

The data output unit is arranged in the second area of the substrate and includes a first inverter; the input end of the first inverter is connected to the output end of the transmission gate; wherein, the first area adjacent to the second region and the oxide diffusion region in both regions is continuous;

Wherein, the source region of the first inverter is located on a side close to the first region in the second region, and the drain region of the first inverter is located in the second region away from the side of the first region.
The dynamic latch according to claim 1, wherein at least one empty cell for filling is provided between the transmission gate and the data output unit.
The dynamic latch according to claim 2, wherein the oxide diffusion region in the empty cell is connected to a preset voltage.
The dynamic latch according to claim 1, wherein the dynamic latch further comprises a diode unit; the diode unit is arranged in a third region of the substrate, and the third region is located in the Between the first area and the second area.
The dynamic latch according to claim 4, wherein the diode unit includes a PMOS transistor and an NMOS transistor; the gate of the PMOS transistor is connected to the source of the PMOS transistor, and the gate of the NMOS transistor The pole is connected to the source of the NMOS transistor, and the source of the PMOS transistor is connected to the source of the NMOS transistor.
The dynamic latch according to claim 5, wherein the drain region of the PMOS transistor and the drain region of the NMOS transistor are located on a side close to the first region in the third region ; The source region of the PMOS transistor and the source region of the NMOS transistor are located on a side close to the second region in the third region.
The dynamic latch according to claim 1, wherein the data output unit further comprises a second inverter; the input terminal of the second inverter is connected to the output terminal of the first inverter connect.
The dynamic latch according to claim 7, wherein the first inverter and the second inverter share the same source region;

The drain region of the second inverter is located on a side close to the first region in the second region, and the drain region of the first inverter is located in the second region away from the first region. one side of the first region, the source region shared between the first inverter and the second inverter is located at the drain region of the first inverter and the second inverter between the drain regions.
The dynamic latch according to claim 7, wherein the source of the PMOS transistor in the first inverter and the source of the PMOS transistor in the second inverter are connected to the same drain voltage source ; The source of the NMOS transistor in the first inverter and the source of the NMOS transistor in the second inverter are connected to the same source voltage source.
The dynamic latch according to any one of claims 1-9, wherein the transmission gate comprises a first clock signal input terminal and a second clock signal input terminal;

The first clock signal input terminal is used to connect the first clock signal, and the second clock signal input terminal is used to connect the second clock signal, wherein the first clock signal and the second clock signal are opposite to each other phase signal.
A semiconductor chip, characterized by comprising one or more dynamic latches according to any one of claims 1-10.
A computing power board, characterized in that it comprises one or more semiconductor chips as claimed in claim 11.
A computing device, characterized in that it includes a power board, a control board, a connection board, a radiator, and a plurality of power boards according to claim 12; the power board is connected to the control board and the connection board respectively , the heat sink and each of the computing power boards; the control board is connected to the computing power boards through the connecting board, and the radiator is arranged close to the computing power boards.