WO2023046762A1 - Dispositif optoélectronique - Google Patents

Dispositif optoélectronique Download PDF

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Publication number
WO2023046762A1
WO2023046762A1 PCT/EP2022/076242 EP2022076242W WO2023046762A1 WO 2023046762 A1 WO2023046762 A1 WO 2023046762A1 EP 2022076242 W EP2022076242 W EP 2022076242W WO 2023046762 A1 WO2023046762 A1 WO 2023046762A1
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WO
WIPO (PCT)
Prior art keywords
waveguide
silicon
bridge
lll
semiconductor
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PCT/EP2022/076242
Other languages
English (en)
Inventor
Yu GUOMIN
Aaron John Zilkie
Andrew George Rickman
Original Assignee
Rockley Photonics Limited
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Publication date
Priority claimed from US17/848,328 external-priority patent/US20230090189A1/en
Application filed by Rockley Photonics Limited filed Critical Rockley Photonics Limited
Publication of WO2023046762A1 publication Critical patent/WO2023046762A1/fr

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/015—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction
    • G02F1/017—Structures with periodic or quasi periodic potential variation, e.g. superlattices, quantum wells
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/015—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction
    • G02F1/025—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction in an optical waveguide structure
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12035—Materials
    • G02B2006/12061—Silicon
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12035—Materials
    • G02B2006/12078—Gallium arsenide or alloys (GaAs, GaAlAs, GaAsP, GaInAs)
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12083—Constructional arrangements
    • G02B2006/12097—Ridge, rib or the like
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13—Integrated optical circuits characterised by the manufacturing method
    • G02B6/132—Integrated optical circuits characterised by the manufacturing method by deposition of thin films
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13—Integrated optical circuits characterised by the manufacturing method
    • G02B6/136—Integrated optical circuits characterised by the manufacturing method by etching

Definitions

  • the present invention relates to optoelectronic device and method of manufacturing an optoelectronic device.
  • Hybrid integration of lll-V semiconductor based electro-optical devices e.g., modulators
  • SOI silicon-on-insulator
  • Micro-transfer printing is therefore being considered as an alternative way to integrate lll-V semiconductor based devices with SOI wafer.
  • the lll-V semiconductor based device can be printed into a cavity on the SOI in the same orientation in which it was manufactured, and the alignment between the lll-V semiconductor based waveguide and the SOI waveguide is predetermined in the vertical direction (Z- di recti on).
  • the gap that exists between the lll-V semiconductor based waveguide and the SOI waveguide facets is filled with a filling material.
  • a filling material for example, as proposed in WO 2021/094473, the gap between the lll-V semiconductor based device and the silicon waveguide, having a thickness of around 1 pm, is filled with Benzocyclobutene.
  • the thickness of this filling material should be kept as small as possible so as to minimise the extent to which the light travels through it and experiences losses.
  • the present inventors have come to the realisation that there should be a minimum depth of this filling material. This is due to their insights into the growth of the filling material, and specifically that 1) if the gap is too narrow defects (e.g. voids) form within the filling material; and 2) there is no optical confinement in the filling material in the lateral direction (perpendicular to the light propagation direction) which decrease the efficiency of optical coupling between the SOI waveguide and the lll-V semiconductor based device.
  • the gap is too narrow defects (e.g. voids) form within the filling material.
  • embodiments of the invention provide an optoelectronic device, the optoelectronic device including: a silicon platform, including a silicon waveguide and a cavity, wherein a bed of the cavity is provided at least in part by a buried oxide layer; a lll-V semiconductor-based optoelectronic component, bonded to the bed of the cavity of the silicon platform; and a bridge-waveguide, located between the silicon waveguide and the lll-V semiconductor-based optoelectronic component.
  • the buried oxide layer may extend entirely beneath: the silicon waveguide; the lll-V semiconductor-based optoelectronic component, and the bridge-waveguide, so as to separate them from a silicon substrate.
  • the buried oxide layer may extend entirely beneath: the lll-V semiconductor-based optoelectronic component and the bridge-waveguide, so as to separate them from a silicon substrate.
  • the fabrication process as a single etch can be performed do define the cavities.
  • the bridge-waveguide may have a thickness, as measured in a direction from the silicon waveguide to the lll-V semiconductor-based optoelectronic component, of at least 10 pm. It has been ascertained by the inventors that this minimum thickness ensures that the bridgewaveguide can be formed substantially or entirely defect free.
  • the bridge-waveguide may comprise amorphous silicon.
  • the bridge-waveguide may have a thickness of at least 11 m, at least 12pm, at least 13pm, at least 14pm, at least 15pm, or at least 20 pm.
  • the bridge-waveguide may have a thickness of no more than 20 pm, no more than 15 pm, no more than 14 pm, no more than 13pm, no more than 12 pm, or no more than 11 pm.
  • the thickness of the bridge-waveguide may be in a range of from 10 pm to 20pm.
  • the bridge-waveguide may have a thickness of 10 pm or substantially 10 pm.
  • the lll-V semiconductor-based optoelectronic component includes an antireflective coating located adjacent to the bridge-waveguide.
  • the anti-reflective coating may include plural layers.
  • the plural layers may be silicon based. They may include: a first silicon dioxide layer, a silicon nitride layer, and a second silicon dioxide layer, wherein the silicon nitride layer is interposed between the first silicon dioxide layer and the second silicon dioxide layer.
  • the first and second silicon dioxide layers may have a thickness, measured in the same direction as the bridge-waveguide thickness of at least 90 nm and no more than 100 nm.
  • the first silicon dioxide layer which may be the one closest to the bridge-waveguide, may have a thickness of 90 nm.
  • the second silicon dioxide layer which may be the one furthest from the bridge-waveguide, may have a thickness of 100 nm.
  • the silicon nitride layer may have a thickness of 140 nm.
  • the lll-V semiconductor-based optoelectronic component may include an isolation layer, and the anti-reflective coating may extend from the isolation layer up a lateral facet of the lll-V semiconductor-based optoelectronic component.
  • the lll-V semiconductor-based optoelectronic component may include a T-bar interface between the lll-V semiconductor-based optoelectronic component and the bridgewaveguide.
  • the bridge-waveguide may include a T-bar interface between the bridge-waveguide and the lll-V semiconductor-based optoelectronic component.
  • the lll-V semiconductor-based optoelectronic component may include a waveguide, which may be butt coupled to the bridge-waveguide. There may, or may not, be an antireflective coating between the bridge-waveguide and the waveguide of the lll-V semiconductor-based optoelectronic component.
  • the silicon waveguide may be butt coupled to the bridge- waveguide. There may, or may not, be an antireflective coating between the silicon waveguide and the bridge-waveguide.
  • An interface between the lll-V semiconductor-based optoelectronic component and the bridge-waveguide is angled relative to a transmission direction of light through the bridgewaveguide.
  • the angle is greater than 0°.
  • the angle may be less than 20°.
  • the angle may be, for example, 10°.
  • the bridge-waveguide may include a tapered region, tapering form a first width proximal to the lll-V semiconductor-based optoelectronic component to a second width proximal to the silicon waveguide, wherein the first width is smaller than the second width.
  • the widths may be measured in a direction perpendicular to the guiding direction of the bridge-waveguide and/or silicon waveguide.
  • the first width may have a value of equal to or less than 0.5 pm.
  • the second width may have a value of at least 0.5 pm and/or no more than 2.6 pm.
  • the silicon waveguide may include a tapered region, tapering from a first width proximal to the bridge-waveguide to a second width distal to the bridge-waveguide, wherein the first width is smaller than the second width.
  • the widths may be measured in a direction perpendicular to the guiding direction of the bridge-waveguide and/or silicon waveguide.
  • the first width may have a value of at least 0.5 pm and/or less than 2.6 pm .
  • the second width may have a value of 2.6 pm.
  • a lower cladding layer for each of the lll-V semiconductor-based optoelectronic component, the bridge-waveguide, and the silicon waveguide may be provided by a shared insulator layer.
  • the shared insulator layer may be the buried oxide layer.
  • the height of the buried oxide layer may vary. That is, the height of the cavity may vary as a function of position within the cavity. By height, it may be meant a direction perpendicular to the guiding direction of the silicon waveguide, e.g. it may be a direction connecting an uppermost portion of a sidewall of the cavity to the bed of the cavity.
  • the buried oxide layer may be thinner in a cavity of the optoelectronic device containing a DFB laser, in that the height of the buried oxide layer may be lower relative to surrounding portions of the buried oxide layer.
  • the cooling of the laser can be improved as there is less buried oxide to insulate it from the bulk device.
  • the bridge-waveguide and the silicon waveguide may each include a respective slab region and ridge region.
  • the 11 l-V semiconductor based optoelectronic component may include a plurality of layers, and a bottommost layer which is adjacent to the bed of the cavity may have a height of no more than 0.3 pm.
  • embodiments of the invention provide a method of manufacturing an optoelectronic device, including steps of: bonding a 11 l-V semiconductor-based optoelectronic component to a bed of a cavity, wherein the bed of the cavity is provided at least in part by a buried oxide layer, the cavity being located in a silicon platform, such that there is a space between the 11 l-V semiconductor-based optoelectronic component and a sidewall of a cavity; and filling the space between the 11 l-V semiconductor-based optoelectronic component and the sidewall with a bridge-waveguide material.
  • the space between the 11 l-V semiconductor-based optoelectronic component and the sidewall of the cavity may have a thickness, as measured in a direction from the sidewall to the 11 l-V semiconductor-based optoelectronic component, of at least 10 pm.
  • the method may further include a step, after bonding the 11 l-V semiconductor-based optoelectronic component, of performing one or more further processing steps on the 11 l-V semiconductor-based optoelectronic component.
  • the one or more further processing steps may include one or more of the following: a waveguide etch; an isolation etch; a via opening etc; and a metallisation step.
  • the one or more further processing steps may include a waveguide patterning step, in which waveguides are simultaneously patterned in each of the lll-V semiconductor-based optoelectronic component, the bridge-waveguide material, and the silicon platform. By simultaneously patterning these, the subsequently etched waveguides are self-aligned and so optical loss when coupling between them is reduced.
  • the waveguides patterned in the bridge-waveguide material and the silicon platform may be etched simultaneously.
  • the bonding of the lll-V semiconductor-based optoelectronic components can be done in a ‘care-free’ manner in at least one dimension (e.g. the x-direction, which is perpendicular to the guiding direction of the various waveguides).
  • the bridge-waveguide(s) can be provided or formed with an alignment error of +/- 0.2 pm via stepper lithography. This can result in a coupling loss of around or less than 0.25 dB.
  • the lll-V semiconductor-based optoelectronic component may include a plurality of lll-V semiconductor layers.
  • the lll-V semiconductor-based optoelectronic component may include a waveguide.
  • the lll-V semiconductor-based optoelectronic component may be an electro-absorption modulator and may contain a multiple quantum well layer.
  • the lll-V semiconductor-based electro-absorption modulator may contain a waveguide which is straight, that is substantially uncurved.
  • the lll-V semiconductor-based optoelectronic component may be a laser, for example a distributed feedback laser and may contain a multiple quantum well layer and/or a grating layer.
  • the invention includes the combination of the aspects and preferred features described except where such a combination is clearly impermissible or expressly avoided.
  • the lll-V semiconductor-based optoelectronic component may include one or more electrical traces making electrical contact on respectively portions of the lll-V semiconductor-based optoelectronic component.
  • Figure 1 shows a top-down view of an optoelectronic device including both an EAM and a DFB laser;
  • Figures 2A - 2H show, respectively, section views of the device of Figure 1 along the lines A - H;
  • Figure 3 shows a silicon platform before the lll-V semiconductor-based optoelectronic component has been bonded to the bed of the cavity;
  • Figure 4 shows a top-down view of an EAM device coupon for use with the silicon platform of Figure 3;
  • Figures 5A and 5B show, respectively, section views of the device coupon of Figure 4 along the lines X and Y;
  • Figure 6 shows a top-down view of a DFB laser device coupon for use with the silicon platform of Figure 3;
  • Figures 7A and 7B show, respectively, section views of the device coupon of figure 6 along the lines X and Y;
  • Figure 8 shows a top-down view of a variant EAM device coupon for use with the silicon platform of Figure 3;
  • Figures 9A and 9B show, respectively, section views of the device coupon of Figure 8 along the lines X and Y;
  • Figure 10 shows a top-down view of a variant DFB laser device coupon for use with the silicon platform of Figure 3;
  • Figures 11A and 11 B show, respectively, section views of the device coupon of Figure 10 along the lines X and Y;
  • Figure 12 shows the structure of a EAM I a-Si waveguide interface
  • Figure 13 shows the structure of a DFB laser / a-Si waveguide interface
  • Figure 14 shows simulated optical modes in various portions of the optoelectronic device of Figure 1;
  • Figures 15A and 15B show top-down views of interfaces between an EAM and a-Si waveguide with and without T-bar interfaces formed in the a-Si waveguide;
  • Figure 16 is a plot of coupling loss against centre alignment horizontal shift for the interfaces in Figures 15A and 15B;
  • Figures 17A and 17B show top-down views of interfaces between a DFB laser and a-Si waveguide with and without T-bar interfaces formed in the a-Si waveguide;
  • Figure 18 is a plot of coupling loss against centre alignment horizontal shift for the interfaces in Figures 17A and 17B;
  • Figure 19 shows a fabrication process
  • Figures 20(i) - 20(viii) show various fabrication steps
  • Figure 21 shows a variant optoelectronic device
  • Figure 22 shows a section view along the line D of the optoelectronic device of Figure 21 ;
  • Figure 23 shows a further variation of the optoelectronic device of Figure 1 ;
  • Figure 24 shows a further variation of the optoelectronic device of Figure 1 ;
  • Figure 25 shows a variant fabrication process
  • Figures 26(i) - 26(xv) show various fabrication steps.
  • Figure 1 shows a top-down view of an optoelectronic device 100 including both a distributed feedback (DFB) laser 102 and an electro-absorption modulator (EAM) 118 which are provided as discrete lll-V semiconductor-based optoelectronic components integrated into a silicon platform which includes a silicon substrate 101 and buried oxide layer 103.
  • Figures 2A - 2H show, respectively, section views of the device of Figure 1 along the lines A - H.
  • the DFB laser includes a lll-V waveguide 104, which is coupled via an antireflective coating 120 to an a-Si waveguide.
  • the a-Si waveguide is around 1.8 pm tall, as measured from a buried oxide layer beneath the waveguide to a point distalmost from the buried oxide layer and comprises a slab region 108 and ridge or rib region 106 above the slab.
  • the ridge or rib region tapers in taper region 110 to increase in width in a direction away from the DFB laser.
  • the slab portion 108 has a height of around 0.2 pm, and so the ridge or ridge is around 1.6 pm tall.
  • the a-Si waveguide is coupled to a silicon waveguide 112, with a tapered region 114 at either end.
  • the taper regions of 110 and 114 form a taper that completes the optical mode transition from the 1.8 pm a-Si waveguide 106 to the silicon waveguide 112.
  • the silicon waveguide 112 is around 3.0 m tall, and carries light generated by the DFB on to the EAM 118.
  • This coupling is via a second a-Si waveguide located between the silicon waveguide 112 and the EAM 118.
  • the second contains a tapered upper ridge or rib which is atop a slab.
  • An end of the second a-Si waveguide adjacent to a first (input) facet of the EAM is provided with antireflective coating 120.
  • the EAM includes quantum well layer 132 as shown in Figure 2A cross-section.
  • the second (output) facet of the EAM is also provided with an antireflective coating, and couples light into a third a-Si waveguide having the same structure as the first.
  • light is coupled into a second silicon waveguide 128.
  • the second silicon waveguide in this example, is around 3 pm tall (as measured from the buried oxide layer to the uppermost surface, as shown in Figure 2A) with a 1.8 pm slab portion 124 on top of a 0.2 pm slab portion 126.
  • the quantum well layer 130 in DFB 102 extends through the slab portion of the lll-V waveguide.
  • the quantum well layer 132 in the EAM 118 is present only in the rib or ridge portion of the waveguide.
  • the section view in Figure 2D, along the line D in Figure 1 shows that a portion of the a-Si waveguide nearest to the EAM (in this example, but equally nearest to the DFB if the first a-Si is considered) has a rib or ridge region having a height from the buried oxide layer of around 1.8 pm.
  • a taper begins with a height of 1.2 pm and a width W1, which is less than or equal to 0.5 pm.
  • the total height of slab, rib or ridge, and taper is around 3 pm.
  • the taper increases in width, as shown in Figure 2F, to width W2, which has a value of at least 0.5 pm and no more than 2.6 pm.
  • the light is then coupled into the silicon waveguide, which has its own taper from width W3, between 0.5 pm and 2.6 pm to width W4, which is 2.6 pm.
  • the taper ceases as shown in Figure 2H, where the rib or ridge has width W4, where W1 ⁇ W2 ⁇ W3 ⁇ W4.
  • the DFB/a-Si waveguide mode coupling loss is 0.53 dB
  • the mode coupling loss between each a-Si/EAM waveguides is 0.8dB
  • the coupling loss of the antireflective coating 120 between each lll-V optoelectronic component waveguide facet and each a-Si waveguide facet is 0.003dB
  • the optical losses in the tapered waveguide(s) is 0.1 dB.
  • EPI structure for the DFB laser is shown in Table 1 below, and an example EPI structure for the EAM is shown in Table 2 below.
  • the same epitaxial structures may be kept with a reduced height of the InP bottom cladding layer to maximise the mode alignment efficiency.
  • FIG. 3 shows a silicon platform 300 before the lll-V semiconductor-based optoelectronic component(s) have been provided.
  • the silicon platform includes the silicon substrate 101 referred to previously, atop of which is an insulator layer 103 (in this example a buried oxide layer).
  • the insulator layer in this example has a height (as measured from the substrate to the device layer) of 400 nm.
  • Atop of the silicon device layer 302 is a hard mask (in this example formed of silicon dioxide).
  • the silicon device layer has a height, as measured from the insulator layer to the hard mask, of 3 pm.
  • a portion of the silicon device layer is removed to form cavity 306, the cavity having a bed 308 and sidewalls 310a and 310b.
  • the cavity is substantially square, and so two further sidewalls are present (not visible in this section view).
  • an ARC coating can be provided over the sidewalls.
  • Figure 4 shows a top-down view of an EAM device coupon for use with the silicon platform of Figure 3.
  • Figures 5A and 5B show, respectively, section views of the device coupon of Figure 4 along the lines X and Y.
  • the coupon in this example is finished, in that no further processing is required to the device coupon for the EAM device to function.
  • the coupon is attached via dielectric tether to a lll-V semiconductor (in this example, InP) substrate 416.
  • a release layer previously located between the coupon and the substrate has been removed, for example via a wet etch.
  • n-electrode 406 and p-electrode 410 In an upper region of the device coupon is n-electrode 406 and p-electrode 410.
  • the p- electrode sits atop waveguide 408.
  • the dielectric tether 402 does extend over these electrodes, however for the sake of clarity the electrodes are shown in the top-down view of Figure 4.
  • a dielectric 412 layer is used to isolate the EAM from the metal electrodes asides from dedicated vias therethrough.
  • the p-electrode contacts an upper p-doped layer, P-lll-V, of the device, whereas the n-electrode contacts a lower n-doped layer, N-lll-V.
  • the n-electrode extends from an upper surface of the device coupon down towards the InP substrate so as to contact the lower n-doped layer.
  • the n-electrode and p-electrode have a same height on the upper surface of the device coupon.
  • the device also includes an isolation layer 414 which is the lowermost portion of the device coupon.
  • Input and output facets of the device coupon are covered by antireflective coatings 404
  • Figure 6 shows a top-down view of a DFB laser device coupon for use with the silicon platform of Figure 3.
  • Figures 7A and 7B show, respectively, section views of the device coupon of figure 6 along the lines X and Y. Where it shares features with the EAM device coupon of Figure 4, like features are indicated by like reference numerals.
  • the DFB laser device coupon does not include an isolation layer. It does include a grating layer 702, located within the upper p- doped lll-V layer and spaced from the quantum well layer.
  • Figure 8 shows a top-down view of a variant EAM device coupon for use with the silicon platform of Figure 3.
  • Figures 9A and 9B show, respectively, section views of the device coupon of Figure 8 along the lines X and Y.
  • this device coupon is unfinished.
  • subsequent processing is required before it can be used.
  • the device coupon is merely a multi-layered stack with: a dielectric layer; a p-doped layer, P-lll-V; a quantum well layer; an n-doped layer, N-lll-V; and an isolation layer 414.
  • Figure 10 shows a top-down view of a variant DFB laser device coupon for use with the silicon platform of Figure 3.
  • Figures 11A and 11 B show, respectively, section views of the device coupon of Figure 10 along the lines X and Y. Where it shares features with the unfinished DFB laser device coupon of Figure 6, like features are indicated by like reference numerals. In contrast to the device coupon in Figure 6, this device coupon is unfinished. Once printed, subsequent processing is required before it can be used. Specifically, no waveguides have been etched, and no metallisation process has been performed to provide electrodes.
  • the device coupon is merely a multi-layered stack with: a dielectric layer; a p-doped layer, P-lll-V; grating layer 702; a quantum well layer; and an n-doped layer, N-lll-V.
  • Figure 12 shows the structure of a EAM I a-Si waveguide interface in the finished optoelectronic device (e.g. after the MTP process has been performed) in more detail.
  • the anti-reflective coating present on the facet of the EAM lll-V device coupon is multi-layered in this example, and comprises: an inner silicon dioxide layer (in this example 100 nm in thickness); an intermediate silicon nitride layer (in this example formed of SiaN4 and having a thickness of 140 nm); and an outer silicon dioxide layer (in this example 90 nm in thickness).
  • the a-Si had a refractive index of 3.42, and a height as measured from the buried oxide layer of around 1800 nm.
  • the isolation layer extends underneath the anti- reflective coating, that is between the anti-reflective coating and the buried oxide layer on which the MTP has been bonded after printing.
  • Figure 13 shows the structure of a DFB laser I a-Si waveguide interface in the finished optoelectronic device (e.g. after the MTP process has been performed) in more detail.
  • the anti-reflective coating present on the facet of the DFB lll-V device coupon is multi-layered in this example, and comprises: an inner silicon dioxide layer (in this example 100 nm in thickness); an intermediate silicon nitride layer (in this example formed of SiaN4 and having a thickness of 140 nm); and an outer silicon dioxide layer (in this example 90 nm in thickness).
  • the a-Si had a refractive index of 3.42, and a height as measured from the buried oxide layer of around 1800 nm.
  • the lower n-doped layer extends underneath the anti-reflective coating, that is between the anti-reflective coating and the buried oxide layer on which the MTP has been bonded after printing..
  • Figure 14 shows simulated optical modes in various portions of the optoelectronic device of Figure 1 .
  • the upper pair show the optical modes in a a-Si waveguide and the adjacent SOI waveguide.
  • the mode coupling efficiency was found to be 99.28%, corresponding to mode mismatch loss of 0.003 dB.
  • the middle pair show the optical modes in a a-Si waveguide and adjacent EAM lll-V device coupon.
  • the mode coupling efficiency was found to be 83.5%, corresponding to a mode mismatch loss of 0.783 dB.
  • the lower pair show the optical modes in a a-Si waveguide and adjacent DFB lll-V device coupon.
  • the mode coupling efficiency was found to be 92.96%, corresponding to a mode mismatch loss of 0.317 dB.
  • Figures 15A and 15B show top-down views of interfaces between an EAM and a-Si waveguide with and without T-bar interfaces formed in the a-Si waveguide.
  • the EAM lll-V device coupon includes a T-bar interface adjacent to the a-Si waveguide.
  • the a-Si waveguide does not include a T-bar interface, and so has a width proximal to the lll-V device coupon which is smaller than the bar of the T-bar interface.
  • the T-bar interface in the lll-V device coupon has a thickness (as measured parallel to a guiding direction of the waveguides) of around 1 pm.
  • the lll-V waveguide in the lll-V device coupon has a width (as measured perpendicular to the guiding direction) of 2.5 pm.
  • the a-Si waveguide has a width (as measured perpendicular to the guiding direction) of 2.6 pm.
  • Figure 15B is the same arrangement, but where the a-Si waveguide also includes a 1 pm thick T-bar interface.
  • Figure 16 is a plot of simulated coupling loss against centre alignment horizontal shift for the interfaces in Figures 15A and 15B, (finite-difference time-domain simulation at 1311nm operating wavelength).
  • a-Si waveguide includes a T- bar interface perform worse than examples without a T-bar interface with respect to coupling losses. This is likely due to the optical mode in the T-bar expanding, and so there is an extra loss in waveguides containing a T-bar than in those without.
  • Figures 17A and 17B show top-down views of interfaces between a DFB laser and a-Si waveguide with and without T-bar interfaces formed in the a-Si waveguide.
  • the DFB lll-V device coupon includes a T-bar interface adjacent to the a-Si waveguide.
  • the a-Si waveguide does not include a T-bar interface, and so has a width proximal to the lll-V device coupon which is smaller than the bar of the T-bar interface.
  • the T-bar interface in the lll-V device coupon has a thickness (as measured parallel to a guiding direction of the waveguides) of around 1 pm.
  • the lll-V waveguide in the lll-V device coupon has a width (as measured perpendicular to the guiding direction) of 2.5 pm.
  • the a-Si waveguide has a width (as measured perpendicular to the guiding direction) of 2.6 pm.
  • Figure 15B is the same arrangement, but where the a-Si waveguide also includes a 1 pm thick T-bar interface.
  • Figure 18 is a plot of simulated coupling loss against centre alignment horizontal shift for the interfaces in Figures 17A and 17B (finite-difference time-domain simulation at 1311nm operating wavelength). As can be seen, examples where the a-Si waveguide includes a T- bar interface perform worse than examples without a T-bar interface with respect to coupling losses.
  • Step 1902 shows a fabrication process. Steps 1902 - 1906 can be performed in parallel or in series, and in any order. Step 1902 corresponds to the preparation of the full DFB device coupon, which in itself includes the sub-steps of: etching one or more waveguides; etching a via or window for the n-electrode provision; opening a via or window for the p-electrode; a metallization step to provide the p- and n-electrodes; a coupon definition step (in which e.g. the outer periphery of the coupon is defined and etched); a facet processing step (in which the anti-reflective coating and any protection layers are provided); a tether provision step; and a release etch.
  • etching one or more waveguides etching a via or window for the n-electrode provision
  • opening a via or window for the p-electrode a metallization step to provide the p- and n-elect
  • Step 1904 corresponds to the preparation of the silicon platform, which in itself includes a step of etching the cavity through the SOI and/or partially through the buried oxide layer.
  • the etch into the cavity could be a single etch or it could be multiple etches, for example if different thicknesses of buried oxide layer are desired.
  • Step 1906 corresponds to the preparation of the full EAM device coupon, which in itself includes the sub-steps of: etching one or more waveguides; performing an isolation etch (in which, e.g., an area of a stack forming the EAM is removed so as to isolate the contact pad of one polarity from layers containing dopants of the opposite polarity); opening vias for the electrodes; a metallization step to provide the p- and n-electrodes; a coupon definition step (in which, e.g., the outer periphery of the coupon is defined and etched; a facet processing step (in which the anti-reflective coating and any protection layers are provided); a tether provision step; and a release etch.
  • an isolation etch in which, e.g., an area of a stack forming the EAM is removed so as to isolate the contact pad of one polarity from layers containing dopants of the opposite polarity
  • opening vias for the electrodes e.g
  • the isolation etch in some examples etches away, sometimes a circular area, around the stack for the p-contact pad, which completely removes the n-doped layer(s) in this area and so isolates the layers in the stack for the p- contact pad from the rest of the n-doped layers in the device (or vice versa). This is done so as to reduce the parasitic capacitance, which provides higher operating speeds.
  • step 1908 the process moves to step 1908 in which the EAM and DFB device coupons are micro-transfer printed into respective cavities in the silicon platform.
  • step 1910 a-Si is deposited to fill the gap between the device coupons and the SOI waveguides.
  • This a-Si is then partially etched in step 1912 to release strain in the material, and then planarized in step 1914 using a chemical-mechanical planarization process.
  • step 1916 the SOI layer and a-Si regions are etched to make the rib or ridge waveguides and tapered regions.
  • step S1918 the SOI layer and a-Si regions are etched again to make the 1.8 pm tall strip waveguides.
  • contact windows are opened to allow wire bonding.
  • Figures 20(i) - 20(viii) show various fabrication steps.
  • Figure 20(i) corresponds to step 1908, in which an EAM device coupon has been micro-transfer printed into a cavity of a silicon platform.
  • the buried oxide layer has a uniform height but in other examples the height of the buried oxide layer may vary. The height is measured from the surface of the substrate Si-Sub adjacent to the buried oxide to a surface of the buried oxide layer distalmost from the substrate.
  • the hard mask atop the SOI layer has a height which is the same as or higher than (as measured relative to the buried oxide layer) than the lll-V device coupon.
  • Figure 20(H) corresponds to step 1910, where a-Si has been bulk deposited (e.g.
  • Figure 20(iii) corresponds to step 1912, in which the a-Si outside of the cavity (e.g. in a direction laterally around the cavity) is etched away to release stress in the a-Si material.
  • Figure 20(iv) corresponds to step 1914, in which the a-Si is subjected to a planarization process (e.g. chemical-mechanical planarization). The uppermost surface of the a-Si after this process is aligned with the uppermost surface of the hard mask and/or lll-V device coupon.
  • Figure 20(v) shows a subsequent step in which the a-Si is etched so that the uppermost surface of it is aligned with the SOI device layer.
  • Figure 20(vi) corresponds to step 1916, showing a top-view and AB section view after the rib waveguide(s) and taper regions have been etched.
  • Figure 20(vii) corresponds to step 1918, showing a top-view and AB section view after the strip waveguide(s) have been etched.
  • Figure 20(viii) corresponds to step 1920, showing a top-view and AB section view after the contact window is opened.
  • Figure 21 shows a variant optoelectronic device.
  • the a-Si waveguides include T-bar interfaces as shown.
  • Figure 22 shows a section view along the line D of the optoelectronic device of Figure 21.
  • the T-bar interface can be seen resulting in a uniform height of the a-Si waveguide.
  • Figure 23 shows a further variation of the optoelectronic device of Figure 1. It differs form the optoelectronic device of Figure 1 in that the interfaces between the lll-V waveguide(s) and a-Si waveguide(s) are angled, for example relative to the guiding direction, to reduce back reflection. That is, the interface is angled relative to the x-direction, and can be angled at, for example, 10°. In this example, the interface between the DFB laser and the first a-Si waveguide, the interface between the second a-Si waveguide and the EAM, and the interface between the EAM and the third a-Si waveguides are angled.
  • Figure 24 shows a further variation of the optoelectronic device of Figure 1. It differs from the optoelectronic device both due to the angled interfaces discussed with respect to Figure 23, but also due to the a-Si waveguides not including any taper region. Instead, only the SOI waveguide is tapered. In some examples, the interfaces are not angled but the lack of taper in the a-Si is retained.
  • Step 25 shows a variant fabrication process. It differs from the fabrication process shown in Figure 19 in that the DFB and EAM device coupons are not fully prepared before they are bonded to the SOI platform. Steps 2500 - 2502 can be performed in parallel or in series, and in any order. Step 2500 corresponds to the partial preparation of the DFB device coupon, which in itself includes the sub-steps of: a coupon definition step (in which, e.g., the outer periphery of coupon is defined and etched); a facet processing step (in which the anti- reflective coating and any protection layers are provided); a tether provision step; and a release etch.
  • a coupon definition step in which, e.g., the outer periphery of coupon is defined and etched
  • a facet processing step in which the anti- reflective coating and any protection layers are provided
  • tether provision step in which the anti- reflective coating and any protection layers are provided
  • Step 2501 corresponds to the preparation of the silicon platform, which in itself includes a step of etching the cavity through the SOI and/or partially through the buried oxide layer.
  • Step 2502 corresponds to the partial preparation of the EAM device coupon, which in itself includes the sub-steps of: a coupon definition step (in which, e.g., the outer periphery of coupon is defined and etched); a facet processing step (in which the anti-reflective coating and any protection layers are provided); a tether provision step; and a release etch.
  • step 2503 the process moves to step 2503 in which the EAM and DFB device coupons are micro-transfer printed into respective cavities in the silicon platform.
  • step 2504 a-Si is deposited to fill the gap between the device coupons and the SOI waveguides.
  • This a-Si is then partially etched in step 2506 to release strain in the material, and then planarized in step 2508 using a chemical-mechanical planarization process.
  • step 2510 the SOI layer and a-Si regions are etched to make the rib or ridge waveguide and tapered regions, this etch having a depth of 1.2 pm.
  • step 2512 the waveguides to be provided in the device coupons, a-Si, and SOI are patterned (that is, a mask is provided and then selectively removed, for example by lithography, so as to define the waveguides that are self aligned).
  • the waveguide(s) in the DFB device coupon are etched in step 2514 and the waveguide(s) in the EAM device coupon are etched in step 2516.
  • the a -Si and SOI layer are etched 1.6 pm again to make the 1.8 pm tall strip waveguides in a -Si and 3.0 pm strip waveguide in SOI.
  • the n-electrode contact windows are then etched into both the DFB and EAM device coupons in step 2520.
  • An EAM isolation etch is then performed in step 2522, and contact windows opened in the DFB and EAM device for the p-electrodes.
  • a metallisation step is then performed in step 2526.
  • Figures 26(i) - 26(xv) show various fabrication steps.
  • Figure 26(i) corresponds to step 2503 in which an EAM device coupon has been micro-transfer printed into a cavity of a silicon platform.
  • the hard mask atop the SOI has a height which is the same as or higher than (as measured relative to the buried oxide) than the 11 l-V device coupon.
  • Figure 26(H) corresponds to step 2504 in which the a-Si is bulk deposited (e.g. via chemical vapour deposition).
  • Figure 26(iii) corresponds to step 2506 in which the a-Si outside of the cavity (e.g. in a direction laterally around the cavity) is etched away to release stress in the a-Si material.
  • Figure 26(iv) corresponds to step 2508, in which the a-Si is subjected to a planarization process (e.g. chemical-mechanical planarization). The uppermost surface of the a-Si after this process is aligned with the uppermost surface of the hard mask and/or III- V device coupon.
  • Figure 26(v) shows subsequent step in which the a-Si is etched so that the uppermost surface of it is aligned with the SOI device layer.
  • Figure 26(vi) corresponds to step 2510, showing a top-view and AB section view after the rib waveguide(s) and taper regions in the a-Si and SOI have been etched.
  • Figure 26(vii) corresponds to step 2512, in that a hard mask (in this example Sisl ⁇ ) is provided and patterned so as to define the waveguides in the lll-V device coupons, the a-Si and, and the SOI layer.
  • Figure 26(viii) corresponds to step 2514, wherein the DFB waveguide(s) are etched for the DFB laser.
  • Figure 26(ix) corresponds to step 2516, in which the SiO2 hard mask is stripped, re-deposited, and re-patterned to define the EAM waveguide(s).
  • Figure 26(x) corresponds to step 2518 in which the SiO2 is again stripped, redeposited, and re-patterned to define the a-Si and SOI strip waveguide(s).
  • Figure 26(xi) the hard mask is stripped once more, and the waveguide etching steps are therefore complete.
  • Figure 26(xii) corresponds to step 2520, in which the n-electrode contact windows are etched. This exposes the n-doped regions of the EAM and DFB device coupons, and the n-electrode seed metal is fabricated.
  • Figure 26(xiii) corresponds to step 2522 in which the p- contact isolation area is etched in the EAM device coupon.
  • Figure 26(xiv) corresponds to step 2524, wherein the p-electrode and n-electrode contact windows are opened in the EAM and DFB device coupons such that the p-doped regions and n-electrode seed metal of each are exposed.
  • Figure 26(xv) corresponds to step 2526, in which a metallization process is performed so that an n-electrode and p-electrode are provided which contact the respective doped regions.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Optical Integrated Circuits (AREA)

Abstract

L'invention concerne un dispositif optoélectronique. Le dispositif optoélectronique comprend : une plate-forme en silicium, comprenant un guide d'ondes en silicium et une cavité, un lit de la cavité étant prévu au moins en partie par une couche d'oxyde enterrée; un composant optoélectronique à base de semi-conducteurs III-V, lié à un lit de la cavité de la plate-forme de silicium; et un guide d'ondes en pont, situé entre le guide d'ondes en silicium et le composant optoélectronique à base de semi-conducteurs III-V.
PCT/EP2022/076242 2021-09-22 2022-09-21 Dispositif optoélectronique WO2023046762A1 (fr)

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US63/247,297 2021-09-22
US17/848,328 US20230090189A1 (en) 2021-09-22 2022-06-23 Optoelectronic device
US17/848,328 2022-06-23

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160274319A1 (en) * 2009-10-13 2016-09-22 Skorpios Technologies, Inc. Integration of an unprocessed, direct-bandgap chip into a silicon photonic device
WO2021094473A1 (fr) 2019-11-15 2021-05-20 Rockley Photonics Limited Dispositif optoélectronique et procédé de fabrication associé
GB2592282A (en) * 2020-06-09 2021-08-25 Rockley Photonics Ltd Optoelectronic device and method of manufacture thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160274319A1 (en) * 2009-10-13 2016-09-22 Skorpios Technologies, Inc. Integration of an unprocessed, direct-bandgap chip into a silicon photonic device
WO2021094473A1 (fr) 2019-11-15 2021-05-20 Rockley Photonics Limited Dispositif optoélectronique et procédé de fabrication associé
GB2592282A (en) * 2020-06-09 2021-08-25 Rockley Photonics Ltd Optoelectronic device and method of manufacture thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ZHANG JING ET AL: "III-V-on-Si photonic integrated circuits realized using micro-transfer-printing", APL PHOTONICS, AMERICAN INSTITUTE OF PHYSICS, 2 HUNTINGTON QUADRANGLE, MELVILLE, NY 11747, vol. 4, no. 11, 4 November 2019 (2019-11-04), XP012241950, DOI: 10.1063/1.5120004 *

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