WO2023046129A1 - 计算机设备、处理数据的方法及计算机系统 - Google Patents

计算机设备、处理数据的方法及计算机系统 Download PDF

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Publication number
WO2023046129A1
WO2023046129A1 PCT/CN2022/121181 CN2022121181W WO2023046129A1 WO 2023046129 A1 WO2023046129 A1 WO 2023046129A1 CN 2022121181 W CN2022121181 W CN 2022121181W WO 2023046129 A1 WO2023046129 A1 WO 2023046129A1
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Prior art keywords
processor
persistent
memory
data
management chip
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PCT/CN2022/121181
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English (en)
French (fr)
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侯宝臣
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超聚变数字技术有限公司
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Publication of WO2023046129A1 publication Critical patent/WO2023046129A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of computer technology, in particular to computer equipment, a data processing method and a computer system.
  • Persistent storage refers to a storage method that will not cause data loss due to power failure or restart of the device. How to store data persistently has become an urgent problem to be solved.
  • the application provides a computer device, a data processing method and a computer system to realize persistent storage of data, and the technical solution is as follows:
  • a computer device which includes: a processor, at least one management chip, and at least two persistent memories, at least two persistent memories connected to the processor through at least one management chip, and at least two persistent memories Each persistent memory in persistent memory is used for persistent storage of data.
  • at least one management chip is used to control the connection state between each persistent memory and the processor, and the processor is used to access any one of the at least two persistent memories connected to the processor.
  • the present application controls the connection state of the persistent memory and the processor through the management chip, so that the processor is connected with at least two persistent memories. Since the processor can access at least two persistent memories connected to the processor, and the persistent memory can be used for persistent storage of data, it not only expands the storage capacity for persistent storage of data, but also avoids In the case of insufficient storage capacity, a new method of persistently storing data is also provided, which is different from the method of persistently storing data only through disks in related technologies.
  • persistent memory also known as non-volatile memory (non-volatile memory, NVM)
  • non-volatile memory is used for persistent storage of data and is a storage that will not lose data due to power failure or restart of the device.
  • Media also called memory or storage hardware.
  • the processor can access the persistent memory through instructions, and the access process does not involve input/output interface (input/output, IO) operations, that is, no IO operation is required to access the persistent memory.
  • input/output interface input/output
  • the computer device further includes a memory controller, at least two persistent memories are connected to the memory controller, and the memory controller is connected to the processor through at least one management chip.
  • the processor is used for accessing the memory controller based on the logical address
  • the memory controller is used for converting the logical address into a physical address, and accessing any one of the at least two persistent memories connected to the processor based on the physical address.
  • the logical address is an address used by the processor side
  • the physical address is an address used by the persistent memory side, that is to say, addresses used by the processor and the persistent memory are different.
  • the memory controller needs to translate addresses to allow the processor to access persistent memory.
  • the processor includes a logic controller, the logic controller is used to store redundant array of independent disks (redundant arrays of independent disks, RAID) information, and the processor is used to access and communicate with the RAID information stored in the logic controller.
  • RAID redundant arrays of independent disks
  • the processor is used to access and communicate with the RAID information stored in the logic controller. Any one of at least two persistent memories connected to the processor. Since there are at least two persistent memories connected to the processor in the present application, the RAID mechanism can be implemented based on the at least two persistent memories connected to the processor, which improves the reliability of the computer equipment.
  • the processor includes a logical controller, and the logical controller is used to partition at least two persistent memories to obtain domains and namespaces.
  • the processor is used to access at least one of domains and namespaces included in any one of the at least two persistent memories communicated with the processor.
  • the processor accesses the persistent memory in units of at least one of the domain and the namespace, which not only makes the access method more flexible, but also improves the access efficiency.
  • the processor includes a logic controller, and the logic controller is configured to control at least one management chip, so as to control a connection state between each persistent memory and the processor through the at least one management chip.
  • the management chip is controlled by the logic controller, so as to control the connection status between each persistent memory and the processor. This control method is more flexible.
  • the number of management chips is at least two, the number of management chips is at least two, at least two management chips are respectively connected to the processor, and any of the at least two persistent memories
  • the memory is connected to the processor through any one of the at least two management chips.
  • the persistent memory is set horizontally through the management chip, thereby realizing the expansion of the storage capacity for persistently storing data.
  • the number of management chips is at least two, the first management chip of the at least two management chips is connected to the processor, and the second management chip of the at least two management chips is connected to the first management chip Connection, any persistent memory in the at least two persistent memories is connected to the processor through the first management chip or the second management chip, the first management chip is at least one of the at least two management chips, and the second management chip The chips are other management chips except the first management chip among the at least two management chips.
  • the persistent memory is configured vertically through the management chip, thereby realizing the expansion of the storage capacity for persistently storing data.
  • the computer device further includes a volatile memory, the volatile memory is connected to the processor, and the processor is also used to access the volatile memory.
  • the volatile memory is connected to the processor, and the processor is also used to access the volatile memory.
  • computer equipment can also perform non-persistent storage of data through volatile memory.
  • a method for processing data is provided.
  • the method is applied to a computer device.
  • the device includes a processor, at least one management chip, and at least two persistent memories.
  • the at least two persistent memories communicate with the processor through at least one management chip. Connection, the connection state between each persistent memory and the processor in the at least two persistent memories is controlled by at least one management chip, and each persistent memory is used for persistent storage of data, and the methods include:
  • the processor receives a data processing request
  • the processor accesses the target persistent memory among the at least two persistent memories connected to the processor, so as to read data from the target persistent memory or write data to the target persistent memory.
  • the device further includes a memory controller, at least two persistent memories are connected to the memory controller, and the memory controller is connected to the processor through at least one management chip.
  • the processor accesses the target persistent memory in the at least two persistent memories connected to the processor based on the data processing request, including: the processor accesses the memory controller according to the logical address based on the data processing request.
  • the memory controller converts logical addresses into physical addresses, and accesses target persistent memory based on physical addresses.
  • the processor includes a logic controller, the logic controller stores RAID information, and the processor accesses the target persistent memory in the at least two persistent memories connected to the processor based on the data processing request, including : Based on the data processing request, the processor accesses the target persistent memory in at least two persistent memories connected to the processor according to the RAID information stored in the logic controller.
  • the processor includes a logic controller, and the method further includes: the logic controller partitions at least two persistent memories to obtain domains and namespaces.
  • the processor accesses the target persistent memory in the at least two persistent memories connected to the processor based on the data processing request, including: the processor accesses the target persistent memory in the at least two persistent memories connected to the processor based on the data processing request
  • the memory includes at least one of domains and namespaces.
  • the processor includes a logic controller, and the method further includes: the logic controller controls at least one management chip, so as to control a connection state between each persistent memory and the processor through the at least one management chip.
  • the device further includes a volatile memory
  • the volatile memory is connected to the processor
  • the method further includes: the processor accesses the volatile memory based on a data processing request, so as to read from the volatile memory fetch data, or write data to volatile memory.
  • a computer system in a third aspect, includes at least two computer devices, where the computer devices are the computer devices provided in the first aspect or any possible implementation manner of the first aspect.
  • the first computer device among the at least two computer devices is used to send data to the second computer device, and the second computer device is used to store the received data in the persistent memory of the second computer device, and the first computer device is at least Any one of the two computer devices, the second computer device is at least one of the at least two computer devices except the first computer device.
  • the data is data stored in a persistent memory of the first computer device.
  • FIG. 1 is a schematic structural diagram of a computer device provided in an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a storage medium provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a computer device provided in an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a computer device provided in an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a computer device provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a computer device provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a computer device provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a computer device provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a computer device provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a computer device provided by an embodiment of the present application.
  • FIG. 11 is a flow chart of a method for processing data provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a computer device provided by an embodiment of the present application.
  • FIG. 13 is a schematic diagram of an address translation provided by an embodiment of the present application.
  • FIG. 14 is a schematic diagram of an address translation provided by an embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of a computer device provided by an embodiment of the present application.
  • FIG. 16 is a schematic diagram of a domain and a namespace provided by an embodiment of the present application.
  • Persistent storage refers to a storage method that will not cause data loss due to power failure or restart of the device.
  • the disk includes a solid state disk (solid state disk, SSD), a hard disk drive (hard disk drive, HDD), a magnetic tape (tape), and the like.
  • solid state disk solid state disk
  • HDD hard disk drive
  • tape magnetic tape
  • a persistent memory is used to replace the disk in the related art, and the persistent memory stores data persistently, thereby providing a new way of persistently storing data.
  • the number of persistent memory used to replace the disk is at least two, which can expand the storage capacity for persistent storage of data and avoid the occurrence of insufficient storage capacity.
  • the embodiment of the present application provides a computer device, referring to Fig. 1, the device includes: a processor (processor) 101, at least one management chip 102, and at least two persistent memories 103, at least two persistent memories 103 pass at least one
  • the management chip 102 is connected to the processor 101, and the persistent memory 103 is used for persistently storing data.
  • At least one management chip 102 is used to control the connection status between each persistent memory 103 and the processor 101 .
  • the processor 101 is configured to access any one of the at least two persistent memories 103 connected to the processor 101 , so as to read data from the persistent memory 103 or write data to the persistent memory 103 .
  • the process of the processor 101 accessing the persistent memory 103 refer to the description in the method embodiments later, and details will not be described here.
  • the management chip 102 controls the connection state between each persistent memory 103 and the processor 101 according to the following control manner, so as to control the topological link relationship between the persistent memory 103 and the processor 101 . It can be understood that the following control methods are only examples, and this embodiment does not limit the control methods used by the management chip 102, and the management chip 102 can select an appropriate control method according to actual needs.
  • the management chip 102 has a switch function, that is to say, the management chip 102 includes an on state and an off state. Since at least two persistent memories 103 are connected to the processor 101 through at least one management chip 102 , at least one management chip 102 is included between one persistent memory 103 and the processor 101 . For a persistent memory 103, in response to all management chips 102 between the persistent memory 103 and the processor 101 being on, the persistent memory 103 communicates with the processor 101 (that is, the persistent memory 103 and the processor 101), the processor 101 can access the persistent memory 103.
  • the persistent memory 103 is not connected to the processor 101 (that is, the persistent memory 103 is unbound from the processor 101) , the processor 101 cannot access the persistent memory 103 .
  • the management chip 102 can control whether any persistent memory 103 connected to the management chip 102 communicates with the processor 101 .
  • the processor 101 and the two persistent memories 103 are respectively connected to the management chip 102 .
  • the management chip 102 can control one of the persistent memories 103 to communicate with the processor 101 , and control the other persistent memory 103 not to communicate with the processor 101 .
  • the persistent memory 103 is a memory that does not need to perform input/output interface (input/output, IO) operations.
  • IO operation is an operation that needs to be performed when the disk is accessed, and the IO operation is, for example, a track-seeking operation or a sector-finding operation. It is precisely because the IO operation needs to be performed when the disk is accessed that the efficiency of data processing by accessing the disk is low.
  • the access to the persistent memory 103 does not need to perform IO operations, it not only makes the efficiency of data processing by accessing the persistent memory 103 higher, but also improves the number of daily full disk writes (drive writes per day, DWPD) of the persistent memory 103 ), so that the persistent memory 103 has higher reliability.
  • the device contains such a persistent memory 103 that does not need to perform IO operations, if the device goes down and the business is interrupted, the data stored in the persistent memory 103 will not be lost, and the data stored in the persistent memory 103 will not be lost due to access to this persistent memory.
  • the data processing efficiency of the memory 103 is relatively high and the recovery time objective (recovery time object, RTO) is shortened, thereby ensuring service stability.
  • the persistent memory 103 instead of the disk, not only a new persistent storage method is provided, but also because there are at least two persistent memories 103 in the embodiment of the present application, it is possible to realize the The storage capacity of persistent storage can be expanded to avoid insufficient storage capacity.
  • accessing the persistent memory 103 does not require IO operations, but accessing the disk requires IO operations, therefore, by using the persistent memory 103, no IO operations are involved in the data processing process, saving time for performing IO operations, so that Improve data processing efficiency.
  • the persistent memory 103 includes but not limited to persistent memory (persistent memory, PMEM).
  • PMEM persistent memory
  • FIG. 2 it can be seen that compared with disks in the related art (such as SSD, HDD and magnetic tape shown in FIG. 2 ), PMEM has smaller delay and higher data processing efficiency.
  • At least two persistent memories 103 are arranged horizontally.
  • the number of management chips 102 is at least two, at least two management chips 102 are respectively connected to the processor 101, any persistent memory in the at least two persistent memories 103 passes through any management chip in the at least two management chips 102 Connect with processor 101.
  • the management chip 1 and the management chip 2 are respectively connected to the processor, the persistent memory 1 and the persistent memory 2 are connected to the management chip 1 , and the persistent memory 3 and the persistent memory 4 are connected to the management chip 2 .
  • At least two persistent memories 103 are arranged vertically.
  • the number of management chips 102 is at least two, the first management chip of the at least two management chips 102 is connected to the processor 101, the second management chip of the at least two management chips 102 is connected to the first management chip, and at least two Any persistent memory in the persistent memory 103 is connected to the processor 101 through the first management chip or the second management chip.
  • the first management chip is at least one management chip in the at least two management chips 102
  • the second management chip is other management chips in the at least two management chips 102 except the first management chip.
  • the first management chip includes management chip 1 and management chip 2
  • the second management chip includes management chip 3 . Referring to FIG.
  • the management chip 1 and the management chip 2 are respectively connected to the processor, and the management chip 3 is connected to the management chip 1 .
  • the persistent memory 1 is connected to the management chip 1
  • the persistent memory 2 is connected to the management chip 2
  • the persistent memory 3 is connected to the management chip 3 .
  • the number of the first management chip and the number of the second management chip are at least one, and this embodiment does not limit the number of the first management chip and the second management chip.
  • the processor 101 the management chip 102 and the persistent memory 103 included in the computer device have been described.
  • the computer device further includes other components, which will be described respectively below.
  • a device memory controller is also included in the computer device. At least two persistent memories 103 are connected to the memory controller, and the memory controller is connected to the processor 101 through at least one management chip 102 . Exemplarily, the memory controller corresponds to the persistent memory 103 one by one. Referring to FIG. 5, the memory controller and the persistent memory 103 constitute a logical device (logical device, LD). Wherein, the functions of the memory controller include but are not limited to: converting logical addresses and physical addresses. Wherein, the logical address is a host physical address (host physical address, HPA) used by the processor 101 side, and the physical address is a device physical address (device physical address, HPA) used by the persistent memory 103 side.
  • host physical address host physical address
  • HPA device physical address
  • the processor 101 interacts with the memory controller through a compute express link (compute express link, CXL) technology, so a logic device including a memory controller is also called a CXL device.
  • CXL compute express link
  • the CXL technology used in this embodiment is CXL 2.0, and this embodiment does not limit the CXL technology used.
  • the processor 101 includes a logic controller for performing logic device manager (logic device manager, LDM).
  • the function of the logic controller includes: partitioning the persistent memory 103 .
  • the LD where the persistent memory 103 is located is a multi-logical device (multi-logical device, LD).
  • the LD where the persistent memory 103 is located is a single-logical device (single-logical device, SLD).
  • partitioning the persistent memory 103 through the logic controller is only an example.
  • a baseboard management controller (baseboard management controller, BMC) or a basic input/output system (basic input/output system, BIOS) and other components can also be used.
  • BMC baseboard management controller
  • BIOS basic input/output system
  • the function of the logic controller further includes: storing RAID information, and the RAID information is used to implement a RAID mechanism between at least two persistent memories 103 .
  • the function of the logic controller further includes: controlling the management chip 102 . According to the above description, it can be seen that the management chip 102 can control the connection status between each persistent memory 103 and the processor 101 .
  • the processor 101 includes a logic controller
  • the logic controller controls the connection state between each persistent memory 103 and the processor 101 through the management chip 102 .
  • the logic controller sends a control instruction to the management chip 102, and the management chip 102 controls the connection state between each persistent memory 103 and the processor 101 according to the control instruction.
  • the function of the logic controller further includes: detecting the health status of the persistent memory 103, and giving an alarm when the health status of the persistent memory 103 does not meet requirements.
  • the health status of the persistent memory 103 is the occupancy rate of the persistent memory 103. If the occupancy rate is higher than the threshold, the health status of the persistent memory 103 is deemed not to meet the requirements.
  • This embodiment does not limit the threshold. It can be understood that the function of the logic controller described above is only an example, and this embodiment does not limit the function of the logic controller. The functions of the logic controller will be described in detail in the following method embodiments, and will not be repeated here.
  • the computer device further includes a volatile memory connected to the processor 101 .
  • a volatile memory connected to the processor 101 .
  • Both the persistent memory and the disk described above are used for persistent storage of data, that is, a storage method that will not cause data loss due to power failure or restart of the device.
  • the volatile memory is used for non-persistent storage of data, that is, a storage method in which data will be lost if the device is powered off or restarted.
  • the volatile memory includes but not limited to dynamic random access memory (dynamic random access memory, DRAM), cache memory (cache) and register (register) shown in FIG. 2 .
  • DRAM dynamic random access memory
  • cache cache memory
  • register register
  • FIG. 2 Data stored in volatile memory is lost when the computer equipment is powered off or restarted.
  • the processor 101 accesses the persistent memory 103 to read the data stored in the persistent memory 103, and stores the read data in the volatile memory.
  • the processor 101 can access the volatile memory for data processing. It can be seen from FIG. 2 that the latency of the volatile memory is lower than that of the persistent memory 103, so this approach can reduce latency and improve data processing efficiency.
  • the processor 101 includes a root complex (root complex), and the root complex includes an IO bridge (bridge) and the logic controller in the above description.
  • the IO bridge is connected with the root port (root port), and the root port is connected with the management chip 102 in the above description.
  • Processor 101 also includes a home agent (home agent), the home agent is connected to the core (core), the home agent is also connected to the host memory controller (host memory controller), and the host memory controller is connected to the volatile memory in the above description .
  • home agent home agent
  • core core
  • host memory controller host memory controller
  • the computer device further includes a disk, and the disk and at least two persistent memories 103 are jointly used for persistently storing data. Since the process of accessing the disk requires IO operations, but the process of accessing the persistent memory 103 does not require IO operations, the data processing efficiency when accessing the disk is low. Exemplarily, in this implementation manner, it may be determined according to processing requirements whether to use persistent memory for persistent storage of data or to use disk for persistent storage of data. For example, in response to the requirement that the data processing delay is lower than the threshold, the persistent memory 103 is used to persistently store the data. In response to allowing the data processing delay to be higher than the threshold, the disk is used to persistently store the data. This embodiment does not limit the threshold.
  • the persistent memory 103 in response to the data type being the target type, the persistent memory 103 is used to persistently store the data. In response to the fact that the data type is not the target type, a disk is used to persistently store the data.
  • the data type may include multiple types, and the target type is at least one type among the multiple types. For example, multiple types include integer (int), floating point (float), and character (char), and the target type is int.
  • the persistent memory 103 is used to persistently store the data.
  • a disk is used to store the data persistently.
  • the disk is connected to the processor 101 .
  • the disk can also be connected to the management chip 102 .
  • the management chip 102 is not only used to control the connection state between the persistent memory 103 and the processor 101 , but also used to control the connection state between the disk and the processor 101 .
  • the processor 101 may persistently store data in a persistent memory 103 or a disk connected to the processor 101.
  • the process of controlling the connection state by the management chip 102 refers to the description above, and will not be repeated here.
  • an embodiment of the present application provides a method for processing data, and the method is applied to an interaction process between a processor and a persistent memory. Referring to Fig. 11, the method includes the following steps.
  • the processor receives a data processing request.
  • the processor receives a data processing request from an operating system (operating system, OS), and the data processing request is determined by the OS according to the APP request.
  • the data processing request includes a processing identifier and an address, and the processing identifier is used to indicate a processing method, and the processing method includes reading (load) and writing (store).
  • the address is the address of the data to be processed.
  • the processor accesses a target persistent memory among at least two persistent memories connected to the processor, so as to read data from the target persistent memory or write data to the target persistent memory.
  • the way for the processor to access a persistent memory includes: the processor sends a data processing instruction to the persistent memory.
  • the processor determines whether the data to be processed is persistent data based on the address in the data processing request.
  • the processor sends a data processing instruction to the target persistent memory.
  • the address range corresponding to each persistent memory is stored in the processor, and in response to the address in the data processing request being located in the address range corresponding to the persistent memory, it is determined that the data to be processed is persistent data.
  • the processor obtains the data processing instruction based on the processing identifier and address encapsulation, so as to send the data processing instruction to the target persistent memory.
  • the data processing instruction is used for the processor to read the persistent data from the target persistent memory according to the address.
  • the processor may return the read data to the OS, or return the processing result to the OS after performing calculation and other processing on the read data, so as to complete the processing of the data processing request.
  • FIG. 13 shows the case where the processing mode is reading.
  • the method further includes: sending data to the target persistent memory, where the data processing instruction is used by the processor to write the data into the target persistent memory according to the address.
  • FIG. 14 shows the case where the processing mode is writing.
  • the target persistent memory after the data is written into the target persistent memory, the target persistent memory also returns feedback information, and the processor can determine that the writing to the target persistent memory has been completed. It should be noted that writing includes two different situations. The first case is to write meaningful data into the target persistent memory, so that the target persistent memory stores the written data. The second case is to write data that has no practical significance into the target persistent memory, so as to erase the stored data in the target persistent memory.
  • the processor in response to determining that the data to be processed is non-persistent data, the processor no longer accesses the persistent memory, but accesses the volatile memory in the computer device. Then in an exemplary embodiment, the method further includes: the processor accesses the volatile memory based on the data processing request, so as to read data from the volatile memory or write data to the volatile memory.
  • the processor stores an address range corresponding to the volatile memory, and in response to the address of the data to be processed is located in the address range corresponding to the volatile memory, it is determined that the data to be processed is non-persistent data. Therefore, the data processing instruction is obtained based on the processing identifier and address encapsulation, and the data processing instruction is sent to the volatile memory.
  • the address in the data processing instruction is the physical address of the persistent data (that is, the DPA used by the persistent memory side).
  • the address in the data processing instruction is the logical address of the persistent data (that is, the HPA used by the processor side). Then, based on the data processing request, the processor accesses the target persistent memory in the at least two persistent memories connected to the processor, including: the processor accesses the memory controller according to the logical address based on the data processing request.
  • the memory controller converts logical addresses into physical addresses, and accesses target persistent memory based on physical addresses.
  • the processor stores the logical address range corresponding to each persistent memory, and the processor accesses the memory controller based on the logical address, including: the logical address of the persistent data is located in the logical address range corresponding to the persistent memory, then the processor Then access the memory controller corresponding to which persistent memory, that is, send a data processing instruction including a processing identifier and a logical address to the memory controller corresponding to which persistent memory.
  • the memory controller parses the data processing instruction to obtain the processing identifier and the logical address, thereby converting the logical address into a physical address. Referring to Fig. 13 and Fig. 14, Fig. 13 shows the process of address translation performed by the memory controller when the processing mode indicated by the processing flag is read, and Fig.
  • the memory controller The process of address translation by the device. After the memory controller converts the logical address into a physical address, the target persistent memory can be accessed based on the physical address. The memory controller accesses the target persistent memory based on the physical address, including: the memory controller sends a data processing instruction including a processing identifier and a physical address to the target persistent memory.
  • the method when the processor includes a logic controller, the method further includes: the logic controller partitions at least two persistent memories to obtain a domain and a namespace (namespace).
  • namespace namespace
  • the first byte range in the persistent memory is used to store the LSA
  • the second byte range is used to persistently store the data.
  • the first byte range includes bytes of the reference length starting from the start address of the persistent memory
  • the second byte range includes other bytes after the first byte range. This embodiment does not refer to The length is limited.
  • the persistent memory consists of multiple storage units, which are not limited in this embodiment.
  • the persistent memory includes at least one region, and in response to a region covering more than two storage units, the region is an interleaved (interleaved) type.
  • a field is of non-interleaved type in response to it covering only one memory unit.
  • a domain includes at least one namespace, and this embodiment does not limit the number of namespaces included in the domain.
  • the LSA includes a domain label (label) and a namespace label, the domain label is used to indicate the domain in the persistent memory, and the namespace is used to indicate the namespace in the persistent memory.
  • the domain tag includes the following information a-e
  • the namespace tag includes the following information f-i.
  • UUID universally unique identifier
  • interleaving information used to indicate whether the field is an interleaving type, and if the field is an interleaving type, further indicate the storage unit covered by the field.
  • Address correspondence that is, the correspondence between logical addresses and physical addresses.
  • the address correspondence is used by the memory controller to perform conversion between logical addresses and physical addresses.
  • Domain information Namely, the namespace identifier of the namespace included in the domain, and the namespace identifier is used to uniquely identify the namespace.
  • the address range corresponding to the domain such as the start address and length of the domain.
  • Byte alignment information For each piece of data in the namespace, adjust the storage address of the data according to the data length and the access granularity of the persistent memory, so that the starting address of a piece of data is an integer multiple of a certain value .
  • the byte alignment information is the adjustment amount of the storage address of the data. Exemplarily, the magnitude of the value is mega (Mbyte, M), such as 256M, which is not limited in this embodiment.
  • Namespace information the address range of the namespace, such as the start address and length of the namespace.
  • Logical block address (logical block address, LBA) information that namespace includes LBA information includes LBA identification and LBA address range, LBA address range such as the start address and length of LBA, a namespace includes at least one LBA.
  • the logical controller partitions at least two persistent memories, including: the logical controller sends a query instruction to the persistent memory, the query instruction is used to obtain memory information of the persistent memory, and the persistent memory is based on the query instruction to send memory information to the logic controller. Afterwards, the logic controller sends configuration instructions to the persistent memory based on the memory information.
  • the configuration instructions are used to configure domains and namespaces of the persistent memory, and the persistent memory configures domains and namespaces based on the configuration instructions.
  • this configuration directive can also be used to instruct persistent memory to configure domain labels and namespace labels.
  • the memory information includes but not limited to memory capacity information and LSA information
  • the memory capacity information includes used capacity and information that has been configured but not put into use (will be put into use later)
  • the LSA information includes domain labels and namespaces Label Information.
  • the processor obtains memory capacity information through the query command get partition information, and obtains LSA information through the query command get LSA.
  • the configuration command includes set partition information, which is used to indicate the persistent memory configuration domain and namespace, and the configuration command also includes set LSA, which is used to indicate the persistent memory configuration domain label and namespace label.
  • the processor can also obtain the total capacity of persistent memory through the identify memory device command command.
  • the processor accesses the target persistent memory in at least two persistent memories connected to the processor based on the data processing request, including: the processor bases the data processing request on the access and At least one of domains and namespaces included in the target persistent memory among the at least two persistent memories connected to the processor.
  • the data processing instruction sent by the processor includes at least one of the above-mentioned domain UUID and namespace identifier in addition to the processing identifier and address, and the domain UUID is used to indicate that the persistent data is stored in the persistent memory The domain in which the namespace is located, and the namespace identifier is used to indicate the namespace in which the persistent data is located in the persistent memory.
  • the data processing instruction when the processor accesses the domain, includes the domain UUID.
  • the data processing instruction includes only the namespace identifier, or includes both the namespace identifier and the domain UUID.
  • the relative position of the persistent data in the domain or namespace is determined based on the address, and the persistent data is sequentially indexed based on the relative position.
  • the process of indexing into persistent data may be performed by the memory controller.
  • the process of indexing to persistent data is described by taking access to the namespace in the persistent memory and only including the namespace identifier in the data processing instruction as an example.
  • the domain information of the domain label includes the namespace identifiers of each namespace in the domain, so the domain information of the namespace indicated by the namespace identifier can be determined by querying the domain information based on the namespace identifier included in the data processing instruction.
  • the namespace information of the namespace tag includes the address range of the namespace, such as the start address and length of the namespace. Therefore, according to the namespace information and address, the name of the persistent data indicated by the namespace tag can be determined. relative position in space. Exemplarily, the relative position is an offset (position) of the start address of the persistent data relative to the start address of the namespace. Therefore, first index to the domain where the namespace is located, and then index to the namespace in the domain, and then index to the persistent data according to the relative position of the persistent data in the namespace.
  • the apparatus for processing data in this embodiment includes at least two persistent memories, a RAID mechanism can be implemented based on at least two persistent memories, thereby improving the reliability of computer equipment.
  • the processor when the processor includes a logic controller, and the logic controller stores RAID information, the processor accesses target persistent objects in at least two persistent memories communicated with the processor based on a data processing request.
  • the memory includes: based on the data processing request, the processor accesses the target persistent memory among the at least two persistent memories connected to the processor according to the RAID information stored by the logic controller.
  • the RAID mechanism defines a data stripe, and a data stripe includes at least two data blocks.
  • the RAID mechanism includes but is not limited to multiple levels such as RAID 0-6. This embodiment does not limit the levels included in the RAID mechanism, and any RAID level can be selected according to actual needs.
  • the RAID information stored in the logic controller includes but not limited to: the protocol stack and level of the RAID. For example, in RAID 0, each data block included in the data stripe is distributed to at least two persistent memories for storage, and one persistent memory is used to store at least one data block.
  • a data stripe includes 8 data blocks A0-A7, and the number of persistent memories is two, then one persistent memory stores data blocks A0-A3, and the other persistent memory stores data blocks A4-A7 .
  • RAID 1 at least two persistent memories are used to respectively store each data block included in the data stripe, so that at least two persistent memories form a mirror image.
  • the number of persistent memories is at least three
  • the first persistent memory of the at least three persistent memories stores check data
  • the second persistent memory of the at least three persistent memories Data blocks are stored in .
  • the processor accesses the target persistent memory in the at least two persistent memories connected to the processor according to the RAID information stored in the logic controller, including: the processor responds to detecting that the data block stored in the target second persistent memory is invalid, According to the RAID information, the verification data and other data blocks stored in the first persistent memory are obtained, and the processor restores the invalid data block in the target second persistent memory based on the verification data and other data blocks stored in the second persistent memory .
  • Other data blocks are data blocks stored in other second persistent memories other than the target second persistent memory.
  • the first persistent memory is any one of the at least three persistent memories
  • the second persistent memory is a persistent memory other than the first persistent memory among the at least three persistent memories.
  • the second persistent memory is the persistent memory where the address in the data processing request is located. That is to say, when the processor accesses a persistent memory based on a data processing request, in response to detecting that a data block in the persistent memory is invalid, it can execute the method in the above description to restore the invalid block in the persistent memory. data block.
  • the persistent memory is used to persistently store at least one data stripe, and one data stripe corresponds to verification data.
  • the verification data and each data block are persistently stored in different persistent memories.
  • the processor obtains the verification data from the first persistent memory, and obtains other data blocks in the data stripe except the invalid data block from the other second persistent memory, so that the processor can obtain data based on the verification data and other data Block recovery of invalid data blocks.
  • the above describes the case where a data stripe is stored in the persistent memory.
  • the situation of storing at least two data stripes in the persistent memory is the same as that described above, and will not be repeated here.
  • the verification data corresponding to the at least two data stripes are respectively located in different persistent memories.
  • the embodiment of the present application controls the connection state between the persistent memory and the processor through the management chip, so that the processor is connected to at least two persistent memories. Since the processor can access at least two persistent memories connected to the processor, and the persistent memory can be used for persistent storage of data, it not only expands the storage capacity for persistent storage of data, but also avoids Insufficient storage capacity has occurred.
  • a new method for persistently storing data is also provided, which is different from the method for persistently storing data only through disks in related technologies.
  • An embodiment of the present application provides a computer system, and the computer system includes at least two computer devices, and the computer devices are the computer devices corresponding to any one of Fig. 1 to Fig. 10 . At least two computer devices are connected to each other, thereby forming a memory pool between different computer devices, increasing the stability and flexibility of the system.
  • the first computer device is used to send data to the second computer device
  • the second computer device is used to store the received data in the persistent memory of the second computer device
  • the first computer device It is any one of the at least two computer devices
  • the second computer device is at least one of the at least two computer devices except the first computer device.
  • the second computer device writes the received data into the persistent memory of the second computer device.
  • the first computer device sends data to the second computer device through a high-speed network, and this embodiment does not limit the manner of data transmission between the first computer device and the second computer device.
  • the data is data stored in a persistent memory of the first computer device.
  • the first computer device reads the data from the persistent memory of the first computer device. For the reading process, refer to the description of the method embodiment above, and details are not repeated here.
  • processor can be a central processing unit (Central Processing Unit, CPU), and can also be other general-purpose processors, digital signal processing (digital signal processing, DSP), application specific integrated circuit (application specific integrated circuit, ASIC), field-programmable gate array (field-programmable gate array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • a general purpose processor may be a microprocessor or any conventional processor or the like. It should be noted that the processor may be a processor supporting advanced RISC machines (ARM) architecture.
  • ARM advanced RISC machines
  • all or part of them may be implemented by software, hardware, firmware or any combination thereof.
  • software When implemented using software, it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions according to the present application will be generated in whole or in part.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website, computer, server or data center Transmission to another website site, computer, server, or data center by wired (eg, coaxial cable, optical fiber, DSL) or wireless (eg, infrared, wireless, microwave, etc.) means.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center integrated with one or more available media.
  • the available medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, DVD), or a semiconductor medium (for example, a Solid State Disk).

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Abstract

本申请公开了计算机设备、处理数据的方法及计算机系统，属于计算机技术领域。计算机设备包括：处理器、至少一个管理芯片和至少两个持久化内存，至少两个持久化内存通过至少一个管理芯片与处理器连接，持久化内存用于对数据进行持久化存储。至少一个管理芯片用于控制各个持久化内存与处理器的连通状态，处理器用于访问与处理器连通的至少两个持久化内存中的任一持久化内存。本申请通过管理芯片控制持久化内存与处理器的连通状态，使得处理器与至少两个持久化内存相连通。处理器能够访问与处理器相连通的至少两个持久化内存，从而扩展了用于对数据进行持久化存储的存储容量，避免了存储容量不足，提供了一种对数据进行持久化存储的新方式。

Description

计算机设备、处理数据的方法及计算机系统
本申请要求于2021年09月26日提交中国专利局、申请号为202111130176.5、申请名称为“计算机设备、处理数据的方法及计算机系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机技术领域，特别涉及计算机设备、处理数据的方法及计算机系统。
背景技术
随着计算机技术的发展，设备需要处理的数据也越来越多。在需要处理的数据中，有些数据需要进行持久化存储。持久化存储是指：不会由于设备的断电或重启而导致数据丢失的存储方式。如何对数据进行持久化存储，成为亟待解决的问题。
发明内容
本申请提供了一种计算机设备、处理数据的方法及计算机系统，以实现对数据的持久化存储，技术方案如下：
第一方面，提供了一种计算机设备，该设备包括：处理器、至少一个管理芯片和至少两个持久化内存，至少两个持久化内存通过至少一个管理芯片与处理器连接，至少两个持久化内存中的各个持久化内存用于对数据进行持久化存储。其中，至少一个管理芯片用于控制各个持久化内存与处理器的连通状态，处理器用于访问与处理器连通的至少两个持久化内存中的任一持久化内存。
本申请通过管理芯片控制持久化内存与处理器的连通状态，使得处理器与至少两个持久化内存相连通。由于处理器能够访问与处理器相连通的至少两个持久化内存，且持久化内存能够用于对数据进行持久化存储，因而不仅扩展了用于对数据进行持久化存储的存储容量，避免了发生存储容量不足的情况，还提供了一种对数据进行持久化存储的新的方式，与相关技术中仅通过磁盘对数据进行持久化存储的方式存在不同。
需要说明的是，持久化内存又称非易失性内存(non-volatile memory，NVM)，用于对数据进行持久化存储，是一种不会由于设备的断电或重启而丢失数据的存储介质(又可以称为存储器或存储硬件)。处理器能够通过指令(instruction)对持久化内存进行访问，该访问过程不涉及输入输出接口(input/output，IO)操作，即访问持久化内存无需执行IO操作。
在一种可能的实现方式中，计算机设备还包括内存控制器，至少两个持久化内存与内存控制器连接，内存控制器通过至少一个管理芯片与处理器连接。其中，处理器用于基于逻辑地址访问内存控制器，内存控制器用于将逻辑地址转换为物理地址，基于物理地址访问与处理器连通的至少两个持久化内存中的任一持久化内存。其中，逻辑地址是处理器侧使用的地址，物理地址是持久化内存侧使用的地址，也就是说处理器与持久化内存使用的地址不同。内存控制器需要对地址进行转换，以实现处理器对持久化内存的访问。
在一种可能的实现方式中，处理器包括逻辑控制器，逻辑控制器用于存储独立磁盘冗余阵列(redundant arrays of independent disks，RAID)信息，处理器用于按照逻辑控制器存储的RAID信息访问与处理器连通的至少两个持久化内存中的任一持久化内存。由于本申请中有至少两个持久化内存与处理器连通，因而能够基于与处理器连通的至少两个持久化内存实现RAID机制，提高了计算机设备的可靠性。
在一种可能的实现方式中，处理器包括逻辑控制器，逻辑控制器用于对至少两个持久化内存进行分区，得到域和命名空间。处理器用于访问与处理器连通的至少两个持久化内存中的任一持久化内存包括的域和命名空间中的至少一个。处理器以域和命名空间中的至少一个为单位对持久化内存进行访问，不仅访问方式较为灵活，还提高了访问效率。
在一种可能的实现方式中，处理器包括逻辑控制器，逻辑控制器用于控制至少一个管理芯片，以通过至少一个管理芯片控制各个持久化内存与处理器的连通状态。管理芯片接受逻辑控制器的控制，从而对各个持久化内存与处理器的连通状态进行控制，该控制方式较为灵活。
在一种可能的实现方式中，管理芯片的数量为至少两个，管理芯片的数量为至少两个，至少两个管理芯片分别与处理器连接，至少两个持久化内存中的任一持久化内存通过至少两个管理芯片中的任一管理芯片与处理器连接。在该实现方式中，通过管理芯片对持久化内存进行横向设置，从而实现了用于对数据进行持久化存储的存储容量的扩展。
在一种可能的实现方式中，管理芯片的数量为至少两个，至少两个管理芯片中的第一管理芯片与处理器连接，至少两个管理芯片中的第二管理芯片与第一管理芯片连接，至少两个持久化内存中的任一持久化内存通过第一管理芯片或者第二管理芯片与处理器连接，第一管理芯片为至少两个管理芯片中的至少一个管理芯片，第二管理芯片为至少两个管理芯片中除第一管理芯片之外的其他管理芯片。在该实现方式中，通过管理芯片对持久化内存进行纵向设置，从而实现了用于对数据进行持久化存储的存储容量的扩展。
在一种可能的实现方式中，计算机设备还包括易失性内存，易失性内存与处理器连接，处理器还用于访问易失性内存。在持久化内存的基础上，计算机设备还能够通过易失性内存对数据进行非持久化存储。
第二方面，提供了一种处理数据的方法，方法应用于计算机设备，设备包括处理器、至少一个管理芯片和至少两个持久化内存，至少两个持久化内存通过至少一个管理芯片与处理器连接，至少两个持久化内存中的各个持久化内存与处理器的连通状态均由至少一个管理芯片控制，各个持久化内存用于对数据进行持久化存储，方法包括：
处理器接收数据处理请求；
处理器基于该数据处理请求访问与处理器连通的至少两个持久化内存中的目标持久化内存，以从目标持久化内存中读取数据，或者向目标持久化内存中写入数据。
在一种可能的实现方式中，设备还包括内存控制器，至少两个持久化内存与内存控制器连接，内存控制器通过至少一个管理芯片与处理器连接。处理器基于数据处理请求访问与处理器连通的至少两个持久化内存中的目标持久化内存，包括：处理器基于该数据处理请求，按照逻辑地址访问内存控制器。内存控制器将逻辑地址转换为物理地址，基于物理地址访问目标持久化内存。
在一种可能的实现方式中，处理器包括逻辑控制器，逻辑控制器存储有RAID信息， 处理器基于数据处理请求访问与处理器连通的至少两个持久化内存中的目标持久化内存，包括：处理器基于数据处理请求，按照逻辑控制器存储的RAID信息访问与处理器连通的至少两个持久化内存中的目标持久化内存。
在一种可能的实现方式中，处理器包括逻辑控制器，方法还包括：逻辑控制器对至少两个持久化内存进行分区，得到域和命名空间。处理器基于数据处理请求访问与处理器连通的至少两个持久化内存中的目标持久化内存，包括：处理器基于数据处理请求访问与处理器连通的至少两个持久化内存中的目标持久化内存包括的域和命名空间中的至少一个。
在一种可能的实现方式中，处理器包括逻辑控制器，方法还包括：逻辑控制器控制至少一个管理芯片，以通过至少一个管理芯片控制各个持久化内存与处理器的连通状态。
在一种可能的实现方式中，设备还包括易失性内存，易失性内存与处理器连接，方法还包括：处理器基于数据处理请求访问易失性内存，以从易失性内存中读取数据，或者向易失性内存中写入数据。
第三方面，提供了一种计算机系统，该计算机系统包括至少两个计算机设备，计算机设备是第一方面或第一方面的任一种可能的实现方式中提供的计算机设备。至少两个计算机设备中的第一计算机设备用于向第二计算机设备发送数据，第二计算机设备用于将接收到的数据存储于第二计算机设备的持久化内存中，第一计算机设备为至少两个计算机设备中的任一计算机设备，第二计算机设备为至少两个计算机设备中除第一计算机设备之外的至少一个计算机设备。
在一种可能的实现方式中，数据为第一计算机设备的持久化内存中存储的数据。
附图说明
图1为本申请实施例提供的一种计算机设备的结构示意图；
图2为本申请实施例提供的一种存储介质的示意图；
图3为本申请实施例提供的一种计算机设备的结构示意图；
图4为本申请实施例提供的一种计算机设备的结构示意图；
图5为本申请实施例提供的一种计算机设备的结构示意图；
图6为本申请实施例提供的一种计算机设备的结构示意图；
图7为本申请实施例提供的一种计算机设备的结构示意图；
图8为本申请实施例提供的一种计算机设备的结构示意图；
图9为本申请实施例提供的一种计算机设备的结构示意图；
图10为本申请实施例提供的一种计算机设备的结构示意图；
图11为本申请实施例提供的一种处理数据的方法的流程图；
图12为本申请实施例提供的一种计算机设备的结构示意图；
图13为本申请实施例提供的一种地址转换的示意图；
图14为本申请实施例提供的一种地址转换的示意图；
图15为本申请实施例提供的一种计算机设备的结构示意图；
图16为本申请实施例提供的一种域和命名空间的示意图。
具体实施方式
本申请的实施方式部分使用的术语仅用于对本申请的具体实施例进行解释，而非旨在限定本申请。
随着面向数据的应用程序(application，APP)的数量增长，设备需要处理的数据量也不断增长。在设备中，有些数据需要进行持久化存储。持久化存储是指：不会由于设备的断电或重启而导致数据丢失的存储方式。
相关技术中，通过磁盘对数据进行持久化存储。示例性地，磁盘包括固态硬盘(solid state disk，SSD)、硬盘驱动器(hard disk drive，HDD)和磁带(tape)等。
本实施例采用持久化内存代替相关技术中的磁盘，由持久化内存对数据进行持久化存储，从而提供了一种对数据进行持久化存储的新的方式。并且，用于代替磁盘的持久化内存的数量为至少两个，能够扩展用于对数据进行持久化存储的存储容量，避免发生存储容量不足的情况。
本申请实施例提供了一种计算机设备，参见图1，该设备包括：处理器(processor)101、至少一个管理芯片102和至少两个持久化内存103，至少两个持久化内存103通过至少一个管理芯片102与处理器101连接，持久化内存103用于对数据进行持久化存储。
在该计算机设备中，至少一个管理芯片102用于控制各个持久化内存103与处理器101的连通状态。处理器101用于访问与处理器101连通的至少两个持久化内存103中的任一持久化内存103，以从持久化内存103中读取数据，或者向持久化内存103中写入数据。其中，处理器101访问持久化内存103的过程参见后文方法实施例中的说明，此处暂不进行赘述。
示例性地，管理芯片102按照如下的控制方式控制各个持久化内存103与处理器101的连通状态，从而控制持久化内存103与处理器101之间的拓扑链接关系。能够理解的是，如下的控制方式仅为举例，本实施例不对管理芯片102使用的控制方式加以限定，管理芯片102能够根据实际需要选择合适的控制方式。
管理芯片102具备开关(switch)功能，也就是说管理芯片102包括开启状态和关闭状态。由于至少两个持久化内存103通过至少一个管理芯片102与处理器101连接，因而一个持久化内存103与处理器101之间包括至少一个管理芯片102。对于一个持久化内存103而言，响应于该持久化内存103与处理器101之间的所有管理芯片102均处于开启状态，则该持久化内存103与处理器101连通(即持久化内存103与处理器101绑定)，处理器101能够访问该持久化内存103。或者，响应于该持久化内存103与处理器101之间的任一管理芯片102处于关闭状态，则该持久化内存103不与处理器101连通(即持久化内存103与处理器101解绑)，处理器101不能够访问该持久化内存103。示例性地，对于一个管理芯片102而言，该管理芯片102能够控制与该管理芯片102连接的任一持久化内存103是否与处理器101连通。例如，处理器101和两个持久化内存103分别与管理芯片102连接。管理芯片102能够控制其中一个持久化内存103与处理器101连通，而控制另一个持久化内存103不与处理器101连通。
在示例性实施例中，持久化内存103为无需执行输入输出接口(input/output，IO)操作的内存。其中，IO操作是磁盘被访问时需要执行的操作，IO操作例如为寻找磁道操作、寻找扇区操作。正是由于磁盘被访问时需要执行IO操作，因而才导致通过访问磁盘进行 数据处理的效率较低。而由于访问持久化内存103无需执行IO操作，因而不仅使得通过访问持久化内存103进行数据处理的效率较高，还提高了持久化内存103的每日全盘写入次数(drive writes per day，DWPD)，从而使得持久化内存103具备较高的可靠性。当设备中包含此种无需执行IO操作的持久化内存103时，如果设备发生宕机而导致业务中断，则持久化内存103中存储的数据不会发生丢失，且会由于通过访问此种持久化内存103进行数据处理的效率较高而缩短恢复时间目标(recovery time object，RTO)，保证了业务稳定性。
在该实施例中，通过使用持久化内存103代替磁盘，不仅提供了一种新的持久化存储方式，且由于本申请实施例中的持久化内存103为至少两个，能够实现用于对数据进行持久化存储的存储容量的可扩展，避免造成存储容量不足的情况。此外，由于访问持久化内存103无需执行IO操作，而访问磁盘需要执行IO操作，因此，通过使用持久化内存103能够使得数据处理过程中不涉及IO操作，节约了执行IO操作的时间，以便于提高数据处理效率。
示例性地，持久化内存103包括但不限于持久内存(persistent memory，PMEM)。参见图2可知，相比于相关技术中的磁盘(例如图2所示的SSD、HDD和磁带)，PMEM的延迟较小、数据处理效率较高。
在示例性实施例中，至少两个持久化内存103横向设置。管理芯片102的数量为至少两个，至少两个管理芯片102分别与处理器101连接，至少两个持久化内存103中的任一持久化内存通过至少两个管理芯片102中的任一管理芯片与处理器101连接。例如，参见图3，管理芯片1和管理芯片2分别与处理器连接，持久化内存1和持久化内存2与管理芯片1连接，持久化内存3和持久化内存4与管理芯片2连接。
在示例性实施例中，至少两个持久化内存103纵向设置。管理芯片102的数量为至少两个，至少两个管理芯片102中的第一管理芯片与处理器101连接，至少两个管理芯片102中的第二管理芯片与第一管理芯片连接，至少两个持久化内存103中的任一持久化内存通过第一管理芯片或者第二管理芯片与处理器101连接。其中，第一管理芯片为至少两个管理芯片102中的至少一个管理芯片，第二管理芯片为至少两个管理芯片102中除第一管理芯片之外的其他管理芯片。例如，第一管理芯片包括管理芯片1和管理芯片2，第二管理芯片包括管理芯片3。参见图4，管理芯片1和管理芯片2分别与处理器连接，管理芯片3与管理芯片1连接。持久化内存1与管理芯片1连接，持久化内存2与管理芯片2连接，持久化内存3与管理芯片3连接。示例性地，第一管理芯片和第二管理芯片的数量均为至少一个，本实施例不对第一管理芯片和第二管理芯片的数量加以限定。
以上，对计算机设备中包括的处理器101、管理芯片102和持久化内存103进行了说明。示例性地，计算机设备中还包括其他部件，以下分别进行说明。
在示例性实施例中，计算机设备中还包括内存控制器(device memory controller)。至少两个持久化内存103与内存控制器连接，内存控制器通过至少一个管理芯片102与处理器101连接。示例性地，内存控制器与持久化内存103一一对应。参见图5，内存控制器与持久化内存103构成逻辑设备(logical device，LD)。其中，内存控制器的功能包括但不限于：进行逻辑地址与物理地址的转换。其中，逻辑地址是处理器101侧使用的主机物理地址(host physical address，HPA)，物理地址是持久化内存103侧使用的设备物理地址 (device physical address，HPA)。后文方法实施例中会对内存控制器的功能进行详细说明，此处暂不进行赘述。示例性地，处理器101通过计算快速链接(compute express link，CXL)技术与内存控制器进行交互，因而包括有内存控制器的逻辑设备也称为CXL设备。示例性地，本实施例中采用的CXL技术为CXL 2.0，本实施例不对所采用的CXL技术加以限定。通过采用CXL技术，无需针对持久化内存103增加冗余的内存管理硬件，不仅实现了更高的性能，降低了软件堆栈复杂性，而且节约了成本。
在示例性实施例中，参见图6，处理器101中包括逻辑控制器，该逻辑控制器用于进行逻辑设备管理(logic device manager，LDM)。示例性地，逻辑控制器的功能包括：对持久化内存103进行分区。其中，在对持久化内存103进行分区的情况下，持久化内存103所在的LD为多逻辑设备(multi-logical device，LD)。在不对持久化内存103进行分区的情况下，持久化内存103所在的LD为单逻辑设备(single-logical device，SLD)。当然，通过逻辑控制器对持久化内存103进行分区仅为举例，本实施例还可以通过基板管理控制器(baseboard management controller，BMC)或者基本输入输出系统(basic input/output system，BIOS)等部件对持久化内存103进行分区。示例性地，逻辑控制器的功能还包括：存储RAID信息，该RAID信息用于在至少两个持久化内存103之间实现RAID机制。示例性地，逻辑控制器的功能还包括：对管理芯片102进行控制。根据上文的说明可知，管理芯片102能够控制各个持久化内存103与处理器101的连通状态。在处理器101中包括逻辑控制器的情况下，示例性地，逻辑控制器通过管理芯片102对各个持久化内存103与处理器101的连通状态进行控制。例如，逻辑控制器向管理芯片102发送控制指令，管理芯片102按照该控制指令对各个持久化内存103与处理器101的连通状态进行控制。在一些实施方式中，逻辑控制器的功能还包括：检测持久化内存103的健康状态，在持久化内存103的健康状态不满足要求时进行告警。例如，持久化内存103的健康状态为持久化内存103的占用率，响应于占用率高于阈值，则认为持久化内存103的健康状态不满足要求，本实施例不对该阈值加以限定。能够理解的是，以上说明的逻辑控制器的功能仅为举例，本实施例不对逻辑控制器的功能加以限定。后文方法实施例中会对逻辑控制器的功能进行详细说明，此处暂不进行赘述。
示例性地，参见图7，计算机设备还包括与处理器101连接的易失性内存。上文说明中的持久化内存和磁盘均用于对数据进行持久化存储，即不会由于设备的断电或重启而导致数据丢失的存储方式。而易失性内存用于对数据进行非持久化存储，即设备的断电或重启会导致数据丢失的存储方式。
示例性地，易失性内存包括但不限于图2所示的动态随机存取存储器(dynamic random access memory，DRAM)、高速缓冲存储器(cache)和缓存器(register)。在计算机设备断电或重启后，易失性内存中存储的数据会发生丢失。此种情况下，处理器101访问持久化内存103，以读取持久化内存103中存储的数据，将读取到的数据存储于易失性内存中。在后续计算机设备的运行过程中，处理器101能够访问易失性内存以进行数据处理。根据图2可知，易失性内存的延迟低于持久化内存103的延迟，因而此种方式能够降低延迟，提高数据处理效率。
示例性地，参见图8，图8示出了计算机设备的一种示例性结构。其中，处理器101包括根复合体(root complex)，根复合体包括IO桥(bridge)和上述说明中的逻辑控制器。 IO桥与根端口(root port)连接，根端口与上述说明中的管理芯片102连接。处理器101还包括归属代理(home agent)，归属代理与核(core)连接，归属代理还与主机内存控制器(host memory controller)连接，主机内存控制器与上述说明中的易失性内存连接。
在一些实施方式中，参见图9，计算机设备中还包括磁盘，磁盘和至少两个持久化内存103共同用于对数据进行持久化存储。由于访问磁盘的过程需要进行IO操作，而访问持久化内存103的过程不需要IO操作，因而访问磁盘时的数据处理效率较低。示例性地，在该实现方式中，可以根据处理需求来确定是使用持久化内存对数据进行持久化存储，还是使用磁盘对数据进行持久化存储。例如，响应于要求数据处理延迟低于阈值，则采用持久化内存103对该数据进行持久化存储。响应于允许数据处理延迟高于阈值，再采用磁盘对该数据进行持久化存储。本实施例不对阈值加以限定。或者，该实现方式中还可以根据数据类型来确定是使用持久化内存对数据进行持久化存储，还是使用磁盘对数据进行持久化存储。示例性地，响应于数据类型为目标类型，则采用持久化内存103对数据进行持久化存储。响应于数据类型不为目标类型，则采用磁盘对数据进行持久化存储。其中，数据类型可以包括多种类型，目标类型是多种类型中的至少一种类型。例如，多种类型包括整型(int)、浮点型(float)和字符型(char)，目标类型为int。则响应于数据类型为int，采用持久化内存103对数据进行持久化存储。响应于数据类型为float或者char，采用磁盘对数据进行持久化存储。
在图9中，磁盘与处理器101连接。参见图10，磁盘还可以与管理芯片102连接。则管理芯片102不仅用于控制持久化内存103与处理器101的连通状态，还用于控制磁盘与处理器101的连通状态。对于处理器101而言，处理器101可以将数据持久化存储于与处理器101连通的持久化内存103或者磁盘中。其中，管理芯片102控制连通状态的过程参见上文说明，此处不再进行赘述。
基于上述图1-图10说明的计算机设备，本申请实施例提供了一种处理数据的方法，该方法应用于处理器与持久化内存的交互过程。参见图11，该方法包括如下的步骤。
1101，处理器接收数据处理请求。
示例性地，参见图12，处理器从操作系统(operating system，OS)接收数据处理请求，该数据处理请求是OS根据APP的请求确定的。在一些实施方式中，数据处理请求中包括处理标识和地址，处理标识用于指示处理方式，处理方式包括读取(load)和写入(store)。地址为需要处理的数据的地址。
1102，处理器基于数据处理请求访问与处理器连通的至少两个持久化内存中的目标持久化内存，以从目标持久化内存中读取数据，或者向目标持久化内存中写入数据。
其中，处理器访问一个持久化内存的方式包括：处理器向该持久化内存发送数据处理指令。示例性地，处理器基于数据处理请求中的地址确定需要处理的数据是否为持久化数据。响应于确定需要处理的数据为持久化数据，则处理器向目标持久化内存发送数据处理指令。示例性地，处理器中存储有各个持久化内存对应的地址范围，响应于数据处理请求中的地址位于持久化内存对应的地址范围中，则确定需要处理的数据为持久化数据。之后，处理器基于处理标识和地址封装得到数据处理指令，从而向目标持久化内存发送数据处理指令。
其中，响应于处理标识指示的处理方式为读取，则该数据处理指令用于处理器按照地址从目标持久化内存中读取持久化数据。处理器可以将读取到的数据返回OS，或者对读取到的数据进行计算等处理后将处理结果返回OS，从而完成针对数据处理请求的处理。参见图13，图13示出了处理方式为读取的情况。或者，响应于处理标识指示的处理方式为写入，方法还包括：向目标持久化内存发送数据，该数据处理指令用于处理器按照地址将数据写入目标持久化内存中。参见图14，图14示出了处理方式为写入的情况。示例性地，将数据写入目标持久化内存之后，目标持久化内存还返回反馈信息，则处理器能够确定目标持久化内存已完成写入。需要说明的是，写入包括两种不同的情况。第一种情况是将具有实际意义的数据写入目标持久化内存中，以使得目标持久化内存对写入的数据进行存储。第二种情况是将不具有实际意义的数据写入目标持久化内存中，以对目标持久化内存中已存储的数据进行擦除。
当然，响应于确定需要处理的数据为非持久化数据，处理器则不再访问持久化内存，而是访问计算机设备中的易失性内存。则在示例性实施例中，方法还包括：处理器基于数据处理请求访问易失性内存，以从易失性内存中读取数据，或者向易失性内存中写入数据。示例性地，处理器中存储有易失性内存对应的地址范围，响应于需要处理的数据的地址位于易失性内存对应的地址范围，则确定需要处理的数据为非持久化数据。因此，基于处理标识和地址封装得到数据处理指令，向易失性内存发送该数据处理指令。
对于需要处理的数据为持久化数据的情况，在一些实施方式中，数据处理指令中的地址为持久化数据的物理地址(即持久化内存侧使用的DPA)。在另一些实施方式中，在计算机设备中包括用于进行地址转换的内存控制器的情况下，数据处理指令中的地址为持久化数据的逻辑地址(即处理器侧使用的HPA)。则处理器基于数据处理请求访问与处理器连通的至少两个持久化内存中的目标持久化内存，包括：处理器基于数据处理请求，按照逻辑地址访问内存控制器。内存控制器将逻辑地址转换为物理地址，基于物理地址访问目标持久化内存。
其中，处理器存储有各个持久化内存对应的逻辑地址范围，处理器基于逻辑地址访问内存控制器，包括：持久化数据的逻辑地址位于哪一个持久化内存对应的逻辑地址范围中，则处理器便访问哪一个持久化内存对应的内存控制器，也就是向哪一个持久化内存对应的内存控制器发送包括有处理标识和逻辑地址的数据处理指令。内存控制器解析数据处理指令能够得到处理标识和逻辑地址，从而将逻辑地址转换为物理地址。参见图13和图14，图13示出了处理标识指示的处理方式为读取时，内存控制器进行地址转换的过程，图14示出了处理标识指示的处理方式为写入时，内存控制器进行地址转换的过程。在内存控制器将逻辑地址转换为物理地址之后，便能够基于物理地址访问目标持久化内存。内存控制器基于物理地址访问目标持久化内存，包括：内存控制器向目标持久化内存发送包括有处理标识和物理地址的数据处理指令。
在示例性实施例中，在处理器包括逻辑控制器的情况下，方法还包括：逻辑控制器对至少两个持久化内存进行分区，得到域和命名空间(namespace)。为便于理解，接下来首先结合图15对域和命名空间进行说明。
在持久化内存中，包括存储区标签(the label storage area，LSA)和数据。示例性地，持久化内存中的第一字节范围用于存储LSA，第二字节范围用于对数据进行持久化存储。 在一些实施方式中，第一字节范围包括从持久化内存的起始地址开始的参考长度的字节，第二字节范围包括第一字节范围之后的其他字节，本实施例不对参考长度加以限定。
持久化内存由多个存储单元组成，本实施例不对存储单元加以限定。参见图16，持久化内存包括至少一个域(region)，响应于一个域覆盖两个以上的存储单元，则该域为交织(interleaved)类型。响应于一个域仅覆盖一个存储单元，则该域为非交织(non-interleaved)类型。仍参见图16，一个域包括至少一个命名空间，本实施例不对域中包括的命名空间的数量加以限定。
LSA中包括域标签(label)和命名空间标签，域标签用于对持久化内存中的域进行指示，命名空间用于对持久化内存中的命名空间进行指示。示例性地，域标签中包括如下信息a-e，命名空间标签中包括如下信息f-i。
a)域通用唯一识别码(universally unique identifier，UUID)，用于对持久化内存包括的各个域进行唯一标识，也就是说域与域UUID一一对应。
b)交织信息，用于指示域是否为交织类型，如果域为交织类型，则进一步指示域所覆盖的存储单元。
c)地址对应关系，即逻辑地址与物理地址之间的对应关系。该地址对应关系用于内存控制器进行逻辑地址与物理地址的转换。
d)域信息：即域中包括的命名空间的命名空间标识，命名空间标识用于唯一标识命名空间。
e)域对应的地址范围，例如域的起始地址和长度。
f)命名空间的标识。
g)字节对齐信息：对于命名空间中的每份数据，根据数据长度和持久化内存的存取粒度对数据的存储地址进行调整，使得一份数据的起始地址为某个数值的整数倍。字节对齐信息即为数据的存储地址的调整量。示例性地，该数值的数量级为兆(Mbyte，M)，例如256M，本实施例不对数值加以限定。
h)命名空间信息：命名空间的地址范围，例如命名空间的起始地址和长度。
i)命名空间包括的逻辑区块地址(logical block address，LBA)信息，LBA信息包括LBA标识和LBA地址范围，LBA地址范围例如LBA的起始地址和长度，一个命名空间包括至少一个LBA。
以上，对域和命名空间进行了说明。在示例性实施例中，逻辑控制器对至少两个持久化内存进行分区，包括：逻辑控制器向持久化内存发送查询指令，查询指令用于获得持久化内存的内存信息，持久化内存基于查询指令向逻辑控制器发送内存信息。之后，逻辑控制器基于内存信息向持久化内存发送配置指令，配置指令用于持久化内存配置域和命名空间，则持久化内存基于配置指令配置域和命名空间。当然，除了域和命名空间外，该配置指令还能够用于指示持久化内存配置域标签和命名空间标签。
示例性地，内存信息包括但不限于内存容量信息和LSA信息，内存容量信息包括已使用的容量和已配置但未投入使用(会在后续投入使用)的信息，LSA信息包括域标签和命名空间标签信息。处理器通过get partition information这一查询指令获得内存容量信息，通过get LSA这一查询指令获得LSA信息。配置指令包括set partition information，用于指示持久化内存配置域和命名空间，配置指令还包括set LSA，用于指示持久化内存配置域标 签和命名空间标签。另外，处理器还能够通过identify memory device command指令获得持久化内存的总容量。
在逻辑控制器对持久化内存进行了分区的情况下，处理器基于数据处理请求访问与处理器连通的至少两个持久化内存中的目标持久化内存，包括：处理器基于数据处理请求访问与处理器连通的至少两个持久化内存中的目标持久化内存包括的域和命名空间中的至少一个。示例性地，此种情况下处理器发送的数据处理指令中除了包括处理标识和地址以外，还包括上述域UUID和命名空间标识中的至少一个，域UUID用于指示持久化数据在持久化内存中所位于的域，命名空间标识用于指示持久化数据在持久化内存中所位于的命名空间。示例性地，在处理器访问域的情况下，该数据处理指令中包括域UUID。在处理器访问命名空间的情况下，该数据处理指令中仅包括命名空间标识，或者既包括命名空间标识又包括域UUID。在确定域或者命名空间之后，基于地址确定持久化数据在域或者命名空间中的相对位置，基于该相对位置依次索引至持久化数据。在处理器包括内存控制器的情况下，索引至持久化数据的过程可以由内存控制器执行。接下来，以访问持久化内存中的命名空间，且数据处理指令中仅包括命名空间标识为例，对索引至持久化数据的过程进行说明。
其中，在域标签的域信息中，包括域中的各个命名空间的命名空间标识，因而基于数据处理指令包括的命名空间标识查询域信息，即可确定命名空间标识指示的命名空间所在的域。另外，在命名空间标签的命名空间信息中，包括命名空间的地址范围，例如命名空间的起始地址和长度，因而根据命名空间信息和地址，能够确定持久化数据在命名空间标签所指示的命名空间中的相对位置。示例性地，该相对位置为持久化数据的起始地址相对于命名空间的起始地址的偏移量(position)。由此，首先索引至命名空间所在的域，在该域中索引至命名空间，接着根据持久化数据在命名空间中的相对位置即可索引至持久化数据。
另外，由于本实施例中处理数据的装置包括至少两个持久化内存，因而能够基于至少两个持久化内存实现RAID机制，从而提升了计算机设备的可靠性。在示例性实施例中，在处理器包括逻辑控制器，且逻辑控制器存储有RAID信息的情况下，处理器基于数据处理请求访问与处理器连通的至少两个持久化内存中的目标持久化内存，包括：处理器基于数据处理请求，按照逻辑控制器存储的RAID信息访问与处理器连通的至少两个持久化内存中的目标持久化内存。
其中，RAID机制定义了数据条带，一个数据条带包括至少两个数据块。RAID机制包括但不限于RAID 0-6等多种级别，本实施例不对RAID机制包括的级别加以限定，根据实际需要选择任一RAID级别即可。示例性地，逻辑控制器中存储的RAID信息包括但不限于：RAID的协议栈和级别。例如，在RAID 0中，将数据条带包括的各个数据块分散到至少两个持久化内存中进行存储，一个持久化内存用于存储至少一个数据块。比如，一个数据条带中包括8个数据块A0-A7，持久化内存的数量为两个，则一个持久化内存中存储数据块A0-A3，另一个持久化内存中存储数据块A4-A7。又例如，在RAID 1中，通过至少两个持久化内存分别存储数据条带包括的各个数据块，从而使得至少两个持久化内存形成镜像。接下来，对RAID 5进行说明。
在示例性实施例中，持久化内存的数量为至少三个，至少三个持久化内存中的第一持 久化内存中存储有校验数据，至少三个持久化内存中的第二持久化内存中存储有数据块。处理器按照逻辑控制器存储的RAID信息访问与处理器连通的至少两个持久化内存中的目标持久化内存，包括：处理器响应于检测到目标第二持久化内存中存储的数据块失效，按照RAID信息获得第一持久化内存中存储的校验数据以及其他数据块，处理器基于校验数据和其他第二持久化内存中存储的数据块恢复目标第二持久化内存中失效的数据块。其他数据块为除目标第二持久化内存之外的其他第二持久化内存中存储的数据块。
其中，第一持久化内存为至少三个持久化内存中的任一持久化内存，第二持久化内存为至少三个持久化内存中除第一持久化内存之外的持久化内存，本实施例不对第一持久化内存和第二持久化内存的数量加以限定。示例性地，该第二持久化内存为数据处理请求中的地址所在的持久化内存。也就是说，当处理器基于数据处理请求访问一个持久化内存时，响应于检测到该持久化内存中的数据块失效，则可以执行上述说明中的方法，以恢复该持久化内存中失效的数据块。
示例性地，持久化内存用于持久化存储至少一个数据条带，一个数据条带对应有校验数据。校验数据和各个数据块分别持久化存储于不同的持久化内存中。则，在一个存储有数据块的第二持久化内存发生损坏时，该第二持久化内存中存储的数据块失效。因此，处理器从第一持久化内存中获取校验数据，从其他第二持久化内存中获取数据条带中除失效的数据块之外的其他数据块，从而能够基于校验数据和其他数据块恢复失效的数据块。以上对持久化内存存储一个数据条带的情况进行了说明。持久化内存存储至少两个数据条带的情况与上文说明中的相同，此处不再进行赘述。在一些实施方式中，持久化内存对至少两个数据条带进行存储时，至少两个数据条带对应的校验数据分别位于不同的持久化内存中。
综上所述，本申请实施例通过管理芯片控制持久化内存与处理器的连通状态，使得处理器与至少两个持久化内存相连通。由于处理器能够访问与处理器相连通的至少两个持久化内存，且持久化内存能够用于对数据进行持久化存储，因而不仅扩展了用于对数据进行持久化存储的存储容量，避免了发生存储容量不足的情况。还提供了一种对数据进行持久化存储的新的方式，与相关技术中仅通过磁盘对数据进行持久化存储的方式存在不同。
本申请实施例提供了一种计算机系统，该计算机系统包括至少两个计算机设备，计算机设备是图1-图10任一附图对应的计算机设备。至少两个计算机设备互相连接，从而在不同计算机设备之间形成内存池，增加了系统的稳定性和灵活性。
其中，至少两个计算机设备中的第一计算机设备用于向第二计算机设备发送数据，第二计算机设备用于将接收到的数据存储于第二计算机设备的持久化内存中，第一计算机设备为至少两个计算机设备中的任一计算机设备，第二计算机设备为至少两个计算机设备中除第一计算机设备之外的至少一个计算机设备。第二计算机设备将接收到的数据写入第二计算机设备的持久化内存，写入过程参见上文方法实施例中的说明，此处不再进行赘述。示例性地，第一计算机设备通过高速网络向第二计算机设备发送数据，本实施例不对数据在第一计算机设备和第二计算机设备之间的传输方式加以限定。
在示例性实施例中，数据为第一计算机设备的持久化内存中存储的数据。第一计算机设备从第一计算机设备的持久化内存中读取该数据，读取过程参见上文方法实施例的说明， 此处不再加以赘述。
应理解的是，上述处理器可以是中央处理器(Central Processing Unit，CPU)，还可以是其他通用处理器、数字信号处理器(digital signal processing，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field－programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者是任何常规的处理器等。值得说明的是，处理器可以是支持进阶精简指令集机器(advanced RISC machines，ARM)架构的处理器。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线)或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘Solid State Disk)等。
以上所述仅为本申请的实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (16)

  1. 一种计算机设备，其特征在于，所述设备包括：处理器、至少一个管理芯片和至少两个持久化内存，所述至少两个持久化内存通过所述至少一个管理芯片与所述处理器连接，所述至少两个持久化内存中的各个持久化内存用于对数据进行持久化存储；
    所述至少一个管理芯片用于控制各个持久化内存与所述处理器的连通状态；
    所述处理器用于访问与所述处理器连通的至少两个持久化内存中的任一持久化内存。
  2. 根据权利要求1所述的设备，其特征在于，所述设备还包括内存控制器，所述至少两个持久化内存与所述内存控制器连接，所述内存控制器通过所述至少一个管理芯片与所述处理器连接；
    所述处理器用于基于逻辑地址访问所述内存控制器；
    所述内存控制器用于将所述逻辑地址转换为物理地址，基于所述物理地址访问与所述处理器连通的至少两个持久化内存中的任一持久化内存。
  3. 根据权利要求1或2所述的设备，其特征在于，所述处理器包括逻辑控制器，所述逻辑控制器用于存储独立磁盘冗余阵列RAID信息；
    所述处理器用于按照所述逻辑控制器存储的RAID信息访问与所述处理器连通的至少两个持久化内存中的任一持久化内存。
  4. 根据权利要求1-3任一所述的设备，其特征在于，所述处理器包括逻辑控制器，所述逻辑控制器用于对所述至少两个持久化内存进行分区，得到域和命名空间；
    所述处理器用于访问与所述处理器连通的至少两个持久化内存中的任一持久化内存包括的域和命名空间中的至少一个。
  5. 根据权利要求1-4任一所述的设备，其特征在于，所述处理器包括逻辑控制器，所述逻辑控制器用于控制所述至少一个管理芯片，以通过所述至少一个管理芯片控制各个持久化内存与所述处理器的连通状态。
  6. 根据权利要求1-5任一所述的设备，其特征在于，所述管理芯片的数量为至少两个，至少两个管理芯片分别与所述处理器连接，所述至少两个持久化内存中的任一持久化内存通过所述至少两个管理芯片中的任一管理芯片与所述处理器连接。
  7. 根据权利要求1-5任一所述的设备，其特征在于，所述管理芯片的数量为至少两个，至少两个管理芯片中的第一管理芯片与所述处理器连接，所述至少两个管理芯片中的第二管理芯片与所述第一管理芯片连接，所述至少两个持久化内存中的任一持久化内存通过所述第一管理芯片或者所述第二管理芯片与所述处理器连接，所述第一管理芯片为所述至少两个管理芯片中的至少一个管理芯片，所述第二管理芯片为所述至少两个管理芯片中除所述第一管理芯片之外的其他管理芯片。
  8. 根据权利要求1-7任一所述的设备，其特征在于，所述设备还包括易失性内存，所述易失性内存与所述处理器连接，所述处理器还用于访问所述易失性内存。
  9. 一种处理数据的方法，其特征在于，所述方法应用于计算机设备，所述设备包括处理器、至少一个管理芯片和至少两个持久化内存，所述至少两个持久化内存通过所述至少一个管理芯片与所述处理器连接，所述至少两个持久化内存中的各个持久化内存与所述处理器的连通状态均由所述至少一个管理芯片控制，所述各个持久化内存用于对数据进行持久化存储，所述方法包括：
    所述处理器接收数据处理请求；
    所述处理器基于所述数据处理请求访问与所述处理器连通的至少两个持久化内存中的目标持久化内存，以从所述目标持久化内存中读取数据，或者向所述目标持久化内存中写入数据。
  10. 根据权利要求9所述的方法，其特征在于，所述设备还包括内存控制器，所述至少两个持久化内存与所述内存控制器连接，所述内存控制器通过所述至少一个管理芯片与所述处理器连接；
    所述处理器基于所述数据处理请求访问与所述处理器连通的至少两个持久化内存中的目标持久化内存，包括：
    所述处理器基于所述数据处理请求，按照逻辑地址访问所述内存控制器；
    所述内存控制器将所述逻辑地址转换为物理地址，基于所述物理地址访问所述目标持久化内存。
  11. 根据权利要求9或10所述的方法，其特征在于，所述处理器包括逻辑控制器，所述逻辑控制器存储有独立磁盘冗余阵列RAID信息，所述处理器基于所述数据处理请求访问与所述处理器连通的至少两个持久化内存中的目标持久化内存，包括：
    所述处理器基于所述数据处理请求，按照所述逻辑控制器存储的RAID信息访问与所述处理器连通的至少两个持久化内存中的目标持久化内存。
  12. 根据权利要求9-11任一所述的方法，其特征在于，所述处理器包括逻辑控制器，所述方法还包括：
    所述逻辑控制器对所述至少两个持久化内存进行分区，得到域和命名空间；
    所述处理器基于所述数据处理请求访问与所述处理器连通的至少两个持久化内存中的目标持久化内存，包括：
    所述处理器基于所述数据处理请求访问与所述处理器连通的至少两个持久化内存中的目标持久化内存包括的域和命名空间中的至少一个。
  13. 根据权利要求9-12任一所述的方法，其特征在于，所述处理器包括逻辑控制器，所述方法还包括：
    所述逻辑控制器控制所述至少一个管理芯片，以通过所述至少一个管理芯片控制各个持久化内存与所述处理器的连通状态。
  14. 根据权利要求9-13任一所述的方法，其特征在于，所述设备还包括易失性内存，所述易失性内存与所述处理器连接，所述方法还包括：
    所述处理器基于所述数据处理请求访问所述易失性内存，以从所述易失性内存中读取数据，或者向所述易失性内存中写入数据。
  15. 一种计算机系统，其特征在于，所述系统包括至少两个权利要求1-8任一所述的计算机设备，至少两个计算机设备中的第一计算机设备用于向第二计算机设备发送数据，所述第二计算机设备用于将接收到的数据存储于所述第二计算机设备的持久化内存中，所述第一计算机设备为所述至少两个计算机设备中的任一计算机设备，所述第二计算机设备为所述至少两个计算机设备中除所述第一计算机设备之外的至少一个计算机设备。
  16. 根据权利要求15所述的系统，其特征在于，所述数据为所述第一计算机设备的持久化内存中存储的数据。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140264904A1 (en) * 2013-03-13 2014-09-18 Apple Inc. Unified pcb design for ssd applications, various density configurations, and direct nand access
CN108241585A (zh) * 2016-12-23 2018-07-03 北京忆芯科技有限公司 大容量nvm接口控制器
CN108614668A (zh) * 2016-12-12 2018-10-02 北京忆恒创源科技有限公司 基于kv模型的数据访问方法与固态存储设备
CN110096452A (zh) * 2018-01-31 2019-08-06 北京忆恒创源科技有限公司 非易失随机访问存储器及其提供方法
CN110780942A (zh) * 2019-09-29 2020-02-11 华为技术有限公司 系统启动方法、装置、节点设备及计算机可读存储介质

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140264904A1 (en) * 2013-03-13 2014-09-18 Apple Inc. Unified pcb design for ssd applications, various density configurations, and direct nand access
CN108614668A (zh) * 2016-12-12 2018-10-02 北京忆恒创源科技有限公司 基于kv模型的数据访问方法与固态存储设备
CN108241585A (zh) * 2016-12-23 2018-07-03 北京忆芯科技有限公司 大容量nvm接口控制器
CN110096452A (zh) * 2018-01-31 2019-08-06 北京忆恒创源科技有限公司 非易失随机访问存储器及其提供方法
CN110780942A (zh) * 2019-09-29 2020-02-11 华为技术有限公司 系统启动方法、装置、节点设备及计算机可读存储介质

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