WO2023045625A1

WO2023045625A1 - Code block transmission method and apparatus, and storage medium

Info

Publication number: WO2023045625A1
Application number: PCT/CN2022/112712
Authority: WO
Inventors: 单哲; 龚源泉; 龚海东
Original assignee: 苏州盛科通信股份有限公司
Priority date: 2021-09-23
Filing date: 2022-08-16
Publication date: 2023-03-30
Also published as: CN115883689A

Abstract

The present application discloses a code block transmission method and apparatus, and a storage medium. The code block transmission method comprises: determining a counting threshold of a counter that counts clock pulses according to the period of the clock pulses, the bandwidth of a client and the intervals of code blocks transmitted by clients having different bandwidths, where the clients having different bandwidths correspond to different counters; when the counting value of the n-th counter reaches the counting threshold of the n-th counter, a counting flag corresponding to the n-th counter in a register is set to a preset value, where the value of n is less than or equal to N, and N is the number of clients; scanning the register; and when the scanned counting flag corresponding to the m-th counter in the register has the preset value, receiving the code block sent by the client corresponding to the m-th counter or sending the code block to the client corresponding to the m-th counter, where the value of m is less than or equal to N. The present application can conserve chip resources and is feasible, and meets the time interval required by a code block transmission standard.

Description

Code block transmission method, device and storage medium

This application claims the priority of the Chinese patent application with the application number 202111113008.5 and the title of the invention "code block transmission method, device and storage medium" submitted to the China Patent Office on September 23, 2021, the entire contents of which are incorporated by reference in this application middle.

technical field

The present application relates to the technical field of network communication, and in particular to a code block transmission method, device and storage medium.

Background technique

Flexible Ethernet (FlexEthernet, referred to as FlexE) technology is based on Ethernet (Ethernet) technology, developed to meet the needs of high-speed transmission, flexible bandwidth configuration and other requirements.

In flexible Ethernet, according to the relevant standard requirements of OAM (Operation, Administration and Maintenance, operation, management and maintenance), according to the relevant standard requirements of flexible Ethernet OAM, for different types of OAM code blocks, the code block interval is different . For example, the code block interval requirement for transmitting BAS code blocks (Basic basic code blocks) is 16K frames, or 32K, 64K, 128K, 256K, 512K frames under the bandwidth of the FlexE Client (Flexible Ethernet client) to which it belongs. The interval between sending and receiving (K is 1024), and other types of OAM frames are also sent and received based on this interval unit, or with a time unit of 1 second.

Due to the flexibility of 5G (Giga bps (bit per second), rate unit) granularity that can support bandwidth, the bandwidth of each FlexE Client may be different, even if the code block is transmitted at the same code block interval, the FlexE Client transmission with different bandwidth The time interval of the code blocks is also different. If multiple timers are used to realize the time interval required for clients of different bandwidths to reach the code block transmission standard, it will lead to waste of chip resources. If one timer is used to realize the time interval required for clients of different bandwidths to reach the code block transmission standard , it may be difficult to achieve.

Contents of the invention

Embodiments of the present application provide a code block transmission method, device, and storage medium.

The technical scheme of the present application is realized like this:

In a first aspect, a code block transmission method is provided, the method comprising:

According to the period of the clock pulse, the bandwidth of the client, and the code block interval of the client transmitting the code block with different bandwidths, determine the counting threshold for the counter to count the clock pulses; wherein, the counters corresponding to the clients with different bandwidths are different;

When the count value of the nth counter reaches the counting threshold of the nth counter, the counting flag position corresponding to the nth counter in the register is set to a preset value; wherein, the value of n is less than or Equal to N, where N is the number of clients;

scan the register;

When it is scanned that the counting flag corresponding to the mth counter in the register is the preset value, receive the code block sent by the client corresponding to the mth counter or send a message to the mth counter The corresponding client sends the code block, where the value of m is less than or equal to N.

In the above technical solution, the scanning of the register includes:

The register is scanned within a timing period of a timer, wherein the timing period of the timer is less than or equal to a period of the clock pulse.

In the above technical solution, the determination of the counting threshold for the counter to count the clock pulses according to the period of the clock pulse, the bandwidth of the client, and the code block interval of the client transmitting code blocks with different bandwidths includes:

Determine the time interval for transmitting the code block according to the bandwidth of the nth client, the code block interval, and the number of bits contained in each frame in the code block interval;

determining a quotient between the time interval and the period of the clock pulse;

An integer part of the quotient is determined as a count threshold of the nth counter.

In the above technical solution, the method also includes:

When the quotient has a decimal part, record the decimal part of the quotient;

When the product of the fractional part and s is greater than or equal to 1, determine that the maximum value of the count of the nth counter this time is the count threshold plus 1, where s is the nth counter that counts continuously from 0 to all The counting round of this counting that is the above counting threshold.

In the above technical solution, the code blocks include: a first type of code block and a second type of code block, wherein the code block interval of the second type of code block is P of the code block interval of the first type of code block times, the P is a positive integer greater than or equal to 2;

The counting threshold of the nth counter is: determined according to the code block interval of the first type of code block;

When the count value of the nth counter reaches the counting threshold of the nth counter, setting the count flag position corresponding to the nth counter in the register as a preset value, including:

Whenever the count value of the nth counter reaches the counting threshold of the nth counter, set the count flag position corresponding to the first type code block of the nth counter in the register to the the above preset values; and/or,

When the count value of the nth counter reaches the counting threshold of the nth counter continuously for P times, the counting flag position corresponding to the second type code block of the nth counter in the register is set to the the default value mentioned above.

In the above technical solution, the code blocks further include a third type of code block, wherein the time interval for the nth client to transmit the third type of code block is that the nth client transmits the first q times the time interval of the class code block, the interval unit of the time interval is different from the interval unit of the code block interval, and the q is a positive integer greater than or equal to 2;

When the count value of the nth counter reaches the counting threshold of the nth counter, setting the counting flag position corresponding to the nth counter in the register as a preset value also includes:

When the count value of the nth counter reaches the counting threshold of the nth counter for q consecutive times, the counting flag position corresponding to the third type code block of the nth counter in the register is set to the the default value mentioned above.

In the above technical solution, the method also includes:

If the code block sent by the client corresponding to the mth counter is not received for the preset consecutive times, a timeout alarm is generated; wherein, the preset consecutive times are: the count value of the mth counter reaches consecutively The number of count thresholds for the mth counter.

In a second aspect, a code block transmission device is provided, the device comprising:

The determination module is configured to determine the counting threshold for the counter to count the clock pulses according to the period of the clock pulse, the bandwidth of the client, and the code block interval of the client with different bandwidths to transmit code blocks; wherein, the client with different bandwidths The counters corresponding to the terminals are different;

The setting module is configured to set the count flag position corresponding to the nth counter in the register as a preset value when the count value of the nth counter reaches the counting threshold of the nth counter; wherein, The value of n is less than or equal to N, where N is the number of clients;

a scanning module configured to scan the register;

The transmission module is configured to receive the code block sent by the client corresponding to the mth counter or send the code block to the The client corresponding to the mth counter sends the code block, where the value of m is less than or equal to N.

In a third aspect, an electronic device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the code described in any one of the first aspect. block transfer method.

In a fourth aspect, a computer-readable storage medium is provided, and a computer program is stored in the storage medium, wherein the computer program is configured to execute the code block transmission method described in any one of the first aspect when running.

In the technical solution provided by this application, since the counting threshold for the counter to count the clock pulses is determined according to the period of the clock pulse, the bandwidth of the client, and the interval between code blocks transmitted by clients with different bandwidths, the corresponding The counters are different. In this way, compared with the time interval required for clients with different bandwidths to reach the code block transmission standard using multiple timers, the counters corresponding to different bandwidth clients in this application share the same clock pulse for counting, which is equivalent to For different bandwidth clients, only one timer is used to realize pulse counting, which can greatly save chip resources; in addition, since the same main frequency/frequency division pulse signal does not need to be used as the least common divisor of different time intervals, there is no need to be limited Due to the size of the pulse signal, it is more feasible to determine the counting threshold of the counters corresponding to the clients with different bandwidths to count the clock pulses; in addition, by the count value of the nth counter reaching the nth counter When counting the threshold, set the counting flag position corresponding to the nth counter in the register as the preset value, scan the register, and when the counting flag bit corresponding to the mth counter in the register is scanned as the preset value, receive the mth counter The code block sent by the client corresponding to the counter or the code block sent to the client corresponding to the mth counter, where the value of m is less than or equal to N, thus fully considering chip resource conservation and feasibility, it can be guaranteed The time accuracy of the code block transmission meets the time interval requirements required by the code block transmission standard.

Description of drawings

Figure 1a is a schematic flow diagram of a design scheme using multiple timers;

Figure 1b is a schematic flow diagram of a design scheme using a timer;

FIG. 2 is a schematic flowchart of a code block transmission method provided in an embodiment of the present application;

FIG. 3 is another schematic flowchart of a code block transmission method provided in an embodiment of the present application;

FIG. 4 is another schematic flowchart of a code block transmission method provided by an embodiment of the present application;

FIG. 5a is a schematic diagram of a two-level timer framework in the code block transmission method provided by the embodiment of the present application;

Figure 5b is the pseudo-code logic of the method of using the timer counter register provided by the embodiment of the present application:

FIG. 5c is a flow chart of a code block transmission method based on a two-stage timer provided in an embodiment of the present application;

Figure 5d is a flow chart of the timer-triggered BAS overtime processing mechanism provided by the embodiment of the present application;

FIG. 5e is a flow chart of the timeout count update processing mechanism in the receiving direction provided by the embodiment of the present application;

FIG. 6 is a schematic structural diagram of a code block transmission device provided by an embodiment of the present application;

FIG. 7 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of the application clearer, the technical solutions in the embodiments of the application will be clearly and completely described below in conjunction with the drawings in the embodiments of the application. Obviously, the described embodiments are only It is a part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application. In the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other. The steps shown in the flowcharts of the figures may be performed in a computer system, such as a set of computer-executable instructions. Also, although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that shown or described herein.

It should be noted that, unless the context clearly requires, the words "include", "include" and other similar words in the entire specification and claims should be interpreted as an inclusive meaning rather than an exclusive or exhaustive meaning; that is, " including but not limited to ".

In addition, in the description of the present application, it should be understood that the terms "first", "second" and so on are only used for descriptive purposes, and should not be understood as indicating or implying relative importance. In addition, in the description of the present application, unless otherwise specified, "plurality" means two or more.

According to the relevant standard requirements of the flexible Ethernet OAM, the time intervals for different types of OAM code blocks are different. For the BAS code block (Basic basic code block), the function of this code block is to regularly monitor the basic code block of the FlexE Client (flexible Ethernet client), and the code block interval for transmitting this code block is required to be 16K/32K/64K/128K /256K/512K block (data frame), the data frame adopts 66bit/64bit (binary digit, bit, the smallest unit of measurement information), that is, the actual effective data of each frame is 8Byte (byte). For the APS code block (the code block used for protection switching), when a link failure is detected, three APS code blocks need to be sent consecutively with the same code block interval as the BAS code block. For other code blocks, such as CV code block (connectivity verification code block), 1DM code block (one-way delay code block), 2DMM code block (two-way delay measurement code block), 2DMR (two-way delay response code block) , CS code block (customer signal indication code block), all take 1 second, 10 seconds or 1 minute as the time unit.

Due to the flexibility of the FlexE Client bandwidth of Flexible Ethernet, Flexible Ethernet defines the bandwidth of its FlexE Client with 5G as the minimum unit, which can be combined, and the maximum capability supported by the chip, such as 400G or 800G. For a simple example, it can support 25G, or 50G, or 105G, or 195G, and so on. Bandwidth combinations in units of 5G. Therefore, when the code block intervals of the FlexE Client transmission code blocks of different bandwidths are the same, the time interval of the transmission code blocks It is different. For example, if 16K frames are used as the block interval for transmitting BAS code blocks, the time interval for transmitting BAS code blocks between FlexE Client with 25G bandwidth and FlexE Client with 50G bandwidth is different.

The implementation method of the general timer is: do frequency division configuration according to the main frequency of the chip, take the main frequency as the minimum unit, update the counter, and trigger a certain operation process by configuring the threshold value reached by the counter, so as to realize the timing function. For example, assuming that the main frequency of the chip is 500MHz (Mega Hertz, frequency unit, megahertz), if you want to configure a 1ms (millisecond, millisecond) timer, you need to design a counter. Add 1 operation, when the counter reaches 500M/1000/1, that is, 500000, it means that it reaches 1ms, and a certain operation will be performed at this time.

Facing the flexibility of 5G granularity that can support bandwidth and the requirements of OAM-related standards, in order to realize the code block transmission of FlexE Client with different bandwidths, there are generally two schemes from the design point of view.

Solution 1: As shown in Figure 1a, Figure 1a is a flow diagram of the design scheme using multiple timers. Since the bandwidth of each FlexE Client may be different, the threshold configuration of the counter has no certain calculation relationship, and it needs to be specific to each FlexE Client. The client designs a timer respectively, and the timer time can be set according to different bandwidths. Although this solves the problem of timers, it needs to use a large number of timers, which is a big waste of chip resources.

Solution 2: As shown in Figure 1b, Figure 1b is a schematic flow diagram of the design scheme using a timer. Using a timer, all time units with different bandwidths are generated from this timer. On a timer, by configuring Different accumulation registers of timing counters and different thresholds can achieve the functions of different time intervals. However, due to the diversity of FlexE Client bandwidth, if a FlexE Client needs to support 55G bandwidth, it is calculated according to the time interval of 16K frames: 64bit*16K/55G＝19065.018ns (nanosecond, nanosecond), another FlexE Client needs to support 105G, it is calculated according to the time interval of 16K frames as 64bit*16K/105G=9986.438ns, using the same main frequency/frequency division pulse signal, that is, it is necessary to find the least common divisor of the time interval between the two before using this method to configure different The timing counter to achieve the purpose of using a timer. And, with the bandwidth granularity of 5G, it is very likely that the least common divisor of the time interval of 16K frames of all bandwidths needs to reach the level of 1ns or less than 1ns, and even if the main frequency of the chip can meet the pulse granularity of 1ns, but in 1ns Within the specified time, the chip cannot complete the operations that need to be done after the timer reaches the threshold, such as sending FlexE OAM code blocks. Therefore, this plan is not feasible.

In view of this, the embodiment of the present application provides a code block transmission method, which can ensure the time accuracy of code block transmission and meet the time interval requirements required by the code block transmission standard while fully considering chip resource saving and feasibility. . The method can be executed by a code block transmission device, the device can be implemented in the form of software and/or hardware, and can be deployed in a switching chip supporting FlexE OAM, the chip can be an Application Specific Integrated Circuit (Application Specific Integrated Circuit, referred to as ASIC) chip, or Field Programmable Gate Array (Field Programmable Gata Array, referred to as FPGA) chip, or NP (Network Processor, network processor), etc., can be adjusted according to the actual situation.

Referring to Figure 2, an embodiment of the present application provides a code block transmission method, which may include:

S11. Determine the counting threshold for the counter to count the clock pulses according to the period of the clock pulse, the bandwidth of the client, and the code block interval of the code block transmitted by the client with different bandwidths; wherein, the counters corresponding to different bandwidth clients are different.

Wherein, the clock pulse may be a time pulse signal obtained by frequency-dividing the main frequency generated by the switch chip, and each time a clock pulse is generated, the count of the activated counter will increase by one. Here, the period of the clock pulse can be set according to actual needs, preferably, the period of the clock pulse is set to 32 ns. Here, the activated counter may be a counter corresponding to the client that needs to perform code block transmission between the current devices.

Wherein, the client can be a flexible Ethernet client FlexE Client, and under its own bandwidth, send or receive OAM code blocks according to the code block interval required by the OAM standard. Here, there are multiple clients, and the bandwidth of multiple clients can be Some of them may be the same, or they may all be different.

Wherein, the code block interval may be a specified number of data frames required by the code block transmission standard. For example, when the code block interval of the transmission code block is 16K data frames, it means that a code block is transmitted every 16K data frames, in which, the data frame adopts 66bit/64bit encoding, and the actual effective data of each frame is 8Byte.

The counter that is set to count clock pulses is a count register, and the count threshold that is set to record counters to clock pulses is a configuration register. More specifically, the first count field of the count register is used to record the current count of clock pulses. Counting value, the first configuration field of the configuration register is used to record the counting threshold of clock pulses.

It can be understood that, under the same code block interval, counters corresponding to different bandwidth clients have different counting thresholds for counting clock pulses.

S12. When the counting value of the nth counter reaches the counting threshold of the nth counter, set the counting flag position corresponding to the nth counter in the register as a preset value; wherein, the value of n is less than or equal to N, N is the number of clients.

Among them, when the counting value of the nth counter corresponding to the nth client reaches the counting threshold of the nth counter, the counting value of the nth counter is cleared, and the counting corresponding to the nth counter in the register is triggered The logo position is the default value. Wherein, the corresponding counting flag bit of the counter in the register adopts different values to indicate whether the counting value of the counter reaches the counting threshold.

During specific implementation, the register may use the binary bits in the bitmap data structure as the counting flag bits corresponding to the counter. Here, the bitmap data structure refers to a data structure using a bitmap type field, each bit in the field represents a counter (or the client corresponding to the counter), and each bit is represented by 0 The count value of the counter does not reach the count threshold, and 1 is used to indicate that the count value of the counter reaches the count threshold; or, 0 is used to indicate that the count value of the counter has reached the count threshold, and 1 is used to indicate that the count value of the counter has not reached the count threshold.

When the counting value of a certain counter reaches the counting threshold of the counter, the bit representing the counter is set in the register to a preset value indicating reaching the counting threshold.

S13. Scanning registers.

In one embodiment, the registers may be scanned repeatedly;

In another embodiment, specifically, according to the timing period of the timer, the counting flags corresponding to different counters in the register can be scanned, and when a counting flag is scanned, it is determined whether the value of the counting flag is default value.

S14. When it is scanned that the counting flag corresponding to the mth counter in the register is a preset value, receive the code block sent by the client corresponding to the mth counter or send the code block to the client corresponding to the mth counter, Wherein, the value of m is less than or equal to N.

In one example, the code block transmission device is located in the exchange chip as the receiving end, and when the count flag bit corresponding to the m-th counter in the register is scanned to be a preset value, it means: the client corresponding to the m-th counter has been received The time interval of the code blocks sent by the end, at this time, the code block transmission device receives the code blocks sent by the client corresponding to the mth counter;

In another example, the code block transmission device is located in the switching chip as the sending end, and when the count flag bit corresponding to the m-th counter in the register is scanned to be a preset value, it means: the counter corresponding to the m-th counter has been reached The time interval for the client to send the code block. At this time, the code block transmission device sends the code block to the client corresponding to the mth counter.

In the embodiment of the present application, when the code block is transmitted, since the counting threshold for the counter to count the clock pulses is determined according to the cycle of the clock pulse, the bandwidth of the client, and the code block interval for different bandwidth clients to transmit code blocks, different bandwidth clients The corresponding counters are different. In this way, compared with the time interval required for clients with different bandwidths to reach the code block transmission standard by using multiple timers, the counters corresponding to clients with different bandwidths in this application share the same clock pulse for counting. It is equivalent to using only one timer to realize pulse counting for different bandwidth clients, which can greatly save chip resources; in addition, since the same main frequency/frequency division pulse signal does not need to be used as the least common divisor of different time intervals, there is no need to be affected by Limited to the size of the pulse signal, it is only necessary to determine the counting threshold of the counters corresponding to the clients of different bandwidths to count the clock pulses, which is more feasible; in addition, through the count value of the nth counter to reach the nth counter When the counting threshold is set, the counting flag position corresponding to the nth counter in the register is set as the preset value, and the register is scanned. When the counting flag bit corresponding to the mth counter in the register is scanned to be the preset value, the mth counter is received The code block sent by the client corresponding to the counter or the code block sent to the client corresponding to the m-th counter, wherein the value of m is less than or equal to N, thus fully considering the resource saving and feasibility of the chip. Ensure the time accuracy of code block transmission and meet the time interval requirements required by code block transmission standards.

In one embodiment, as shown in FIG. 3, in the above step S11, the counting threshold for the counter to count the clock pulses is determined according to the cycle of the clock pulses, the bandwidth of the client, and the code block intervals of the code blocks transmitted by clients with different bandwidths, Can include:

S111. Determine a time interval for transmitting code blocks according to the bandwidth of the nth client, the code block interval, and the number of bits included in each frame in the code block interval.

Wherein, the bandwidth of the client is negatively correlated with the time interval at which the client transmits code blocks.

Specifically, the product of the code block interval and the number of bits contained in the code block is determined, and the quotient between the product and the bandwidth of the nth client is taken as the time interval for the nth client to transmit the code block.

For example, taking the code block as a BAS code block as an example, assuming that the bandwidth of the nth client is 55G, the code block interval for transmitting BAS code blocks is 16K frames, and the number of bits contained in each frame is 64 bits, then the nth client The time interval for transmitting code blocks is calculated as: 64bit*16K/55G=19065.018ns.

S112. Determine the quotient between the time interval and the period of the clock pulse.

Here, the quotient between the time interval and the period of the clock pulse can be understood as the number of pulses of the clock pulse within the time interval, and the number of pulses can be a non-integer value.

S113. Determine the integer part of the quotient as the counting threshold of the nth counter.

Specifically, the configuration register of the nth counter stores a first configuration field and a second configuration field. The first configuration field is used to configure the counting threshold of the nth counter, that is, the integer part of the quotient between the time interval of the nth client transmitting the code block and the period of the clock pulse; the second configuration field is used to configure the nth counter The configuration value for the fractional count portion of the counter.

In one embodiment, as shown in Figure 4, based on Figure 3, the method may further include:

S114. When the quotient has a decimal part, record the decimal part of the quotient.

Specifically, for the time interval for the nth client to transmit the code block, the fractional part of the quotient between the time interval and the period of the clock pulse can be used as the configuration value of the fractional count part of the nth counter and configured in the configuration register in the second configuration field within the .

Exemplarily, assuming that the bandwidth of the nth client is 55G, the code block is transmitted at a code block interval of 16K data frames, and its transmission time interval is 19065.018ns. For a time pulse with a pulse period of 32ns, the required number of pulses is : 19065.018/32=595.782, in order to achieve a more precise time interval, in addition to using the integer part 595 of the pulse number as the configuration value of the counting threshold of the nth counter in the first configuration field in the configuration register, you can also In the second configuration field in the configuration register, the fractional part of the pulse number 0.782 is used as the configuration value of the fractional counting part of the nth counter.

S115. When the product of the fractional part and s is greater than or equal to 1, determine that the maximum value of the current count of the nth counter is the counting threshold plus 1, where s is the current count of the nth counter continuously counting from 0 to the counting threshold The counting rounds to count.

Specifically, when the product of the fractional part and s is greater than or equal to 1, the value of the product is recorded in the second counting field of the counting register in the nth counter, and the first counting of the counting register in the nth counter The field is used to record the current counting value of the clock pulse by the nth counter.

In this embodiment, by counting the counting rounds of the nth counter continuously from 0 to the counting threshold, and counting the fractional part of the number of clock pulses in the time interval of the nth client transmitting the code block Product operation, and when the result of the product operation is greater than or equal to 1, determine the maximum value of the current count of the nth counter as the count threshold plus 1, which not only enables the counting process of the fractional part to be approximately averaged in multiple pulse periods , and it is beneficial to further improve the time precision of code block transmission.

In one embodiment, the code blocks include: a first type of code block and a second type of code block, wherein the interval between the code blocks of the second type of code block is P times the interval between the code blocks of the first type of code block, and P is greater than or a positive integer equal to 2; the counting threshold of the nth counter is determined according to the code block interval of the first type of code block.

Here, for the convenience of description, the code block interval of the first type of code blocks may be recorded as the first code block interval, and the code block interval of the second type of code blocks may be recorded as the second code block interval. Here, the first code block interval may be 16K data frames, and the second code block interval may be 32K data frames, 64K data frames, 128K data frames, 256K data frames or 512K data frames, but this embodiment of the application is not limited thereto.

The first code block interval may be the minimum code block interval supported by the corresponding client, and the second code block interval may be P times the minimum code block interval.

Wherein, the counting threshold of the nth counter is determined according to the code block interval of the first type of code block, including:

According to the period of the clock pulse, the bandwidth of the nth client, and the code block interval of the first type of code block, determine the counting threshold for the nth counter to count the clock pulses.

Specifically, for the implementation process of this step, reference may be made to step S111 to step S113 in the above embodiment, which will not be repeated here.

In the above step S12, when the count value of the n counter reaches the count threshold of the n counter, the count flag position corresponding to the n counter in the register is set as a preset value, which may include steps S121 and S122. at least one:

S121. Whenever the counting value of the nth counter reaches the counting threshold of the nth counter, set the counting flag position in the register corresponding to the first type code block of the nth counter as a preset value.

In this embodiment, since the counting threshold of the nth counter is determined according to the code block interval of the first type of code block, when the counting value of the nth counter reaches the counting threshold of the nth counter, it indicates that the nth counter The corresponding nth client has reached the code block interval for transmitting the first type of code block, by setting the count flag position corresponding to the first type of code block of the nth counter in the register as a preset value, so that the scan register During the process, it will be scanned that the counting mark position corresponding to the first type of code block of the nth counter in the register is the preset value, so as to receive the first type of code block sent by the nth client or send a message to the nth client The terminal sends the first type of code block, so that clients with different bandwidths can transmit the first type of code block according to the code block transmission standard, and the time accuracy of the code block transmission can be guaranteed.

S122. When the counting value of the nth counter reaches the counting threshold of the nth counter for P consecutive times, set the counting flag position in the register corresponding to the second type code block of the nth counter as a preset value.

In this embodiment, because the code block interval of the second type of code block is P times of the code block interval of the first type of code block, and because the counting threshold of the nth counter is determined according to the code block interval of the first type of code block , then when the counting value of the nth counter reaches the counting threshold of the nth counter for P consecutive times, it indicates that the nth client corresponding to the nth counter has reached the code block interval for transmitting the second type of code block, through The counting flag position corresponding to the second type code block of the nth counter in the register is a preset value, so that in the process of scanning the register, it will be scanned to correspond to the second type code block of the nth counter in the register The position of the counting flag is a preset value to receive the second type of code block sent by the nth client or send the second type of code block to the nth client, so that clients with different bandwidths can perform code block transmission according to the code block transmission standard The code block of the second type is transmitted, and the time accuracy of the code block transmission can be guaranteed. In one embodiment, the code block further includes a third type of code block, wherein the time interval for the nth client to transmit the third type of code block is q times the time interval for the nth client to transmit the first type of code block , the interval unit of the time interval is different from that of the code block interval, and q is a positive integer greater than or equal to 2.

Here, the time interval may be a second-level time as an interval unit, and the code block interval may be a data frame number as an interval unit. As an example, the third type of code block can be a CV code block that is transmitted in seconds or minutes, and the first type of code block can be a BAS code block or an APS code block that is transmitted at a 16K data frame interval. etc., but the embodiment of the present application is not limited thereto.

Among them, the time interval for the nth client to transmit the first type of code block can be determined in the following manner:

According to the bandwidth of the nth client, the code block interval at which the nth client transmits the first type of code block, and the number of bits contained in each frame code block within the code block interval, determine that the nth client transmits the first type of code block time interval.

In the above step S12, when the count value of the n counter reaches the count threshold of the n counter, the count flag position corresponding to the n counter in the register is a preset value, and may also include:

S123. When the counting value of the nth counter reaches the counting threshold of the nth counter for q consecutive times, set the counting flag position in the register corresponding to the third type code block of the nth counter as a preset value.

In this embodiment, since the time interval for the nth client to transmit the third type of code block is q times the time interval for the nth client to transmit the first type of code block, the count value of the nth counter is continuous for q When the counting threshold of the nth counter is reached for the first time, it indicates that the nth client has reached the time interval for transmitting the third type of code block, and the position of the count flag corresponding to the third type of code block of the nth counter in the register is In this way, in the process of scanning the register, the counting flag position corresponding to the third type code block of the nth counter in the register will be scanned as the preset value, so as to receive the third code block sent by the nth client Class code block or send the third type of code block to the nth client, so that clients with different bandwidths can transmit the third type of code block according to the code block transmission standard, and the time accuracy of code block transmission can be guaranteed.

In one embodiment, in the above step S13, scanning the register may include:

The register is scanned within a timing period of the timer, wherein the timing period of the timer is less than or equal to the period of the clock pulse.

Wherein, the timer may be a timer to which the register belongs, that is, a second-level timer.

Among them, the timing period of the timer is an adjustable value, which can be adjusted within the allowable range of the chip design, and scan the register with a smaller timing period as much as possible. It can be understood that the smaller the timing period of the timer, The more the code block transmission time accuracy can be improved, preferably, the timing period of the timer is set to 8 ns.

In one embodiment, the method may also include:

If the code block sent by the client corresponding to the m-th counter is not received for the preset consecutive times, a timeout alarm will be generated; where the preset consecutive times are: the count value of the m-th counter reaches the count of the m-th counter continuously Threshold times.

Wherein, the preset consecutive times can be set according to the actual application, for example, it is set to 3, that is, if the code block sent by the client corresponding to the m-th counter is not received for 3 consecutive times, a timeout alarm is generated.

It should be noted that when the number of consecutive code blocks sent by the client corresponding to the m-th counter is not received is lower than the preset consecutive number of times, a timeout alarm will not be generated.

Next, the code block transmission method provided by the embodiment of the present application will be described with reference to FIG. 5a to FIG. 5e.

Take the FlexE Client that supports 800G in total as an example. When the 5G bandwidth is the minimum bandwidth granularity, there are at most 800/5(G)=160 FlexE Clients. The 16K data frame is used as the code block interval of each FlexE Client transmission code block.

As shown in Figure 5a, in the first-level timer, a counter is set for each FlexE Client, and each counter includes a counting register and a configuration register. The counting register is DsFlexEOamTxScanCounter, and the counting register holds two fields: counter and counterFrac , counter is used to save the integer part of the current timer count, and counterFrac is used to save the fractional part of the current timer count. The configuration register is DsFlexEOamTxScanCfg, which saves two fields: counterThrd and counterFracCfg, counterThrd is used to configure the counting threshold for the FlexE Client 16K data frame, and counterFracCfg is used to configure the configuration value of the fractional part of each pulse update.

In the second-level timer, the trigger register is set as FlexEOamTxScanBitmap, and this register holds a field, which is updateEnBitmap (data update bitmap). This field can be a bitmap type, that is, each bit in it represents a FlexE Client, and when it is 1, it means that the 16K frame time interval of the current FlexE Client has been reached.

Figure 5b is the pseudo code logic of the usage method of the timer counter register. Considering that the 32ns time pulse is used as a fixed pulse, it is generally not divisible for different bandwidths. Taking the 55G bandwidth as an example, according to the calculation in the previous embodiment, the time interval for the code block to be transmitted with 16K data frames as the code block interval is 19065.018ns , for a time pulse of 32ns, 19065.018/32=595.782 is required. To achieve a precise time interval, DsFlexEOamTxScanCfg.countertThrd can be configured as 595, and DsFlexEOamTxScanCfg.counterFracCfg is about 0.C8H. According to the pseudo-code logic in Fig. 5b, the required time interval can be achieved. In particular, considering that special-purpose switching chips generally do not support decimal operations, using the pseudo-code logic here, every time counterThrd is reached, the decimal counting part is incremented, and when the decimal part is carried, the threshold for meeting the condition next time needs to be increased by 1 , that is, DsFlexEOamTxScanCounter.counterFrac[8] is 1, so that the decimal counting process is approximately averaged in multiple cycles.

When the count value of the nth counter reaches the counting threshold of the nth counter, set the bit of the FlexE Client corresponding to the nth counter in FlexEOamTxScanBitmap.updateEnBitmap to 1, indicating that the FlexE Client corresponding to the nth counter has reached the 16K frame The time trigger condition can be used for timing processing of the second-level timer to trigger subsequent operations.

It should be noted that the DsFlexEOamTxScanCounter and DsFlexEOamTxScanCfg registers need to save relevant counters and configurations for each FlexE Client, so that FlexE Clients with different bandwidth rates can have different time interval configurations.

The second-level timer can use an 8ns fixed polling timer to process the follow-up processing of the FlexE Client corresponding to a bit in FlexEOamTxScanBitmap.updateEnBitmap that is 1 every 8ns. Here 8ns is an adjustable value, which can be adjusted within the allowable range of the chip design, and the follow-up processing should be performed with a smaller polling time as much as possible.

As shown in Figure 5c, based on the timing processing of the first-level timer and the second-level timer, when the processing logic proceeds to the function processing module, it means that the time interval of the 16K data frame corresponding to the bandwidth of the current FlexE Client has been reached. Other code block intervals can be obtained from multiple processing of the code block interval of the 16K data frame. For example, the transmission of BAS code blocks needs to support the code block interval of 16K/32K/64K/128K/256K/512K.

Optionally, a counting register, called BasPeriodCounter, can be added to the BAS Period Counter (basic code block overtime counter) module of the function processing module, which is used to configure multiples of 16K. For example, the current FlexE Client needs to be configured as a code of 64K frames. block interval, configure the count value to 4. When BasPeriodCounter is not 0, do not process, wait for the next round of 16K frame code block interval trigger; when BasPeriodCounter is reduced to 0, trigger the sending of BAS frame, and set BasPeriodCounter to the initial value 4, wait for the next round of 16K Trigger on the code block interval of the frame.

Optionally, for other frames that need to be sent at a second-level rate, the previously calculated 16K frame time interval corresponding to the current FlexE Client bandwidth is calculated to a multiple of 1 second. For example, taking the 55G bandwidth as an example, the corresponding 16K frame time interval The time interval is 19065.018ns, then the multiple value of 1 second can be configured as 52452, and the decimal processing can be omitted under the premise of allowing a certain error. Here you can configure OneSecPeriodCounter (1-second period count value) to 52452. The processing flow is similar to BasPeriodCounter. When OneSecPeriodCounter decreases to 0, it means that the 1-second time interval is triggered.

Optionally, similar processing is performed for different OAM frames that require second-level time intervals, and a CV code block is used as an example here. If the CV code block generation rate needs to be set to 1 second, then configure the initial value of CVPeriodCounter (connectivity verification code block period count) to 1, and by analogy, if it needs to be set to 10 seconds, then configure the initial value of CVPeriodCounter to 10. 1 minute , set it to 60. Use similar logic later, when CVPeriodCounter is 0, trigger sending CV frame, and restore CVPeriodCounter to the initial value. Other second-level OAM frames are processed using similar logic.

FIG. 5d is a schematic diagram of a timer-triggered BAS timeout processing mechanism provided by an embodiment of the present application, and FIG. 5e is a flow chart of a timeout count update processing mechanism in the receiving direction. As shown in Figure 5d, the BasExpiredCount (basic code block timeout counter) minus 1 operation is triggered at a time interval of 16K frames. BasExpiredCount is used to configure the preset consecutive times for timeout alarms. When BasExpiredCount is reduced to 0, it is considered that a timeout occurs. Trigger an alert. At the same time, as shown in Figure 5e, in the receiving direction, when BAS is received, BasExpiredCount will be updated to the pre-configured preset consecutive times. For example, if it is necessary to consider that BAS has not been received for three consecutive 16K frame interval periods, it is timed out. Then configure this pre-configured default number of consecutive times to be 3. Through the timing decrement of the timer and the refresh processing of the receiving direction, the timeout alarm mechanism can be realized.

In summary, this application uses two-level timers, and only two timers are needed. By cascading the two-level timers, while ensuring the transmission time accuracy of the FlexE OAM (Flexible Ethernet Operation, Management and Maintenance) frame, Fully consider the resource saving and feasibility of chip design, and meet the time interval requirements required by the standard. At the same time, based on the two-level timer, a set of processing procedures can be used for the time interval processing of different FlexE OAM frame types, which can support various time intervals required by the standard and has strong scalability.

It should be noted that although this application is aimed at the code block transmission method based on the two-level timer brought by the flexible bandwidth of FlexE OAM. However, this idea can be used in the chip-level processing of similar code block transmission requirements based on two-level timers, and is not limited to the single scenario of FlexE OAM.

As shown in Figure 6, an embodiment of the present application provides a code block transmission device, which may include:

The determination module 601 is configured to determine the counting threshold for the counter to count the clock pulses according to the period of the clock pulse, the bandwidth of the client, and the code block interval of the code blocks transmitted by the clients of different bandwidths; wherein, the counters corresponding to different bandwidth clients are different ;

The setting module 602 is configured to set the counting flag position corresponding to the nth counter in the register as a preset value when the count value of the nth counter reaches the counting threshold of the nth counter; wherein, the value of n is less than Or equal to N, where N is the number of clients;

The scanning module 603 is configured as a scanning register;

The transmission module 604 is configured to receive the code block sent by the client corresponding to the m-th counter or send the code block to the client corresponding to the m-th counter when the counting flag bit corresponding to the m-th counter in the register is scanned to be a preset value. The terminal sends a code block, where the value of m is less than or equal to N.

In one embodiment, the scanning module is specifically configured to:

In one embodiment, the determining module is specifically configured to:

Determine the time interval for transmitting code blocks according to the bandwidth of the nth client, the code block interval, and the number of bits contained in each frame in the code block interval;

Determine the quotient between the time interval and the period of the clock pulse;

The integer part of the quotient is determined as the count threshold of the nth counter.

In one embodiment, the determining module is further configured to:

When the quotient has a decimal part, record the decimal part of the quotient;

When the product of the fractional part and s is greater than or equal to 1, determine that the maximum value of the current count of the nth counter is the count threshold plus 1, where s is the current count of the nth counter that counts continuously from 0 to the count threshold Count rounds.

In one embodiment, the code blocks include: a first type of code block and a second type of code block, wherein the interval between the code blocks of the second type of code block is P times the interval between the code blocks of the first type of code block, and P is greater than or a positive integer equal to 2; the counting threshold of the nth counter is: determined according to the code block interval of the first type of code block;

Setup modules include:

The first setting unit is configured to set the counting flag position corresponding to the first type code block of the nth counter in the register as a preset value whenever the counting value of the nth counter reaches the counting threshold of the nth counter ;

The second setting unit is set to when the counting value of the nth counter reaches the counting threshold value of the nth counter for P consecutive times, the counting flag position corresponding to the second type code block of the nth counter in the register is set as a preset set value.

In one embodiment, the code block further includes a third type of code block, wherein the time interval for the nth client to transmit the third type of code block is q times the time interval for the nth client to transmit the first type of code block , the interval unit of the time interval is different from that of the code block interval, and q is a positive integer greater than or equal to 2:

The setup module also includes:

The third setting unit is set to when the counting value of the nth counter reaches the counting threshold of the nth counter for q consecutive times, the counting flag position corresponding to the third type code block of the nth counter in the register is set as a preset set value.

In one embodiment, the device also includes:

The alarm module is set to generate a timeout alarm if the code block sent by the client corresponding to the m-th counter is not received for the preset consecutive times; wherein, the preset consecutive times are: the count value of the m-th counter continuously reaches The number of count thresholds for the mth counter.

It should be noted that: when the code block transmission device provided by the above-mentioned embodiments executes the code block transmission method, the division of the above-mentioned program modules is used as an example for illustration. In practical applications, the above-mentioned processing can be assigned to different programs according to needs. Module completion means that the internal structure of the device is divided into different program modules to complete all or part of the processing described above. In addition, the code block transmission device and the code block transmission method embodiment provided by the above embodiment belong to the same concept, and the specific implementation process thereof is detailed in the method embodiment, and will not be repeated here.

An embodiment of the present application also provides an electronic device, including: a memory, a processor, and a computer program stored on the memory and operable on the processor, wherein: when the processor executes the computer program, any one of the embodiments described in the present application is implemented. The steps of the code block transmission method.

FIG. 7 shows a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present application. The electronic device 700 shown in FIG. 7 includes: at least one processor 701 , a memory 702 , and at least one network interface 703 . Various components in the electronic device 700 are coupled together through a bus system 704 . It can be appreciated that the bus system 704 is configured to implement connection communication between these components. In addition to the data bus, the bus system 704 also includes a power bus, a control bus and a status signal bus. However, for clarity of illustration, the various buses are labeled as bus system 704 in FIG. 7 .

It can be understood that the memory 702 may be a volatile memory or a non-volatile memory, and may also include both volatile and non-volatile memories.

The memory 702 in the embodiment of the present application is configured to store various types of data to support the operation of the electronic device 700 . Examples of these data include: any computer program for operating on the electronic device 700, such as an executable program, and the program for implementing the method in the embodiment of the present application may be included in the executable program.

The embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps in the code block transmission method described in any one of the embodiments of the present application are implemented.

It should be noted that the storage medium in the embodiment of the present application may be implemented by any type of volatile or non-volatile storage device, or a combination thereof. Among them, the non-volatile memory can be read-only memory (ROM, Read Only Memory), programmable read-only memory (PROM, Programmable Read-Only Memory), erasable programmable read-only memory (EPROM, Erasable Programmable Read-Only Memory) Only Memory), Electrically Erasable Programmable Read-Only Memory (EEPROM, Electrically Erasable Programmable Read-Only Memory), Magnetic Random Access Memory (FRAM, Ferromagnetic Random Access Memory), Flash Memory (Flash Memory), Magnetic Surface Memory , CD, or CD-ROM (Compact Disc Read-Only Memory); magnetic surface storage can be disk storage or tape storage. The volatile memory may be random access memory (RAM, Random Access Memory), which is used as an external cache. By way of illustration and not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM, Static Random Access Memory), Synchronous Static Random Access Memory (SSRAM, Synchronous Static Random Access Memory), Dynamic Random Access Memory Memory (DRAM, Dynamic Random Access Memory), synchronous dynamic random access memory (SDRAM, Synchronous Dynamic Random Access Memory), double data rate synchronous dynamic random access memory (DDRSDRAM, Double Data Rate Synchronous Dynamic Random Access Memory), enhanced Synchronous Dynamic Random Access Memory (ESDRAM, Enhanced Synchronous Dynamic Random Access Memory), Synchronous Link Dynamic Random Access Memory (SLDRAM, SyncLink Dynamic Random Access Memory), Direct Memory Bus Random Access Memory (DRRAM, Direct Rambus Random Access Memory ). The storage medium described in the embodiments of the present application is intended to include but not limited to these and any other suitable types of storage.

In the several embodiments provided in this application, it should be understood that the disclosed devices and methods may be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined or integrated. to another system, or some features may be ignored, or not implemented. In addition, the coupling, or direct coupling, or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical or other forms of.

The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units; Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can be used as a single unit, or two or more units can be integrated into one unit; the above-mentioned integration The unit can be realized in the form of hardware or in the form of hardware plus software functional unit.

Those of ordinary skill in the art can understand that all or part of the steps for realizing the above-mentioned method embodiments can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the Including the steps of the foregoing method embodiments; and the foregoing storage medium includes: a removable storage device, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, etc. A medium on which program code can be stored.

Alternatively, if the above-mentioned integrated units of the present application are realized in the form of software function modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for Make an electronic device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the methods in the various embodiments of the present application. The aforementioned storage medium includes: various media capable of storing program codes such as removable storage devices, ROM, RAM, magnetic disks or optical disks.

The methods disclosed in several method embodiments provided in this application can be combined arbitrarily to obtain new method embodiments under the condition of no conflict.

The features disclosed in several product embodiments provided in this application can be combined arbitrarily without conflict to obtain new product embodiments.

The above is only the specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application, and should cover Within the protection scope of this application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

A code block transmission method, the method comprising:

According to the period of the clock pulse, the bandwidth of the client, and the code block interval of the client transmitting the code block with different bandwidths, determine the counting threshold for the counter to count the clock pulses; wherein, the counters corresponding to the clients with different bandwidths are different;

When the count value of the nth counter reaches the counting threshold of the nth counter, the counting flag position corresponding to the nth counter in the register is set to a preset value; wherein, the value of n is less than or Equal to N, where N is the number of clients;

scan the register;

When it is scanned that the counting flag corresponding to the mth counter in the register is the preset value, receive the code block sent by the client corresponding to the mth counter or send a message to the mth counter The corresponding client sends the code block, where the value of m is less than or equal to N.
The method according to claim 1, wherein said scanning said register comprises:

The register is scanned within a timing period of a timer, wherein the timing period of the timer is less than or equal to a period of the clock pulse.
The method according to claim 1, wherein, according to the period of the clock pulse, the bandwidth of the client, and the code block interval of the client transmitting code blocks with different bandwidths, determine the counting threshold for the counter to count the clock pulses, include:

Determine the time interval for transmitting the code block according to the bandwidth of the nth client, the code block interval, and the number of bits contained in each frame in the code block interval;

determining a quotient between the time interval and the period of the clock pulse;

An integer part of the quotient is determined as a count threshold of the nth counter.
The method according to claim 3, wherein the method further comprises:

When the quotient has a decimal part, record the decimal part of the quotient;

When the product of the fractional part and s is greater than or equal to 1, determine that the maximum value of the count of the nth counter this time is the count threshold plus 1, where s is the nth counter that counts continuously from 0 to all The counting round of this counting that is the above counting threshold.
The method according to any one of claims 1 to 4, wherein,

The code blocks include: a first type of code block and a second type of code block, wherein the interval between the code blocks of the second type of code block is P times the interval between the code blocks of the first type of code block, and the P is a positive integer greater than or equal to 2;

The counting threshold of the nth counter is: determined according to the code block interval of the first type of code block;

When the count value of the nth counter reaches the counting threshold of the nth counter, setting the count flag position corresponding to the nth counter in the register as a preset value, including:

Whenever the count value of the nth counter reaches the counting threshold of the nth counter, set the count flag position corresponding to the first type code block of the nth counter in the register to the the above preset values; and/or,

When the count value of the nth counter reaches the counting threshold of the nth counter continuously for P times, the counting flag position corresponding to the second type code block of the nth counter in the register is set to the the default value mentioned above.
The method according to claim 5, wherein the code blocks further include a third type of code block, wherein the time interval for the nth client to transmit the third type of code block is the nth client The terminal transmits q times the time interval of the first type of code block, the interval unit of the time interval is different from the interval unit of the code block interval, and the q is a positive integer greater than or equal to 2;

When the count value of the nth counter reaches the counting threshold of the nth counter, setting the count flag position corresponding to the nth counter in the register as a preset value, further comprising:

When the count value of the nth counter reaches the counting threshold of the nth counter for q consecutive times, the counting flag position corresponding to the third type code block of the nth counter in the register is set to the the default value mentioned above.
The method according to claim 1, wherein the method further comprises:

If the code block sent by the client corresponding to the mth counter is not received for the preset consecutive times, a timeout alarm is generated; wherein, the preset consecutive times are: the count value of the mth counter reaches consecutively The number of count thresholds for the mth counter.
A code block transmission device, the device comprising:

The determination module is configured to determine the counting threshold for the counter to count the clock pulses according to the period of the clock pulse, the bandwidth of the client, and the code block interval of the client with different bandwidths to transmit code blocks; wherein, the client with different bandwidths The counters corresponding to the terminals are different;

The setting module is configured to set the count flag position corresponding to the nth counter in the register as a preset value when the count value of the nth counter reaches the counting threshold of the nth counter; wherein, The value of n is less than or equal to N, where N is the number of clients;

a scanning module configured to scan the register;

The transmission module is configured to receive the code block sent by the client corresponding to the mth counter or send the code block to the The client corresponding to the mth counter sends the code block, where the value of m is less than or equal to N.
An electronic device, comprising a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the code block described in any one of claims 1 to 7 transfer method.
A computer-readable storage medium, wherein a computer program is stored in the storage medium, wherein the computer program is configured to execute the code block transmission method described in any one of claims 1 to 7 when running.