WO2023045200A1 - 一种cpu性能调节方法、装置及介质 - Google Patents

一种cpu性能调节方法、装置及介质 Download PDF

Info

Publication number
WO2023045200A1
WO2023045200A1 PCT/CN2022/074608 CN2022074608W WO2023045200A1 WO 2023045200 A1 WO2023045200 A1 WO 2023045200A1 CN 2022074608 W CN2022074608 W CN 2022074608W WO 2023045200 A1 WO2023045200 A1 WO 2023045200A1
Authority
WO
WIPO (PCT)
Prior art keywords
cpu
operating frequency
psu
voltage
mapping relationship
Prior art date
Application number
PCT/CN2022/074608
Other languages
English (en)
French (fr)
Inventor
罗嗣恒
孔财
冯子秋
Original Assignee
苏州浪潮智能科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 苏州浪潮智能科技有限公司 filed Critical 苏州浪潮智能科技有限公司
Priority to US18/280,222 priority Critical patent/US20240152191A1/en
Publication of WO2023045200A1 publication Critical patent/WO2023045200A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the technical field of power supply reliability design, and in particular to a CPU performance adjustment method, device and medium.
  • some users will upgrade and reconfigure according to their own business scenarios after purchasing server products. If it is upgraded to a high-power CPU, the PSU model will not be adjusted accordingly. In this way, when the CPU switches to the performance acceleration mode (overclocking), there will be a probability of triggering the PSU over-power protection, resulting in the risk of downtime.
  • Some users will set the PSU power threshold in the system BMC (ie Baseboard Management Controller, Baseboard Management Controller). When the CPU is overclocked, the system power is too high to trigger the threshold value, and the PSU will send an ALERT (alarm) signal to control the CPU to reduce the frequency to overcome the downtime problem.
  • BMC Baseboard Management Controller
  • the purpose of this application is to provide a CPU performance adjustment method, device and medium, which can avoid the problem that the CPU triggers PSU overpower protection or CPU frequency reduction in the overclocking working state, thereby affecting the end user business processing, and Avoid cost escalation.
  • the specific plan is as follows:
  • the present application discloses a method for adjusting CPU performance, including:
  • the first preset mapping relationship is a corresponding relationship between each voltage range and each highest operating frequency.
  • determining the rated power of the PSU powering the current CPU through the BMC includes:
  • the rated power of the PSU is determined according to the product model.
  • the target encoding signal corresponding to the rated power is generated by the BMC based on a second preset mapping relationship; wherein, the second preset mapping relationship is a corresponding relationship between different rated powers and different encoding signals;
  • the outputting the control signal corresponding to the rated power through the CPLD includes:
  • the outputting the control signal corresponding to the rated power through the CPLD includes:
  • the third mapping relationship is a corresponding relationship between different rated powers and different control signals.
  • the outputting the voltage value corresponding to the control signal through the preset conversion unit includes:
  • the reference voltage is a voltage converted by using the power supply voltage of the PSU, and the resistance values of the voltage dividing resistors in different branches of the preset conversion unit are different, and the target branch is the preset Let a branch in the transformation unit be assumed.
  • the determining the highest operating frequency of the CPU in the overclocking state according to the voltage value and the first preset mapping relationship includes:
  • the determining the highest operating frequency of the CPU in the overclocking state according to the conversion value and the first preset mapping relationship includes:
  • the highest operating frequency corresponding to the target voltage range is determined based on the first preset mapping relationship, and the highest operating frequency of the CPU in an overclocking state is obtained.
  • a CPU performance adjustment device including:
  • BMC used to determine the power rating of the PSU powering the current CPU
  • CPLD used to output the control signal corresponding to the rated power
  • a preset conversion unit configured to output a voltage value corresponding to the control signal
  • a maximum operating frequency determination module configured to determine the maximum operating frequency of the CPU in an overclocking state according to the voltage value and the first preset mapping relationship
  • the first preset mapping relationship is a corresponding relationship between each voltage range and each highest operating frequency.
  • the module for determining the highest operating frequency includes:
  • a CPU voltage regulator configured to perform AD conversion on the voltage value to obtain a corresponding conversion value
  • the CPU is configured to determine the highest operating frequency of the CPU in an overclocking state according to the conversion value and the first preset mapping relationship.
  • the present application discloses a computer-readable storage medium for storing a computer program, and when the computer program is executed by a processor, the foregoing CPU performance adjustment method is implemented.
  • the application first determines the rated power of the PSU that supplies power to the current CPU through the BMC, then outputs the control signal corresponding to the rated power through the CPLD, and then outputs the voltage value corresponding to the control signal through the preset conversion unit, and finally according to the specified
  • the voltage value and the first preset mapping relationship determine the maximum operating frequency of the CPU in an overclocking state; wherein, the first preset mapping relationship is a corresponding relationship between each voltage range and each highest operating frequency.
  • the application first determines the rated power of the PSU that supplies power to the current CPU through the BMC, and converts the corresponding control signal by the CPLD, and corresponds the rated power of the PSU to the voltage output of the preset conversion unit, and finally converts the output of the conversion unit.
  • the output voltage corresponds to the maximum operating frequency setting under the CPU overclocking state.
  • the highest operating frequency in the CPU overclocking state corresponds to the rated power of the PSU, which can prevent the CPU from triggering PSU overpower protection or CPU frequency reduction in the overclocking state, thereby affecting end-user business processing and avoiding costs. promote.
  • Fig. 1 is the schematic diagram of a kind of existing motherboard CPU power supply structure that the application provides;
  • FIG. 2 is a flow chart of a CPU performance adjustment method disclosed in the present application.
  • FIG. 3 is a structural diagram of a specific preset conversion unit disclosed in the present application.
  • FIG. 4 is a schematic diagram of a specific power supply structure for adaptively adjusting CPU performance according to different types of PSUs disclosed in the present application;
  • FIG. 5 is a schematic structural diagram of a CPU performance adjustment device disclosed in the present application.
  • FIG. 6 is a schematic structural diagram of a computer-readable storage medium disclosed in the present application.
  • FIG. 1 is a schematic diagram of an existing mainboard CPU power supply structure provided by an embodiment of the present application.
  • 1+1 redundant power supply PSU0 and PSU1, BMC, P12V_EFUSE (EFUSE, Electronic fuse, electronic fuse) is a 12V load switch with overcurrent protection, CPU voltage regulator, CPU0, CPU1.
  • PSU0 and PSU1 are combined into 1+1 redundant power supply output P12V_PSU (voltage) directly into the motherboard, P12V_EFUSE is transferred out of P12V, and then converted to CPU power by the CPU voltage regulator.
  • the BMC communicates with the PSU through the PMBUS (Power Management Bus, power management bus) bus, which can realize the monitoring of the overall power consumption of the server system, and at the same time, the PSU power monitoring unit can realize the system power limit adjustment by setting the power consumption threshold Strategy: That is: when the CPU is overclocking, when the system power consumption exceeds the power threshold, the PSU power consumption monitoring module will send an ALERT (alarm) signal to trigger the CPU to reduce the frequency.
  • PMBUS is the communication and interaction bus between BMC and PSU, which realizes the monitoring and management of the working status of PSU (including: voltage, current, power consumption, temperature, etc.).
  • the alarm signal sent by the PSU is used to limit the power of the PSU and control the frequency reduction of the CPU.
  • the disadvantages of the existing technology are: when the motherboard is equipped with a high-spec CPU, in the overclocking working state, there is a risk of triggering PSU power-off or CPU down-frequency, which will affect the business processing of the end user; in order to support the high-spec CPU and ensure the overclocking performance, If a high-power PSU is used, although it can meet the performance requirements, it will increase the overall cost of the product and reduce the market competitiveness of the product. For this reason, the present application provides a CPU performance adjustment solution, which can avoid the problem that the CPU triggers the PSU overpower protection or the CPU frequency reduction in the overclocking state, thereby affecting the service processing of the end user, and avoiding the cost increase.
  • the embodiment of the present application discloses a CPU performance adjustment method, including:
  • Step S11 Determine the rated power of the PSU powering the current CPU through the BMC.
  • the product model of the PSU can be read from the memory of the PSU powering the current CPU through the BMC; the rated power of the PSU can be determined according to the product model.
  • the memory may be a PIROM (Processor Information ROM, product information memory) unit.
  • the BMC accesses the data in the PIROM storage unit inside the PSU through the PMBUS bus. In order to obtain the product model of the PSU.
  • Step S12 Outputting a control signal corresponding to the rated power through a CPLD (Complex Programmable Logic Device, Complex Programmable Logic Device).
  • CPLD Complex Programmable Logic Device, Complex Programmable Logic Device
  • the BMC generates the target coded signal corresponding to the rated power based on the second preset mapping relationship; wherein, the second preset mapping relationship is the corresponding relationship between different rated powers and different coded signals;
  • the target coding signal is input into the CPLD, and the control signal corresponding to the target coding signal is output through the CPLD.
  • the BMC generates the corresponding coded signal A (Am, ..., A2, A1), where the value of m is determined by the number of rated power types corresponding to the PSU powered by the server product system, so as to give the server
  • the corresponding relationship between signal A and PSU power value is shown in Table 1 below:
  • the BMC encodes the rated power P_PSU of the PSU to generate an encoded signal A, which is fed back to the CPLD through the I2C bus.
  • the rated power corresponding to the target coded signal may be determined through the CPLD, and a control signal corresponding to the rated power is output according to a third preset mapping relationship; wherein, the third mapping relationship It is the corresponding relationship between different rated power and different control signals.
  • control signal corresponding to the coded signal may also be output according to a fourth preset mapping relationship; wherein, the fourth preset mapping relationship is a correspondence between different coded signals and different control signals.
  • Step S13 Outputting the voltage value corresponding to the control signal through the preset conversion unit.
  • the MOS i.e. Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide-Semiconductor Field-Effect Transistor
  • the voltage dividing resistor on the target branch divides the reference voltage to obtain the voltage value corresponding to the control signal; wherein, the reference voltage is a voltage converted from the power supply voltage of the PSU, and the preset Assuming that the resistance values of the voltage dividing resistors in different branches in the conversion unit are different, the target branch is a branch in the preset conversion unit.
  • the CPLD is used to convert the encoded signal A into the control signal B through logic processing, thereby controlling the output voltage value of the conversion unit.
  • FIG. 3 is a structural diagram of a specific preset conversion unit disclosed in the embodiment of the present application.
  • the preset conversion unit is composed of voltage divider resistors and MOS.
  • VDD is a reference voltage
  • R is a preset resistor
  • Ri is a voltage dividing resistor
  • Each group of control signals corresponds to a PSU power value P_PSU (P1, P2, P3, P4), and a corresponding output voltage Vo (V1, V2, V3, V4).
  • P_PSU P1, P2, P3, P4
  • Vo output voltage
  • Table 2 which includes the corresponding relationship between rated power, control signal B and voltage value.
  • the corresponding relationship between the rated power and the control signal B is a specific case of the above-mentioned third preset mapping relationship.
  • Step S14 Determine the highest operating frequency of the CPU in an overclocking state according to the voltage value and the first preset mapping relationship.
  • the first preset mapping relationship is a corresponding relationship between each voltage range and each highest operating frequency.
  • the voltage value is subjected to AD (that is, analogue-to-digital, analog signal is converted into a digital signal) conversion to obtain a corresponding conversion value; according to the conversion value and the first preset mapping relationship, determine The maximum operating frequency of the CPU in an overclocking state.
  • AD that is, analogue-to-digital, analog signal is converted into a digital signal
  • the CPU VR Voltage Regulator
  • the CPU VR Voltage Regulator chip will perform AD conversion on the Vo voltage value, and then pass the AD conversion value to the PCU unit of the CPU through the SVID bus.
  • the CPU will determine the operating frequency according to the corresponding relationship in Table 3 below.
  • V_ADC is the AD conversion voltage value corresponding to Vo
  • V_ADC_L and V_ADC_H are the upper and lower voltage thresholds of the voltage range
  • F_CPU is the highest operating frequency under the overclocking state set by the CPU.
  • the CPU will set the maximum operating frequency under the overclocking state to f1; if the detected conversion voltage value is V2_L ⁇ V_ADC ⁇ V2_H, the CPU will set the maximum operating frequency under the overclocking state to Set it to f2; if the detected conversion voltage value is V3_L ⁇ V_ADC ⁇ V3_H, the CPU will set the maximum operating frequency in the overclocking state to f3; if the detected conversion voltage value is V4_L ⁇ V_ADC ⁇ V4_H, the CPU will set the maximum operating frequency in the overclocking state to The highest operating frequency is set to f4.
  • FIG. 4 is a schematic diagram of a specific power supply structure for adaptively adjusting CPU performance according to different models of PSUs disclosed in the embodiment of the present application. It mainly includes: PSU0 and CPU01 with 1+1 redundant power supply (output P12V_PSU to supply power to the motherboard), CPLD, BMC, CPU voltage regulator, CPU0, CPU1 and PSU memory, specifically PSU PIROM. Its working principle is as follows: First, the BMC on the motherboard accesses the PIROM units in PSU0 and PSU1 through the PMBUS bus, reads the product models of PSU0 and PSU1 from the PIROM units, and determines the rated power of the PSU according to the product models.
  • the BMC encodes according to the rated power to obtain the encoded signal A, and sends the signal A to the CPLD through the GPIO (General-purpose input/output, general-purpose input and output) interface, and the CPLD will send out the control signal B after receiving the signal.
  • the preset conversion unit outputs a corresponding voltage value.
  • the voltage value output by the conversion unit is given to the CPU voltage regulator, and the CPU voltage regulator performs AD conversion on the voltage value to obtain a converted voltage value.
  • the converted voltage value is given to the PCU (ie Power Control Unit, power control unit) unit inside the CPU through the SVID (Serial Voltage Identification, serial voltage identification) bus.
  • the embodiment of the present application introduces a BMC identification mechanism, through which the BMC identifies the PSU model and outputs a coded signal, which is converted into a control signal by the CPLD, and the power of the PSU corresponds to the voltage output of the conversion unit.
  • the CPU operating frequency setting mechanism is introduced to match the output voltage of the conversion unit with the operating frequency setting of the CPU.
  • the CPU When the CPU is overclocking, it will automatically set the highest operating frequency under the overclocking state according to the rated power value of the current matching PSU, which can ensure the maximum performance of the CPU within the power supply capacity of the PSU.
  • the upper limit of the operating frequency to which the CPU overclocking performance can be accelerated is determined according to the power output capability that the PSU can provide. In order to achieve how much power the PSU has, the CPU can work at a high operating frequency. In this way, the power supply capability of the PSU can be fully utilized, and the performance of the CPU can be improved, without affecting the services of end users.
  • solution provided by this application can also be used in high-density, full-rack server, storage and other product power supply applications.
  • a CPU performance adjustment device including:
  • BMC11 used to determine the rated power of the PSU powering the current CPU
  • CPLD12 configured to output a control signal corresponding to the rated power
  • a preset conversion unit 13 configured to output a voltage value corresponding to the control signal
  • a maximum operating frequency determination module 14 configured to determine the maximum operating frequency of the CPU in an overclocking state according to the voltage value and the first preset mapping relationship;
  • the first preset mapping relationship is a corresponding relationship between each voltage range and each highest operating frequency.
  • the application first determines the rated power of the PSU that supplies power to the current CPU through the BMC, then outputs the control signal corresponding to the rated power through the CPLD, and then outputs the voltage value corresponding to the control signal through the preset conversion unit, and finally according to the specified
  • the voltage value and the first preset mapping relationship determine the maximum operating frequency of the CPU in an overclocking state; wherein, the first preset mapping relationship is a corresponding relationship between each voltage range and each highest operating frequency.
  • the application first determines the rated power of the PSU that supplies power to the current CPU through the BMC, and converts the corresponding control signal by the CPLD, and corresponds the rated power of the PSU to the voltage output of the preset conversion unit, and finally converts the output of the conversion unit.
  • the output voltage corresponds to the maximum operating frequency setting under the CPU overclocking state.
  • the highest operating frequency in the CPU overclocking state corresponds to the rated power of the PSU, which can prevent the CPU from triggering PSU overpower protection or CPU frequency reduction in the overclocking state, thereby affecting end-user business processing and avoiding costs. promote.
  • the BMC 11 is specifically configured to read the product model of the PSU from the memory of the PSU powering the current CPU through the BMC; determine the rated power of the PSU according to the product model.
  • BMC11 is specifically configured to generate the target coded signal corresponding to the rated power based on the second preset mapping relationship; wherein, the second preset mapping relationship is the corresponding relationship between different rated powers and different coded signals;
  • the target coding signal is input to CPLD.
  • the CPLD is used to output the control signal corresponding to the target coding signal.
  • the CPLD is used to determine the rated power corresponding to the target coded signal, and output the control signal corresponding to the rated power according to a third preset mapping relationship; wherein, the third mapping relationship is different Correspondence between rated power and different control signals.
  • the preset conversion unit is specifically used to control the MOS in the target branch to turn on under the control of the control signal, and use the voltage dividing resistor on the target branch to divide the reference voltage to obtain the voltage corresponding to the control signal value;
  • the reference voltage is a voltage converted by using the power supply voltage of the PSU, and the resistance values of the voltage dividing resistors in different branches of the preset conversion unit are different, and the target branch is the preset Let a branch in the transformation unit be assumed.
  • the highest operating frequency determination module 14 specifically includes:
  • a CPU voltage regulator configured to perform AD conversion on the voltage value to obtain a corresponding conversion value
  • the CPU is configured to determine the highest operating frequency of the CPU in an overclocking state according to the conversion value and the first preset mapping relationship.
  • the CPU is specifically used to determine the voltage range to which the converted value belongs to obtain the target voltage range; determine the highest operating frequency corresponding to the target voltage range based on the first preset mapping relationship, and obtain the The highest operating frequency under overclocking state.
  • FIG. 6 is a schematic structural diagram of a computer-readable storage medium disclosed in the present application.
  • the embodiment of the present application also discloses a computer-readable storage medium 601 for storing a computer program 610, Wherein, when the computer program 610 is executed by the processor, the CPU performance adjustment method disclosed in the foregoing embodiments is implemented.
  • each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same or similar parts of each embodiment can be referred to each other.
  • the description is relatively simple, and for the related information, please refer to the description of the method part.
  • RAM random access memory
  • ROM read-only memory
  • EEPROM electrically programmable ROM
  • EEPROM electrically erasable programmable ROM
  • registers hard disk, removable disk, CD-ROM, or any other Any other known storage medium.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)

Abstract

本申请公开了一种CPU性能调节方法、装置及介质，包括：通过BMC确定为当前CPU供电的PSU的额定功率；通过CPLD输出额定功率对应的控制信号；通过预设转换单元输出控制信号对应的电压值；根据电压值以及第一预设映射关系确定CPU在超频状态下的最高工作频率；第一预设映射关系为各电压范围与各最高工作频率的对应关系。这样，CPU超频状态下的最高工作频率是与PSU额定功率相对应的，能够避免CPU在超频工作状态下触发PSU过功率保护或是CPU降频，从而影响终用户业务处理的问题，以及避免成本提升。

Description

一种CPU性能调节方法、装置及介质
本申请要求在2021年09月27日提交中国专利局、申请号为202111132410.8、发明名称为“一种CPU性能调节方法、装置及介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及供电可靠性设计技术领域，特别涉及一种CPU性能调节方法、装置及介质。
背景技术
伴随着云计算技术的不断兴起，互联网业务量不断增加。对机房服务器的数据处理能力、存储容量都提出了更高的要求。作为传统机房中的单元，机柜系统，要求部署在机柜内部服务器计算节点的数据处理能力越来越强，部署密度越来越高。随着互联网用户业务的增长，网络数据吞吐量也越来越大，作为数据中心的基本数据处理单元的服务器，的工作负荷也越来越大。尤其是服务器内部的CPU(即Central Processing Unit，中央处理器)芯片，其工作负载电流越来越大，电流多达100至550A。在实际的服务器产品开发过程中，基于产品设计成本与性能的权衡考量。对于计算性能要求不高的应用场景，通常会选用低功率的PSU(即Power Supply Unit，电源供应器)来适配低配置，采用高功率PSU来适配高配置服务器产品。
当前，有些用户在采购服务器产品后，会根据自身的业务场景进行升级改配。若是升级为高功耗CPU，PSU型号不去做相应的调整，这样在CPU切换到性能加速工作模式时(超频)，就会存在概率性触发PSU过功率保护，造成宕机的风险。有的用户，会在系统BMC(即Baseboard Management Controller，基板管理控制器)中设置PSU功率门限。当CPU超频时，系统功率过高触发到该门限值，PSU就会发出ALERT(告警)信号控制CPU降频，来克服宕机问题。但通常BMC从监控到高系统功率值，到响应处理，直到触发CPU降频需 要一段处理时间。在这段时间内，CPU处理的有些业务会处于停滞状态，会影响到用户端的业务处理。因此，有些用户，为避免影响到用户端业务，会选型大功率PSU来适配服务器，这样又会带来产品成本的整体上升。
发明内容
有鉴于此，本申请的目的在于提供一种CPU性能调节方法、装置及介质，能够避免CPU在超频工作状态下触发PSU过功率保护或是CPU降频，从而影响终用户业务处理的问题，以及避免成本提升。其具体方案如下：
第一方面，本申请公开了一种CPU性能调节方法，包括：
通过BMC确定为当前CPU供电的PSU的额定功率；
通过CPLD输出所述额定功率对应的控制信号；
通过预设转换单元输出所述控制信号对应的电压值；
根据所述电压值以及第一预设映射关系确定所述CPU在超频状态下的最高工作频率；
其中，所述第一预设映射关系为各电压范围与各最高工作频率的对应关系。
可选的，所述通过BMC确定为当前CPU供电的PSU的额定功率，包括：
通过BMC从为当前CPU供电的PSU的存储器中读取所述PSU的产品型号；
根据所述产品型号确定出所述PSU的额定功率。
可选的，还包括：
通过BMC基于第二预设映射关系生成所述额定功率对应的目标编码信号；其中，所述第二预设映射关系为不同额定功率与不同编码信号的对应关系；
相应的，所述通过CPLD输出所述额定功率对应的控制信号，包括：
将所述目标编码信号输入CPLD，并通过所述CPLD输出所述目标编码信号对应的控制信号。
可选的，所述通过CPLD输出所述额定功率对应的控制信号，包括：
通过CPLD确定出所述目标编码信号对应的额定功率，并根据第三预设映射关系输出该额定功率对应的控制信号；
其中，所述第三映射关系为不同额定功率与不同控制信号的对应关系。
可选的，所述通过预设转换单元输出所述控制信号对应的电压值，包括：
通过所述控制信号控制所述预设转换单元中目标支路中的MOS开通，并利用所述目标支路上的分压电阻对参考电压进行分压，得到所述控制信号对应的电压值；
其中，所述参考电压为利用所述PSU的供电电压转换出的电压，并且，所述预设转换单元中不同支路中的分压电阻的阻值不同，所述目标支路为所述预设转换单元中的一个支路。
可选的，所述根据所述电压值以及第一预设映射关系确定所述CPU在超频状态下的最高工作频率，包括：
对所述电压值进行AD转换，得到相应的转换值；
根据所述转换值以及第一预设映射关系确定所述CPU在超频状态下的最高工作频率。
可选的，所述根据所述转换值以及第一预设映射关系确定所述CPU在超频状态下的最高工作频率，包括：
确定出所述转换值所属的电压范围，得到目标电压范围；
基于所述第一预设映射关系确定出所述目标电压范围对应的最高工作频率，得到所述CPU在超频状态下的最高工作频率。
第三方面，本申请公开了一种CPU性能调节装置，包括：
BMC，用于确定为当前CPU供电的PSU的额定功率；
CPLD，用于输出所述额定功率对应的控制信号；
预设转换单元，用于输出所述控制信号对应的电压值；
最高工作频率确定模块，用于根据所述电压值以及第一预设映射关系确定所述CPU在超频状态下的最高工作频率；
其中，所述第一预设映射关系为各电压范围与各最高工作频率的对应关系。
可选的，所述最高工作频率确定模块，包括：
CPU电压调整器，用于对所述电压值进行AD转换，得到相应的转换值；
CPU，用于根据所述转换值以及第一预设映射关系确定所述CPU在超频状态下的最高工作频率。
第四方面，本申请公开了一种计算机可读存储介质，用于保存计算机程序，所述计算机程序被处理器执行时实现前述的CPU性能调节方法。
可见，本申请先通过BMC确定为当前CPU供电的PSU的额定功率，之后通过CPLD输出所述额定功率对应的控制信号，然后通过预设转换单元输出所述控制信号对应的电压值，最后根据所述电压值以及第一预设映射关系确定所述CPU在超频状态下的最高工作频率；其中，所述第一预设映射关系为各电压范围与各最高工作频率的对应关系。也即，本申请先通过BMC确定为当前CPU供电的PSU的额定功率，并由CPLD转换出相应的控制信号，将PSU的额定功率与预设转换单元的电压输出对应起来，最后将转换单元的输出电压与CPU超频状态下的最高工作频率设定对应起来。这样，CPU超频状态下的最高工作频率是与PSU额定功率相对应的，能够避免CPU在超频工作状态下触发PSU过功率保护或是CPU降频，从而影响终用户业务处理的问题，以及避免成本提升。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为本申请提供的一种现有主板CPU供电结构示意图；
图2为本申请公开的一种CPU性能调节方法流程图；
图3为本申请公开的一种具体的预设转换单元结构图；
图4为本申请公开的一种具体的根据不同型号PSU来自适应调节CPU性能的供电结构示意图；
图5为本申请公开的一种CPU性能调节装置结构示意图；
图6为本申请公开的一种计算机可读存储介质结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
参见图1所示，图1为本申请实施例提供的一种现有主板CPU供电结构示意图。包含：1+1冗余供电的PSU0和PSU1、BMC、P12V_EFUSE(EFUSE，即Electronic fuse，电子保险丝)为带有过流保护的12V负载开关、CPU电压调整器、CPU0、CPU1。其工作原理如下：PSU0和PSU1组合成1+1冗余电源输出P12V_PSU(电压)直入主板，经P12V_EFUSE转出P12V，再经CPU电压调整器转换给CPU供电。其中：BMC通过PMBUS(即Power Management Bus，电源管理总线)总线与PSU通信，可实现对服务器系统整机功耗的监控，同时PSU功率监控单元通过设定功耗门限，可实现系统功率限制调节策略：即：CPU在做超频时，当系统功耗超出功率门限值，PSU功耗监控模块会发出ALERT(告警)信号触发CPU降频。其中：PMBUS为BMC与PSU通信交互总线，实现对PSU的工作状态的监控及管理(包含：电压、电流、功耗、温度等)。PSU发出的告警信号，用来实现PSU限功率，控制CPU降频。现有技术的缺点为：主板搭配高规格的CPU时，在超频工作状态，存在触发PSU掉电或是CPU降频的风险，影响终端用户的业务处理；为支持高规格CPU，保证超频性能，若选用高功率PSU，虽然能满足性能需要，但会带来产品整体成本的上升，产品市场竞争力下降。为此，本申请提供了一种CPU性能调节方案，能够避免CPU在超频工作状态下触发PSU过功率保护或是CPU降频，从而影响终用户业务处理的问题，以及避免成本提升。
参见图2所示，本申请实施例公开了一种CPU性能调节方法，包括：
步骤S11：通过BMC确定为当前CPU供电的PSU的额定功率。
在具体的实施方式中，可以通过BMC从为当前CPU供电的PSU的存储器中读取所述PSU的产品型号；根据所述产品型号确定出所述PSU的额定功率。
其中，存储器可以为PIROM(即Processor Information ROM，产品信息存储器)单元。并且，BMC通过PMBUS总线来访问PSU内部的PIROM存储单元 中的数据。从而获取PSU的产品型号。
步骤S12：通过CPLD(即Complex Programmable Logic Device，复杂可编程逻辑器件)输出所述额定功率对应的控制信号。
在具体的实施方式中，通过BMC基于第二预设映射关系生成所述额定功率对应的目标编码信号；其中，所述第二预设映射关系为不同额定功率与不同编码信号的对应关系；将所述目标编码信号输入CPLD，并通过所述CPLD输出所述目标编码信号对应的控制信号。
例如，BMC根据PSU型号对应的额定功率，产生对应的编码信号A(Am，…，A2，A1)，其中，m的数值由服务器产品系统供电的PSU对应的额定功率种类数量确定，以给服务器产品系统供电的PSU，采用4种功率值P1、P2、P3、P4为例)，信号A与PSU功率值对应关系即第二映射关系如下表1所示：
表1
Figure PCTCN2022074608-appb-000001
在具体的实施方式中，BMC将PSU的额定功率P_PSU进行编码，产生编码信号A，通过I2C总线反馈给CPLD。
进一步的，在具体的实施方式中，可以通过CPLD确定出所述目标编码信号对应的额定功率，并根据第三预设映射关系输出该额定功率对应的控制信号；其中，所述第三映射关系为不同额定功率与不同控制信号的对应关系。
当然，在另外一些实施例中，也可以根据第四预设映射关系输出编码信号对应的控制信号；其中，所述第四预设映射关系为不同编码信号与不同控制信号的对应关系。
步骤S13：通过预设转换单元输出所述控制信号对应的电压值。
在具体的实施方式中，可以通过所述控制信号控制所述预设转换单元中 目标支路中的MOS(即Metal-Oxide-Semiconductor Field-Effect Transistor，金氧半场效晶体管)开通，并利用所述目标支路上的分压电阻对参考电压进行分压，得到所述控制信号对应的电压值；其中，所述参考电压为利用所述PSU的供电电压转换出的电压，并且，所述预设转换单元中不同支路中的分压电阻的阻值不同，所述目标支路为所述预设转换单元中的一个支路。
也即，CPLD用于将编码信号A经逻辑处理转换为控制信号B，由此控制转换单元的输出电压值。
参见图3所示，图3为本申请实施例公开的一种具体的预设转换单元结构图。预设转换单元由分压电阻和MOS组成。预设转换单元是通过CPLD发出控制信号来控制相应的MOS(q1，q2，…，qn)开通，VDD通过R与Ri分压(i＝1,2,…,n)，来得出不同的输出电压Vo，电压值计算公式如下：
Vo＝VDD*Ri/(R+Ri)
其中，VDD为参考电压，R为预设电阻，Ri为分压电阻。
其中，CPLD发出的控制信号B(Gn,…,G2,G1)，以n＝4为例，类似于4位数字选择器。4个电平信号，有高电平，有低电平。且每次输出的4位信号只有1位是高电平“H”，其他位是低电平“L”。高电平“H”则相应支路上的MOS开通，该支路上的分压电阻参与分压，其他支路上MOS不开通，其他支路上的分压电阻不参与分压。每一组控制信号，对应一个PSU功率值P_PSU(P1，P2，P3，P4)，对应的输出电压Vo(V1，V2，V3，V4)。参见表2所示，表2中包括额定功率、控制信号B和电压值的对应关系。其中，额定功率、控制信号B的对应关系即为上述第三预设映射关系的一种具体情况。
表2
Figure PCTCN2022074608-appb-000002
步骤S14：根据所述电压值以及第一预设映射关系确定所述CPU在超频状态下的最高工作频率。
其中，所述第一预设映射关系为各电压范围与各最高工作频率的对应关系。
在具体的实施方式中，对所述电压值进行AD(即analogue-to-digital，模拟信号转换为数字信号)转换，得到相应的转换值；根据所述转换值以及第一预设映射关系确定所述CPU在超频状态下的最高工作频率。
进一步的，确定出所述转换值所属的电压范围，得到目标电压范围；基于所述第一预设映射关系确定出所述目标电压范围对应的最高工作频率，得到所述CPU在超频状态下的最高工作频率。
在具体的实施方式中，CPU VR(即Voltage Regulator，电压调整器)芯片在接收到Vo信号后，会将Vo电压值做AD转换，然后通过SVID总线将AD转换值传递到CPU的PCU单元。CPU会根据下表3的对应关系确定工作频率。其中：V_ADC是对应Vo的AD转换电压值，V_ADC_L和V_ADC_H分别为电压范围的电压上下阈值，F_CPU是CPU设定的超频状态下的最高工作频率。
若检测的转换电压值V1_L<V_ADC≤V1_H时，CPU会将超频状态下的最高工作频率设置为f1；若检测的转换电压值V2_L<V_ADC≤V2_H时，CPU会将超频状态下的最高工作频率设置为f2；若检测的转换电压值V3_L<V_ADC≤V3_H时，CPU会将超频状态下的最高工作频率设置为f3；若检测的转换电压值V4_L<V_ADC≤V4_H时，CPU会将超频状态下的最高工作频率设置为f4。
表3
Figure PCTCN2022074608-appb-000003
参见图4所示，图4为本申请实施例公开的一种具体的根据不同型号PSU来自适应调节CPU性能的供电结构示意图。主要包含：1+1冗余供电的PSU0和CPU01(输出P12V_PSU给主板供电)、CPLD、BMC、CPU电压调整器、 CPU0、CPU1及PSU的存储器，具体为PSU PIROM。其工作原理如下：首先，主板上的BMC通过PMBUS总线访问PSU0和PSU1内的PIROM单元，从PIROM单元中读取PSU0和PSU1的产品型号，并依据产品型号来确定出PSU的额定功率。然后BMC根据该额定功率进行编码，得到编码信号A，通过GPIO(即General-purpose input/output，通用型之输入输出)接口发出信号A给到CPLD，CPLD收到信号后会发出控制信号B控制预设转换单元输出相应的电压值。接着，转换单元输出的电压值会给到CPU电压调整器，由CPU电压调整器将电压值进行AD转换，得到转换电压值。并将转换电压值通过SVID(即Serial Voltage Identification，串行电压标识)总线给到CPU内部的PCU(即Power Control Unit，电源控制单元)单元。最后，PCU单元收到转换电压值后，CPU会依据转换电压值大小设定超频的最高工作频率，以此来实现CPU达到最高性能与PSU最高供电能力的匹配。也即，本申请实施例引入BMC识别机制，通过BMC识别PSU型号并输出编码信号，由CPLD转换成控制信号，将PSU的功率与转换单元的电压输出对应起来。引入CPU工作频率设定机制，将转换单元的输出电压与CPU的工作频率设定对应起来。CPU在超频工作时，会根据当前搭配PSU的额定功率值自动设定超频状态下的最高工作频率，可保证PSU供电能力之内，实现CPU最大性能提升。从而有效解决主板搭配高规格的CPU时，在超频工作状态，存在触发PSU掉电或是CPU降频的风险，影响终端用户的业务处理的问题，以及为支持高规格CPU，保证超频性能，若选用高功率PSU，虽然能满足性能需要，但会带来产品整体成本的上升，产品市场竞争力下降的问题。根据产品配置PSU的功率规格及搭配的CPU规格，根据PSU能提供的功率输出能力来决定CPU做超频性能加速到的工作频率的上限。以达到PSU有多大功率，CPU就能够工作在多高的工作频率。从而既充分发挥PSU的供电能力，又能兼顾CPU性能提升，且不影响终端用户业务。
另外，本申请提供的方案还可用在高密度、整机柜服务器、存储等产品供电应用场合。
参见图5所示，本申请公开了一种CPU性能调节装置，包括：
BMC11，用于确定为当前CPU供电的PSU的额定功率；
CPLD12，用于输出所述额定功率对应的控制信号；
预设转换单元13，用于输出所述控制信号对应的电压值；
最高工作频率确定模块14，用于根据所述电压值以及第一预设映射关系确定所述CPU在超频状态下的最高工作频率；
其中，所述第一预设映射关系为各电压范围与各最高工作频率的对应关系。
可见，本申请先通过BMC确定为当前CPU供电的PSU的额定功率，之后通过CPLD输出所述额定功率对应的控制信号，然后通过预设转换单元输出所述控制信号对应的电压值，最后根据所述电压值以及第一预设映射关系确定所述CPU在超频状态下的最高工作频率；其中，所述第一预设映射关系为各电压范围与各最高工作频率的对应关系。也即，本申请先通过BMC确定为当前CPU供电的PSU的额定功率，并由CPLD转换出相应的控制信号，将PSU的额定功率与预设转换单元的电压输出对应起来，最后将转换单元的输出电压与CPU超频状态下的最高工作频率设定对应起来。这样，CPU超频状态下的最高工作频率是与PSU额定功率相对应的，能够避免CPU在超频工作状态下触发PSU过功率保护或是CPU降频，从而影响终用户业务处理的问题，以及避免成本提升。
在具体的实施方式中，BMC11，具体用于通过BMC从为当前CPU供电的PSU的存储器中读取所述PSU的产品型号；根据所述产品型号确定出所述PSU的额定功率。
进一步的，BMC11，具体用于基于第二预设映射关系生成所述额定功率对应的目标编码信号；其中，所述第二预设映射关系为不同额定功率与不同编码信号的对应关系；将所述目标编码信号输入CPLD。
相应的，CPLD用于输出所述目标编码信号对应的控制信号。
在具体的实施方式中，CPLD，用于确定出所述目标编码信号对应的额定功率，并根据第三预设映射关系输出该额定功率对应的控制信号；其中，所述第三映射关系为不同额定功率与不同控制信号的对应关系。
预设转换单元具体用于在所述控制信号的控制下控制目标支路中的MOS开通，并利用所述目标支路上的分压电阻对参考电压进行分压，得到所述控制信号对应的电压值；
其中，所述参考电压为利用所述PSU的供电电压转换出的电压，并且，所 述预设转换单元中不同支路中的分压电阻的阻值不同，所述目标支路为所述预设转换单元中的一个支路。
其中，所述最高工作频率确定模块14，具体包括：
CPU电压调整器，用于对所述电压值进行AD转换，得到相应的转换值；
CPU，用于根据所述转换值以及第一预设映射关系确定所述CPU在超频状态下的最高工作频率。
进一步的，CPU具体用于确定出所述转换值所属的电压范围，得到目标电压范围；基于所述第一预设映射关系确定出所述目标电压范围对应的最高工作频率，得到所述CPU在超频状态下的最高工作频率。
进一步的，图6为本申请公开的一种计算机可读存储介质结构示意图，参见图6所示，本申请实施例还公开了一种计算机可读存储介质601，用于保存计算机程610序，其中，所述计算机程序610被处理器执行时实现前述实施例公开的CPU性能调节方法。
关于上述CPU性能调节方法的具体过程可以参考前述实施例中公开的相应内容，在此不再进行赘述。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其它实施例的不同之处，各个实施例之间相同或相似部分互相参见即可。对于实施例公开的装置而言，由于其与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。
结合本文中所公开的实施例描述的方法或算法的步骤可以直接用硬件、处理器执行的软件模块，或者二者的结合来实施。软件模块可以置于随机存储器(RAM)、内存、只读存储器(ROM)、电可编程ROM、电可擦除可编程ROM、寄存器、硬盘、可移动磁盘、CD-ROM、或技术领域内所公知的任意其它形式的存储介质中。
以上对本申请所提供的一种CPU性能调节方法、装置及介质进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均 会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (11)

  1. 一种CPU性能调节方法，其特征在于，包括：
    通过BMC确定为当前CPU供电的PSU的额定功率；
    通过CPLD输出所述额定功率对应的控制信号；
    通过预设转换单元输出所述控制信号对应的电压值；
    根据所述电压值以及第一预设映射关系确定所述CPU在超频状态下的最高工作频率；
    其中，所述第一预设映射关系为各电压范围与各最高工作频率的对应关系。
  2. 根据权利要求1所述的CPU性能调节方法，其特征在于，所述通过BMC确定为当前CPU供电的PSU的额定功率，包括：
    通过BMC从为当前CPU供电的PSU的存储器中读取所述PSU的产品型号；
    根据所述产品型号确定出所述PSU的额定功率。
  3. 根据权利要求1所述的CPU性能调节方法，其特征在于，还包括：
    通过BMC基于第二预设映射关系生成所述额定功率对应的目标编码信号；其中，所述第二预设映射关系为不同额定功率与不同编码信号的对应关系；
    相应的，所述通过CPLD输出所述额定功率对应的控制信号，包括：
    将所述目标编码信号输入CPLD，并通过所述CPLD输出所述目标编码信号对应的控制信号。
  4. 根据权利要求3所述的CPU性能调节方法，其特征在于，所述通过CPLD输出所述额定功率对应的控制信号，包括：
    通过CPLD确定出所述目标编码信号对应的额定功率，并根据第三预设映射关系输出该额定功率对应的控制信号；
    其中，所述第三预设映射关系为不同额定功率与不同控制信号的对应关系。
  5. 根据权利要求1所述的CPU性能调节方法，其特征在于，所述通过预设转换单元输出所述控制信号对应的电压值，包括：
    通过所述控制信号控制所述预设转换单元中目标支路中的MOS开通，并利用所述目标支路上的分压电阻对参考电压进行分压，得到所述控制信号对应的电压值；
    其中，所述参考电压为利用所述PSU的供电电压转换出的电压，并且，所述预设转换单元中不同支路中的分压电阻的阻值不同，所述目标支路为所述预设转换单元中的一个支路。
  6. 根据权利要求1至5任一项所述的CPU性能调节方法，其特征在于，所述根据所述电压值以及第一预设映射关系确定所述CPU在超频状态下的最高工作频率，包括：
    对所述电压值进行AD转换，得到相应的转换值；
    根据所述转换值以及第一预设映射关系确定所述CPU在超频状态下的最高工作频率。
  7. 根据权利要求6所述的CPU性能调节方法，其特征在于，所述根据所述转换值以及第一预设映射关系确定所述CPU在超频状态下的最高工作频率，包括：
    确定出所述转换值所属的电压范围，得到目标电压范围；
    基于所述第一预设映射关系确定出所述目标电压范围对应的最高工作频率，得到所述CPU在超频状态下的最高工作频率。
  8. 一种CPU性能调节装置，其特征在于，包括：
    BMC，用于确定为当前CPU供电的PSU的额定功率；
    CPLD，用于输出所述额定功率对应的控制信号；
    预设转换单元，用于输出所述控制信号对应的电压值；
    最高工作频率确定模块，用于根据所述电压值以及第一预设映射关系确定所述CPU在超频状态下的最高工作频率；
    其中，所述第一预设映射关系为各电压范围与各最高工作频率的对应关系。
  9. 根据权利要求8所述的CPU性能调节装置，其特征在于，所述最高工作频率确定模块，包括：
    CPU电压调整器，用于对所述电压值进行AD转换，得到相应的转换值；
    CPU，用于根据所述转换值以及第一预设映射关系确定所述CPU在超频状态下的最高工作频率。
  10. 根据权利要求8所述的CPU性能调节装置，其特征在于，BMC，还用于基于第二预设映射关系生成所述额定功率对应的目标编码信号；其中，所述第二预设映射关系为不同额定功率与不同编码信号的对应关系；将所述目标编码信号输入CPLD；
    相应的，CPLD用于输出所述目标编码信号对应的控制信号。
  11. 一种计算机可读存储介质，其特征在于，用于保存计算机程序，所述计算机程序被处理器执行时实现如权利要求1至7任一项所述的CPU性能调节方法。
PCT/CN2022/074608 2021-09-27 2022-01-28 一种cpu性能调节方法、装置及介质 WO2023045200A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/280,222 US20240152191A1 (en) 2021-09-27 2022-01-28 Cpu performance adjustment method and apparatus, and medium

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111132410.8A CN113589913B (zh) 2021-09-27 2021-09-27 一种cpu性能调节方法、装置及介质
CN202111132410.8 2021-09-27

Publications (1)

Publication Number Publication Date
WO2023045200A1 true WO2023045200A1 (zh) 2023-03-30

Family

ID=78242413

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/074608 WO2023045200A1 (zh) 2021-09-27 2022-01-28 一种cpu性能调节方法、装置及介质

Country Status (3)

Country Link
US (1) US20240152191A1 (zh)
CN (1) CN113589913B (zh)
WO (1) WO2023045200A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113589913B (zh) * 2021-09-27 2021-12-17 苏州浪潮智能科技有限公司 一种cpu性能调节方法、装置及介质
CN114461055B (zh) * 2022-04-14 2022-07-08 苏州浪潮智能科技有限公司 一种调节功耗的系统、方法、装置、设备及介质
CN114816024B (zh) * 2022-05-31 2023-07-14 苏州浪潮智能科技有限公司 对服务器主板负载端进行保护的方法、系统、设备及介质

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7519843B1 (en) * 2008-05-30 2009-04-14 International Business Machines Corporation Method and system for dynamic processor speed control to always maximize processor performance based on processing load and available power
CN102541239A (zh) * 2010-12-16 2012-07-04 鸿富锦精密工业（深圳）有限公司 网络设备及其功耗控制方法
CN111475009A (zh) * 2020-04-16 2020-07-31 苏州浪潮智能科技有限公司 一种服务器内gpu的降功耗电路及服务器
CN113157076A (zh) * 2021-04-22 2021-07-23 中科可控信息产业有限公司 一种电子设备及功耗控制方法
CN113589913A (zh) * 2021-09-27 2021-11-02 苏州浪潮智能科技有限公司 一种cpu性能调节方法、装置及介质

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201224728A (en) * 2010-12-14 2012-06-16 Hon Hai Prec Ind Co Ltd Power self-controlling networking device and method of controlling power
CN107678855B (zh) * 2017-09-19 2020-06-12 中国电子产品可靠性与环境试验研究所 处理器动态调节方法、装置及处理器芯片
CN112667470A (zh) * 2020-12-25 2021-04-16 苏州浪潮智能科技有限公司 一种服务器功率评估及检测的系统、方法及介质

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7519843B1 (en) * 2008-05-30 2009-04-14 International Business Machines Corporation Method and system for dynamic processor speed control to always maximize processor performance based on processing load and available power
CN102541239A (zh) * 2010-12-16 2012-07-04 鸿富锦精密工业（深圳）有限公司 网络设备及其功耗控制方法
CN111475009A (zh) * 2020-04-16 2020-07-31 苏州浪潮智能科技有限公司 一种服务器内gpu的降功耗电路及服务器
CN113157076A (zh) * 2021-04-22 2021-07-23 中科可控信息产业有限公司 一种电子设备及功耗控制方法
CN113589913A (zh) * 2021-09-27 2021-11-02 苏州浪潮智能科技有限公司 一种cpu性能调节方法、装置及介质

Also Published As

Publication number Publication date
US20240152191A1 (en) 2024-05-09
CN113589913A (zh) 2021-11-02
CN113589913B (zh) 2021-12-17

Similar Documents

Publication Publication Date Title
WO2023045200A1 (zh) 一种cpu性能调节方法、装置及介质
US9261945B2 (en) Dynanmic peak power limiting to processing nodes in an information handling system
US10268262B2 (en) Dynamic peak power limiting to processing nodes in an information handling system
US7418608B2 (en) Method and an apparatus for managing power consumption of a server
US20220229479A1 (en) Power supply unit (psu)-based power supply system
US10754408B2 (en) Power supply unit mismatch detection system
US9733686B1 (en) Systems and methods for management controller enhanced power supply unit current sharing
US11086390B2 (en) Method and apparatus for improving power management by controlling a system input current in a power supply unit
WO2022148297A1 (zh) 多节点服务器电源失效的保护设备、方法及可读存储介质
US9411388B2 (en) Dynamic power system adjustment to store energy for power excursions
US9268393B2 (en) Enforcing a power consumption duty cycle in a processor
US11226665B2 (en) Systems and methods for optimizing fault tolerant redundancy for an information handling system with multiple power supply units
US11144105B2 (en) Method and apparatus to provide platform power peak limiting based on charge of power assist unit
US20160139645A1 (en) Computing system and power-on method and updating method
US20230054476A1 (en) Real-time communication of power supply unit power loading status
WO2021088255A1 (zh) 系统管理总线链路及其上拉电阻确定方法、装置和设备
US11599182B2 (en) Method and apparatus to distribute current indicator to multiple end-points
US10970686B2 (en) Testing power reuse system, power reuse circuit and testing power reuse method
US10116231B2 (en) Digital current-sharing loop design of PSUs to ensure output voltage regulation during dynamic load transients
US10951051B2 (en) Method and apparatus to charge power assist unit
CN109976490B (zh) 电源控制方法及电子设备
US7523321B2 (en) Information handling system including a battery switching circuit
US11500402B2 (en) Power-availability-based power delivery configuration system
US20230418349A1 (en) Input current limiting for redundant power supply loss on modular platforms
US20240126358A1 (en) Low power management for erp6 compliance

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22871267

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 18280222

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE