WO2023040330A1 - 数据处理的方法、装置以及系统 - Google Patents

数据处理的方法、装置以及系统 Download PDF

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Publication number
WO2023040330A1
WO2023040330A1 PCT/CN2022/094557 CN2022094557W WO2023040330A1 WO 2023040330 A1 WO2023040330 A1 WO 2023040330A1 CN 2022094557 W CN2022094557 W CN 2022094557W WO 2023040330 A1 WO2023040330 A1 WO 2023040330A1
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Prior art keywords
request
processor
data processing
queue
present application
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PCT/CN2022/094557
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English (en)
French (fr)
Inventor
吉辛·维克多
李君瑛
曲会春
古列维奇·埃琳娜
陆钢
毛修斌
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超聚变数字技术有限公司
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Publication of WO2023040330A1 publication Critical patent/WO2023040330A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]

Definitions

  • the present application relates to the field of storage, and more specifically, to a data processing method, device and system.
  • the data operation request (for example, write data request) sent by the application program in the processor can be sent to the target through the input and output (input output, IO) device (for example, network card). processor.
  • input and output (input output, IO) device for example, network card.
  • a data processing method based on a doorbell (DB) mechanism and an interrupt mechanism is proposed. Based on this method, the IO device can receive a data operation request sent by an application program in a processor, and perform an operation corresponding to the data operation request (that is, send the data operation request to a destination processor).
  • DB doorbell
  • the IO device can receive a data operation request sent by an application program in a processor, and perform an operation corresponding to the data operation request (that is, send the data operation request to a destination processor).
  • the present application provides a data processing method, device and system, based on the method, an IO device can flexibly process a received data request.
  • a data processing method comprising: an input/output IO device receives a first request; the IO device stores the first request; the IO device sends the first request according to the order in which the first request is received ask.
  • the IO device can send the first request according to the order of the first request, and based on this method, the IO device can flexibly process the received data request.
  • the storing the first request by the IO device includes: storing the first request in a queue by the IO device.
  • the IO device storing the first request to a queue includes: the IO device determining available units in the queue; the IO device storing the first request to The available unit.
  • the IO device sends the processing request according to the order in which the first request is received, including: the IO device determines the storage order of the first request in the queue; the When all the requests before the storage sequence of the first request have been sent, the IO device acquires the first request and sends the first request to the remote device, which communicates with the device where the IO device is located through the network. communication equipment.
  • the IO device is a network card or an accelerator.
  • the IO device may also be a processor bus adapter (host bus adapter, HBA), or a processor channel adapter (host channel adapter, HCA).
  • HBA host bus adapter
  • HCA host channel adapter
  • a data processing device which includes: a transceiver unit, configured to receive a first request; a processing unit, configured to store the first request; and the transceiver unit, configured to receive the first request The first request is sent in the order of requests.
  • the processing unit is further configured to store the first request in a queue.
  • the processing unit is further configured to: determine an available unit in the queue; and store the first request in the available unit.
  • the processing unit is further configured to: determine the storage order of the first request in the queue; the processing unit is further configured to: determine the storage order of the first request When the sending operation of the previous requests is completed, the first request is obtained; the transceiver unit is also used to: send the first request to a remote device, and the remote device is a device that communicates with the device where the IO device is located through the network.
  • the IO device is a network card or an accelerator.
  • the present application provides an IO device, and the IO device has a function of implementing the method in the first aspect and any possible implementation manner of the first aspect.
  • the functions may be implemented by hardware, or may be implemented by executing corresponding software through hardware.
  • Hardware or software includes one or more units corresponding to the functions described above.
  • the present application provides an IO device or other combined devices, components, etc. that can realize the functions of the above-mentioned IO device, including at least one processor and a communication interface.
  • the at least one processor is configured to execute computer programs or instructions, so that the IO device can implement the first aspect and the communication method in any possible implementation manner of the first aspect.
  • the IO device further includes at least one memory, the at least one memory is coupled to the at least one processor, and the computer program or instruction is stored in the at least one memory.
  • the memory can be integrated with the processor, or the memory can be set separately from the processor.
  • the IO device is a chip or a chip system.
  • the communication interface may be an input/output interface, an interface circuit, an output circuit, an input circuit, a pin or a related circuit on the chip or the chip system.
  • a processor may also be embodied as processing circuitry or logic circuitry.
  • the IO device is a chip or a chip system configured in the IO device.
  • the transceiver may be a transceiver circuit.
  • the input/output interface may be an input/output circuit.
  • a computer-readable storage medium for storing a computer program
  • the computer program includes instructions for executing the method in the above-mentioned first aspect and any possible implementation manner of the above-mentioned first aspect.
  • a sixth aspect provides a chip system, including at least one processor and an interface; the at least one processor is used to call and run a computer program, so that the chip system executes the first aspect and the first aspect above.
  • a chip system including at least one processor and an interface; the at least one processor is used to call and run a computer program, so that the chip system executes the first aspect and the first aspect above.
  • an instruction of a method in any possible implementation is used to call and run a computer program, so that the chip system executes the first aspect and the first aspect above.
  • the above-mentioned chip system may be a system on chip (system on chip, SOC), or a baseband chip, etc., wherein the baseband chip may include a processor, a channel encoder, a digital signal processor, a modem, and an interface module.
  • SOC system on chip
  • baseband chip may include a processor, a channel encoder, a digital signal processor, a modem, and an interface module.
  • a data processing system in a seventh aspect, includes the aforementioned IO device, or the aforementioned data processing apparatus.
  • FIG. 1 is a schematic diagram of a system architecture 100 applicable to an embodiment of the present application.
  • FIG. 2 is a schematic flowchart of a data processing method 200 provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a data processing method 300 provided by an embodiment of the present application.
  • Fig. 4 is a schematic diagram of a receiving loop provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a data processing device 500 provided in an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a hardware structure of a data processing apparatus 2000 according to an embodiment of the present application.
  • the present application presents various aspects, embodiments or features in terms of a system that can include a number of devices, components, modules and the like. It is to be understood and appreciated that the various systems may include additional devices, components, modules, etc. and/or may not include all of the devices, components, modules etc. discussed in connection with the figures. In addition, combinations of these schemes can also be used.
  • the network architecture and business scenarios described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute limitations on the technical solutions provided by the embodiments of the present application.
  • the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.
  • references to "one embodiment” or “some embodiments” or the like in this specification means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application.
  • appearances of the phrases “in one embodiment,” “in some embodiments,” “in other embodiments,” “in other embodiments,” etc. in various places in this specification are not necessarily All refer to the same embodiment, but mean “one or more but not all embodiments” unless specifically stated otherwise.
  • the terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to”, unless specifically stated otherwise.
  • At least one means one or more, and “multiple” means two or more.
  • “And/or” describes the association relationship of associated objects, indicating that there can be three types of relationships, for example, A and/or B, which can mean: A exists alone, A and B exist at the same time, and B exists alone, where A, B can be singular or plural.
  • the character “/” generally indicates that the contextual objects are an “or” relationship.
  • “At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items.
  • At least one item (piece) of a, b, or c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single or multiple .
  • FIG. 1 is a schematic diagram of a system architecture 100 applicable to an embodiment of the present application.
  • the system architecture 100 includes but is not limited to: a processor, a memory space 1 , an IO space 1 , an IO device (also called a peripheral device of the processor), an IO space 2 , a memory space 2 and an external network.
  • the following protocol can be used for communication between the processor and the IO device, but is not limited to: high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIe), or computer express link (compute express link, CXL) protocol.
  • PCIe peripheral component interconnect express
  • CXL compute express link
  • the address space addressable by the processor includes: the memory space 1 of the processor, the IO space 1 of the processor and the IO space 2 of the IO device (that is, the memory area of the IO device that allows the processor to access address space).
  • the IO space 2 may be an address space of a base address register (BAR) in an IO device.
  • BAR base address register
  • the IO space 2 can be mapped to the IO space 1 that the processor can recognize based on the address mapping method, so that the processor can access the IO space 2 of the IO device by accessing the IO space 1 to Realize getting information stored in IO space 2.
  • the processor may be a central processing unit (central process unit, CPU), and the processor may also be other general processors, digital signal processors (digital signal processor, DSP), application specific integrated circuits (application specific integrated circuit, ASIC), field-programmable gate array (field-programmable gate array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • a general purpose processor may be a microprocessor or any conventional processor or the like.
  • the processor may also be an on-chip (system of chip, SoC) or embedded processor.
  • SoC system of chip
  • the processor supports the functions of the memory management unit (MMU) (that is, mapping virtual addresses to physical addresses), and the functions of the input/output memory management unit (IOMMU) (that is, map physical addresses to virtual addresses).
  • Memory space 1, IO space 1, IO space 2 and memory space 2 can be composed of random access memory (random access memory, RAM), double data rate synchronous dynamic random access memory (DDR) or other storage media implementation.
  • the IO device may be not limited to: a network interface controller (network interface controller, NIC), a processor bus adapter (host bus adapter, HBA), a processor channel adapter (host channel adapter, HCA), Accelerator.
  • the structure of the external network is not specifically limited, for example, the external network may include at least one IO device, at least one processor and a memory.
  • system architecture 100 shown in FIG. 1 is only for illustration, and does not constitute any limitation to the applicable system architecture of this embodiment of the present application.
  • system architecture 100 shown in FIG. 1 only one processor communicates with one IO device is shown as an example.
  • the one processor in the system architecture 100 may also communicate with multiple IO devices.
  • the embodiment of the present application provides a data processing method, based on which an IO device can flexibly process a received data request.
  • FIG. 2 is a schematic flowchart of a data processing method 200 provided by an embodiment of the present application. As shown in FIG. 2 , the method 200 includes steps 210 to 230 , and the steps 210 to 230 will be described in detail below.
  • Step 210 the input/output IO device receives a first request.
  • Step 220 the IO device stores the first request.
  • the storing the first request by the IO device may include: storing the first request in a queue by the IO device.
  • storing the first request in the queue by the IO device may include the following steps: the IO device determines an available unit in the queue; and the IO device stores the first request in the available unit.
  • Step 230 the IO device sends the first request according to the order in which the first request is received
  • the IO device sends processing requests according to the order in which the first requests are received, which may include the following steps: the IO device determines the storage order of the first request in the queue; When the sending operation of all the requests is completed, the first request is obtained and the first request is sent to the remote device.
  • the remote device is a device that communicates with the device where the IO device is located through the network.
  • FIG. 3 is only intended to help those skilled in the art understand the embodiment of the present application, and is not intended to limit the embodiment of the application to the illustrated specific values or specific scenarios. Those skilled in the art can obviously make various equivalent modifications or changes according to the example in FIG. 3 given below, and such modifications and changes also fall within the scope of the embodiments of the present application.
  • the processor 1 and the IO device can also communicate based on the CXL protocol.
  • FIG. 3 is a schematic diagram of a data processing method 300 provided by an embodiment of the present application. As shown in FIG. 3 , the method 300 includes steps 310 to 390 . Steps 310 to 390 will be described in detail below.
  • the communication between the IO device and the processor 1 is based on the PCIe protocol, so the message sent between the IO device and the processor 1 is also called a PCIe message.
  • Step 310 the IO device sets entry address 1 and entry address 2 in the IO space 2 of the IO device, and sets an execution queue (execution queue, ExcQ) 1 and a submission queue (submission queue, SuQ) in the memory space 2 of the IO device 1.
  • execution queue execution queue
  • submission queue submission queue
  • the IO space 2 of the IO device is an address space accessible by the processor 1 .
  • the IO space 2 is mapped to the IO space 1 of the processor 1, so that the processor 1 can obtain information in the IO space 2 by accessing the IO space 1 (for example, entry address 1 or entry address 2).
  • the IO device can determine the destination address 1 according to the entry address 1 or the entry address 2, and the destination address 1 refers to the address stored by SuQ1 in the memory space 2 of the IO device.
  • ExcQ1 is used to process the submission queue element (submission queue element, SuQE) submitted by SuQ, and SuQE is used to carry the data operation request sent by the process of the application program in processor 1.
  • ExcQ1 may be used to send data operation requests corresponding to one or more SuQEs to a destination processor.
  • multiple ExcQ1s may be set in the memory space 2 of the IO device, and the multiple ExcQ1s correspond to multiple destination processors.
  • SuQ1 is used for buffering one or more SuQEs received by the IO device.
  • multiple SuQs may also be set in the memory space 2 of the IO device, and the multiple SuQs correspond to multiple priorities.
  • one SuQ can be used to receive the WQE of the priority corresponding to the one SuQ.
  • the priority of WQE1 is priority 1
  • the priority of SuQ1 is priority 1. In this way, WQE1 can be submitted to SuQ1.
  • step 390 may also be included: the processor 1 sends a creation message to the IO device, and the creation message is used to indicate that one or more SuQs are created in the memory space 2 of the IO device, and the one or more The plurality of SuQs includes SuQ1.
  • the creation message may also be used to indicate the queue depth information of one or more created SuQs, and the queue depth information of any SuQ indicates the maximum number of SuQEs that any SuQ can handle.
  • SuQ1 may be set in the pinned memory (pinned memory) of the IO space 2 of the IO device, or in the address space corresponding to the non-pinned memory (non-pinned memory), which is not specifically limited.
  • Step 320 processor 1 creates acceptance ring (acceptance ring, AR) 1 and AR2 in memory space 1 of processor 1, and sets AR1 to be associated with entry address 1, and set AR2 to be associated with entry address 2.
  • the memory space 1 of the processor 1 may be understood as the memory space corresponding to the memory of the processor 1 .
  • AR can be understood as a section of address space, that is, AR is a section of address space in memory space 1 corresponding to processor 1, and this section of address space can be pinned memory or non-pinned memory ) corresponding to the address space.
  • An AR includes multiple AEs (for example, but not limited to, 64 AEs), and each AE may include field 1, field 2, and field 3.
  • field 1 can occupy 1 bit, and the value of this 1 bit is used to indicate IO device or processor 1.
  • the value of this field 1 can be set equal to "1" to indicate an IO device, and the value of this field 1 can be set to A value equal to "0" indicates processor 1.
  • processor 1 determines that the value of field 1 in an AE indicates an IO device
  • processor 1 needs to (re)send the SuQE associated with the AE to the IO device.
  • processor 1 determines that the value of field 1 in an AE indicates processor 1
  • processor 1 can know that the SuQE associated with this AE has been successfully executed by the IO device based on the AE, and then processor 1 will Clear the content recorded in this AE.
  • Field 2 indicates the execution result of the SuQE associated with the AE
  • Field 3 indicates the index value of the SuQE associated with the AE, and the index value is the same as the index value of the AE in the AR.
  • FIG. 4 shows a schematic diagram of the AR provided in this application.
  • AR in FIG. 4 is a section of address corresponding to the fixed memory in memory space 1 of processor 1
  • a value of 1 indicates an IO device.
  • step 330 processor 1 acquires SuQE1 and generates PCIe packet 1, PCIe packet 1 includes information of entry address 1, SuQE1 and index value 1 associated with SuQE1.
  • the acquisition of SuQE1 by processor 1 may include the following operations: process 1 of application program 1 in processor 1 sends a WQE1; processor 1 converts the format of WQE1 to obtain SuQE1.
  • SuQE1 can be used to request data 1 to be written into processor 2
  • SuQE1 can carry information including the following: data 1 information (the address information for storing data 1, the length information of data 1, and the memory space of data 1 in processor 2 location in ) and information for identifying processor 2 (for example, a media access control (media access control, MAC) address of processor 2 or an identifier of processor 2).
  • the index value 1 is used to indicate an AE in AR1, and the index value of the AE in AR1 is equal to the index value 1.
  • the AE in the AR1 indicated by the index value 1 is denoted as AE1 hereinafter.
  • the index value 1 is a value in the tag list (tag list), and this value corresponds to an index value of an AE in the AR one by one.
  • the application program that sends the data operation request is a trusted application program, or it may be an untrusted application program.
  • the hypervisor layer is credible, because the provider of the cloud service is responsible for this part.
  • VM virtual machine
  • VM virtual machine
  • Step 340 the processor 1 sends the PCIe packet 1 to the IO device.
  • processor 1 sets the field content of AE1 in AR1 corresponding to index value 1.
  • processor 1 sets the value of field 1 of AE1, the set value of field 1 indicates processor 1, and sets the content of field 3 as index value 1.
  • the content of field 2 can be empty.
  • the value of field 1 indicates processor 1. It can be understood that the SuQE1 associated with the AE1 where field 1 is located has been sent to the IO device. The content of the field 2 may be empty, which means that the processor 1 has not yet received the execution result of the IO device on the SuQE1 associated with the AE1 where the field 2 is located.
  • Step 360 the IO device processes the PCIe message 1, first submits SuQE1 to SuQ1, and then submits SuQE in SuQ1 to ExcQ.
  • the IO device receives the PCIe message 1 and processes the PCIe message 1, the following information can be obtained: the information of the entry address 1, the index value 1 associated with SuQE1 and SuQE1. Thereafter, the IO device determines the destination address 1 according to the information of the entry address 1, and the destination address 1 refers to the address stored by SuQ1 in the memory space 2 of the IO device. Based on this, the IO device can submit SuQE1 to SuQ1 according to the destination address 1.
  • the IO device can submit SuQE1 in SuQ1 to the corresponding ExcQ1 according to certain rules, and ExcQ1 can process the received SuQE1, that is, the result of the processing is to send the data operation request corresponding to SuQE1 to the destination processor. So far, the IO device has successfully executed the data operation request corresponding to SuQE1.
  • the IO device can submit SuQE1 in SuQ1 to ExcQ1 according to certain rules, which are not specifically limited.
  • the IO device may submit SuQE1 from SuQ1 to ExcQ1 according to the priority corresponding to SuQE1.
  • the multiple SuQEs include SuQE1, and SuQE1 has the highest priority among the multiple SuQEs. Based on this, the IO device can first submit SuQE1 in SuQ1 to ExcQ1.
  • Step 370 the IO device sends a PCIe message 2 to the processor 1, the PCIe message 2 includes an index value 1, and the execution result of SuQE1 associated with the index value 1.
  • the execution result of the SuQE1 associated with the index value 1 is successful, that is, the IO device has successfully processed the data operation request corresponding to the SuQE1.
  • step 380 processor 1 processes PCIe packet 2, and updates the content of AE associated with index value 1.
  • the processor 1 parses the PCIe message 1 to obtain the following information: index value 1, and the execution result of SuQE1 associated with the index value 1.
  • the processor 1 updates the content of the AE associated with the index value 1, which may include the following steps: according to the index value 1, it is determined that the AE associated with the index value 1 is AE1 in AR1; the processor 1 determines that the AE associated with the index value 1 After the execution result of SuQE1 is successful, processor 1 will record the contents in AE1, after that, the AE1 can be used to record the contents of other SuQEs.
  • the IO device successfully processes the received SuQE1 and the interaction process between the IO device and the processor 1 .
  • the IO device fails to process the received SuQE1 successfully, and thereafter, the following operation 1 or operation 2 may be performed:
  • the IO device sends a PCIe message 2 to the processor 1.
  • the PCIe message 2 includes indication information 1, and the indication information 1 is used to instruct the processor 1 to resubmit SuQE1 to the IO device through the entry address 1.
  • processor 1 receives PCIe message 2, it will not modify the field content of the AE associated with the SuQE1.
  • processor 1 will resend a PCIe message to the IO device according to the method described in step 330 above.
  • the content carried by the PCIe message is the same as the content carried by the PCIe message 1 in step 330 above.
  • the IO device sends a PCIe message 2 to the processor 1.
  • the PCIe message 2 includes instruction information 1, and the instruction information 1 is used to instruct the processor 1 to resubmit SuQE1 to the IO device through the entry address 2, where the entry address 2 is associated with AR2.
  • the processor 1 can generate a PCIe message 3 according to the PCIe message 2.
  • the PCIe message 3 includes: the information of the entry address 2, the index value 2 associated with SuQE1 and SuQE1, and the index value 2 is used to indicate an AE in AR2 (denoted as AE2), that is, the index value 2 is in one-to-one correspondence with the index value of AE2 in AR2.
  • the processor 1 sends the PCIe message 3 to the IO device.
  • the IO device receives the PCIe message 3 and executes the above step 360 to the above step 380 .
  • the IO device can generate a PCIe message 4, which includes a data operation request corresponding to SuQE1 and information for identifying the destination processor (for example, MAC address of the destination processor). Thereafter, the IO device sends a PCIe packet 4 .
  • the destination processor will receive the PCIe message 4 and execute the data operation request (for example, write data request) in the PCIe message 4 .
  • FIG. 3 is only for illustration, and does not constitute any limitation to the data processing method provided in the embodiment of the present application.
  • two ARs that is, AR1 and AR2
  • two entry addresses that is, entry address 1 and entry address 2
  • An ExcQ is set as an example, and the data processing method provided by the embodiment of the present application is introduced.
  • the AR in the foregoing method 300 may also be in the form of a list, etc., which is not specifically limited.
  • the AE in the AR can be used to record the processing result of the data operation request corresponding to SuQE in processor 1, so that processor 1 can quickly obtain the data operation request corresponding to SuQE The processing result of the data operation request.
  • the IO device By setting one or more SuQs in the memory space 2 of the IO device, one or more SuQEs submitted by the processor to the IO device due to insufficient processing capacity of the IO device (for example, the ExcQ queue in the IO device is full) can be avoided. missing problem.
  • SuQ is set in the memory space 2 of the IO device, which is also beneficial to improve the utilization rate of the memory of the processor 1 . To sum up, based on the data processing method provided by the embodiment of the present application, the IO device can flexibly process the received data request.
  • FIG. 2 to FIG. 4 The data processing methods described above in FIG. 2 to FIG. 4 are only illustrative, and do not constitute any limitation to the data processing methods provided in the embodiments of the present application.
  • the data processing method provided by the embodiment of the present application is described in detail above with reference to FIG. 2 to FIG. 4 , and the embodiment of the device of the present application will be described in detail below in conjunction with FIG. 5 and FIG. 6 .
  • the descriptions of the method embodiments correspond to the descriptions of the device embodiments. Therefore, for parts not described in detail, reference may be made to the foregoing method embodiments.
  • FIG. 5 is a schematic structural diagram of a data processing device 500 provided in an embodiment of the present application.
  • the data processing apparatus 500 shown in FIG. 5 may execute corresponding steps of the data transmission method in the foregoing embodiments.
  • the data processing apparatus 500 includes: a transceiver unit 510 and a processing unit 520 .
  • the data processing apparatus 500 is set in an IO device, and the transceiver unit 510 is configured to perform the above-mentioned step 210 , step 230 , step 340 , step 370 and step 390 .
  • the processing unit 520 is configured to execute the above step 220 , step 310 and step 360 .
  • the data processing device 500 is set in a processor (for example, the processor 1 in the above-mentioned method 300), and the transceiver unit 510 is configured to perform the above-mentioned step 340, step 370 and step 390 .
  • the processing unit 520 is configured to execute the above step 320 , step 330 , step 350 and step 380 .
  • FIG. 6 is a schematic diagram of a hardware structure of a data processing apparatus 2000 according to an embodiment of the present application.
  • the data processing apparatus 2000 shown in FIG. 6 may execute the data processing method in the foregoing embodiments.
  • the data processing apparatus 2000 includes a processor 2001 , a memory 2002 , an interface 2003 and a bus 2004 .
  • the interface 2003 can be implemented in a wireless or wired way, specifically, it can be a network card.
  • the aforementioned processor 2001 , memory 2002 and interface 2003 are connected through a bus 2004 .
  • the interface 2003 may specifically include a transmitter and a receiver, and the device for data processing implements the above-mentioned sending and receiving.
  • the processor 2001 is configured to execute the processing performed by the data processing device in the above embodiments.
  • the memory 2002 includes an operating system 20021 and an application program 20022 for storing programs, codes or instructions.
  • the memory 2002 may include a read-only memory (read-only memory, ROM) and a random access memory (random access memory, RAM).
  • ROM read-only memory
  • RAM random access memory
  • the ROM includes a basic input/output system (basic input/output system, BIOS) or an embedded system
  • BIOS basic input/output system
  • the RAM includes an application program and an operating system.
  • Fig. 6 only shows a simplified design of the device 2000 for data processing. In practical applications, the data processing device may contain any number of interfaces, processors or memories.
  • the embodiment of the present application also provides a computer-readable medium, the computer-readable medium stores program codes, and when the computer program codes run on the computer, the computer executes the above-mentioned IO device or the method performed by the processor 1 .
  • These computer-readable storages include, but are not limited to, one or more of the following: read-only memory (read-only memory, ROM), programmable ROM (programmable ROM, PROM), erasable PROM (erasable PROM, EPROM), Flash memory, electrical EPROM (electrically EPROM, EEPROM) and hard drive (hard drive).
  • the embodiment of the present application also provides a chip system, the chip system includes: at least one processor, at least one memory and an interface circuit, the interface circuit is responsible for information exchange between the chip system and the outside world, the at least one memory, The interface circuit and the at least one processor are interconnected through a line, and instructions are stored in the at least one memory; the instructions are executed by the at least one processor, so as to perform the IO involved in the method of the above-mentioned various aspects. Operation of device or processor 1.
  • the chip system can be based on a central processing unit (central processing unit, CPU), a microcontroller (micro controller unit, MCU), a microprocessor (micro processing unit, MPU), a digital signal processor (digital signal processor) signal processing, DSP), system on chip (system on chip, SoC), application-specific integrated circuit (application-specific integrated circuit, ASIC), field programmable gate array (field programmable gate array, FPGA) or programmable logic device (programmable logic device, PLD) in the form of realization.
  • CPU central processing unit
  • MCU microcontroller
  • MPU microprocessor
  • DSP digital signal processor
  • SoC system on chip
  • ASIC application-specific integrated circuit
  • FPGA field programmable gate array
  • PLD programmable logic device
  • the embodiment of the present application also provides a computer program product, which is applied to the IO device or the processor 1.
  • the computer program product includes a series of instructions. When the instructions are executed, the above-mentioned various aspects are performed The operation of the IO device or processor 1 described in the method.
  • the embodiment of the present application also provides a system, including the above data processing apparatus 500 .
  • the disclosed systems, devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the functions described above are realized in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disc and other media that can store program codes. .

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Abstract

本申请提供了一种数据处理的方法、装置以及系统。该方法包括：输入输出IO设备接收第一请求；IO设备存储第一请求；IO设备根据接收第一请求的顺序发送第一请求。基于该方法IO设备能够灵活地对接收到的数据请求进行处理。

Description

数据处理的方法、装置以及系统
本申请要求于2021年09月14日提交中国专利局、申请号为202111076869.0、申请名称为“数据处理的方法、装置以及系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储领域，更具体地，涉及一种数据处理的方法、装置以及系统。
背景技术
目前，处理器中的应用程序发送的数据操作请求(例如，写数据请求)，可以通过输入输出(input output，IO)设备(例如，网卡)，将该应用程序对应的数据操作请求发送至目的处理器。
在相关技术中，提出了一种基于门铃(doorbell，DB)机制和中断机制的数据处理的方法。基于这种方法可以实现IO设备接收一个处理器中的应用程序发送的数据操作请求，并执行数据操作请求对应的操作(即，将该数据操作请求发送至目的处理器)。但基于这种实现方式，存在数据处理过程复杂和内存利用率低的问题。
发明内容
本申请提供一种数据处理的方法、装置以及系统，基于该方法IO设备能够灵活地对接收到的数据请求进行处理。
第一方面，提供了一种数据处理的方法，该方法包括：输入输出IO设备接收第一请求；该IO设备存储该第一请求；该IO设备根据接收该第一请求的顺序发送该第一请求。
上述技术方案中，IO设备接收第一请求后，IO设备能够根据该第一请求的顺序发送该第一请求，基于该方法IO设备能够灵活地对接收到的数据请求进行处理。
结合第一方面，在第一方面的某些实现方式中，该IO设备存储该第一请求，包括：该IO设备将该第一请求存储至队列。
结合第一方面，在第一方面的某些实现方式中，该IO设备将该第一请求存储至队列，包括：该IO设备确定该队列中可用单元；该IO设备将该第一请求存储至该可用单元。
结合第一方面，在第一方面的某些实现方式中，该IO设备根据接收该第一请求的顺序发送该处理请求，包括：该IO设备确定该队列中该第一请求的存储顺序；该IO设备在该第一请求的存储顺序前的请求均完成发送操作时，获取该第一请求，并向远端设备发送该第一请求，该远端设备为与该IO设备所在设备通过网络进行通信的设备。
结合第一方面，在第一方面的某些实现方式中，该IO设备为网卡或加速器。
可选的，IO设备还可以是处理器总线适配器(host bus adapter，HBA)，或处理器通道适配器(host channel adapter，HCA)。
第二方面，提供了一种数据处理的装置，该装置包括：收发单元，用于接收第一请求；处理单元，用于存储该第一请求；该收发单元，还用于根据接收该第一请求的顺序发送该第一请求。
结合第二方面，在第二方面的某些实现方式中，该处理单元，还用于将该第一请求存 储至队列。
结合第二方面，在第二方面的某些实现方式中，该处理单元还用于：确定该队列中可用单元；将该第一请求存储至该可用单元。
结合第二方面，在第二方面的某些实现方式中，该处理单元还用于：确定该队列中该第一请求的存储顺序；该处理单元还用于：在该第一请求的存储顺序前的请求均完成发送操作时，获取该第一请求；该收发单元还用于：向远端设备发送该第一请求，该远端设备为与该IO设备所在设备通过网络进行通信的设备。
结合第二方面，在第二方面的某些实现方式中，该IO设备为网卡或加速器。
第三方面，本申请提供了一种IO设备，IO设备具有实现第一方面以及第一方面中任一种可能的实现方式中的方法的功能。功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。硬件或软件包括一个或多个与上述功能相对应的单元。
第四方面，本申请提供一种IO设备或者其他可实现上述IO设备功能的组合器件、部件等，包括至少一个处理器和通信接口。该至少一个处理器，用于执行计算机程序或指令，以使得该IO设备可以实现上述第一方面以及第一方面中任一种可能实现方式中的通信方法。
可选地，该IO设备还包括至少一个存储器，该至少一个存储器与该至少一个处理器耦合，该计算机程序或指令存储在该至少一个存储器中。其中，该存储器可以与该处理器集成在一起，或者该存储器与处理器分离设置。
在一种实现方式中，该IO设备为芯片或芯片系统。当该IO设备为芯片或芯片系统时，通信接口可以是该芯片或芯片系统上的输入/输出接口、接口电路、输出电路、输入电路、管脚或相关电路等。处理器也可以体现为处理电路或逻辑电路。
在另一种实现方式中，该IO设备为配置于IO设备中的芯片或芯片系统。
可选地，收发器可以为收发电路。可选地，输入/输出接口可以为输入/输出电路。
第五方面，提供了一种计算机可读存储介质，用于存储计算机程序，该计算机程序包括用于执行上述第一方面，以及上述第一方面的任意可能的实现方式中的方法的指令。
第六方面，提供了一种芯片系统，包括至少一个处理器和接口；所述至少一个所述处理器，用于调用并运行计算机程序，以使所述芯片系统执行上述第一方面以及上述第一方面任意可能的实现方式中的方法的指令。
上述芯片系统可以是片上系统(system on chip，SOC)，也可以是基带芯片等，其中基带芯片可以包括处理器、信道编码器、数字信号处理器、调制解调器和接口模块等。
第七方面，提供了一种数据处理的系统，所述系统包括前述的IO设备，或前述的数据处理的装置。
附图说明
图1是适用于本申请实施例的一种系统架构100的示意图。
图2是本申请实施例提供的一种数据处理的方法200的示意性流程图。
图3是本申请实施例提供的一种数据处理的方法300的示意性。
图4是本申请实施例提供的一种接收环的示意图。
图5是本申请实施例提供的一种数据处理的装置500的示意性结构图。
图6是本申请实施例的数据处理的装置2000的硬件结构示意图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
本申请的实施方式部分使用的术语仅用于对本申请的具体实施例进行解释，而非旨在限定本申请。
本申请中术语“第一”“第二”“第三”等字样用于对作用和功能基本相同的相同项或相似项进行区分，“第一”、“第二”和“第三”之间不具有逻辑或时序上的依赖关系，也不对数量和执行顺序进行限定。
本申请将围绕可包括多个设备、组件、模块等的系统来呈现各个方面、实施例或特征。应当理解和明白的是，各个系统可以包括另外的设备、组件、模块等，并且/或者可以并不包括结合附图讨论的所有设备、组件、模块等。此外，还可以使用这些方案的组合。
另外，在本申请实施例中，“示例的”、“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用示例的一词旨在以具体方式呈现概念。
本申请实施例描述的网络架构以及业务场景是为了更加清楚的说明本申请实施例的技术方案，并不构成对于本申请实施例提供的技术方案的限定，本领域普通技术人员可知，随着网络架构的演变和新业务场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
在本说明书中描述的参考“一个实施例”或“一些实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在一些实施例中”、“在其他一些实施例中”、“在另外一些实施例中”等不是必然都参考相同的实施例，而是意味着“一个或多个但不是所有的实施例”，除非是以其他方式另外特别强调。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A,B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a,b,或c中的至少一项(个)，可以表示：a,b,c,a-b,a-c,b-c,或a-b-c，其中a,b,c可以是单个，也可以是多个。
下面，介绍本申请实施例的相关技术：
图1是适用于本申请实施例的一种系统架构100的示意图。如图1所示，系统架构100中包括但不限于：处理器，内存空间1，IO空间1，IO设备(又称为处理器的外围设备)，IO空间2，内存空间2和外部网络。其中，处理器与IO设备之间可以但不限于使用如下协议通信：高速串行计算机扩展总线标准(peripheral component interconnect express，PCIe)，或计算机快速互联(compute express link，CXL)协议。
在系统架构100中，处理器可寻址的地址空间包括：处理器的内存空间1，处理器的IO空间1和IO设备的IO空间2(即，IO设备的存储区域中允许处理器访问的地址空间)。例如IO空间2可以为IO设备中基地址寄存器的地址空间(baseaddress register，BAR)。在本申请实施例中，基于地址映射的方式可以将IO空间2映射到处理器可以识别的IO空间1中，这样，处理器就可以通过访问IO空间1来访问IO设备的IO空间2，以实现获取存储 在IO空间2中的信息。
本申请实施例中，处理器可以为中央处理单元(central process unit，CPU)，该处理器还可以是其他通用处理器、数字信号处理器(digital signal processor，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field-programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者是任何常规的处理器等。该处理器还可以为一种片上芯片(system of chip，SoC)或者嵌入式处理器。该处理器支持发送容量至少64字节的PCIe报文。该处理器支持内存管理单元(memory management unit，MMU)的功能(即，将虚拟地址映射成物理地址)，以及输入/输出内存管理单元(input/output memory management unit，IOMMU)的功能(即，将物理地址映射成虚拟地址)。内存空间1，IO空间1，IO空间2和内存空间2可以由随机存取器(random access memory，RAM)，双倍速率同步动态随机存储器(double data rate synchronous dynamic random access memory，DDR)或其他存储介质实现。本申请实施例中，IO设备可以不但不限于是：网络接口控制器(network interface controller，NIC)，处理器总线适配器(host bus adapter，HBA)，处理器通道适配器(host channel adapter，HCA)，加速器(accelerator)。对外部网络的结构不作具体限定，例如外部网络可以包括至少一个IO设备，至少一个处理器和存储器。
应理解，图1所示的系统架构100仅为示意，并不对本申请实施例适用的系统架构构成任何限定。图1所示的系统架构100中仅以一个处理器与一个IO设备通信为例示出，可选的，系统架构100中的该一个处理器还可以与多个IO设备通信。
本申请实施例提供了一种数据处理的方法，基于该方法IO设备能够灵活地对接收到的数据请求进行处理。
图2是本申请实施例提供的一种数据处理的方法200的示意性流程图。如图2所示，该方法200包括步骤210至步骤230，下面具体介绍步骤210至步骤230。
步骤210，输入输出IO设备接收第一请求。
步骤220，IO设备存储所述第一请求。
可选的，在一些实现方式中，IO设备存储第一请求，可以包括：IO设备将第一请求存储至队列。
可选的，在一些实现方式中，IO设备将第一请求存储至队列，可以包括如下步骤：IO设备确定队列中可用单元；IO设备将第一请求存储至可用单元。
步骤230，IO设备根据接收所述第一请求的顺序发送所述第一请求
可选的，在一些实现方式中，IO设备根据接收第一请求的顺序发送处理请求，可以包括如下步骤：IO设备确定队列中第一请求的存储顺序；IO设备在第一请求的存储顺序前的请求均完成发送操作时，获取第一请求，并向远端设备发送第一请求，远端设备为与IO设备所在设备通过网络进行通信的设备。
下面结合图3，介绍本申请实施例提供的数据处理的方法的实施例。图3的例子仅仅是为了帮助本领域技术人员理解本申请实施例，而非要将申请实施例限制于所示例的具体数值或具体场景。本领域技术人员根据下面所给出的图3的例子，显然可以进行各种等价的修改或变化，这样的修改和变化也落入本申请实施例的范围内。例如，处理器1与IO设备还可以基于CXL协议进行通信。
图3是本申请实施例提供的一种数据处理的方法300的示意性。如图3所示，该方法300包括步骤310至步骤390。下面具体介绍步骤310至步骤390。
在本申请实施例中，IO设备与处理器1之间基于PCIe协议进行通信，故IO设备与处理器1之间发送的报文又称为PCIe报文。
步骤310，IO设备在IO设备的IO空间2中设置入口地址1和入口地址2，以及在IO设备的内存空间2中设置执行队列(execution queue，ExcQ)1和提交队列(submission queue，SuQ)1。
其中，IO设备的IO空间2是处理器1可以访问的地址空间。具体实现时，基于地址映射的方式，将IO空间2映射至处理器1的IO空间1中，这样，处理器1可以通过访问IO空间1以获取IO空间2中的信息(例如，入口地址1或入口地址2)。IO设备根据入口地址1或入口地址2，可以确定目的地址1，目的地址1是指SuQ1在IO设备的内存空间2中存储的地址。
其中，ExcQ1用于对SuQ提交的提交队列元素(submission queue element，SuQE)进行处理，SuQE用于携带是处理器1中的应用程序的进程发送的数据操作请求。在本申请实施例中，ExcQ1可以用于将一个或多个SuQE对应的数据操作请求发送至一个目的处理器。可选的，IO设备的内存空间2中可以设置多个ExcQ1，多个ExcQ1对应多个目的处理器。
其中，SuQ1用于缓存IO设备接收到的一个或多个SuQE。可选的，在另一些实现方式中，在IO设备的内存空间2中还可以设置多个SuQ，该多个SuQ对应多个优先级。其中，一个SuQ可以用于接收与该一个SuQ对应的优先级的WQE。例如，WQE1的优先级为优先级1，SuQ1的优先级为优先级1，这样，WQE1就可以提交至SuQ1中。
可选的，在上述步骤310之前，还可以包括步骤390：处理器1向IO设备发送创建消息，该创建消息用于指示在IO设备的内存空间2中创建一个或多个SuQ，该一个或多个SuQ包括SuQ1。可选的，该创建消息还可以用于指示创建的一个或多个SuQ的队列深度信息，任意一个SuQ的队列深度信息指示该任意一个SuQ能够处理的SuQE的最大数目。
在本申请实施例中，SuQ1可以设置在IO设备的IO空间2的固定内存(pinned memory)，或非固定内存(non-pinned memory)对应的地址空间中，对此不作具体限定。
步骤320，处理器1在处理器1的内存空间1中创建接收环(acceptance ring，AR)1和AR2，并设置AR1与入口地址1关联，以及设置AR2与入口地址2关联。
其中，处理器1的内存空间1，可以理解为，处理器1的存储器对应的内存空间。
其中，AR可以理解为是一段地址空间，即AR是对应处理器1的内存空间1中的一段地址空间，该一段地址空间可以是固定内存(pinned memory)，或非固定内存(non-pinned memory)对应的地址空间。一个AR中包括多个AE(例如但不限于，64个AE)，每个AE可以包括字段1，字段2和字段3。其中，字段1可以占用1个比特，该1个比特的取值用于指示IO设备或处理器1，例如可以设置该字段1的取值等于“1”指示IO设备，设置该字段1的取值等于“0”指示处理器1。当处理器1确定一个AE中的字段1的取值指示是IO设备时，处理器1需要将与该一个AE关联的SuQE(重新)发送给IO设备。当处理器1确定一个AE中的字段1的取值指示是处理器1时，处理器1基于该一个AE可以得知与该一个AE关联的SuQE已经被IO设备成功执行，此后处理器1会将该一个AE中记录的内容清空。字段2指示与该一个AE关联的SuQE的执行结果，字段3指示与该一个AE关 联的SuQE的索引值，且该索引值与该一个AE在AR中的索引值相同。
如图4示出了本申请提供的AR的示意图。图4中AR是处理器1的内存空间1中固定内存对应的一段地址，O＝H表示对应的AE中的字段1的取值指示是处理器1，O＝H表示对应的AE中的字段1的取值指示是IO设备。
步骤330，处理器1获取SuQE1，并生成PCIe报文1，PCIe报文1包括入口地址1的信息，SuQE1和SuQE1关联的索引值1。
其中，处理器1获取SuQE1，可以包括如下操作：处理器1中的应用程序1的进程1发送一个WQE1；处理器1对WQE1的格式进行转换得到SuQE1。当SuQE1可以用于请求将数据1写入处理器2时，SuQE1可以携带包括如下信息：数据1的信息(存储数据1的地址信息，数据1的长度信息以及数据1在处理器2的内存空间中的位置)和用于标识处理器2的信息(例如，处理器2的媒体接入控制(media access control，MAC)地址或处理器2的标识)。
其中，索引值1用于指示AR1中的一个AE，且该一个AE在AR1的索引值大小等于该索引值1的大小。为便于描述，下文中将索引值1指示的AR1中的AE，记为AE1。例如，图4所示，索引值1是标签列表(tag list)中的一个值，该一个值与AR中的一个AE的索引值一一对应。
在本申请实施例中，对发送数据操作请求的应用程序(例如，上述应用程序1)的类型不作具体限定。例如，发送数据操作请求的应用程序是可信任的应用程序，也可以是不可信任的应用程序。在一个示例中，可以根据是否存在恶意攻击行为来判断一个应用程序是可信任的应用程序或是不可信任的应用程序。例如，在虚拟化场景一般可以认为超级监督者(hypervisor)层是可信的，因为这部分有云业务的提供商负责。又如，虚拟机(virtual machine，VM)VM会租给租房使用，可能会有篡改、恶意的攻击行为发生的可能性，所以可以认为虚拟机里的应用程序是不可信任的应用程序。在另一个示例中，可以根据软件质量的好坏判断一个应用程序是可信任的应用程序或是不可信任的应用程序。
步骤340，处理器1向IO设备发送PCIe报文1。
步骤350，处理器1设置索引值1对应的AR1中的AE1的字段内容。
其中，处理器1设置AE1的字段1的值，设置后的字段1的值指示处理器1，设置字段3的内容为索引值1。此时，字段2的内容可以空。字段1的值指示处理器1，可以理解为，与该字段1所在的AE1关联的SuQE1已经发送给了IO设备。字段2的内容可以空，可以理解为，处理器1尚未接收到IO设备对与该字段2所在的AE1关联的SuQE1的执行结果。
步骤360，IO设备对PCIe报文1进行处理，先将SuQE1提交至SuQ1中，再将SuQ1中的SuQE提交至ExcQ中。
上述步骤360中，IO设备接收到PCIe报文1后，对PCIe报文1进行处理后，可以得到如下信息：入口地址1的信息，SuQE1和SuQE1关联的索引值1。此后，IO设备根据入口地址1的信息，确定目的地址1，目的地址1是指SuQ1在IO设备的内存空间2中存储的地址。基于此，IO设备可以根据目的地址1将SuQE1提交至SuQ1中。此后，IO设备可以按照一定的规则将SuQ1中的SuQE1提交至对应的ExcQ1中，ExcQ1可以对应接收到的SuQE1进行处理，即处理的结果是将SuQE1对应的数据操作请求发送至目的处理器中，至 此，IO设备成功执行了SuQE1对应的数据操作请求。
其中，IO设备可以按照一定的规则将SuQ1中的SuQE1提交至ExcQ1中，对该规则不作具体限定。例如，IO设备可以根据SuQE1对应的优先级，将SuQE1从SuQ1中提交至ExcQ1。例如，当SuQ1中存储多个SuQE，多个SuQE包括SuQE1，且SuQE1是该多个SuQE中优先级最高的。基于此，IO设备可以先将SuQ1中的SuQE1提交至ExcQ1中。
步骤370，IO设备向处理器1发送PCIe报文2，PCIe报文2包括索引值1，索引值1关联的SuQE1的执行结果。
其中，索引值1关联的SuQE1的执行结果为成功，即IO设备已经成功处理了该SuQE1对应的数据操作请求。
步骤380，处理器1对PCIe报文2进行处理，并对与索引值1关联的AE的内容进行更新。
其中，处理器1接收PCIe报文2后，对PCIe报文1进行解析，可以得到如下信息：索引值1，索引值1关联的SuQE1的执行结果。
其中，处理器1对与索引值1关联的AE的内容进行更新，可以包括如下步骤：根据索引值1确定与索引值1关联的AE是AR1中的AE1；处理器1确定索引值1关联的SuQE1的执行结果为成功后，处理器1将AE1中记录的内容情况，此后，该AE1可以用于记录其它SuQE的内容。
可以理解的是，上述步骤350至上述步骤380中，以IO设备成功处理接收到的SuQE1，以及IO设备与处理器1之间的交互流程。可选的，在另一些实现方式中，在上述步骤350中IO设备未能成功处理接收到的SuQE1，此后还可以执行如下操作1或操作2：
操作1：
IO设备向处理器1发送PCIe报文2，PCIe报文2包括指示信息1，指示信息1用于指示处理器1通过入口地址1重新向IO设备提交SuQE1。相应地，处理器1接收到PCIe报文2，并不会修改与该SuQE1关联的AE的字段内容，此时，处理器1会按照上述步骤330中所描述的方法向IO设备重新发送一个PCIe报文，该一个PCIe报文携带的内容与上述步骤330中的PCIe报文1携带的内容相同。
操作2：
IO设备向处理器1发送PCIe报文2，PCIe报文2包括指示信息1，指示信息1用于指示处理器1通过入口地址2重新向IO设备提交SuQE1，其中，入口地址2与AR2关联。相应地，处理器1接收到PCIe报文2后，根据PCIe报文2可以生成PCIe报文3，PCIe报文3包括：入口地址2的信息，SuQE1和SuQE1关联的索引值2，该索引值2用于指示AR2中的一个AE(记为AE2)，即索引值2与AR2中的AE2的索引值一一对应。此后，处理器1向IO设备发送PCIe报文3。相应的，IO设备接收到PCIe报文3执行上述步骤360至上述步骤380。
可选的，IO设备在ExcQ1中对SuQE1进行处理后，IO设备可以生成一个PCIe报文4，该一个PCIe报文4包括SuQE1对应的数据操作请求和用于标识目的处理器的信息(例如，目的处理器的MAC地址)。此后，IO设备发送PCIe报文4。相应地，目的处理器会接收到PCIe报文4，并执行PCIe报文4中的数据操作请求(例如，写数据请求)。
应理解，上述图3仅为示意，并不对本申请实施例提供的数据处理的方法构成任何限 定。在上述图3中以在处理器1中设置2个AR(即，AR1和AR2)，在IO设备设置两个入口地址(即，入口地址1和入口地址2)，在IO设备的内存空间2中设置一个ExcQ为例，介绍了本申请实施例提供的数据处理的方法。可选的，在一些实现方式中，上述方法300中的AR还可以是列表形式等，对此不作具体限定。
在本申请实施例中，通过在处理器1中设置AR，该AR中的AE可以用于记录处理器1中的SuQE对应的数据操作请求的处理结果，能够实现处理器1快速获取SuQE对应的数据操作请求的处理结果。通过在IO设备的内存空间2中设置一个或多个SuQ，可以避免由于IO设备处理能力不足(例如，IO设备中的ExcQ队列已满)，导致处理器提交至IO设备的一个或多个SuQE丢失的问题。另外，SuQ设置在IO设备的内存空间2，还有利于提高处理器1的内存的利用率。综上，基于本申请实施例提供的数据处理的方法，IO设备能够灵活地对接收到的数据请求进行处理。
上述图2至图4所描述的数据处理的方法仅为示意，并不对本申请实施例提供的数据处理的方法构成任何限定。上文结合图2至图4，详细描述了本申请实施例提供的数据处理的方法，下面将结合图5和图6，详细描述本申请的装置的实施例。方法实施例的描述与装置实施例的描述相互对应，因此，未详细描述的部分可以参见前面方法实施例。
图5是本申请实施例提供的一种数据处理的装置500的示意性结构图。图5所示的数据处理的装置500可以执行上述实施例的数据传输的方法的相应步骤。如图5所示，该数据处理的装置500包括：收发单元510和处理单元520。
在一些实现方式中，该数据处理的装置500设置于IO设备中，收发单元510用于执行上述步骤210，步骤230，步骤340，步骤370和步骤390。处理单元520用于执行上述步骤220，步骤310，步骤360。
可选的，在另一些实现方式中，该数据处理的装置500设置于处理器(例如，上述方法300中的处理器1)中，收发单元510用于执行上述步骤340，步骤370和步骤390。处理单元520用于执行上述步骤320，步骤330，步骤350，步骤380。
图6是本申请实施例的数据处理的装置2000的硬件结构示意图。图6所示的数据处理的装置2000可以执行上述实施例的数据处理的方法。
如图6所示，该数据处理的装置2000包括处理器2001、存储器2002、接口2003和总线2004。其中接口2003可以通过无线或有线的方式实现，具体来讲可以是网卡。上述处理器2001、存储器2002和接口2003通过总线2004连接。所述接口2003具体可以包括发送器和接收器，用于数据处理的装置实现上述收发。所述处理器2001用于执行上述实施例中由数据处理的装置进行的处理。存储器2002包括操作系统20021和应用程序20022，用于存储程序、代码或指令，当处理器或硬件设备执行这些程序、代码或指令时可以完成方法实施例中IO设备或处理器1的处理过程。可选的，所述存储器2002可以包括只读存储器(read-only memory，ROM)和随机存取存储器(random access memory，RAM)。其中，所述ROM包括基本输入/输出系统(basic input/output system，BIOS)或嵌入式系统；所述RAM包括应用程序和操作系统。当需要运行数据处理的装置2000时，通过固化在ROM中的BIOS或者嵌入式系统中的bootloader引导系统进行启动，引导数据处理的装置2000进入正常运行状态。在数据处理的装置2000进入正常运行状态后，运行在RAM中的应用程序和操作系统，从而，完成方法实施例中涉及数据处理的装置2000的处理过程。图6仅仅 示出了数据处理的装置2000的简化设计。在实际应用中，数据处理的装置可以包含任意数量的接口，处理器或者存储器。
本申请实施例还提供了一种计算机可读介质，该计算机可读介质存储有程序代码，当该计算机程序代码在计算机上运行时，使得计算机执行上述IO设备或处理器1执行的方法。这些计算机可读存储包括但不限于如下的一个或者多个：只读存储器(read-only memory，ROM)、可编程ROM(programmable ROM，PROM)、可擦除的PROM(erasable PROM，EPROM)、Flash存储器、电EPROM(electrically EPROM，EEPROM)以及硬盘驱动器(hard drive)。
本申请实施例还提供了一种芯片系统，该芯片系统包括：至少一个处理器、至少一个存储器和接口电路，所述接口电路负责所述芯片系统与外界的信息交互，所述至少一个存储器、所述接口电路和所述至少一个处理器通过线路互联，所述至少一个存储器中存储有指令；所述指令被所述至少一个处理器执行，以进行上述各个方面的所述的方法中涉及IO设备或处理器1的操作。在具体实现过程中，该芯片系统可以以中央处理器(central processing unit，CPU)、微控制器(micro controller unit，MCU)、微处理器(micro processing unit，MPU)、数字信号处理器(digital signal processing，DSP)、片上系统(system on chip，SoC)、专用集成电路(application-specific integrated circuit，ASIC)、现场可编程门阵列(field programmable gate array，FPGA)或可编辑逻辑器件(programmable logic device，PLD)的形式实现。
本申请实施例还提供了一种计算机程序产品，应用于IO设备或处理器1中，所述计算机程序产品包括一系列指令，当所述指令被运行时，以进行上述各个方面的所述的方法中所述IO设备或处理器1的操作。
本申请实施例还提供了一种系统，包括上述数据处理的装置500。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各 个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种数据处理的方法，其特征在于，所述方法包括:
    输入输出IO设备接收第一请求；
    所述IO设备存储所述第一请求；
    所述IO设备根据接收所述第一请求的顺序发送所述第一请求。
  2. 根据权利要求1所述的方法，其特征在于，所述IO设备存储所述第一请求，包括：
    所述IO设备将所述第一请求存储至队列。
  3. 根据权利要求2所述的方法，其特征在于，所述IO设备将所述第一请求存储至队列，包括：
    所述IO设备确定所述队列中可用单元；
    所述IO设备将所述第一请求存储至所述可用单元。
  4. 根据权利要求1所述的方法，其特征在于，所述IO设备根据接收所述第一请求的顺序发送所述处理请求，包括：
    所述IO设备确定所述队列中所述第一请求的存储顺序；
    所述IO设备在所述第一请求的存储顺序前的请求均完成发送操作时，获取所述第一请求，并向远端设备发送所述第一请求，所述远端设备为与所述IO设备所在设备通过网络进行通信的设备。
  5. 根据权利要求1至4中任一项所述的方法，其特征在于，所述IO设备为网卡或加速器。
  6. 一种数据处理的装置，其特征在于，所述装置包括:
    收发单元，用于接收第一请求；
    处理单元，用于存储所述第一请求；
    所述收发单元，还用于根据接收所述第一请求的顺序发送所述第一请求。
  7. 根据权利要求6所述的装置，其特征在于，
    所述处理单元，还用于将所述第一请求存储至队列。
  8. 根据权利要求7所述的装置，其特征在于，
    所述处理单元还用于：
    确定所述队列中可用单元；
    将所述第一请求存储至所述可用单元。
  9. 根据权利要求6所述的装置，其特征在于，
    所述处理单元还用于：确定所述队列中所述第一请求的存储顺序；
    所述处理单元还用于：在所述第一请求的存储顺序前的请求均完成发送操作时，获取所述第一请求；
    所述收发单元还用于：向远端设备发送所述第一请求，所述远端设备为与所述IO设备所在设备通过网络进行通信的设备。
  10. 根据权利要求6至9中任一项所述的装置，其特征在于，所述IO设备为网卡或加速器。
  11. 一种数据处理的系统，其特征在于，包括如权利要求6至10中任一项所述的数据处理的装置。
  12. 一种计算机可读存储介质，其特征在于，包括计算机程序，当所述计算机程序在计算机上运行时，使得所述计算机执行权利要求1至5中任一项所述的方法。
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US20190155662A1 (en) * 2017-11-22 2019-05-23 Fujitsu Limited Information processing system and data processing method
CN111488220A (zh) * 2020-04-09 2020-08-04 北京字节跳动网络技术有限公司 一种启动请求处理方法、装置和电子设备
CN112882813A (zh) * 2021-03-18 2021-06-01 苏州科达科技股份有限公司 任务调度方法、装置、系统及电子设备
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