WO2023035646A1 - Procédé et appareil d'extension de mémoire et dispositif associé - Google Patents

Procédé et appareil d'extension de mémoire et dispositif associé Download PDF

Info

Publication number
WO2023035646A1
WO2023035646A1 PCT/CN2022/091824 CN2022091824W WO2023035646A1 WO 2023035646 A1 WO2023035646 A1 WO 2023035646A1 CN 2022091824 W CN2022091824 W CN 2022091824W WO 2023035646 A1 WO2023035646 A1 WO 2023035646A1
Authority
WO
WIPO (PCT)
Prior art keywords
storage medium
processor
address
storage
virtual memory
Prior art date
Application number
PCT/CN2022/091824
Other languages
English (en)
Chinese (zh)
Inventor
姚建业
张瑛
赵金蔚
程龙
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2023035646A1 publication Critical patent/WO2023035646A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication

Definitions

  • the present application relates to the field of storage technologies, and in particular to a method, device and related equipment for expanding memory.
  • the capacity of the memory in the computing device affects the performance of the application.
  • the larger the capacity of the memory in the computing device the more data can be stored in the memory, so the application on the computing device has a higher probability of accessing data from the memory, so as to improve the efficiency of the application to obtain data .
  • the computing device will swap out some data that is not currently being accessed in the physical memory to other locations (such as swapping out to the solid state drive, etc.) , to free up free memory space, and then swap the data that the processor needs to access from the solid-state disk into the free physical memory space, and obtain the data by accessing the physical memory again.
  • the virtual memory address mapped based on the solid-state disk is usually relatively large, which makes the computing device frequently perform page fault interrupts and data swapping in and out, thereby affecting the data access performance of the processor. For example, the computing device accesses the data with high delay and resource consumption.
  • the embodiment of the present application provides a method for expanding the memory, so as to prevent the data access performance of the processor from degrading after the memory of the computing device is expanded.
  • the embodiments of the present application also provide a device for expanding memory, a computing device, a computer-readable medium, and a computer program product.
  • the embodiment of the present application provides a method for expanding memory, which is used to expand the memory of a computing device, where the computing device includes a processor and a first storage device, and the first storage device includes a first A storage medium and a second storage medium, the access delay of the first storage medium is less than the access delay of the second storage medium, usually, the data read and write performance of the first storage medium can be better than that of the second storage medium Read and write performance.
  • the processor When expanding the memory, acquires the physical address of the first storage medium and the physical address of the second storage medium, and maps the physical address of the first storage medium into a first virtual memory address, and maps the physical address of the second storage medium to The physical address is mapped to a second virtual memory address, wherein the first virtual memory address and the second virtual memory address can be directly accessed by the processor, and the processor stores the hot data in the storage space indicated by the first virtual memory address , or store the cold data in the storage space indicated by the second virtual memory address.
  • the processor can directly access the first storage medium and/or the second storage medium without performing page fault interrupts and data
  • the process of swapping in and swapping out can effectively avoid the reduction of the data access performance of the processor.
  • the physical addresses of multiple storage media in the storage device can be mapped to the memory of the computing device, which can maximize the utilization
  • the memory resources of the storage device are expanded, so that the memory expansion effect of the computing device can be improved.
  • the extended first virtual memory address and the second virtual memory address in the computing device can be used to respectively store data with different temperatures, so that when the processor accesses data, it can have a relatively high probability of accessing data from a device with a small access delay. (Physical memory or) the data is accessed from the first storage medium, so that the data access performance of the computing device reaches a higher level.
  • the first storage device further includes a third storage medium
  • the processor may also perform memory expansion on the computing device based on the third storage medium.
  • the processor may obtain the physical address of the third storage medium, and map the physical address of the third storage medium into a third virtual memory address, and the processor can directly access the third virtual memory. In this way, more storage media in the first storage device can be used as the extended memory of the computing device, thereby further improving the memory expansion effect of the computing device.
  • the access delay of the second storage medium is shorter than the access delay of the third storage medium.
  • the second storage medium is SCM
  • the third storage medium is flash memory, and so on.
  • the computing device further includes a second storage device, and the computing device can not only use the storage resources on the first storage device to expand memory, but also use the storage resources on the second storage device to Expand memory.
  • the processor may acquire the physical address of at least one storage medium in the second storage device, and map the physical address of the at least one storage medium in the second storage device into a virtual memory address directly accessible by the processor. In this way, the memory of the computing device can be expanded by utilizing storage resources on multiple storage devices, thereby further improving the memory expansion effect of the computing device.
  • the computing device further includes a physical memory, and the heat of the data stored in the physical memory is higher than the heat of the data stored in the storage space indicated by the first virtual memory address, so that subsequent processors When accessing data, there is a relatively high probability that the data can be accessed from the physical memory with a shorter access delay, so that the data access performance of the computing device reaches a higher level.
  • the processor obtains an access request for the target data, and when the physical memory does not include the target data, the processor searches for the target data from the first storage medium according to the first virtual memory address . In this way, when the processor reads data, it can preferentially search for the data from the hot data stored in the physical memory. storage space) to find whether the data to be read is included, so that the data access performance of the computing device can reach a higher level.
  • the first virtual memory address and the second virtual memory address have different attribute identifiers, and the attribute identifiers are used to indicate storage characteristics of the storage medium.
  • the attribute identifiers are used to indicate storage characteristics of the storage medium.
  • the first storage medium is a volatile storage medium
  • the second storage medium is a nonvolatile storage medium
  • its corresponding attribute identifier can be used to indicate that the storage space corresponding to the first virtual memory address can be used for caching data
  • the storage space corresponding to the second virtual memory address can be used for persistent storage of data and the like.
  • the computing device can store data through different virtual memory addresses according to actual application requirements.
  • the first storage medium may be a dynamic random access memory (DRAM), and the second storage medium may be a flash memory (flash).
  • DRAM dynamic random access memory
  • flash flash memory
  • the embodiment of the present application further provides an apparatus for expanding memory, which is used to execute the method described in any one of the implementation manners in the first aspect.
  • an embodiment of the present application further provides a computing device, the computing device includes a memory and a processor, and the processor is configured to execute instructions stored in the memory to execute any one of the implementations in the first aspect method described.
  • a fourth aspect of the present application provides a computer-readable medium, where instructions are stored in the computer-readable medium, and when the computer-readable medium is run on a computer, the computer is made to execute the methods described in the above aspects.
  • the fifth aspect of the present application provides a computer program product, which, when run on a computer, causes the computer to execute the method described in the above aspects.
  • FIG. 1 is a schematic structural diagram of a computing device 110 provided in an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a storage device 105 provided by an embodiment of the present application.
  • FIG. 3 is a schematic flowchart of a method for expanding memory provided in an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another storage device 105 provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another computing device 110 provided by an embodiment of the present application.
  • FIG. 6 is a schematic flowchart of another method for expanding memory provided in the embodiment of the present application.
  • FIG. 7 is a schematic diagram of obtaining two segments of virtual memory addresses according to multiple physical address mappings
  • FIG. 8 is a schematic structural diagram of a device for expanding memory provided by an embodiment of the present application.
  • the embodiment of the present application proposes a method for expanding the memory, so as to prevent the data access performance of the processor from degrading after the memory of the computing device is expanded.
  • FIG. 1 is a schematic structural diagram of a computing device provided by an embodiment of the present application, where the computing device may adopt a fully converged architecture.
  • the fully converged architecture shown in FIG. 1 may include one or more computing devices 110 (in FIG. 1, three computing devices 110 are taken as an example, and any number of computing devices 110 may be included in actual applications), and each computing device 110 can be communicate with each other.
  • the computing device 110 is a device having both computing capability and storage capability, such as a server, a desktop computer, and the like. In terms of software, each computing device 110 has an operating system on it.
  • a virtual machine 107 can be created on the computing device 110, the computing resources required by the virtual machine 107 come from the local processor 112 and memory 113 of the computing device 110, and the storage resources required by the virtual machine 107 can come from the connection with the computing device 110 storage device 105.
  • various application programs can run in the virtual machine 107 , and the user can trigger a read/write data request through the application programs in the virtual machine 107 .
  • the computing device 110 includes at least a processor 112 , a memory 113 and a storage device 105 . Further, the computing device 110 may also include a network card 114 .
  • the processor 112, the memory 113, and the network card 114 are connected through an internal bus in the computing device 110, and the storage device 105 and the computing device 100 are connected through an external bus (such as a serial bus, etc.).
  • the processor 112 and the memory 113 are used to provide computing resources.
  • the processor 112 is a central processing unit (central processing unit, CPU), configured to process data access requests from outside the computing device 110, or requests generated inside the computing device 110.
  • CPU central processing unit
  • the processor 112 when the processor 112 receives the write data request sent by the user, it will temporarily store the data in the data write request in the memory 113 . When the total amount of data in the memory 113 reaches a certain threshold, the processor 112 sends the data stored in the memory 113 to the storage device 105 for storage.
  • the processor 112 is also used for computing or processing data, such as metadata management, deduplication, data compression, data verification, virtualized storage space, and address translation. Only one processor 112 is shown in FIG. 1 . In practical applications, there are usually multiple processors 112 , and one processor 112 has one or more processor cores. This embodiment does not limit the number of processors and the number of processor cores.
  • processor 112 may also be a specific integrated circuit (application specific integrated circuit, ASIC), or be configured as one or more integrated circuits, for example: one or more microprocessors (digital signal processor, DSP), or , one or more field programmable gate arrays (field programmable gate array, FPGA).
  • ASIC application specific integrated circuit
  • DSP digital signal processor
  • FPGA field programmable gate array
  • the memory 113 refers to an internal memory directly exchanging data with the processor. It can read and write data at any time, and the speed is very fast. It is used as a temporary data storage for an operating system or other running programs.
  • Memory includes at least two kinds of memory, for example, memory can be either random access memory or read-only memory (Read Only Memory, ROM).
  • the random access memory is dynamic random access memory (Dynamic Random Access Memory, DRAM), or storage class memory (Storage Class Memory, SCM).
  • DRAM Dynamic Random Access Memory
  • SCM Storage Class Memory
  • DRAM is a semiconductor memory, which, like most Random Access Memory (RAM), is a volatile memory device.
  • SCM is a composite storage technology that combines the characteristics of traditional storage devices and memory.
  • Storage-class memory can provide faster read and write speeds than hard disks, but the access speed is slower than DRAM, and the cost is also cheaper than DRAM.
  • the DRAM and the SCM are only exemplary illustrations in this embodiment, and the memory may also include other random access memories, such as Static Random Access Memory (Static Random Access Memory, SRAM) and the like.
  • Static Random Access Memory Static Random Access Memory
  • the read-only memory for example, it may be a programmable read-only memory (Programmable Read Only Memory, PROM), an erasable programmable read-only memory (Erasable Programmable Read Only Memory, EPROM), and the like.
  • the memory 113 can also be a dual in-line memory module or a dual-line memory module (Dual In-line Memory Module, DIMM for short), that is, a module composed of dynamic random access memory (DRAM), or a solid-state hard disk (Solid State Disk, SSD).
  • DIMM Dual In-line Memory Module
  • multiple memories 113 and different types of memories 113 may be configured in the computing node 110 .
  • This embodiment does not limit the quantity and type of the memory 113 .
  • the memory 113 can be configured to have a power saving function.
  • the power saving function means that the data stored in the memory 113 will not be lost when the system is powered off and then powered on again. Memory with a power saving function is called non-volatile memory.
  • the storage device 105 is used to provide storage resources, such as storing data.
  • the storage device 105 may be used to expand the memory of the computing device 100 . It can include a variety of storage media, such as magnetic disks, solid-state hard disks, shingled magnetic recording hard disks, magnetic random access memory, and the like.
  • the network card 114 is used to support the computing device 110 to communicate with other computing devices 110 .
  • FIG. 1 is only used as an exemplary illustration, and is not used for limitation.
  • the above-mentioned virtual machine 107 and the like may not be created on each computing device 110 .
  • the storage device 105 includes at least two storage media. Specifically, as shown in FIG. 2 , the storage device 105 includes a main control 1051 , a storage medium 1052 , a buffer 1053 and a storage medium 1054 . In FIG. 2 , two kinds of storage media are taken as an example. In actual application, the storage device 105 may also include more types of storage media.
  • the main control 1051 includes drive and control logic, which is used to control and implement data access to the storage medium 1052 and the storage medium 1054, including writing new data to the storage medium 1052 and the storage medium 1054 or reading stored data, etc. , and, the main control 1051 may also control and implement communication between the storage device 105 and the processor 112 .
  • the data read and write performance of the storage medium 1052 is better than the data read and write performance of the storage medium 1054 , specifically, the access delay of the storage medium 1052 is less than the access delay of the storage medium 1054 .
  • the storage medium 1052 may specifically be a DRAM, and the storage medium 1054 may specifically be a flash memory (flash) or an SCM.
  • the storage space of the storage medium 1052 may be smaller than the storage space of the storage medium 1054 .
  • the buffer 1053 can be used as a read-write buffer for the storage medium 1054, that is, for the data to be accessed or written by the computing device 110, the data can be put into the buffer 1053 first, and then the data in the buffer 1053 can be executed Corresponding data read and write operations.
  • the buffer 1053 can provide the computing device 110 with the capability of byte access (that is, data can be read and written in units of bytes), so that when data is stored in the storage medium 1054 in the form of data blocks, through the buffer 1053
  • the access characteristics of the storage medium 1054 may be shielded from the computing device 110, such as shielding the block access characteristics of the storage medium 1054, and the like.
  • both the storage space in the storage medium 1052 and the storage medium 1054 in the storage device 105 can be expanded into the virtual memory of the computing device 110 , so as to realize memory expansion of the computing device 110 .
  • the computing device 110 acquires the physical address of the storage medium 1052 and the physical address of the storage medium 1054 respectively. Then, the computing device 110 maps the physical address of the storage medium 1052 into the first virtual memory address of the computing device 110 , and maps the physical address of the storage medium 1054 into the second virtual memory address of the computing device 110 . In this way, the memory capacity of the computing device 110 can be expanded, and the increased memory capacity is the sum of the capacities corresponding to the first virtual memory address and the second virtual memory address.
  • the processor 112 in the computing device 110 accesses data in the memory, it may first determine whether the data it needs to read exists in the memory 113 . If it exists, the processor 112 directly reads the data from the memory 113; and if it does not exist, the processor 112 can pass the connection between the computing device 110 and the storage device 105 (such as a serial bus connection, etc.), according to the first The virtual memory address looks up the data from the storage medium 1052 . Further, if the storage medium 1052 does not include the data required by the processor 112, the processor 112 may continue searching from the storage medium 1054 according to the second virtual memory address.
  • the processor 112 can directly access the storage medium 1052 on the storage device based on the connection between it and the storage device 105 And/or the storage medium 1054, there is no need to perform processes such as page fault interruption and data swapping in and out, so that the data access performance of the processor 112 can be effectively avoided; and a connection between the processor 112 and the storage device 105 can be established through a bus , so that when expanding the memory of the computing device 110 based on the storage device 105, it is not necessary to occupy limited memory slots in the computing device 110, so that the memory of the computing device 110 can be expanded without increasing the number of memory slots.
  • the physical addresses of multiple storage media in the storage device 105 can be mapped to the memory of the computing device 110, which can maximize the The storage resources of the storage device 105 are utilized to expand the memory, so that the memory expansion effect of the computing device 110 can be improved.
  • each computing device 110 may include multiple storage devices 105 at the same time, for example, the multiple storage devices 105 may form an array and be configured on the computing device 110, etc., so that each computing device 110 may simultaneously utilize multiple storage devices 105
  • the storage resources of the computing device 110 are expanded, that is, the storage resources on multiple storage devices 105 are all used as virtual memory resources of the computing device 110, so that the memory capacity of the computing device 110 can be further increased, and the capacity of expanding the memory can be improved. Effect.
  • FIG. 3 shows a schematic flowchart of a method for expanding memory in an embodiment of the present application.
  • the method may be applied to the computing device shown in FIG. 1 , or may be applied to other applicable computing devices.
  • the storage resource of one storage device 105 is used as an example to expand the memory of the computing device 110 for illustration.
  • the method for expanding memory in this embodiment may specifically include:
  • the storage device 105 reports the physical address of the storage medium 1052 and the physical address of the storage medium 1054 to the processor 112 .
  • the main control 1051 in the storage device 105 can actively connect the storage medium 1052 and the storage
  • the respective physical addresses of the media 1054 on the storage device 105 are sent to the computing device 110 .
  • the physical address may be pre-configured in the main control 1051 by a technician, or may be automatically collected by the main control 1051 .
  • the processor 112 may send a request to the storage device 110 to obtain the physical address on the storage device 105, so that the storage device 105 responds to the request by storing The physical addresses of the medium 1052 and the storage medium 1054 are sent to the computing device 110 .
  • the specific implementation manner of obtaining the physical address by the computing device 110 is not limited.
  • the storage medium 1052 and the storage medium 1054 may be two different types of storage media, specifically, the access delay of the storage medium 1052 may be shorter than the access delay of the storage medium 1054 .
  • the storage medium 1052 is a DRAM
  • the storage medium 1054 is a flash memory or an SCM.
  • the processor 112 and the storage device 105 can be connected through a serial bus, and the transmission protocol adopted by the serial bus can be, for example, an open coherent accelerator processor interface (open coherent accelerator processor interface) , openCAPI) protocol, computer high-speed interconnection (compute express link, CXL) protocol and Z generation (generation Z, GenZ) protocol, or any other applicable transmission protocol, etc., this embodiment does not To limit.
  • the processor 112 in the computing device 110 can directly access the storage medium in the storage device 105 based on the connection.
  • the processor 112 maps the physical address of the storage medium 1052 to a first virtual memory address of the computing device 110, and maps the physical address of the storage medium 1054 to a second virtual memory address of the computing device 110.
  • the computing device 110 may include physical memory (such as the aforementioned memory 113 ), and the address space of the physical memory may be managed by a memory management unit.
  • the capacity of the physical memory is limited, and it may be difficult to support the actual use requirements of the computing device 110.
  • the capacity of the physical memory is difficult to support the computing device 110 to store more business data, etc.
  • the efficiency of business data has an impact. Therefore, in this embodiment, the computing device 110 implements expansion of the memory of the computing device 110 based on the storage resources on the storage device 105 .
  • the basic input output system (basic input output system, BIOS) in the computing device 110 can receive the two address spaces sent by the master 1051 (ie, the storage space indicated by the physical address of the storage device 1052 and the storage device 1054), and send the two address spaces to the memory management unit in the operating system in the computing device 110. Then, the memory management unit maps the physical address of the storage device 1052 to obtain the first virtual memory address of the computing device 110, and generates a first mapping table corresponding to the first virtual memory address, and the first mapping table records the first virtual memory address. Correspondence between the memory address and the physical address of the storage device 1052 .
  • the memory management unit also maps the physical address of the storage device 1054 to obtain the second virtual memory address of the computing device 110, and generates a second mapping table corresponding to the second virtual memory address, and the second mapping table records the second Correspondence between the virtual memory address and the physical address of the storage device 1054 .
  • the memory management unit can notify the processor 112 of the generated first mapping table and the second mapping table, so that the subsequent processor 112 can perform the storage medium in the storage device 105 according to the first mapping table and/or the second mapping table. for data access.
  • the first virtual memory address and the second virtual memory address mentioned in this embodiment both refer to an address space including multiple addresses.
  • the first virtual memory address and the second virtual memory address may be independent of each other in the computing device 110 , and the memory management unit may create two independent memory pools in the computing device 110 based on the two virtual memory addresses.
  • the memory management unit may concatenate the first virtual memory address and the second virtual memory address to obtain a virtual memory address with a larger storage space.
  • the memory management unit may create a memory pool in the computing device 110, and the memory capacity of the created memory pool is the sum of the memory capacity corresponding to the first virtual memory address and the second virtual memory.
  • the memory management unit can create two independent memory pools, or can also create one memory pool. Of course, this is only used as an exemplary description, and is not used to limit the implementation manner of creating a memory pool by the memory management unit.
  • the memory capacity of the computing device 110 can be increased, and the increased memory capacity is the sum of capacities corresponding to the first virtual memory address and the second virtual memory address.
  • the computing device 110 can not only use the physical memory to store business data, but also use the storage medium 1052 corresponding to the first virtual memory address and the storage medium 1054 corresponding to the second virtual memory address to store other business data.
  • the data volume of the service data stored in the memory, and the physical address of multiple storage media in the storage device 105 is used to realize the memory expansion of the computing device 110, which can achieve a higher memory expansion effect.
  • the computing device 110 may also use the first virtual memory address for data caching, and use the second virtual memory address for data caching. Storage, so that when the memory of the computing device 110 is expanded, the cache space and the storage space can be increased simultaneously, such as proportionally.
  • the speed at which the computing device 110 accesses the storage device 105 is similar to that of the computing device 110 The speed of accessing the physical memory, so that when the memory of the computing device 110 is expanded, the data access performance of the computing device 110 can be avoided from being degraded.
  • the processor 112 stores the hot data in the storage space indicated by the first virtual memory address, or stores the cold data in the storage space indicated by the second virtual memory address.
  • the extended first virtual memory address and the second virtual memory address can be used to store data of a specific temperature.
  • the processor 112 may use the storage space indicated by the first virtual memory address to store hot data. of storage space to store cold data with low heat.
  • the processor 112 may simultaneously use the storage space indicated by the first virtual memory address and the storage space indicated by the second virtual memory address to store cold data and the like, which is not limited in this embodiment.
  • the specific implementation manner for determining the popularity of the data may be determined according to the access frequency of the data, the popularity identifier, etc., which is not limited in this embodiment.
  • the hot data and cold data in this embodiment are relative concepts. In other words, the heat of the data stored in the first virtual memory address is greater than the heat of the data stored in the second virtual memory address. Data is divided into hot data and cold data.
  • the processor 112 can access the required data (hereinafter referred to as target data) from the physical memory or the storage medium corresponding to the virtual memory address. Specifically, when the processor 112 needs to acquire data, the method may further include:
  • S304 The processor 112 acquires an access request for the target data.
  • one or more application programs may run on the computing device 110, and the application programs may need to access business data stored in the computing device 110 (or storage device 105) during operation, such as the application program is running In the process, it may be necessary to query business data such as commodity information.
  • the application program can generate an access request for the target data and send it to the processor 112 in the computing device 110 .
  • the processor 112 may automatically generate an access request for business data during the process of providing business services for the application program, and execute a subsequent data access process based on the access request.
  • the specific implementation process of the processor 112 obtaining the access request is not limited.
  • S305 In response to the access request, the processor 112 determines whether the target data to be accessed is stored in the physical memory.
  • the computing device 110 may first query whether the target data is stored in the cache. If there is, the computing device 110 can directly read the target data from the cache; if not, the computing device 110 can continue to search for the target data from memory (including physical memory and virtual memory).
  • the processor 112 when the processor 112 stores data in the memory in advance, it may determine the storage location of the data according to the degree of heat of the data. As an example, the processor 112 may preferentially store the data with the highest heat in the physical memory, and store the data with relatively low heat in the storage medium (including the storage medium 1052 and/or the storage medium 1052) corresponding to the virtual memory address. 1054). Since the speed at which the processor 112 reads data from the physical memory is relatively high, when it is necessary to access data in the memory, the computing device 110 preferentially checks whether the target data is stored in the physical memory with high data heat. If the target data is stored in the physical memory, the processor 112 can directly read the target data from the physical memory, so that the computing device 110 can access data more efficiently. If the target data is not stored in the physical memory, the processor 112 may continue to execute step S305 to further search for the target data.
  • the processor 112 can first search the storage medium 1052 according to the first virtual memory address to see if the target data that it needs to access is stored, and if it exists, the processor 112 directly reads the stored data. Target data in media 1052 . If not, the computing device 110 may continue to execute step S306 to further search for the target data.
  • both the storage medium 1052 and the storage medium 1054 can store hot data or cold data.
  • the storage medium 1054 has relatively large storage space.
  • the processor 112 may continue to search for data from the storage medium 1054 with a larger storage space. Specifically, the processor 112 may access the storage medium 1054 according to the second virtual memory address corresponding to the storage medium 1054 to obtain data stored in the storage medium 1054 .
  • the processor 112 may feed back data search failure and the like.
  • the storage device 105 only includes two storage media, and in other possible embodiments, the storage device 105 may also include more than three (including three) storage media. In this case, the processor 112 may use storage resources of more than three storage media in the storage device 105 to implement memory expansion.
  • the storage device 105 further includes a storage medium 1055 .
  • the storage device 105 may include DRAM, SCM, and flash memory, wherein the storage medium 1052 is specifically a DRAM, the storage medium 1054 is specifically an SCM, and the storage medium 1055 is specifically a flash memory.
  • the storage device 105 can report the physical address of the storage medium 1052, the physical address of the storage medium 1054, and the physical address of the storage medium 105 to the processor 112, so that the processor 112 can not only map the physical address of the storage medium 1052 to obtain The first virtual memory address, the second virtual memory address obtained based on the physical address mapping of the storage medium 1054, and the third virtual memory address of the computing device 110 can also be obtained based on the physical address mapping of the storage medium 1055, and the processor 112 can directly access this The storage space indicated by the third virtual memory address.
  • the memory of the computing device 110 can be further expanded, and the further expanded memory capacity is the memory capacity corresponding to the third virtual memory address.
  • the computing device 110 may The memory expansion is performed based on the storage resources in the multiple storage devices 105 , so as to improve the memory expansion effect for the computing device 110 .
  • FIG. 5 shows a schematic structural diagram of another computing device, in the computing device 110 shown in FIG. 5, the processor 112 is connected to the storage device 105 and the storage device 106, respectively, and , the processor 112 can directly access the storage medium in the storage device 105 and the storage device 106 based on the connection.
  • FIG. 6 shows a schematic flowchart of a method for expanding the memory of the computing device 110 by using the storage device 105 and the storage device 106 .
  • the method for expanding memory shown in Figure 6 includes:
  • the storage device 105 reports the physical address 1 of the storage medium 1052 and the physical address 2 of the storage medium 1054 to the processor 112; and the storage device 106 reports the physical address 3 of the storage medium 1062 and the physical address of the storage medium 1064 to the processor 112 4.
  • the specific implementation process of the storage device 105 and the storage device 106 reporting the physical address to the processor 112 respectively may refer to the related descriptions in the foregoing embodiments, and details are not repeated here.
  • the processor 112 maps the physical addresses reported by the storage device 105 and the storage device 106 into corresponding virtual memory addresses.
  • the processor 112 may map the physical addresses respectively reported by multiple storage devices to virtual memory addresses of the computing device 110 , so as to implement memory expansion for the computing device 110 .
  • the processor 112 may perform virtual memory address mapping for physical addresses on different storage devices, and the virtual memory addresses mapped to different physical addresses are independent of each other in the processor 112 .
  • the processor 112 may manage the mapped multiple virtual memory addresses respectively by creating multiple memory pools.
  • the processor 112 may generate multiple mapping tables for recording virtual memory addresses respectively corresponding to multiple physical addresses.
  • the processor 112 may map physical addresses on multiple storage devices into continuous virtual memory addresses. For example, assume that the physical address 1 of the storage medium 1052 in the storage device 105 is 64M (megabytes), the physical address 2 of the storage medium 1054 is 1024M, the physical address 3 of the storage medium 1062 in the storage device 106 is 64M, and the physical address of the storage medium 1064 4 is 1024M, then the processor 112 can map to obtain a continuous virtual memory address of 2176M (ie 64M+1024M+64M+1024M) based on these 4 physical addresses.
  • the processor 112 can map to obtain a continuous virtual memory address of 2176M (ie 64M+1024M+64M+1024M) based on these 4 physical addresses.
  • the processor 112 may map the 64M virtual memory address 1 based on the 64M physical address 1 corresponding to the storage medium 1052, and obtain the first address a of the virtual memory address 1 and the memory space length (ie 64M). Then, in the process of mapping the physical address 2 of the storage medium 1054 into the virtual memory address 2, the processor 112 can calculate the last address b of the virtual memory address 1 according to the first address a of the virtual memory address 1 and the length of the memory space, And add 1 to the end address b to get a new address (b+1), the new address is the first address of the virtual memory address 2, the length of the virtual memory address 2 is the length of the physical address 2, so according to the first address (b+1) and the length of the virtual memory address 2 can calculate the last address c of the virtual memory address 2.
  • the processor 112 adds 1 to the last address c to obtain the first address (c+1) of the virtual memory address 3 corresponding to the physical address 3, and determines the virtual memory address 3 based on the first address (c+1).
  • the processor 112 can sequentially determine the first address (d+1) and the last address e corresponding to the virtual memory address 4 corresponding to the physical address 4, so that based on the storage resources on the storage device 105 and the storage device 106, it is possible to map Get continuous virtual memory addresses [a, e] whose first address is a and last address is e.
  • the virtual memory address [a, b] in the continuous virtual memory address [a, e] is the virtual memory address 1 corresponding to the physical address 1
  • the virtual memory address [b+ 1, c] is the virtual memory address corresponding to the physical address 2.
  • the virtual memory address [c+1, d] in the virtual memory address [a, e] is the virtual memory address corresponding to the physical address 3.
  • the virtual memory address [d+1, e] in a, e] is the virtual memory address 4 corresponding to the physical address 4.
  • the processor 112 may create a memory pool for managing the mapped continuous virtual memory addresses, and generate a corresponding mapping table for the continuous virtual memory addresses to record virtual memory addresses corresponding to multiple physical addresses. memory address.
  • the storage medium 1052 and the storage medium 1054 in the storage device 105 may belong to different types of storage media, for example, the storage medium 1052 is a volatile storage medium (it is difficult to save data after the power is turned off), while the storage medium 1054 is a volatile storage medium. Non-volatile storage media (data can be saved after the power is turned off). Therefore, in a further possible implementation, the processor 112 can create a corresponding number of memory pools based on the type of the storage medium, and each memory pool is used to manage the continuous virtual memory corresponding to multiple storage media of the same type address.
  • the storage medium 1052 and the storage medium 1062 in the above example are both volatile storage media (such as both storage media are DRAM, etc.), and the storage medium 1054 and the storage medium 1064 are both non-volatile storage media ( If both storage media are flash memory), then the processor 112 can map two segments of virtual memory addresses based on the respective types of the multiple storage media during the process of mapping the virtual memory addresses, which are virtual memory addresses M and The virtual memory address N is shown in Figure 7. Wherein, the virtual memory address M is obtained through address mapping based on a volatile storage medium, and the virtual memory address N is obtained through address mapping based on a nonvolatile storage medium.
  • the processor 112 can map the first address m1 to the virtual memory address M' based on the physical address 1, the current length of the virtual memory address M' is the length of the physical address 1, that is, 64M, and the last address is m2. Then, since the storage medium 1054 and the storage medium 1052 belong to different storage mediums, the processor 112 can map based on the physical address 2 to obtain a virtual memory address N' whose first address is n1, and the current length of the virtual memory address N' is physical The length of address 2 is 1024M, and the last address is n2.
  • the processor 112 can add 1 to the current end address m2 of the virtual memory address M′, and use the obtained new address (m2+1) as the physical Address 3 corresponds to the first address of virtual memory address 3, and completes the address mapping for physical address 3 to obtain virtual memory address M, and the first address of the virtual memory address M is m1, and the length is 128M (that is, 64M+64M ). In this way, the processor 112 can map two independent physical addresses 1 and 3 into a continuous virtual memory address M.
  • the processor can add 1 to the current end address n2 of virtual memory address N', and use the obtained new address (n2+1) as the virtual memory corresponding to physical address 4
  • the first address of the address 4 completes the address mapping for the physical address 4 to obtain the virtual memory address N, and the first address of the virtual memory address N is n1, and the length is 2048M (that is, 1024M+1024M).
  • the processor 112 can map two independent physical addresses 2 and 4 into a continuous virtual memory address N.
  • the processor 112 may also add attribute identifiers to different virtual memory addresses mapped by different types of storage media, so as to identify the storage characteristics of the storage media that realize the virtual memory addresses.
  • the storage characteristics of the storage medium may include, for example, volatility or non-volatility, or may be divided into high-performance reading and writing and low-performance reading and writing according to the data reading and writing performance of the storage medium.
  • the processor 112 may add a label of a volatile storage medium to the mapped virtual memory address M to indicate that the virtual memory address M has a volatile storage characteristic; At the same time, the processor 112 adds a label of a non-volatile storage medium to the mapped virtual memory address N to indicate that the virtual memory address N has a non-volatile storage characteristic (data can be stored persistently).
  • the processor 112 when the processor 112 is connected to a larger number of storage devices, the processor 112 can start from the end address of the virtual memory address M and/or virtual memory address N based on the above-mentioned way of extending memory, and continue to configure other storage devices Address mapping is performed on the physical addresses on the network, which is not described in this embodiment.
  • the processor 112 can refer to the above-mentioned similar process to further increase memory for the processor 112 based on the storage resources on the newly accessed storage device, for example, from the above-mentioned virtual memory Address mapping and the like are continued at the last address of address M and/or virtual memory address N. In this way, dynamic expansion of the memory of the processor 112 can be realized.
  • the processor 112 can release the physical connection of the storage medium in the storage device.
  • the mapping relationship between virtual memory and physical addresses on the storage device may be deleted from the generated mapping table, so as to realize dynamic reduction of memory.
  • multiple storage devices used to expand the memory of the processor 112 may form a storage array, such as a redundant array of independent disks (RAID). Then, in an implementation example, when storing data, the plurality of storage devices may store data in a manner such as RAID 0 or RAID 5. Of course, other methods may also be used to store data, which is not limited in this embodiment.
  • RAID redundant array of independent disks
  • S603 The processor 112 acquires an access request for the target data.
  • S604 In response to the access request, the processor 112 determines whether the target data to be accessed is stored in the physical memory.
  • the processor 112 can first search whether there is target data stored in the storage medium 1052 in the storage device 105 according to the virtual memory address, and if so, the processor 112 can directly read the target data stored in the storage medium 1052 . If not, the processor 112 may continue to search whether the target data is stored in the storage medium 1054 in the storage device 105 . If there is, the processor 112 can directly read the target data stored in the storage medium 1054 . If not, processor 112 may determine that the target data is not stored in storage device 105 .
  • the processor 112 can first search whether there is target data stored in the storage medium 1062 in the storage device 106 according to the virtual memory address, and if so, the processor 112 can directly read the target data stored in the storage medium 1062 . If not, the processor 112 may continue to search whether the target data is stored in the storage medium 1062 in the storage device 106 . If there is, the processor 112 can directly read the target data stored in the storage medium 1064 . If there is still no target data in the storage medium 1064 , the processor 112 may report that the data search fails, or continue to search for data from other storage devices used to expand the memory of the computing device 110 .
  • step S603 to step S606 is similar to the implementation of relevant steps in the foregoing embodiments.
  • steps S603 to step S606 are similar to the implementation of relevant steps in the foregoing embodiments.
  • details please refer to the relevant descriptions of the foregoing embodiments, and details are not repeated here.
  • the processor 112 may construct a large-capacity logical unit number (logical unit number, LUN) based on storage resources on multiple storage devices.
  • the processor 112 can prefetch data, such as prefetching the data stored in the virtual memory address N to the virtual memory address M, to speed up the data reading of the processor 112 and reduce the data reading delay. It can improve the performance of LUN.
  • the storage device 106 also has two different storage media as an example for illustration.
  • the storage In addition to expanding the memory at 110, only the storage medium 1062 in the storage device 106 or only the storage medium 1064 may be used to expand the memory of the computing device 110, which is not limited in this embodiment.
  • the embodiment of the present application also provides a device for expanding memory.
  • FIG. 8 it shows a schematic structural diagram of a device for expanding memory in an embodiment of the present application.
  • the device 800 shown in FIG. The computing device further includes a first storage device, and the first storage device includes a first storage medium and a second storage medium, the access latency of the first storage medium is shorter than the access latency of the second storage medium, and the apparatus 800 Can include:
  • An obtaining module 801 configured to obtain the physical address of the first storage medium; obtain the physical address of the second storage medium;
  • a mapping module 802 configured to map the physical address of the first storage medium into a first virtual memory address, the first virtual memory address can be directly accessed by the processor; and map the physical address of the second storage medium mapped to a second virtual memory address, the second virtual memory address can be directly accessed by the processor;
  • the storage module 803 is configured to store hot data in the storage space indicated by the first virtual memory address, or store cold data in the storage space indicated by the second virtual memory address.
  • the first storage device further includes a third storage medium
  • the acquiring module 801 is further configured to acquire the physical address of the third storage medium
  • the mapping module 802 is further configured to map the physical address of the third storage medium into a third virtual memory address, and the third virtual memory address can be directly accessed by the processor.
  • the computing device further includes a second storage device
  • the acquiring module 801 is further configured to acquire the physical address of at least one storage medium in the second storage device;
  • the mapping module 802 is further configured to map the physical address of the at least one storage medium into a virtual memory address directly accessible by the processor.
  • the computing device further includes a physical memory, and the heat of data stored in the physical memory is higher than the heat of data stored in the storage space indicated by the first virtual memory address.
  • the acquiring module 801 is also configured to acquire an access request for the target data
  • the device 800 also includes:
  • a search module 804, configured to search for the target data from the first storage medium according to the first virtual memory address when the target data is not included in the physical memory.
  • the first virtual memory address and the second virtual memory address have different attribute identifiers, and the attribute identifiers are used to indicate storage characteristics of the storage medium.
  • the first storage medium includes a dynamic random access memory DRAM
  • the second storage medium includes a flash memory
  • the device in the embodiment of the present application may correspond to executing the method described in the embodiment of the present application.
  • the above-mentioned and other operations and/or functions of each module in the apparatus 800 for expanding memory are for realizing corresponding processes of each method in FIG. 3 and FIG. 6 .
  • functions of the above modules reference may be made to the descriptions in the method embodiments shown in FIG. 3 and FIG. 6 .
  • the function of each module in the device for expanding memory 800 can be executed by the processor 112 shown in FIG. 3 and FIG. 6 .
  • the embodiment of the present application also provides a computer-readable medium, where instructions are stored in the computer-readable medium, and when the computer-readable medium is run on a computer, the computer is made to execute the methods described in the above aspects.
  • the embodiment of the present application also provides a computer program product, which, when running on a computer, causes the computer to execute the methods described in the above aspects.
  • modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physically separated. Modules can be located in one place, or can be distributed to multiple network modules. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • connection relationship between the modules indicates that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines.
  • the aforementioned computer-readable storage medium includes: U disk, mobile hard disk, magnetic disk, optical disk, RAM, SSD or non-volatile memory (non-volatile memory), etc., which can store program codes. non-transitory machine-readable media.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

La présente demande concerne un procédé d'extension de mémoire. Le procédé est appliqué à un dispositif informatique comprenant un processeur et un premier dispositif de stockage. Pendant une extension de mémoire, le processeur obtient des adresses physiques d'un premier support de stockage et d'un second support de stockage, mappe l'adresse physique du premier support de stockage dans le dispositif informatique dans une première adresse de mémoire virtuelle à laquelle il est possible d'accéder directement et mappe l'adresse physique du second support de stockage dans une seconde adresse de mémoire virtuelle à laquelle il est possible d'accéder directement. Le processeur stocke des données plus sollicitées dans un espace de stockage indiqué par la première adresse de mémoire virtuelle ou stocke des données moins sollicitées dans un espace de stockage indiqué par la seconde adresse de mémoire virtuelle. De cette manière, non seulement la diminution des performances d'accès aux données du processeur peut être efficacement évitée, mais en plus toutes les adresses physiques d'une pluralité de supports de stockage dans le dispositif de stockage peuvent être mappées dans la mémoire du dispositif informatique, de sorte que l'effet d'extension de la mémoire du dispositif informatique peut être amélioré. La présente demande concerne également un appareil correspondant et un dispositif associé.
PCT/CN2022/091824 2021-09-11 2022-05-10 Procédé et appareil d'extension de mémoire et dispositif associé WO2023035646A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN202111064925.9 2021-09-11
CN202111064925 2021-09-11
CN202111266429.1 2021-10-28
CN202111266429.1A CN115794669A (zh) 2021-09-11 2021-10-28 一种扩展内存的方法、装置及相关设备

Publications (1)

Publication Number Publication Date
WO2023035646A1 true WO2023035646A1 (fr) 2023-03-16

Family

ID=85473619

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/091824 WO2023035646A1 (fr) 2021-09-11 2022-05-10 Procédé et appareil d'extension de mémoire et dispositif associé

Country Status (2)

Country Link
CN (1) CN115794669A (fr)
WO (1) WO2023035646A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116466879A (zh) * 2023-03-17 2023-07-21 北京超弦存储器研究院 一种cxl内存模组、内存数据的置换方法及计算机系统

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116483738B (zh) * 2023-06-20 2023-09-05 苏州浪潮智能科技有限公司 数据访问方法及装置、存储介质及电子装置
CN116644006B (zh) * 2023-07-27 2023-11-03 浪潮电子信息产业股份有限公司 一种内存页面管理方法、系统、装置、设备及计算机介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200327049A1 (en) * 2019-04-11 2020-10-15 Alibaba Group Holding Limited Method and system for memory expansion with low overhead latency
CN112714906A (zh) * 2018-09-28 2021-04-27 英特尔公司 用以使用dram来作为用于高效云应用的慢速可按字节寻址存储器的缓存的方法和装置
CN112764925A (zh) * 2021-01-18 2021-05-07 苏州浪潮智能科技有限公司 基于虚拟内存的数据存储方法、装置、设备及存储介质
CN112860381A (zh) * 2021-03-09 2021-05-28 上海交通大学 基于申威处理器的虚拟机内存扩容方法及系统

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112714906A (zh) * 2018-09-28 2021-04-27 英特尔公司 用以使用dram来作为用于高效云应用的慢速可按字节寻址存储器的缓存的方法和装置
US20200327049A1 (en) * 2019-04-11 2020-10-15 Alibaba Group Holding Limited Method and system for memory expansion with low overhead latency
CN112764925A (zh) * 2021-01-18 2021-05-07 苏州浪潮智能科技有限公司 基于虚拟内存的数据存储方法、装置、设备及存储介质
CN112860381A (zh) * 2021-03-09 2021-05-28 上海交通大学 基于申威处理器的虚拟机内存扩容方法及系统

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116466879A (zh) * 2023-03-17 2023-07-21 北京超弦存储器研究院 一种cxl内存模组、内存数据的置换方法及计算机系统
CN116466879B (zh) * 2023-03-17 2023-12-29 北京超弦存储器研究院 一种cxl内存模组、内存数据的置换方法及计算机系统

Also Published As

Publication number Publication date
CN115794669A (zh) 2023-03-14

Similar Documents

Publication Publication Date Title
WO2023035646A1 (fr) Procédé et appareil d'extension de mémoire et dispositif associé
US11243706B2 (en) Fragment management method and fragment management apparatus
CN102012791B (zh) 基于Flash的数据存储PCIE板卡
US20160085585A1 (en) Memory System, Method for Processing Memory Access Request and Computer System
WO2021218038A1 (fr) Système de stockage, procédé de gestion de mémoire et nœud de gestion
CN112632069B (zh) 哈希表数据存储管理方法、装置、介质和电子设备
EP3974974A1 (fr) Procédé et système de virtualisation pour une mémoire persistante
WO2023125524A1 (fr) Procédé et système de stockage de données, procédé de configuration d'accès au stockage et dispositif associé
WO2023045483A1 (fr) Dispositif et système de stockage et procédé de stockage de données
WO2023051000A1 (fr) Procédé et appareil de gestion de mémoire, processeur et dispositif informatique
WO2015058641A1 (fr) Procédé et dispositif de mise en œuvre de disque dur hybride
US20240070120A1 (en) Data processing method and apparatus
US20240020014A1 (en) Method for Writing Data to Solid-State Drive
CN101377788A (zh) 一种机群文件系统中缓存管理的方法及系统
TW202203033A (zh) 儲存元件以及管理儲存元件中命名空間之系統與方法
US20230367493A1 (en) Capacity adjustment method and related apparatus
CN115203079A (zh) 一种将数据写入固态硬盘的方法
WO2022262345A1 (fr) Procédé et appareil de gestion de données, ainsi que procédé et appareil de gestion d'espace de stockage
US11586353B2 (en) Optimized access to high-speed storage device
US11086379B2 (en) Efficient storage system battery backup usage through dynamic implementation of power conservation actions
CN115793957A (zh) 写数据的方法、装置及计算机存储介质
WO2024045643A1 (fr) Dispositif, procédé et système d'accès à des données, unité de traitement de données et carte d'interface réseau
CN116665727B (zh) 写i/o汇聚方法、装置、存储设备和存储介质
WO2022222523A1 (fr) Procédé et appareil de gestion de journal
WO2023029417A1 (fr) Procédé et dispositif de stockage de données

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22866124

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE