WO2023029007A1

WO2023029007A1 - Method and device for electronic design automation

Info

Publication number: WO2023029007A1
Application number: PCT/CN2021/116544
Authority: WO
Inventors: 孙立杰; 万光星; 黄威森; 余华涛
Original assignee: 华为技术有限公司
Priority date: 2021-09-03
Filing date: 2021-09-03
Publication date: 2023-03-09
Also published as: CN117751364A

Abstract

Embodiments of the present disclosure relate to the field of electronic design automation, and provide a method and device used for electronic design automation. On the basis of a layout database comprising transistors but not redundant transistors, a parasitic capacitance database is queried so as to obtain the coupling capacitance between a transistor and a virtual redundant transistor corresponding to the transistor. On the basis of the coupling capacitor between the transistor and the virtual redundant transistor, a parasitic capacitance network of the transistor may be determined, and then a netlist representing a circuit design is generated. In the foregoing manner, the efficiency of layout parasitic parameter extraction may be significantly increased.

Description

Method and apparatus for electronic design automation

technical field

Embodiments of the present disclosure relate to electronic design automation (Electronic Design Automation, EDA), and more particularly, to methods and devices for electronic design automation.

Background technique

In the advanced process of integrated circuits, process planarization can avoid process defects such as short circuits or open circuits in integrated circuit products. Usually, in order to ensure the stability of process planarization, redundant patterns that do not affect circuit functions are inserted so that the density of the design layout is uniform enough. However, redundant graphics will introduce a large number of parasitic capacitance and resistance networks in the layout, which will reduce the extraction efficiency of layout parasitic parameters. Especially when the number of transistors per unit area of advanced technology is increasing, the parasitic parameter netlist generated by redundant graphics is very large, which affects the efficiency of post-layout simulation and design iterations.

The current technical solution formulates redundant automatic filling codes according to design rules, and automatically inserts redundant graphics into the layout through physical verification software to obtain a layout database containing redundant graphics. Based on the layout database, parasitic parameter extraction is performed by parasitic parameter extraction software to obtain a parasitic parameter netlist, and then post-layout simulation is performed. The parasitic parameter extraction software extracts the layout database containing a large number of redundant graphics, which leads to the low parasitic parameter extraction efficiency of the current technical solution. The layout database contains a large number of redundant graphics, which leads to the low post-layout simulation efficiency of the current technical solution.

Contents of the invention

In the current technical solution, the layout database contains a large number of redundant graphics, and the extraction of the layout database containing a large number of redundant graphics seriously affects the parasitic extraction efficiency and post-layout simulation efficiency.

Embodiments of the present disclosure provide an electronic design automation solution, in particular a parasitic parameter extraction solution for virtual redundant transistor filling.

In a first aspect of the present disclosure, a method of electronic design automation is provided. The method obtains a layout database representing a circuit design, the circuit design including transistors. For example, the circuit design may not include redundant transistors, and the layout database may not include redundant transistors. From the layout database, the parasitic capacitance database can be queried to determine the coupling capacitance between transistors in the circuit design and corresponding virtual redundant transistors. The parasitic capacitance database may include a mapping relationship between layout sizes of transistors and coupling capacitances between transistors and dummy redundant transistors. Based on the obtained coupling capacitance between the transistor and the virtual redundant transistor, the method can determine a parasitic capacitance network of the transistor representing the parasitic capacitance of the transistor. The method then generates a netlist representing the integrated circuit design based on the layout database and the parasitic capacitance network of the transistors. The netlist may be referred to as a parasitic parameter netlist or a post-simulation netlist. The coupling capacitance of a transistor to other conductive components (eg, redundant transistors) represents the parasitic capacitance caused by the coupling between the transistor and the conductive component. In addition to the coupling capacitance, there are also coupling capacitances between different conductive components inside the transistor, and these coupling capacitances are parasitic capacitances inside the transistor.

In the current technical solution, redundant graphics are first inserted into the layout, and then the parasitic parameters of the layout are extracted. Since the layout contains a large number of redundant graphics formed by redundant transistors (for example, redundant polygons, redundant networks, etc.), the efficiency of layout parasitic parameter extraction is low. Different from the current technical solutions, the layout database does not include redundant transistors when extracting parasitic parameters in the embodiments of the present disclosure. On the contrary, the embodiments of the present disclosure simulate the influence of redundant transistors on parasitic parameter extraction by virtual redundant transistors, thereby improving the efficiency of parasitic parameter extraction.

In some embodiments, a coupling capacitor is connected between the transistor and ground to define the parasitic capacitance network of the transistor. In this way, the dummy redundant transistors can be removed, and only the parasitic capacitance caused by the dummy redundant transistors remains, thereby ensuring that redundant transistors are not introduced into the parasitic parameter netlist.

In some embodiments, post-layout simulation is performed on the circuit design based on the parasitic netlist. In the current technical solution, due to the extra parasitic capacitance generated by the redundant filling, the parasitic parameter netlist obtained by the parasitic parameter extraction contains an extra parasitic capacitance network, thereby affecting the efficiency of the post-layout simulation. On the contrary, the embodiments of the present disclosure use virtual redundant transistors to simulate the influence of redundant transistors on the extraction of layout parasitic parameters, thereby improving the efficiency of post-layout simulation.

In some embodiments, redundant transistors corresponding to virtual redundant transistors are added to the layout database for use in generating mask data representing the circuit design. Adding redundant transistors to the layout database after post-layout simulation reduces the computational overhead of post-layout simulation.

In some embodiments, a corresponding parasitic capacitance network may be determined for each electrode of the transistor. Specifically, for the gate of the transistor, the gate coupling capacitance between the gate of the transistor and the adjacent electrode of the virtual redundant transistor can be obtained by querying the parasitic capacitance database, and based on the gate coupling capacitance, the gate of the transistor can be determined pole parasitic capacitance network. For the source of the transistor, the source coupling capacitance between the source of the transistor and the adjacent electrode of the redundant transistor can be obtained by querying the parasitic capacitance database, and based on the source coupling capacitance, the source parasitic capacitance network of the transistor can be determined. For the drain of the transistor, the drain coupling capacitance between the drain of the transistor and the adjacent electrode of the redundant transistor can be obtained by querying the parasitic capacitance database, and the drain parasitic capacitance network of the transistor can be determined based on the drain coupling capacitance.

In some embodiments, the layout size of the virtual redundant transistor and the mapping relationship between the layout size of the virtual redundant transistor and the layout-dependent effect (Layout-Dependent Effect, LDE) parameter of the transistor are obtained; and based on the virtual redundant transistor The layout size, through the mapping relationship between the layout size of the virtual redundant transistor and the LDE parameter, determines the LDE parameter of the transistor in the netlist. In this way, the LDE parameters in the parasitic parameter netlist can be corrected by the layout size of the dummy redundant transistors.

In some embodiments, the layout size of the transistor can be compared with the layout size of the transistor defined in the parasitic capacitance database, so as to determine the transistor in the parasitic capacitance database that matches the transistor. Then, based on the coupling capacitance of the transistor in the parasitic capacitance database, the coupling capacitance corresponding to the transistor is determined. Obtaining the coupling capacitance by comparing and querying can improve the efficiency of parasitic parameter extraction.

In some embodiments, the parasitic capacitance database may be generated based on the layout sizes of the predefined transistors and the layout sizes of virtual redundant transistors corresponding to the predefined transistors. For example, the parasitic capacitance database can be calculated by pattern matching or electromagnetic field solvers.

In some embodiments, the layout hierarchies in the layout database are mapped to corresponding technology hierarchies based on a hierarchy mapping file for mapping layout hierarchies to technology hierarchies. In this way, other parasitic capacitances of the transistor besides the coupling capacitance can be determined.

In a second aspect of the disclosure, the disclosure provides an apparatus. The device comprises: a processor; and a memory coupled to the processor and containing instructions stored thereon which, when executed by the processor, cause the device to perform the method.

In a third aspect of the present disclosure, there is provided a computer-readable storage medium on which computer programs/instructions are stored, and when the computer program/instructions are executed by a processor, the steps of the method in the first aspect of the present disclosure are implemented.

In a fourth aspect of the present disclosure, a computer program product is provided, including computer programs/instructions, which implement the steps of the method in the first aspect of the present disclosure when executed by a processor.

This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or principal characteristics of the disclosure, nor is it intended to limit the scope of the disclosure.

Description of drawings

The above and other objects, features and advantages of the present disclosure will become more apparent by describing the exemplary embodiments of the present disclosure in more detail with reference to the accompanying drawings, wherein, in the exemplary embodiments of the present disclosure, the same reference numerals are generally represent the same part.

FIG. 1 shows a flowchart of a method for designing an integrated circuit according to some embodiments of the present disclosure.

Fig. 2 shows a schematic diagram of a parasitic parameter extraction system according to some embodiments of the present disclosure.

FIG. 3 illustrates a layout of transistors according to some embodiments of the present disclosure.

FIG. 4 shows a layout of transistors according to some embodiments of the present disclosure.

FIG. 5 shows a layout of transistors according to some embodiments of the present disclosure.

FIG. 6 shows a layout of transistors according to some embodiments of the present disclosure.

FIG. 7 shows a schematic diagram of a gate capacitance network according to some embodiments of the present disclosure.

FIG. 8 shows a schematic diagram of a source capacitance network according to some embodiments of the present disclosure.

FIG. 9 shows a flowchart of a method for electronic design automation according to some embodiments of the present disclosure.

FIG. 10 shows a schematic block diagram of a device that can be used to implement embodiments of the present disclosure.

In accordance with common practice, the various features shown in the drawings may not be drawn to scale. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. Additionally, some figures may not depict all components of a given system, method, or device. Finally, like reference numerals may be used to represent like features throughout the specification and drawings.

Detailed ways

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the drawings, it should be understood that the disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein; A more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for exemplary purposes only, and are not intended to limit the protection scope of the present disclosure.

In the description of the embodiments of the present disclosure, the term "comprising" and its similar expressions should be interpreted as an open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be read as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same object. The term "and/or" means at least one of the two items associated with it. For example "A and/or B" means A, B, or A and B. Other definitions, both express and implied, may also be included below.

It should be understood that for the technical solutions provided by the embodiments of the present application, in the introduction of the following specific embodiments, some repetitions may not be repeated, but it should be considered that these specific embodiments have been referred to each other and can be combined with each other.

FIG. 1 shows a flowchart of a method 100 for designing a semiconductor chip according to some embodiments of the present disclosure. The method 100 can be implemented at least in part by an electronic design automation (Electronic Design Automation, EDA) tool. At block 102, the functional requirements of the chip are defined. The chip can be a processor, a memory chip, or a System on Chip (SoC) with multiple components. Functional requirements may include the nature of the chip and the performance goals of the chip.

At block 104, an Electronic System Level (ESL) description is generated based on the functional requirements of the chip. An electronic system-level description focuses on higher levels of abstraction without considering lower-level implementations. The goal of the ESL description is to increase the likelihood of successful functional implementation. Use appropriate abstractions to generate a global level understanding of the chip to be designed.

At block 106, a Register Transfer Level (RTL) description is generated from the ESL description. An RTL description is a description of a semiconductor chip design in terms of its operation. Specifically, the behavior of a circuit is defined in terms of the signal flow between hardware registers in the RTL description. For example, a Hardware Description Language (HDL) can be used to create a high-level representation of a circuit from which a low-level representation and ultimately the actual discrete components and wiring can be derived.

In block 108, logic synthesis is performed on the RTL description of the chip, for example, the RTL description of the chip in HDL form is converted into a gate-level description of the chip. Specifically, the gate-level description is a discrete netlist of logic gate primitives, ie, netlist 110 . After the netlist 110 is obtained, the netlist 110 can be simulated to determine whether the design achieves a predetermined function or design intent. This simulation is also called "pre-simulation" or "pre-layout simulation".

At block 112, the chip is physically designed based on the netlist 110 to construct the physical layout of the chip. For example, you can place components such as logic gates and route the placed components to provide interconnections between the signal and power terminals of the components. In this way, a layout 114 of a chip can be constructed.

At block 116, layout 114 is physically verified. For example, block 116 may include block 118, and at block 118, a design rule check (Design Rule Check, DRC) is performed on the layout 114 . The layout is drawn according to design rules, which can be provided by the fab. In the design rule check, it is checked whether the drawing of the layout 114 satisfies corresponding design rules.

After the layout 114 passes the design rule check, there may still be errors in the layout 114 , and these errors are not caused by violating the design rules, but may be inconsistent with the circuit diagram. For example, layout 114 may lack a connection, and such a small defect is also fatal to the entire chip. Therefore, block 116 may further include block 120. At block 120, a layout versus schematic (Layout Versus Schematic, LVS) is performed on the layout 114, which is also called a consistency check. In the consistency check, the netlist is extracted from the layout 114 and compared with the netlist 110 to ensure that the extracted netlist is consistent with the netlist 110 .

In addition, block 116 may further include block 122 , and at block 122 , parasitic extraction (parasitic extraction, PEX) is performed on layout 114 . In parasitic parameter extraction, parasitic parameters such as resistors and capacitors can be extracted from the layout 114, and a netlist including these parasitic parameters can be output, also called a parasitic parameter netlist. At block 124, the netlist including the parasitic parameters is simulated, which is also referred to as "post-simulation" or "post-layout simulation". Therefore, the parasitic parameter netlist used for post-simulation is also called post-simulation netlist. In post-simulation, the response of an actual digital and/or analog circuit is simulated by constructing an accurate analog model of the circuit.

At block 126 , layout post-processing may be performed on the layout 114 . For example, structures such as sealing rings can be added, resolution enhancement techniques can be applied, and so on. After post-layout processing, mask data 128 may be generated for final chip fabrication.

It should be understood that Fig. 1 only shows a schematic flow chart of IC design. In some embodiments, some steps may be added or deleted, or the sequence of some steps may be modified.

FIG. 2 shows a schematic block diagram of a parasitic parameter extraction system 200 according to some embodiments of the present disclosure. The parasitic parameter extraction system 200 may be implemented at block 122 as shown in FIG. 1 . As shown in FIG. 2 , the parasitic parameter extraction system 200 includes a parasitic parameter extractor 204 , and the parasitic parameter extractor 204 extracts parasitic parameters from the layout database 202 to generate a netlist 212 . Layout database 202 may be a database representation of layout 114 as shown in FIG. 1 . In an embodiment of the present disclosure, no redundant transistors are inserted in the layout 114 before physical verification 116 is performed, ie, the layout 114 does not include redundant transistors. Netlist 212 may be a post-simulation netlist for post-simulation as described with reference to FIG. 1 . The netlist 212 includes the extracted parasitic parameters, so it can also be called a parasitic parameter netlist.

For the convenience of describing the operation and function of the parasitic parameter extraction system 200, an example of the layout database 202 will now be described with reference to FIG. 3 . FIG. 3 illustrates a transistor layout 300 according to some embodiments of the present disclosure. The layout 300 may be a part of the layout represented by the layout database 202 shown in FIG. 2 , or a part of the layout 114 shown in FIG. 1 . As shown in FIG. 3 , the layout 300 includes a transistor 304 including a source electrode (S), a gate electrode (G) and a drain electrode (D). In addition, layout 300 also includes a substrate terminal 302 of the transistor, wherein substrate terminal 302 includes a substrate electrode (B). As shown in FIG. 3 , substrate 302 includes a plurality of fins 306 , in this example four fins. It should be understood that the number of fins is provided as an example only and that embodiments of the present disclosure may have any other suitable number of fins. As shown in FIG. 3 , each substrate electrode (B) vertically spans a plurality of fins 306 . In addition, the transistor 304 also includes a plurality of fins 308 , wherein the source electrode (S), gate electrode (G) and drain electrode (D) vertically span the plurality of fins 308 respectively. It should be understood that although layout 300 shows Fin Field Effect Transistors (FinFETs), embodiments of the present disclosure may also be applied to any other suitable transistors.

Returning to FIG. 2 , in some embodiments, the RC technical file 210 includes a resistance-capacitance (RC) database, and may be provided by a fab. The RC technical file 210 may be generated by an electromagnetic field solver based on an Interconnect Technology File (ITF) describing the process parameters of the conductor layer and the dielectric layer, and the interconnect technology file may also be provided by the fab. For example, the interconnect technical file may include the thickness of the conductor layer, the resistivity of the conductor layer, the dielectric constant of the interlayer dielectric and its thickness, the name of the upper conductor of the via, the name of the lower conductor of the via, the resistance of the via ,etc. For example, the interconnect technology file may also be included in the RC technology file 210 .

For example, the RC database in the RC technical file 210 may be presented in the form of a table and include polygonal figures forming transistors and capacitance values corresponding to the polygonal figures. When the parasitic parameter extractor 204 extracts the parasitic capacitance from the layout database 202 , the circuit layout in the layout database 202 can be divided into small blocks, wherein each small block includes a polygonal figure contained in the RC technology file 210 . Then, the parasitic parameter extractor 204 extracts the parasitic capacitance of the layout database 202 by reading the precalculated capacitance value of the polygon pattern stored in the RC technology file 210 .

In some embodiments, the parasitic parameter extractor 204 maps the layout hierarchy in the layout database 202 to the technology hierarchy in the RC technology file 210 through the hierarchy mapping file 206 . In the layer mapping file 206, each layout layer in the layout database 202 can be mapped to a corresponding technology layer. The layout level indicates the level of the corresponding component in the layout, and the technology level indicates the level of the corresponding component in the manufacturing technology or process, including corresponding technology or process information, for example, parasitic parameters. For example, the layer mapping file 206 can map the layout layer (M1) in the layout database 202 to the technology layer (Metal1) in the RC technology file 210, and map the layout layer (V1) in the layout database 202 to the RC technology file 210 technology level (VIA1), etc. In this way, the layout level of the layout database 202 can be mapped to the corresponding technology level, so as to obtain the corresponding technology information, for example, parasitic parameters. Extract command file 208 may include paths to layout database 202 , hierarchy map file 206 , and RC technology file 210 . The parasitic parameter extractor 204 reads the extraction command file 208 and parses the extraction command file 208 to obtain the paths of the layout database 202 , the layer mapping file 206 and the RC technology file 210 , and so on. Then, the parasitic parameter extractor 204 reads the layout database 202, the layer mapping file 206 and the RC technology file 210 from corresponding paths.

After the parasitic parameter extractor 204 maps the layout level in the layout database 202 to the technology level in the RC technology file 210 based on the level mapping file 206, the parasitic parameter extractor 204 based on the layout size in the layout level and the layout level corresponding to the layout level The parasitic parameters of the layout database 202 are extracted by using the parasitic parameters in the technology level.

In the current technical solution, redundant graphics are inserted into the layout 300, and then layout parasitic parameters are extracted. In this case, the layout will contain a large number of redundant graphics (eg, redundant polygons, redundant nets, etc.). When extracting parasitic parameters, the current technical solution needs to match these large numbers of redundant graphics with the polygonal graphics in the RC technical file 210 to calculate the parasitic capacitance. Therefore, the efficiency of layout parasitic parameter extraction is low. However, the parasitic parameter extraction system 200 performs parasitic parameter extraction on the layout 300 that does not contain redundant patterns, so as to improve the efficiency of parasitic parameter extraction. Since the layout 300 does not contain redundant graphics, in order to accurately extract parasitic parameters, the parasitic parameter extraction system 200 simulates the influence of redundant graphics on the parasitic parameters of the layout 300 by constructing an RC virtual redundancy rule file 214 and a parasitic capacitance database 216 . A detailed description will be made below in conjunction with FIGS. 4-6 .

According to an embodiment of the present disclosure, the extraction command file 208 may also include a path to the RC virtual redundancy rules file 214 . The RC virtual redundancy rule file 214 can define parameters of virtual redundant transistors, for example, layer information of virtual redundant transistors, layout size of virtual redundant transistors, and/or layout size of virtual redundant transistors and parameters used for post-layout simulation. Mapping between layout-dependent effect (Layout-Dependent Effect, LDE) parameters in the netlist 212 . In earlier technologies, transistors were larger in size, and the electrical characteristics of the transistor were independent of the transistor's location in the layout. However, as the size of transistors shrinks gradually, the electrical characteristics of transistors are more and more dependent on the location of transistors in the layout. This effect is called "layout-dependent effect", and the parameters that depend on the position of the transistor in the layout are called LDE parameters.

When parsing the extraction command file 208, the parasitic parameter extractor 204 can obtain the path of the RC virtual redundancy rule file 214, and read the RC virtual redundancy rule file 214 from the corresponding path. Table 1 provides an example of an RC virtual redundancy rules file 214 .

Table 1

As shown in Table 1, the RC virtual redundancy rule file 214 includes three parts, wherein the first part (Dummy_Transistor_Layers) includes the level information of the virtual redundant transistor, the second part (Dummy_Transistor_Dimension) includes the layout size of the virtual redundant transistor, and the third Part includes a mapping between layout dimensions of virtual redundant transistors and layout dependent effect (LDE) parameters in netlist 212 for post-layout simulation.

As shown in Table 1, the first part may include the redundant active area layer (AA_Dum) of the virtual redundant transistor, the redundant polysilicon layer (Poly_dum), the redundant source and drain metal M0 layer (M0_dum), and the N-doped implant layer (NPLUS) or P-doped injection layer (PPLUS), etc.

As shown in Table 1, the second part may include the spacing of the redundant gate (Dummy_poly_spacing), the channel length of the redundant gate (Dummy_poly_length), the length of the active region extending from the top of the redundant gate (Dummy_poly_extension_top), redundant The bottom of the gate protrudes from the active area length (Dummy_poly_extension_bottom), the redundant active area width (Dummy_AA_width), the redundant active area vertical spacing (Dummy_AA_spacing_vertical), the redundant metal layer M0 width (Dummy_M0_width), and the redundant gate terminal spacing (Dummy_poly_end_spacing), redundant metal layer M0 extension length (Dummy_M0_extension), redundant active area lateral spacing (Dummy_AA_spacing_horizon), redundant active area length (Dummy_AA_length), etc.

As shown in Table 1, the third part may include the mapping relationship between the layout size of the virtual redundant transistor and the LDE parameter, including the mapping relationship between the redundant gate spacing (Dummy_poly_spacing) and the gate spacing (PS), The mapping relationship between the redundant active area horizontal spacing (Dummy_AA_spacing_horizon) and the active area horizontal spacing (AAX), the mapping relationship between the redundant active area vertical spacing (Dummy_AA_spacing_vertical) and the active area vertical spacing (AAY), The mapping relationship between the redundant gate end spacing (Dummy_poly_end_spacing) and the gate end spacing (PES), the length of the redundant gate top protruding from the active area (Dummy_poly_extension_top) and the length of the gate top protruding from the active area (PXE1) The mapping relationship between, the mapping relationship between the length of the redundant gate extending from the bottom of the active region (Dummy_poly_extension_bottom) and the length of the gate bottom extending from the active region (PXE2), and so on.

An example of the second part of the RC virtual redundancy rules file 214 will be described below with reference to FIG. 4 . FIG. 4 illustrates a layout 400 of transistors according to some embodiments of the present disclosure. It should be understood that layout 400 is not an actual layout used for parasitic parameter extraction, ie, is not a specific example of layout database 202 . Layout 400 includes transistor 404 and its substrate terminal 402 , wherein substrate terminal 402 and transistor 404 correspond to substrate terminal 302 and transistor 304 shown in FIG. 3 . Additionally,

fins

406 and 408 correspond to

fins

306 and 308 shown in FIG. 3 , respectively. Compared with the layout 300, the layout 400 further includes a redundant pattern, wherein the redundant pattern includes a first virtual redundant transistor 406, a second virtual redundant transistor 408, a third virtual redundant transistor 410, and a fourth virtual redundant transistor 412 and fifth dummy redundancy transistor 414 . The first dummy redundant transistor 406, the second dummy redundant transistor 408, the third dummy redundant transistor 410, the fourth dummy redundant transistor 412 and the fifth dummy redundant transistor 414 respectively comprise a source (S _du ), a gate (G _du ) and drain (D _du ), and includes a substrate terminal 402 shared with transistor 404 . In addition, as shown in FIG. 4 , like the transistor 404 , the fourth dummy redundant transistor 412 also includes a plurality of fins 468 , wherein the source electrode (S _du ), the gate electrode (G _du ) and the drain electrode (D _du ) vertically across the plurality of fins 468 respectively. Similarly, other virtual redundant transistors also include multiple fins.

In FIG. 4 , layout 400 shows the layout dimensions of the dummy redundant transistors. It should be understood that layout 400 is not the actual layout used for parasitic parameter extraction. The first layout size 422 represents the spacing (Dummy_poly_spacing) of the redundant gate, the second layout size 424 represents the channel length (Dummy_poly_length) of the redundant gate, and the third layout size 426 represents that the top of the redundant gate protrudes from the active region Length (Dummy_poly_extenstion_top), the fourth layout size 428 indicates the length of the redundant gate extending from the bottom of the active area (Dummy_poly_extenstion_bottom), the fifth layout size 430 indicates the redundant active area width (Dummy_AA_width), and the sixth layout size 432 indicates redundant The vertical spacing of the active area (Dummy_AA_spacing_vertical), the seventh layout size 434 indicates the redundant metal layer M0 width (Dummy_M0_width), the eighth layout size 436 indicates the redundant gate end spacing (Dummy_poly_end_spacing), and the ninth layout size 438 indicates redundant metal The layer M0 extension length (Dummy_M0_extension), the tenth layout size 440 represents the dummy active area horizontal spacing (Dummy_AA_spacing_horizon), and the eleventh layout size 442 represents the dummy active area length (Dummy_AA_length).

In some embodiments, the layout dimensions of the virtual redundant transistors may be used to determine the LDE parameters of the transistors. FIG. 5 shows a schematic diagram of a layout 500 showing LDE parameters according to some embodiments of the present disclosure. The LDE parameters may be the LDE parameters in the netlist 212, which may be the LDE parameters in the SPICE model. As shown in FIG. 5 , layout 500 includes transistor 502 and its substrate terminal 502 as well as first dummy redundant transistor 506 , second dummy redundant transistor 508 , third dummy redundant transistor 510 , fourth dummy redundant transistor 512 and The fifth virtual redundant transistor 514 is respectively connected with the transistor 404 and its substrate 402 shown in FIG. 4 and the first virtual redundant transistor 406, the second virtual redundant transistor 408, the third virtual redundant transistor 410, the fourth The dummy redundancy transistor 412 corresponds to the fifth dummy redundancy transistor 414 . In FIG. 5, the first layout size 522 represents the gate pitch (PS), the second layout size 532 represents the vertical active area spacing (AAY), the third layout size 536 represents the gate end spacing (PES), and the fourth layout Dimension 540 represents the active area lateral pitch (AAX). These LDE parameters are layout dependent, so layout 400 that includes redundant transistors has different parameter values than layout 300 that does not include redundant transistors.

For example, if the influence of redundant transistors is not considered when extracting the parasitic parameters of the layout 300, some LDE parameters in the netlist 212, such as PS, AAX and AAY, may default to maximum values (1,000,000 meters), affecting Actual Device Performance. If the influence of redundant transistors is considered when extracting the parasitic parameters of the layout 300 , based on the layout size of the redundant transistors, the LDE parameters of the transistors can be determined through the mapping relationship between the layout size of the redundant transistors and the LDE parameters. Table 2 shows an example of a portion of netlist 212 without considering the effect of redundant transistors. Table 3 shows an example of a portion of netlist 212 when the effect of redundant transistors is considered.

Table 2

X0 D1 G1 S1 B1 NMOS L＝7.2e-8 NFIN＝3 SA＝9e-7, SB＝9e-7 PS＝1e+06 AAX＝1e+06 AAY＝1e+06 PES＝1e+06

table 3

X0 D1 G1 S1 B1 NMOS L＝7.2e-08 NFIN＝3 SA＝9e-7, SB＝9e-7 PS＝2.1e-07 AAX＝1e-07 AAY＝1.2e-07 PES＝5e-08

In Table 2 and Table 3, X0 indicates the transistor device, D1, G1, S1, and B1 respectively indicate the drain, gate, source, and substrate terminals of the transistor, NMOS indicates the type of the transistor, and L indicates the terminal of the gate. Length, NFIN represents the number of fins, SA represents the distance from the boundary of the active region of the source region to the gate, SB represents the distance from the boundary of the active region of the drain region to the gate, PS represents the gate spacing, and AAX represents the lateral spacing of the active region, AAY indicates the vertical spacing of active regions, and PES indicates the spacing between gate terminals. As shown in Tables 2 and 3, the LDE parameters (eg, PS, AAX, AAY, PES) depend significantly on the layout size of the redundant transistors. Therefore, through the mapping relationship between the layout size of the redundant transistor and the LDE parameter, the LDE parameter of the transistor can be corrected.

Returning to FIG. 2 , the extraction command file 208 may also include a path to a parasitic capacitance database 216 according to an embodiment of the present disclosure. Parasitic capacitance database 216 may include parasitic capacitance introduced by redundant transistors. For example, parasitic capacitance database 216 may be provided by a foundry. Alternatively, the parasitic capacitance database can also be provided by an EDA software company or a semiconductor design company.

In some embodiments, the parasitic capacitance database 216 may be generated from the RC technology file 210 and the RC virtual redundancy rules file 214 (specifically, the layout size of redundant transistors). The parasitic capacitance database 216 may include the relationship between the layout size of the predefined transistors and the coupling capacitance between the predefined transistors and the virtual redundant transistors corresponding to the predefined transistors. For example, the coupling capacitance between the transistor and the virtual redundant transistor corresponding to the transistor can be calculated by means of pattern matching. Based on the layout dimensions of a transistor, the polygonal shape that makes up the transistor can be determined. Then, from the RC technical file 210, a polygon pattern matching the polygon pattern constituting the transistor is determined. Based on the layout size of the virtual redundant transistor, the polygonal figure constituting the virtual redundant transistor can be determined. Then, from the RC technical file 210, a polygon pattern matching the polygon pattern constituting the dummy redundant transistor is determined. By reading the pre-calculated capacitance values between the polygonal figures in the RC technical document 210 and combining these capacitance values, the coupling capacitance between the transistor and the virtual redundant transistor can be determined. In this manner, the parasitic capacitance database 216 can be constructed. Alternatively, similar to constructing the RC technology file 210, the parasitic capacitance database 216 may be calculated by an electromagnetic field solver based on the interconnect technology file and the layout dimensions of predefined transistors and corresponding virtual redundant transistors.

When parsing the extraction command file 208, the parasitic parameter extractor 204 can obtain the path of the parasitic capacitance database 216, and read the parasitic capacitance database 216 from the corresponding path. The parasitic parameter extractor 204 can determine the corresponding coupling capacitance in the parasitic capacitance database 216 based on the layout size of the transistor 304 in the layout database 202 . Specifically, the parasitic capacitance database 216 can be queried based on the layout database 202 to obtain the coupling capacitance between the transistor 304 in the layout database 202 and the corresponding virtual redundant transistor. For example, the layout size of transistor 304 in layout database 202 may be compared with the layout size of predefined transistors in parasitic capacitance database 216 to determine a predefined transistor matching transistor 304 . Then, the coupling capacitance between the transistor 304 and its corresponding virtual redundant transistor can be determined based on the coupling capacitance between the predefined transistor and its corresponding virtual redundant transistor. In some embodiments, parasitic capacitance database 216 may not include predefined transistors that are exactly equal to the layout size of transistor 304 . In this case, a predefined transistor whose layout size is closest to the transistor 304 can be used as a matching transistor. The extraction of parasitic capacitance will be described below in conjunction with FIGS. 6-8 .

FIG. 6 shows a layout 600 of transistors according to some embodiments of the present disclosure. Layout 600 is substantially the same as layout 400 except that a portion of the coupling capacitance between transistor 404 and first dummy redundant transistor 406 , second dummy redundant transistor 408 , and fourth dummy redundant transistor 412 is shown. It should be understood that only a part of the parasitic capacitances are shown here for convenience, and different models may include more or less parasitic capacitances. For example, only coupling capacitance between dummy redundant transistors adjacent to transistor 404 may be considered. For another example, only the coupling capacitance between the corresponding electrodes of the dummy redundant transistors adjacent to the electrodes of the transistor 404 may be considered. Specifically, FIG. 6 shows the coupling capacitance C Gdu1 between the gate of the transistor 404 and the gate of the second dummy redundant transistor 408 , the coupling capacitance C _Gdu1 between the gate of the transistor 404 and the gate of the fourth dummy redundant transistor 412 The coupling capacitance C _Gdu2 between the gate of the transistor 404 and the gate of the first dummy redundant transistor 406, the coupling capacitance C _Gdu3 between the gate of the transistor 404 and the source of the second dummy redundant transistor 408 The coupling capacitor C _GSdu1 . In addition, FIG. 6 also shows the coupling capacitance C _SSdu1 between the source of the transistor 404 and the source of the second dummy redundant transistor 408 , and the connection between the source of the transistor 404 and the drain of the fourth dummy redundant transistor 412 between the coupling capacitor C _SDdu1 . For simplicity, FIG. 6 does not show the coupling capacitance between the drain of transistor 404 and the dummy redundant transistor. Capacitance values of these coupling capacitors can be obtained from the parasitic capacitance database 216 .

FIG. 7 illustrates a gate parasitic capacitance network of a transistor according to some embodiments of the present disclosure. As shown in FIG. 7 , the gate parasitic capacitance network (NET G) includes coupling capacitances C _Gdu1 , C _Gdu2 , C _Gdu3 and C _GSdu1 . In the gate parasitic capacitance network, one end of the coupling capacitors C _Gdu1 , C _Gdu2 , C _Gdu3 and C _GSdu1 can be grounded instead of being coupled to the dummy redundant transistor. In this way, the coupling capacitances C _Gdu1 , C _Gdu2 , C _Gdu3 , and C _GSdu1 connect the gate of transistor 404 to ground in the gate parasitic capacitance network.

FIG. 8 illustrates a source parasitic capacitance network of a transistor according to some embodiments of the present disclosure. As shown in FIG. 8 , the source parasitic capacitance network (NET S) includes coupling capacitors C _SSdu1 and C _SDdu1 . In the source parasitic capacitance network, one end of the coupling capacitors C _SSdu1 and C _SDdu1 can be grounded instead of being coupled to a dummy redundant transistor. In this way, the coupling capacitors C _SSdu1 and C _SDdu1 connect the source of transistor 404 to ground in the source parasitic capacitance network. Table 4 shows a netlist of the gate parasitic network and the source parasitic network of the transistor 404 .

Table 4

As shown in Table 4, *|NET G represents the gate parasitic capacitance network of the transistor 404, and its capacitance value is 2.12145e-16. C1 and C2 are respectively the gate parasitic capacitance (for example, the coupling capacitance between the gate and the source of the transistor 404, the coupling capacitance between the gate and the drain of the transistor 404) of the transistor 404 itself which has nothing to do with the virtual redundant transistor ), C3-C6 denote coupling capacitors C _Gdu1 , C _Gdu2 , C _Gdu3 and C _GSdu1 respectively. *|NET S represents the source parasitic capacitance network of the transistor 404, and its capacitance value is 8.53246e-17. C1 and C2 are respectively the source parasitic capacitance (for example, the coupling capacitance between the source and the gate of the transistor 404, the coupling capacitance between the source and the drain of the transistor 404) of the transistor 404 itself which has nothing to do with the virtual redundant transistor ), C3 and C4 represent the coupling capacitors C _SSdu1 and C _SDdu1 respectively.

Returning now to FIG. 1 , at block 124 the netlist 212 is post-simulated. Since the netlist 212 does not include redundant transistors, but only includes the effects of redundant transistors on transistors (eg, effects on parasitic capacitance, effects on LDE parameters, etc.), post-simulation efficiency can be greatly improved. Additionally, at block 126, redundant transistors may be added in the layout database 202 for use in generating mask data 128 for final chip fabrication.

FIG. 9 shows a flowchart of a method 900 for electronic design automation according to some embodiments of the present disclosure. For example, the method 900 can be implemented in the parasitic parameter extraction system 200 shown in FIG. 2 .

At block 902, a layout database representing a circuit design, including transistors, is obtained. The circuit design may not include redundant transistors, and the layout database may not include redundant transistors. For example, the layout database may be layout database 202 as shown in FIG. 2 and the transistor may be transistor 304 as shown in FIG. 3 .

At block 904, based on the layout database, the parasitic capacitance database is queried to obtain the coupling capacitance between the transistor and the virtual redundant transistor corresponding to the transistor. The parasitic capacitance database includes a relationship between layout sizes of predefined transistors and coupling capacitances between the predefined transistors and virtual redundant transistors corresponding to the predefined transistors. In some embodiments, a virtual redundant transistor corresponding to a transistor may be a virtual redundant transistor adjacent to the transistor, or a virtual redundant transistor within a certain spatial distance of the transistor. In yet other embodiments, dummy redundant transistors may be specified by the fab's redundant fill process. For example, the transistor may be transistor 404, and the dummy redundant transistor may be first dummy redundant transistor 406, second dummy redundant transistor 408, third dummy redundant transistor 410, fourth dummy redundant transistor 412, and fifth dummy redundant transistor. remaining transistor 414.

In some embodiments, the layout size of transistors in the layout database may be compared with the layout size of predefined transistors in the parasitic capacitance database to determine a predefined transistor matching the transistor. Then, the coupling capacitance between the transistor and its corresponding virtual redundant transistor can be determined based on the coupling capacitance between the predefined transistor and its corresponding virtual redundant transistor. In some embodiments, the parasitic capacitance database may not include predefined transistors that are exactly equal to the transistor's layout size. In this case, a predefined transistor whose layout size is closest to the transistor can be used as a matching transistor.

In some embodiments, the coupling capacitance may include a gate coupling capacitance between the gate of the transistor and an adjacent electrode of the dummy redundant transistor, and a source coupling capacitance between the source of the transistor and an adjacent electrode of the dummy redundant transistor. capacitance, and/or drain coupling capacitance between the drain of the transistor and the adjacent electrode of the dummy redundant transistor. For example, in the embodiment shown in FIG. 6 , the gate coupling capacitance of the transistor 404 may include a coupling capacitance C _Gdu1 between the gate of the transistor 404 and the gate of the second dummy redundant transistor 408 , the gate of the transistor 404 The coupling capacitance C _Gdu2 between the gate of the fourth dummy redundant transistor 412, the coupling capacitance C _Gdu3 between the gate of the transistor 404 and the gate of the first dummy redundant transistor 406, and the gate of the transistor 404 and The coupling capacitance C _GSdu1 between the sources of the second dummy redundancy transistor 408 . For example, in the example shown in FIG. 6 , the source coupling capacitance of transistor 404 may include the coupling capacitance C _SSdu1 between the source of transistor 404 and the source of second dummy redundant transistor 408 , and the source of transistor 404 and the coupling capacitor C _SDdu1 between the drain of the fourth dummy redundant transistor 412 .

At block 906, based on the coupling capacitance between the transistor and the dummy redundant transistor, a parasitic capacitance network of the transistor is determined, the parasitic capacitance network representing the parasitic capacitance of the transistor. The coupling capacitance between the transistor and the virtual redundant transistor can be equivalent to the parasitic capacitance of the transistor, so as to avoid introducing redundant transistors.

In some embodiments, a coupling capacitor is connected between the transistor and ground to define the parasitic capacitance network of the transistor. For example, the gate parasitic capacitance network of the transistor can be determined based on the gate coupling capacitance; the source parasitic capacitance network of the transistor can be determined based on the source coupling capacitance; and the drain parasitic capacitance network of the transistor can be determined based on the drain coupling capacitance. In this way, the parasitic capacitance network of the transistor includes the coupling capacitance of the transistor and the redundant transistor, but does not include the redundant transistor.

At block 908, a netlist representing the circuit design is generated based on the layout database and the parasitic capacitance network of the transistors. The netlist includes the layout dimensions of the transistors and the parasitic capacitance network of the transistors. For example, the layout dimensions of transistors can be determined from a layout database.

In some embodiments, the method 900 further includes: performing post-layout simulation on the circuit design based on the netlist. After the circuit design is verified by post-layout simulation, redundant transistors corresponding to virtual redundant transistors can be added to the layout database for generating mask data representing the circuit design.

In some embodiments, the method 900 further includes: obtaining the layout size of the virtual redundant transistor and the mapping relationship between the layout size of the virtual redundant transistor and the layout dependent effect (LDE) parameter of the transistor; The layout size, through the mapping relationship between the layout size of the virtual redundant transistor and the LDE parameter, determines the LDE parameter of the transistor in the netlist.

FIG. 10 shows a schematic block diagram of a device 1000 that can be used to implement embodiments of the present disclosure. The method 100 shown in FIG. 1 , the system 200 shown in FIG. 2 and the method 900 shown in FIG. 9 may be implemented by the device 1000 .

As shown in Figure 10, the device 1000 includes a central processing unit (Central Processing Unit, CPU) 1001, which can be stored in a computer program instruction in a read-only memory (Read-Only Memory, ROM) 1002 or loaded from a storage unit 1008 to Computer program instructions in a random access memory (Random Access Memory, RAM) 1003 to perform various appropriate actions and processes. In the RAM 1003, various programs and data necessary for the operation of the device 1000 can also be stored. The CPU 1001, ROM 1002, and RAM 1003 are connected to each other via a bus 1004. An input/output (Input/Output, I/O) interface 1005 is also connected to the bus 1004 .

Multiple components in the device 1000 are connected to the I/O interface 1005, including: an input unit 1006, such as a keyboard, a mouse, etc.; an output unit 1007, such as various types of displays, speakers, etc.; a storage unit 1008, such as a magnetic disk, an optical disk, etc. ; and a communication unit 1009, such as a network card, a modem, a wireless communication transceiver, and the like. The communication unit 1009 allows the device 1000 to exchange information/data with other devices through a computer network such as the Internet and/or various telecommunication networks.

The various procedures and processes described above, such as the

method

100 or 900 , can be executed by the processing unit 1001 . For example, in some embodiments,

method

100 or 900 may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as storage unit 1008 . In some embodiments, part or all of the computer program may be loaded and/or installed on the device 1000 via the ROM 1002 and/or the communication unit 1009. When a computer program is loaded into RAM 1003 and executed by CPU 1001, one or more steps of

method

100 or 900 described above may be performed. Alternatively, in other embodiments, the CPU 1001 may be configured to execute the

method

100 or 900 in any other suitable manner (for example, by means of firmware).

The present disclosure may be a method, apparatus, system and/or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions thereon for carrying out various aspects of the present disclosure.

A computer readable storage medium may be a tangible device that can retain and store instructions for use by an instruction execution device. A computer readable storage medium may be, for example, but is not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (Erasable Programmable Read-Only Memory, EPROM) or flash memory, Static Random Access Memory (Static Random Access Memory, SRAM), Portable Compact Disc Read-Only Memory (CD-ROM), Digital Versatile Disk (Digital Video Disc, DVD), memory sticks, floppy disks, mechanically encoded devices such as punched cards or raised structures in grooves with instructions stored thereon, and any suitable combination of the foregoing. As used herein, computer-readable storage media are not to be construed as transient signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., pulses of light through fiber optic cables), or transmitted electrical signals.

Computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a respective computing/processing device, or downloaded to an external computer or external storage device over a network, such as the Internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and/or edge servers. A network adapter card or a network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in each computing/processing device .

Computer program instructions for performing the operations of the present disclosure may be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or in the form of one or more source or object code written in any combination of programming languages, including object-oriented programming languages—such as Python, C++, etc., and conventional procedural programming languages—such as “C” or similar programming languages. Computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server implement. In cases involving a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or it may be connected to an external computer such as use an Internet service provider to connect via the Internet). In some embodiments, electronic circuits, such as programmable logic circuits, field programmable gate arrays (Field Programmable Gate Array, FPGA) or programmable logic arrays (Programmable Logic Array, PLA), the electronic circuit can execute computer-readable program instructions, thereby implementing various aspects of the present disclosure.

Aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It should be understood that each block of the flowcharts and/or block diagrams, and combinations of blocks in the flowcharts and/or block diagrams, can be implemented by computer-readable program instructions.

These computer-readable program instructions may be provided to a processing unit of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine such that when executed by the processing unit of the computer or other programmable data processing apparatus , producing an apparatus for realizing the functions/actions specified in one or more blocks in the flowchart and/or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause computers, programmable data processing devices and/or other devices to work in a specific way, so that the computer-readable medium storing instructions includes An article of manufacture comprising instructions for implementing various aspects of the functions/acts specified in one or more blocks in flowcharts and/or block diagrams.

It is also possible to load computer-readable program instructions into a computer, other programmable data processing device, or other equipment, so that a series of operation steps are performed on the computer, other programmable data processing device, or other equipment to produce a computer-implemented process , so that instructions executed on computers, other programmable data processing devices, or other devices implement the functions/actions specified in one or more blocks in the flowcharts and/or block diagrams.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, a portion of a program segment, or an instruction that includes one or more Executable instructions. In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks in succession may, in fact, be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. It should also be noted that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by a dedicated hardware-based system that performs the specified function or action , or may be implemented by a combination of dedicated hardware and computer instructions.

Having described various embodiments of the present disclosure above, the foregoing description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and alterations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terminology used herein is chosen to best explain the principle of each embodiment, practical application or improvement of technology in the market, or to enable other ordinary skilled in the art to understand each embodiment disclosed herein.

Claims

A method of electronic design automation, comprising:

obtaining a layout database representing a circuit design that includes transistors and does not include redundant transistors;

Based on the layout database, query the parasitic capacitance database to obtain the coupling capacitance between the transistor and the virtual redundant transistor corresponding to the transistor, wherein the parasitic capacitance database includes the layout size of the predefined transistor and the predefined defining a relationship between a transistor and a coupling capacitance between a virtual redundant transistor corresponding to the predefined transistor;

determining a parasitic capacitance network of the transistor based on a coupling capacitance between the transistor and the virtual redundant transistor, the network of parasitic capacitance representing the parasitic capacitance of the transistor; and

A netlist representing the circuit design is generated based on the layout database and the parasitic capacitance network of the transistors.
The method according to claim 1, wherein said determining the parasitic capacitance network of the transistor based on the coupling capacitance between the transistor and the virtual redundant transistor comprises:

The coupling capacitance is connected between the transistor and ground to obtain a parasitic capacitance network of the transistor.
The method according to claim 1 or 2, further comprising:

Based on the netlist, post-layout simulation is performed on the circuit design.
The method according to any one of claims 1-3, wherein said transistor comprises a first electrode, and said parasitic capacitance network comprises a first parasitic capacitance network of said first electrode, and said based on said layout The database, querying the parasitic capacitance database to obtain the coupling capacitance between the transistor and the virtual redundant transistor corresponding to the transistor includes: based on the layout database, querying the parasitic capacitance database to obtain all of the transistors a first coupling capacitance between the first electrode and an adjacent electrode of the dummy redundant transistor, and

The determining the parasitic capacitance network of the transistor based on the coupling capacitance between the transistor and the virtual redundant transistor includes: determining the first electrode parasitic capacitance network of the transistor based on the first coupling capacitance.
The method of claim 4, wherein the first electrode is at least one of a gate, a source, and a drain of the transistor.
The method according to any one of claims 1-5, wherein the parasitic capacitance database is queried based on the layout database to obtain the coupling capacitance between the transistor and a virtual redundant transistor corresponding to the transistor include:

comparing the layout size of the transistor with the layout size of predefined transistors in the parasitic capacitance database to determine a predefined transistor matching the transistor; and

determining the coupling between the transistor and a virtual redundant transistor corresponding to the transistor based on a coupling capacitance between a predefined transistor matching the transistor and a virtual redundant transistor corresponding to the predefined transistor capacitance.
The method according to any one of claims 1-6, further comprising:

Obtaining the layout size of the virtual redundant transistor and a mapping relationship between the layout size of the virtual redundant transistor and a layout dependent effect (LDE) parameter of the transistor; and

Based on the layout size of the virtual redundant transistor, the LDE parameter of the transistor in the netlist is determined through a mapping relationship between the layout size of the virtual redundant transistor and the LDE parameter.
The method according to any one of claims 1-7, further comprising:

Redundant transistors corresponding to the virtual redundant transistors are added to the layout database for use in generating mask data representing the circuit design.
The method according to any one of claims 1-7, further comprising:

The parasitic capacitance database is generated based on a layout size of a predefined transistor and a layout size of a virtual redundant transistor corresponding to the predefined transistor.
The method according to claim 9, wherein said generating the parasitic capacitance database based on the layout size of the predefined transistor and the layout size of the virtual redundant transistor corresponding to the predefined transistor comprises:

determining a polygon pattern associated with the predefined transistor and the virtual redundant transistor based on the layout size of the predefined transistor and the layout size of a virtual redundant transistor corresponding to the predefined transistor; and

calculating coupling capacitances between the predefined transistors and the virtual redundant transistors by matching the polygonal graphics with predefined polygonal graphics having capacitance values of pre-calculated coupling capacitances to generate the parasitic capacitance database .
The method according to claim 9, wherein said generating the parasitic capacitance database based on the layout size of the predefined transistor and the layout size of the virtual redundant transistor corresponding to the predefined transistor comprises:

Based on the interconnect technology file representing the manufacturing process, the layout size of the predefined transistor and the layout size of the virtual redundant transistor corresponding to the predefined transistor, the relationship between the predefined transistor and the virtual transistor is calculated by an electromagnetic field solver. redundant coupling capacitance between transistors to generate the parasitic capacitance database.
The method according to any one of claims 1-11, further comprising:

Mapping the layout hierarchy in the layout database to the corresponding technology hierarchy based on the hierarchy mapping file used for mapping the layout hierarchy to the technology hierarchy.
A device comprising:

processor; and

A memory coupled to the processor and storing instructions that, when executed by the processor, cause the device to implement the method of any one of claims 1-12.
A computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions, when executed by at least one processor, cause the at least one processor to perform the Methods.
A computer program, wherein said computer program, when executed by at least one processor, causes said at least one processor to perform the method according to any one of claims 1-12.