WO2023026945A1

WO2023026945A1 - Slave circuit and remote control system using same

Info

Publication number: WO2023026945A1
Application number: PCT/JP2022/031183
Authority: WO
Inventors: 望古謝; 信桝谷
Original assignee: ローム株式会社
Priority date: 2021-08-26
Filing date: 2022-08-18
Publication date: 2023-03-02
Also published as: JPWO2023026945A1

Abstract

This slave circuit 30 is connected to a master circuit 20 via a bus bar 12. A rectification circuit 32 has an input terminal connected to the bus bar 12 and is constituted to be capable of charging a capacitor C1. A boot monitoring circuit 60 compares a voltage VCC of the capacitor C1 with a prescribed release threshold VTH1 and asserts an enable signal EN when the voltage VCC of the capacitor C1 exceeds the release threshold VTH1. An internal circuit 34 becomes active after the assertion of the enable signal EN and executes a prescribed boot sequence.

Description

SLAVE CIRCUIT AND REMOTE CONTROL SYSTEM USING THE SAME

The present disclosure relates to a slave circuit controlled by a master circuit.

A power supply voltage is supplied from a master circuit to one or more slave circuits connected to it via a bus, and communication is performed between the master circuit and the slave circuits by modulating the voltage of the bus. There is a system (referred to as a remote control system).

Japanese Patent No. 6808814

The present disclosure has been made in this context, and one exemplary purpose of certain aspects thereof is to provide a slave circuit that can be reliably activated.

An aspect of the present disclosure relates to a slave circuit connected to a master circuit via a bus. The slave circuit has an input terminal connected to the bus and a rectifier circuit configured to charge the capacitor, and compares the voltage of the capacitor with a predetermined release threshold so that the voltage of the capacitor exceeds the release threshold. A start-up monitoring circuit that asserts an enable signal when exceeded, and an internal circuit that becomes active after the enable signal is asserted and executes a predetermined start-up sequence.

Arbitrary combinations of the above components, or conversions of the expressions of the present disclosure between methods, devices, etc. are also effective as aspects of the present invention.

According to an aspect of the present disclosure, it is possible to reliably activate the slave circuit.

FIG. 1 is a block diagram of a telecommunications system according to an embodiment. FIG. 2 is a circuit diagram of a slave circuit according to the embodiment. FIG. 3 is a waveform diagram at startup of the telecommunication system of FIG. FIG. 4 is an equivalent circuit diagram explaining the drop in the input voltage _VIN . FIG. 5 is a waveform diagram of a startup sequence in the comparative technique.

(Overview of embodiment)
SUMMARY OF THE INVENTION Several exemplary embodiments of the disclosure are summarized. This summary presents, in simplified form, some concepts of one or more embodiments, as a prelude to the more detailed description that is presented later, and for the purpose of a basic understanding of the embodiments. The size is not limited. This summary is not an extensive overview of all possible embodiments, but is intended to neither identify key or key elements of all embodiments nor delineate the scope of some or all aspects. not. For convenience, "one embodiment" may be used to refer to one embodiment (example or variation) or multiple embodiments (examples or variations) disclosed herein.

A slave circuit according to one embodiment is connected to a master circuit via a bus. The slave circuit has an input terminal connected to the bus and a rectifier circuit configured to charge the capacitor, and compares the voltage of the capacitor with a predetermined release threshold so that the voltage of the capacitor exceeds the release threshold. A start-up monitoring circuit that asserts an enable signal when exceeded, and an internal circuit that becomes active after the enable signal is asserted and executes a predetermined start-up sequence.

By starting the start-up sequence of the internal circuit after the voltage of the capacitor has become sufficiently high, it is possible to prevent a situation in which the voltage of the capacitor is insufficient during the start-up sequence. As a result, the slave circuit can be reliably activated.

An embodiment may further include a reset circuit that resets the slave circuit when the voltage of the capacitor falls below a predetermined reset threshold. A release threshold may be defined such that the voltage on the capacitor does not drop below the reset threshold after the internal circuitry has been activated but before the start-up sequence is completed.

In one embodiment, the slave circuit may comprise a capacitor pin connected with the output of the rectifier circuit. The capacitor may be externally attached to the capacitor pin.

In one embodiment, the internal circuitry may include a microcontroller. After power-on, the microcontroller needs to read the program, which requires a boot sequence. According to this configuration, the microcontroller can be reliably activated.

In one embodiment, when transmitting a signal from the slave circuit to the master circuit, it may further include a transmission circuit that sinks current from the bus to change the voltage of the bus. The internal circuitry may be able to communicate with the master circuitry using the transmission circuitry after activation is complete.

In one embodiment, the rectifier circuit may include a diode bridge circuit.

In one embodiment, the busbar may include a first wire and a second wire.

In one embodiment, the slave circuit may be monolithically integrated on one semiconductor substrate. "Integrated integration" includes the case where all circuit components are formed on a semiconductor substrate, and the case where the main components of a circuit are integrated. A resistor, capacitor, or the like may be provided outside the semiconductor substrate. By integrating the circuits on one chip, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

(embodiment)
Preferred embodiments will be described below with reference to the drawings. The same or equivalent constituent elements, members, and processes shown in each drawing are denoted by the same reference numerals, and duplication of description will be omitted as appropriate. Moreover, the embodiments are illustrative rather than limiting of the disclosure and invention, and not all features or combinations thereof described in the embodiments are necessarily essential to the disclosure and invention. do not have.

In this specification, "a state in which member A is connected to member B" refers to a case in which member A and member B are physically directly connected, as well as a case in which member A and member B are electrically connected to each other. It also includes the case of being indirectly connected through other members that do not substantially affect the physical connection state or impair the functions and effects achieved by their combination.

Similarly, "the state in which member C is connected (provided) between member A and member B" refers to the case where member A and member C or member B and member C are directly connected. In addition, it also includes the case of being indirectly connected through other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their combination.

FIG. 1 is a block diagram of a telecommunications system 10 according to an embodiment. Telecommunications system 10 comprises master circuitry 20 , slave circuitry 30 and bus 12 . Master circuit 20 and slave circuit 30 are connected via bus 12 . The busbar 12 includes a first wire W1 and a second wire W2. Master circuit 20 supplies power supply voltage V _DC (power) to slave circuit 30 via bus 12 . Specifically, the master circuit 20 generates a potential difference corresponding to the power supply voltage _VDC between the first wire W1 and the second wire W2. The potential difference is not particularly limited, but may be 5V, 6V, 8V, 12V, 24V, and the like.

The slave circuit 30 is configured to be operable using the potential difference between the first wire W1 and the second wire W2 as the power supply voltage. Master circuit 20 and slave circuit 30 are configured to communicate via bus 12 . Specifically, the master circuit 20 transmits a signal to the slave circuit 30 by changing the potential difference between the first wire W1 and the second wire W2. Similarly, the slave circuit 30 also transmits a signal to the master circuit 20 by changing the potential difference between the first wire W1 and the second wire W2.

A plurality of slave circuits 30 may be connected to the bus 12 . In that case, an identification number (ID) is assigned to the plurality of slave circuits 30 . The master circuit 20 embeds an identification number in the head part (preamble) of communication to specify the communication partner. When the preamble of the received signal contains its own identification number, the plurality of slave circuits 30 determine that they themselves are the object of communication and respond to the signal from the master circuit 20 .

FIG. 2 is a circuit diagram of the slave circuit 30 according to the embodiment. The slave circuit 30 is a functional IC (Integrated Circuit) integrated on one semiconductor substrate, and includes a first input pin IN1, a second input pin IN2, a rectifying circuit 32, an internal circuit 34, a receiving circuit 40, and a transmitting circuit 50. Prepare.

The rectifier circuit 32 has an input terminal connected to the bus 12 and is configured to charge the capacitor C1. Rectifier circuit 32 is, for example, a diode bridge circuit, and its inputs are connected to first input pin IN1 and second input pin IN2. A rectifier circuit 32 rectifies the voltage _VIN between the two wires W1 and W2. Power supply voltage Vcc of slave circuit 30 is generated using the voltage after rectification by rectification circuit 32 . In this embodiment, the slave circuit 30 has a capacitor pin CP, to which a capacitor C1 is externally attached, and the voltage generated in the capacitor C1 becomes the power supply voltage _VCC of the slave circuit 30. . A rectifying element such as a diode D1 may be inserted between the output node of the rectifying circuit 32 and the capacitor C1. In this example, the diode D1 is built in (integrated) in the slave circuit 30, but the diode D1 may be externally attached to the slave circuit 30. FIG.

The internal circuit 34 has functions according to the application of the slave circuit 30, executes processing according to control commands from the master circuit 20, and responds to inquiries from the master circuit 20. The internal circuit 34 includes, for example, a microcontroller, and becomes operable through a predetermined startup sequence.

The receiving circuit 40 receives signals transmitted from the master circuit 20 . The master circuit 20 switches the voltage _VDC on the bus 12 when transmitting signals to the slave circuit 30 . The receiving circuit 40 generates a receiving signal RX based on changes in the input voltage _VIN .

The internal circuit 34 generates a transmission signal TX when transmitting a signal from the slave circuit 30 to the master circuit 20 . The transmission circuit 50 sinks the current _ITX from the bus 12 and changes the voltage _VDC of the bus 12 according to the transmission signal TX.

Start-up monitor circuit 60 compares voltage _VCC on capacitor C1 with a predetermined release threshold _VTH1 and asserts enable signal EN when voltage _VCC on capacitor C1 exceeds release threshold _VTH1 .

The internal circuit 34 becomes active after the enable signal EN is asserted, and executes a predetermined startup sequence. The consumption current _IDD of the internal circuit 34 increases during the activation sequence, and after the completion of the activation sequence, the sleep state is entered, and the consumption current _IDD decreases.

Reset circuit 62 resets slave circuit 30 (internal circuit 34) when voltage _VCC of capacitor C1 falls below a predetermined reset threshold _VTH2 . After being reset, the internal circuit 34 executes the activation sequence again when the enable signal EN is asserted again.

The above is the configuration of the remote communication system 10. Next, the operation will be explained.

FIG. 3 is a waveform diagram at startup of the telecommunications system 10 of FIG. FIG. 3 representatively shows the operation of one of the plurality of slave circuits 30 of FIG. Prior to time _t10 , telecommunications system 10 has shut down and the DC voltage VDC applied to bus 12 by master circuit 20 is _0V . During shutdown, slave circuit 30 consumes zero current.

At time _t10 , the master circuit 20 applies _{a DC} voltage VDC of a predetermined voltage level (12V or 24V) to the bus 12, which triggers the activation of a plurality of slave circuits 30, and the entire telecommunication system 10. starts up.

As the DC voltage _VDC rises, the input voltage _VIN across the two input pins IN1 and IN2 rises accordingly. As a result, the capacitor C1 is charged by the rectifier circuit 32, and the power supply voltage _VCC generated across the capacitor C1 increases.

When the power supply voltage _VCC rises to the release threshold value _VTH1 at time _t11 , the enable signal EN is asserted by the activation monitoring circuit 60. FIG. Triggered by the assertion of the enable signal EN, the internal circuit 34 shifts to the activation sequence. When the internal circuit 34 shifts to the startup sequence, an operating current _IDD having a current amount _I1 flows. During the activation sequence, only the internal circuit 34 is operating in the slave circuit 30, and the other circuits (the receiving circuit 40 and the transmitting circuit 50) are _stopped . It is equal to the operating current _I1 of the internal circuit 34.

Since this operating current _IDD flows simultaneously in the plurality of slave circuits 30, the voltage drop _VDROP on the bus line 12 increases and the input voltage _VIN decreases.

FIG. 4 is an equivalent circuit diagram explaining the drop in the input voltage _VIN . A parasitic resistance (wiring resistance) R is included in the bus 12 . When the operating current _IDD flows through the slave circuit 30, a voltage drop occurs in the wiring resistance R. The magnitude of the voltage drop is small in the slave circuit 30 closer to the master circuit 20 and larger in the slave circuit 30 farther from the master circuit 20 .

Return to FIG. The slave circuit 30 consumes a current amount _I1 while the internal circuit 34 executes the start-up sequence. During the startup sequence, when the current _I1 consumed by the internal circuit 34 exceeds the charging current supplied from the rectifier circuit 32 to the capacitor C1, the power supply voltage _VCC of the capacitor C1 decreases over time.

The power supply voltage V _CC of capacitor C1 maintains a voltage level higher than the reset threshold V _TH2 until the start-up sequence is completed. In other words, the release threshold VTH1 is defined such that the voltage _VCC on capacitor _C1 does not fall below the reset threshold _VTH2 after the internal circuit 34 becomes active but before the start-up sequence is completed. , and the capacitance of the capacitor C1 is determined.

At time _t12 , when the activation sequence of the internal circuit 34 is completed, the slave circuit 30 (internal circuit 34) transitions to sleep state. The internal circuit 34 in sleep state consumes an amount of current I ₀ (<I ₁ ). Since the amount of current _I0 is small, the voltage drop V _DROP at the bus 12 is small, and the input voltage V _IN rises to near the DC voltage V _DC . As for the capacitor C1, since the charging current by the rectifier circuit 32 is larger than the operating current _I0 of the internal circuit 34, the voltage _VCC of the capacitor C1 rises with time.

The above is the startup operation of the remote communication system 10 . According to this remote communication system 10, in a system in which a plurality of slave circuits 30 are simultaneously activated, each slave circuit 30 can be reliably activated.

The advantages of telecommunication system 10 are made clear by contrast with comparative technologies. In the embodiment, the power supply voltage _VCC generated in the capacitor C1 is compared with the release threshold value _VTH1 and the reset threshold value _VTH2 . In contrast, in the comparison technique, when the input voltage _VIN exceeds the release threshold _VTH1 , the internal circuit 34 becomes active and the start-up sequence begins.

FIG. 5 is a waveform diagram of a startup sequence in the comparative technique. Prior to time _t20 , telecommunications system 10 has shut down and the DC voltage VDC applied to bus 12 by master circuit 20 is _0V . During shutdown, slave circuit 30 consumes zero current.

At time _t20 , the master circuit 20 applies a _DC voltage VDC of a predetermined voltage level (12 V or 24 V) to the bus line 12 . As the DC voltage _VDC rises, the input voltage _VIN across the two input pins IN1 and IN2 rises accordingly. When the input voltage _VIN reaches the release threshold _VTH1 , the internal circuit 34 becomes active and the start-up sequence starts. This time _t21 is earlier than time _t11 in FIG. 3, and therefore power supply voltage _VCC at time _t21 is lower than power supply voltage _VCC at time t11.

When the internal circuit 34 shifts to the start-up sequence, an operating current _IDD having a current amount _I1 flows, and the voltage drop in the bus 12 causes the input voltage _VIN to drop.

During the start-up sequence, a current of current amount _I1 flows through the internal circuit 34, so that the power supply voltage _VCC of the capacitor C1 decreases with time.

Although it takes a predetermined time to start up the internal circuit 34, the power supply voltage _VCC of the capacitor C1 drops to the reset threshold value _VTH2 at time _t22 before the start-up is completed. Then, the reset signal RST is asserted by the reset circuit 62, and the internal circuit 34 is initialized.

Then, when the input voltage _VIN rises and reaches the release threshold value _VTH1 again at time _t23 , the enable signal EN is asserted and the internal circuit 34 repeats the startup sequence again from the beginning. Then, at time _t24 before the startup sequence is completed, the power supply voltage _VCC drops to the reset threshold value _VTH2 , and the internal circuit 34 is reset again.

Thus, in the comparison technique, the internal circuit 34 may fail to start and fall into a state of repeated starting. This is because the power supply voltage _VCC of the capacitor C1 is low when starting the internal circuit 34. According to the embodiment, after the power supply voltage _VCC of the capacitor C1 becomes sufficiently high, the start-up sequence Since it starts, the internal circuit 34 can be reliably activated.

The telecommunication system 10 described above can be used for various purposes. For example, the slave circuit 30 is a temperature sensor, a vibration sensor, or the like centrally managed by the master circuit 20, and responds to control from the master circuit 20 and sends back the measured temperature and acceleration to the master circuit 20. Alternatively, the slave circuit 30 may be electrical or mechanical components such as relays and switches that are centrally managed by the master circuit 20 .

The embodiments are examples, and it should be noted that there are various modifications in the combination of each component and each processing process, and such modifications are included in the present disclosure and can constitute the scope of the present invention. It is understood by those skilled in the art.

(Appendix)
The following techniques are disclosed in this specification.

(Item 1)
A slave circuit connected to a master circuit via a bus,
a rectifier circuit having an input terminal connected to the bus and configured to charge a capacitor;
an activation monitoring circuit that compares the voltage of the capacitor with a predetermined release threshold and asserts an enable signal when the voltage of the capacitor exceeds the release threshold;
an internal circuit that becomes active after the enable signal is asserted and executes a predetermined startup sequence;
a slave circuit.

(Item 2)
further comprising a reset circuit for resetting the slave circuit when the voltage of the capacitor falls below a predetermined reset threshold;
2. According to item 1, the release threshold is defined such that the voltage of the capacitor does not fall below the reset threshold after the internal circuit becomes active but before the start-up sequence is completed. slave circuit.

(Item 3)
a capacitor pin connected to the output of the rectifier circuit;
3. A slave circuit according to item 1 or 2, wherein the capacitor is externally attached to the capacitor pin.

(Item 4)
4. A slave circuit according to any one of items 1 to 3, wherein the internal circuitry comprises a microcontroller.

(Item 5)
further comprising a transmission circuit that sinks current from the bus to change the voltage of the bus when transmitting a signal from the slave circuit to the master circuit;
5. The slave circuit according to any one of items 1 to 4, wherein the internal circuit is capable of communicating with the master circuit using the transmission circuit after activation is completed.

(Item 6)
6. The slave circuit according to any one of items 1 to 5, wherein the rectifier circuit includes a diode bridge circuit.

(Item 7)
7. A slave circuit according to any preceding item, wherein the bus bar includes a first wire and a second wire.

(Item 8)
8. The slave circuit according to any one of items 1 to 7, monolithically integrated on one semiconductor substrate.

(Item 9)
a master circuit;
a slave circuit according to any one of items 1 to 8;
a bus that connects the master circuit and the slave circuit;
A remote control system comprising:

W1 first wire IN1 first input pin W2 second wire IN2 second input pin 10 telecommunication system 12 busbar 20 master circuit 30 slave circuit 32 rectifier circuit 34 internal circuit 40 receiver circuit 50 transmitter circuit 60 activation monitor circuit 62 reset circuit

Claims

A slave circuit connected to a master circuit via a bus,
a rectifier circuit having an input terminal connected to the bus and configured to charge a capacitor;
an activation monitoring circuit that compares the voltage of the capacitor with a predetermined release threshold and asserts an enable signal when the voltage of the capacitor exceeds the release threshold;
an internal circuit that becomes active after the enable signal is asserted and executes a predetermined startup sequence;
a slave circuit.
further comprising a reset circuit for resetting the slave circuit when the voltage of the capacitor falls below a predetermined reset threshold;
2. The reset threshold of claim 1, wherein the release threshold is defined such that the voltage of the capacitor does not drop below the reset threshold after the internal circuitry becomes active and before the start-up sequence is completed. Described slave circuit.
a capacitor pin connected to the output of the rectifier circuit;
3. A slave circuit as claimed in claim 1 or 2, wherein the capacitor is externally attached to the capacitor pin.
A slave circuit according to any one of claims 1 to 3, wherein said internal circuit comprises a microcontroller.
further comprising a transmission circuit that sinks current from the bus to change the voltage of the bus when transmitting a signal from the slave circuit to the master circuit;
5. The slave circuit according to any one of claims 1 to 4, wherein said internal circuit is enabled to communicate with said master circuit using said transmission circuit after completion of activation.
The slave circuit according to any one of claims 1 to 5, wherein said rectifier circuit includes a diode bridge circuit.
The slave circuit according to any one of claims 1 to 6, wherein said bus bar includes a first wire and a second wire.
The slave circuit according to any one of claims 1 to 7, which is monolithically integrated on one semiconductor substrate.
a master circuit;
a slave circuit according to any one of claims 1 to 8;
a bus that connects the master circuit and the slave circuit;
A remote control system comprising: