WO2023024900A1 - 安全启动校验的方法及电子设备 - Google Patents

安全启动校验的方法及电子设备 Download PDF

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Publication number
WO2023024900A1
WO2023024900A1 PCT/CN2022/111184 CN2022111184W WO2023024900A1 WO 2023024900 A1 WO2023024900 A1 WO 2023024900A1 CN 2022111184 W CN2022111184 W CN 2022111184W WO 2023024900 A1 WO2023024900 A1 WO 2023024900A1
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WIPO (PCT)
Prior art keywords
data
hash value
target
step size
electronic device
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PCT/CN2022/111184
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English (en)
French (fr)
Inventor
任伟
胡慧锋
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华为技术有限公司
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Publication of WO2023024900A1 publication Critical patent/WO2023024900A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/51—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems at application loading time, e.g. accepting, rejecting, starting or inhibiting executable software based on integrity or source reliability
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files

Definitions

  • the present application relates to the field of electronic technology, and more specifically, relates to a method and electronic device for secure boot verification.
  • a secure boot function is usually added to the electronic device. In this way, after the electronic device is started, the software package of the software system of the electronic device will be verified for safe start. However, the efficiency of the secure boot verification of the existing electronic equipment is low, and the boot time is long, resulting in poor user experience.
  • the present application provides a secure startup verification method and an electronic device, which can improve the efficiency of the secure startup verification, further shorten the startup time of the electronic device, and improve user experience.
  • a method for secure boot verification is provided, the method is applied to electronic equipment, and the method includes: reading the target data in N times according to the target step size and the starting address of the target data Taken, the target data includes the data corresponding to the software package of the software system of the electronic device, and the N is greater than or equal to 2; after the data is read for the jth time, according to the jth group The data and the result of the j-1th hash value calculation are performed for the jth hash value calculation, wherein the j is an integer greater than 1 and less than or equal to N; according to the calculation result of the Nth hash value , perform a secure boot check.
  • the electronic device is an Internet of Things (Internet of Things, IoT) device.
  • IoT Internet of Things
  • the above j may also be an integer greater than or equal to 1 and less than or equal to N. At this time, when j is equal to 1, the result of the 0th hash value calculation is 0.
  • the calculation of the jth hash value can be started, and the time for reading the j+1th group of data and the calculation of the jth hash value can be realized.
  • the merging of the calculated time further reduces the waiting time of the electronic device, improves the efficiency of the security start-up inspection, reduces the start-up time of the electronic device, and improves the user experience.
  • the electronic device includes a flash memory controller, and reading the target data N times according to the target step size and the start address of the target data includes : According to the step size of the flash memory controller, the target step size and the start address of the target data, determine N start address sets, each start address set in the N start address sets Including n starting addresses, the n being the ratio of the target step size to the step size of the flash controller; controlling the flash controller according to the jth starting address set and the step of the flash controller long, read the jth group of data in n times.
  • the electronic device includes a hash calculation module, and after the data is read for the jth time, according to the jth group of data read for the jth time and the As a result of the j-1 hash value calculation, performing the jth hash value calculation includes: after the flash memory controller performs the jth data reading, controlling the hash calculation module according to the The jth set of data read j times and the result of the j-1th hash value calculation are performed for the jth hash value calculation.
  • the hash calculation module can start to calculate the jth hash value, and realize the time and time for reading the j+1th group of data
  • the combination of the j-th hash value calculation time reduces the waiting time of the electronic device, improves the efficiency of the security startup inspection, reduces the startup time of the electronic device, and improves the user experience.
  • the method further includes: adjusting the target step size so that the first time is greater than the second time, and the first time includes the jth data read Take the required time, the second time includes the time required for the jth hash value calculation.
  • the target step size so that the time required for the j-th data read is greater than the time required for the j-th hash value calculation, it is ensured that during the process of reading the j+1 group of data, the j-th data can be completed Hash calculation of group data. Thereby, the waiting time of the electronic equipment is better reduced, the efficiency of the security startup inspection is improved, the startup time of the electronic equipment is reduced, and the user experience is improved.
  • performing the secure boot verification according to the calculation result of the Nth hash value includes: obtaining a target hash value, the target hash value being the The hash value configured by the data corresponding to the software package of the software system; by comparing the calculation result of the target hash value and the Nth hash value, a secure boot verification is performed.
  • performing the secure boot verification by comparing the calculation result of the target hash value and the Nth hash value includes: In the case where the hash value is consistent with the calculation result of the Nth hash value, the security boot check is passed; or, in the case where the target hash value is inconsistent with the calculation result of the Nth hash value , the secure boot check fails.
  • a method for secure boot verification is provided, the method is applied to electronic equipment, and the method includes: reading the first group of data from the target data according to the target step size and the starting address of the target data , the target data includes data corresponding to the software package of the software system of the electronic device; according to the first set of data, the first hash value calculation is performed, and, according to the target step size and the target data start address, read the second set of data from the target data, the second set of data and the first set of data are different data in the target data; according to the second set of data and the set Perform a second hash value calculation based on the result of the first hash value calculation; perform a security boot verification based on the second hash value calculation result.
  • the electronic device is an IoT device.
  • the first hash value calculation of the first set of data can be started, so as to realize the time of reading the second set of data and the calculation of the first set of data
  • the combination of the time for the first hash value calculation further reduces the waiting time of the electronic device, improves the efficiency of the security startup inspection, reduces the startup time of the electronic device, and improves the user experience.
  • the electronic device includes a flash memory controller, and reading the first set of data from the target data according to the target step size and the start address of the target data includes: According to the step size of the flash memory controller, the target step size and the start address of the target data, determine a first start address set, the first start address set includes n start addresses, and the n is The ratio of the target step size to the step size of the flash controller; control the flash controller to divide n times from the target data according to the first start address set and the step size of the flash controller Read the first set of data.
  • reading the second set of data from the target data according to the target step size and the start address of the target data includes: according to the The step size of the flash memory controller, the target step size and the start address of the target data determine a second start address set, the second start address set includes n start addresses, and the second start address set The start address set is different from the first start address set; the flash controller is controlled to read the target data in n times according to the second start address set and the step size of the flash controller Describe the second set of data.
  • the electronic device includes a hash calculation module, and performing the first hash value calculation according to the first set of data includes: controlling the hash value
  • the calculation module performs a first hash value calculation according to the first set of data; and performs a second hash value calculation according to the second set of data and the result of the first hash value calculation
  • the method includes: controlling the hash calculation module to perform a second hash value calculation according to the second set of data and the result of the first hash value calculation.
  • the hash calculation module can start to calculate the first hash value of the first set of data, and realize the time when the second set of data will be read Combined with the time for calculating the first hash value of the first set of data, the waiting time of the electronic device is reduced, the efficiency of the security startup inspection is improved, the startup time of the electronic device is reduced, and the user experience is improved.
  • the method further includes: adjusting the target step size so that the first time is greater than the second time, and the first time includes reading the second group The time required for the data, the second time includes the time required for the first hash value calculation.
  • the target step size so that the time required to read the second set of data is greater than the time required for the second hash value calculation, it is ensured that the first set of data can be completed during the process of reading the second set of data hash value calculation.
  • the waiting time of the electronic equipment is better reduced, the efficiency of the security startup inspection is improved, the startup time of the electronic equipment is reduced, and the user experience is improved.
  • performing the secure boot verification according to the calculation result of the second hash value includes: obtaining a target hash value, the target hash value being the The hash value configured by the data corresponding to the software package of the software system; by comparing the calculation result of the target hash value and the second hash value, a secure boot verification is performed.
  • performing the secure boot verification by comparing the calculation result of the target hash value and the second hash value includes: In the case that the hash value is consistent with the calculation result of the second hash value, the security boot verification is passed; or, in the case that the calculation result of the target hash value is inconsistent with the second hash value , the secure boot check fails.
  • an electronic device including: one or more processors; one or more memories; one or more computer programs are stored in the one or more memories, and the one or more computer programs include instructions , when the instruction is executed by one or more processors, the method for secure boot verification as described in the first aspect and any possible implementation manner thereof is executed.
  • the electronic device is an IoT device.
  • a computer-readable storage medium including computer instructions, and when the computer instructions are run on an electronic device, the electronic device executes the method described in the first aspect and any possible implementation thereof.
  • a chip including at least one processor and an interface circuit, the interface circuit is used to provide program instructions or data for the at least one processor, and the at least one processor is used to execute the program instructions , so as to implement the method for secure boot verification as described in the first aspect and any possible implementation manner thereof.
  • a computer program product including computer instructions.
  • the secure boot verification as described in the first aspect and any possible implementation thereof method is executed.
  • FIG. 1 is a schematic structural diagram of an example of an electronic device provided by an embodiment of the present application.
  • Fig. 2 is a schematic structural diagram of another example of electronic equipment provided by the embodiment of the present application.
  • Fig. 3 is a schematic diagram of a software structure of an electronic device provided by an embodiment of the present application.
  • Fig. 4 is a schematic flowchart of a method for secure boot verification provided by an embodiment of the present application.
  • FIG. 5 is a schematic flowchart of another example of a method for secure boot verification provided by an embodiment of the present application.
  • Fig. 6 is a schematic flowchart of another example of a method for secure boot verification provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of another example of electronic equipment provided by the embodiment of the present application.
  • the electronic equipment involved in the embodiments of the present application may refer to user equipment, access terminal, subscriber unit, subscriber station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent or user device.
  • the terminal equipment can also be a cellular phone, a cordless phone, a Session Initiation Protocol (Session Initiation Protocol, SIP) phone, a wireless local loop (Wireless Local Loop, WLL) station, a personal digital processing (Personal Digital Assistant, PDA), a wireless communication Functional handheld devices, computing devices or other processing devices connected to wireless modems, in-vehicle devices, wearable devices (such as Bluetooth headsets or smart watches), home devices (such as smart door locks or smart peepholes), terminals in future 5G networks Devices or terminal devices in the future evolved Public Land Mobile Network (PLMN), etc., are not limited in this embodiment of the present application.
  • FIG. 1 shows a schematic structural diagram of an electronic device 100 provided by an embodiment of the present application.
  • the electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (universal serial bus, USB) interface 130, a charging management module 140, a power management module 141, battery 142, antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, audio module 170, speaker 170A, receiver 170B, microphone 170C, earphone jack 170D, sensor module 180, button 190, motor 191, indicator 192, A camera 193, a display screen 194, and a subscriber identification module (subscriber identification module, SIM) card interface 195, etc.
  • SIM subscriber identification module
  • the sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, bone conduction sensor 180M, etc.
  • the structure illustrated in the embodiment of the present application does not constitute a specific limitation on the electronic device 100 .
  • the electronic device 100 may include more or fewer components than shown in the figure, or combine certain components, or separate certain components, or arrange different components.
  • the illustrated components can be realized in hardware, software or a combination of software and hardware.
  • the processor 110 may include one or more processing units, for example: the processor 110 may include an application processor (application processor, AP), a modem processor, a graphics processing unit (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), controller, memory, video codec, digital signal processor (digital signal processor, DSP), baseband processor, and/or neural network processor (neural-network processing unit, NPU) wait. Wherein, different processing units may be independent devices, or may be integrated in one or more processors.
  • application processor application processor, AP
  • modem processor graphics processing unit
  • GPU graphics processing unit
  • image signal processor image signal processor
  • ISP image signal processor
  • controller memory
  • video codec digital signal processor
  • DSP digital signal processor
  • baseband processor baseband processor
  • neural network processor neural-network processing unit, NPU
  • the controller may be the nerve center and command center of the electronic device 100 .
  • the controller can generate an operation control signal according to the instruction opcode and timing signal, and complete the control of fetching and executing the instruction.
  • a memory may also be provided in the processor 110 for storing instructions and data.
  • the memory in processor 110 is a cache memory.
  • the memory may hold instructions or data that the processor 110 has just used or recycled. If the processor 110 needs to use the instruction or data again, it can be called directly from the memory. Repeated access is avoided, and the waiting time of the processor 110 is reduced, thus improving the efficiency of the system.
  • processor 110 may include one or more interfaces.
  • the interface may include an integrated circuit (inter-integrated circuit, I2C) interface, an integrated circuit built-in audio (inter-integrated circuit sound, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous transmitter (universal asynchronous receiver/transmitter, UART) interface, mobile industry processor interface (mobile industry processor interface, MIPI), general-purpose input and output (general-purpose input/output, GPIO) interface, subscriber identity module (subscriber identity module, SIM) interface, and /or universal serial bus (universal serial bus, USB) interface, etc.
  • I2C integrated circuit
  • I2S integrated circuit built-in audio
  • PCM pulse code modulation
  • PCM pulse code modulation
  • UART universal asynchronous transmitter
  • MIPI mobile industry processor interface
  • GPIO general-purpose input and output
  • subscriber identity module subscriber identity module
  • SIM subscriber identity module
  • USB universal serial bus
  • the I2C interface is a bidirectional synchronous serial bus, including a serial data line (serial data line, SDA) and a serial clock line (derail clock line, SCL).
  • the I2S interface can be used for audio communication.
  • processor 110 may include multiple sets of I2S buses.
  • the processor 110 may be coupled to the audio module 170 through an I2S bus to implement communication between the processor 110 and the audio module 170 .
  • the PCM interface can also be used for audio communication, sampling, quantizing and encoding the analog signal.
  • the audio module 170 and the wireless communication module 160 may be coupled through a PCM bus interface.
  • the UART interface is a universal serial data bus used for asynchronous communication.
  • the bus can be a bidirectional communication bus.
  • a UART interface is generally used to connect the processor 110 and the wireless communication module 160 .
  • the MIPI interface can be used to connect the processor 110 with peripheral devices such as the display screen 194 and the camera 193 .
  • the GPIO interface can be configured by software.
  • the GPIO interface can be configured as a control signal or as a data signal.
  • the GPIO interface can be used to connect the processor 110 with the camera 193 , the display screen 194 , the wireless communication module 160 , the audio module 170 , the sensor module 180 and so on.
  • the USB interface 130 is an interface conforming to the USB standard specification, specifically, it can be a Mini USB interface, a Micro USB interface, a USB Type C interface, and the like.
  • the USB interface 130 can be used to connect a charger to charge the electronic device 100 , and can also be used to transmit data between the electronic device 100 and peripheral devices.
  • the interface connection relationship between the modules shown in the embodiment of the present application is only a schematic illustration, and does not constitute a structural limitation of the electronic device 100 .
  • the electronic device 100 may also adopt different interface connection manners in the foregoing embodiments, or a combination of multiple interface connection manners.
  • the charging management module 140 is configured to receive a charging input from a charger.
  • the charger may be a wireless charger or a wired charger.
  • the charging management module 140 can receive charging input from the wired charger through the USB interface 130 .
  • the charging management module 140 may receive a wireless charging input through a wireless charging coil of the electronic device 100 .
  • the charging management module 140 is charging the battery 142 , it can also provide power for electronic devices through the power management module 141 .
  • the power management module 141 is used for connecting the battery 142 , the charging management module 140 and the processor 110 .
  • the wireless communication function of the electronic device 100 can be realized by the antenna 1 , the antenna 2 , the mobile communication module 150 , the wireless communication module 160 , a modem processor, a baseband processor, and the like.
  • the mobile communication module 150 can provide wireless communication solutions including 2G/3G/4G/5G applied on the electronic device 100 .
  • the modem processor may be a stand-alone device. In some other embodiments, the modem processor may be independent from the processor 110, and be set in the same device as the mobile communication module 150 or other functional modules.
  • the wireless communication module 160 can provide wireless local area networks (wireless local area networks, WLAN) (such as wireless fidelity (Wireless Fidelity, Wi-Fi) network), bluetooth (bluetooth, BT), global navigation satellite, etc. applied on the electronic device 100.
  • WLAN wireless local area networks
  • System global navigation satellite system, GNSS
  • frequency modulation frequency modulation, FM
  • near field communication technology near field communication, NFC
  • infrared technology infrared, IR
  • the antenna 1 of the electronic device 100 is coupled to the mobile communication module 150, and the antenna 2 is coupled to the wireless communication module 160, so that the electronic device 100 can communicate with the network and other devices through wireless communication technology.
  • the electronic device 100 realizes the display function through the GPU, the display screen 194 , and the application processor.
  • the GPU is a microprocessor for image processing, and is connected to the display screen 194 and the application processor. GPUs are used to perform mathematical and geometric calculations for graphics rendering.
  • Processor 110 may include one or more GPUs that execute program instructions to generate or change display information.
  • the display screen 194 is used to display images, videos and the like.
  • the display screen 194 includes a display panel.
  • the display panel can be a liquid crystal display (LCD), or an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode, or an active-matrix organic light-emitting diode (active-matrix organic light-emitting diode).
  • LCD liquid crystal display
  • OLED organic light-emitting diode
  • AMOLED organic light emitting diode
  • flexible light-emitting diode flexible light-emitting diode (flex light-emitting diode, FLED), Miniled, MicroLed, Micro-oLed or quantum dot light emitting diodes (quantum dot light emitting diodes, QLED) and other materials. Fabricated display panels.
  • the electronic device 100 may include 1 or N display screens 194 , where N is a positive integer greater than 1.
  • the electronic device 100 can realize the shooting function through the ISP, the camera 193 , the video codec, the GPU, the display screen 194 and the application processor.
  • the external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, so as to expand the storage capacity of the electronic device 100.
  • the internal memory 121 may be used to store computer-executable program codes including instructions.
  • the processor 110 executes various functional applications and data processing of the electronic device 100 by executing instructions stored in the internal memory 121 .
  • the electronic device 100 can implement audio functions through the audio module 170 , the speaker 170A, the receiver 170B, the microphone 170C, the earphone interface 170D, and the application processor. Such as music playback, recording, etc.
  • the audio module 170 is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signal.
  • Speaker 170A also referred to as a "horn” is used to convert audio electrical signals into sound signals.
  • Receiver 170B also called “earpiece”, is used to convert audio electrical signals into sound signals.
  • the microphone 170C also called “microphone” or “microphone” is used to convert sound signals into electrical signals.
  • the earphone interface 170D is used for connecting wired earphones.
  • the pressure sensor 180A is used to sense the pressure signal and convert the pressure signal into an electrical signal.
  • pressure sensor 180A may be disposed on display screen 194 .
  • the gyro sensor 180B can be used to determine the motion posture of the electronic device 100 .
  • the air pressure sensor 180C is used to measure air pressure.
  • the electronic device 100 calculates the altitude based on the air pressure value measured by the air pressure sensor 180C to assist positioning and navigation.
  • the acceleration sensor 180E can detect the acceleration of the electronic device 100 in various directions (generally three axes).
  • the distance sensor 180F is used to measure the distance.
  • the fingerprint sensor 180H is used to collect fingerprints.
  • Touch sensor 180K also known as "touch panel”.
  • the touch sensor 180K can be disposed on the display screen 194, and the touch sensor 180K and the display screen 194 form a touch screen, also called a “touch screen”.
  • the bone conduction sensor 180M can acquire vibration signals.
  • the bone conduction sensor 180M can acquire the vibration signal of the vibrating bone mass of the human voice.
  • the bone conduction sensor 180M can also contact the human pulse and receive the blood pressure beating signal.
  • the keys 190 include a power key, a volume key and the like.
  • the motor 191 can generate a vibrating reminder.
  • the indicator 192 can be an indicator light, and can be used to indicate charging status, power change, and can also be used to indicate messages, missed calls, notifications, and the like.
  • the SIM card interface 195 is used for connecting a SIM card.
  • FIG. 2 shows a schematic structural diagram of another example of the electronic device 100 provided by the embodiment of the present application.
  • the electronic device 100 includes a memory 210 and a processor 220 .
  • the memory 210 is used to store computer programs, which include application programs, operating system programs, operating system boot programs, and the like.
  • the processor 220 is used to read the computer program in the memory 210, and then execute the method defined by the computer program, for example, the processor 220 reads the operating system boot program to guide the operation of the operating system on the electronic device 100, or reads the operating system
  • the program thus runs the operating system on the electronic device 100 and realizes various functions of the operating system, or reads one or more application programs, thereby running applications on the electronic device 100 .
  • the memory 210 also stores other data other than the computer program.
  • Other data may include data generated after the operating system program or application program is run.
  • the data includes system data (such as operating system configuration parameters, operating system software package correspondence data, etc.) and user data.
  • the storage 210 generally includes internal memory and external storage.
  • Memory can be random access memory (random access memory, RAM), read-only memory (read-only memory, ROM), and cache (cache).
  • the external memory can be a hard disk, a CD, a universal serial bus (universal serial bus, USB) disk, a floppy disk, or a tape drive.
  • Computer programs such as application programs can be stored in external memory, the processor will load the computer program from the external memory into the internal memory before executing the processing, and the operating system can be stored in the internal memory.
  • the memory can store computer-executable program code, which includes instructions.
  • the processor 220 executes various functional applications and data processing of the electronic device 100 by executing instructions stored in the memory.
  • the boot program of the operating system contains a computer program that can implement the secure boot verification method provided by the embodiment of the present application, so that the processor 220 starts the security of the electronic device 100 after reading the boot program of the operating system. Start the verification function.
  • the electronic device 100 may further include an interface circuit for providing the memory 210 with the operating system boot program.
  • the interface circuit may use a transceiver device such as but not limited to a transceiver to implement communication between the device and other devices or a communication network.
  • the interface circuit can also be, for example, a communication interface.
  • the electronic device 100 may further include a flash memory (flash) controller 230 for storing data related to software packages of the software system of the electronic device 100 .
  • flash memory controller 230 may be an independent device, or may be integrated in the memory 210 .
  • the electronic device 100 may further include a hash calculation module 240 for performing hash value calculation on the data stored in the flash memory controller 230 related to the software package of the software system of the electronic device 200 .
  • the hash calculation module 240 may be an independent device, or may be integrated in the processor 220 .
  • various components of the electronic device 100 shown in FIG. 2 are connected together through a bus.
  • the structure of the electronic device 100 shown in FIG. 2 illustrated in the embodiment of the present application does not constitute a specific limitation on the electronic device 100 .
  • the electronic device 100 may include more components than those shown in FIG. 2 .
  • the electronic device 100 may also include a display module, a power module, a sensor module, an audio module, a charging management module, a communication module, a battery, an indicator light, an input module (such as a touch panel, a physical keyboard, function keys, etc.) and the like.
  • the electronic device 100 may include some components shown in FIG. 2 combined, or some components shown in FIG. 2 separated, or arranged differently.
  • the illustrated components can be realized in hardware, software or a combination of software and hardware.
  • the software system of the electronic device 100 described in FIG. 1 or FIG. 2 may adopt a layered architecture, an event-driven architecture, a micro-kernel architecture, a micro-service architecture, or a cloud architecture.
  • the software system can be system, system or system etc.
  • FIG. 3 is a block diagram of the software structure of the electronic device 100 according to the embodiment of the present application.
  • the layered architecture divides the software into several layers, and each layer has a clear role and division of labor. Layers communicate through software interfaces.
  • the Android system is divided into four layers, which are application program layer, application program framework layer, system library, and kernel layer from top to bottom.
  • the application layer can consist of a series of application packages.
  • the application package may include applications such as camera, gallery, calendar, call, map, navigation, WLAN, Bluetooth, music, video, and short message.
  • the application framework layer provides an application programming interface (application programming interface, API) and a programming framework for applications in the application layer.
  • the application framework layer includes some predefined functions.
  • the application framework layer can include window manager, content provider, view system, phone manager, resource manager, notification manager, etc.
  • a window manager is used to manage window programs.
  • the window manager can get the size of the display screen, determine whether there is a status bar, lock the screen, capture the screen, etc.
  • Content providers are used to store and retrieve data and make it accessible to applications.
  • Said data may include video, images, audio, calls made and received, browsing history and bookmarks, phonebook, etc.
  • the view system includes visual controls, such as controls for displaying text, controls for displaying pictures, and so on.
  • the view system can be used to build applications.
  • a display interface can consist of one or more views.
  • a display interface including a text message notification icon may include a view for displaying text and a view for displaying pictures.
  • the phone manager is used to provide communication functions of the electronic device 100 . For example, the management of call status (including connected, hung up, etc.).
  • the resource manager provides various resources for the application, such as localized strings, icons, pictures, layout files, video files, and so on.
  • the notification manager enables the application to display notification information in the status bar, which can be used to convey notification-type messages, and can automatically disappear after a short stay without user interaction.
  • the notification manager is used to notify the download completion, message reminder, etc.
  • the notification manager can also be a notification that appears on the top status bar of the system in the form of a chart or scroll bar text, such as a notification of an application running in the background, or a notification that appears on the screen in the form of a dialog window.
  • prompting text information in the status bar issuing a prompt sound, vibrating the electronic device, and flashing the indicator light, etc.
  • the application layer and the application framework layer run in virtual machines.
  • the virtual machine executes the java files of the application program layer and the application program framework layer as binary files.
  • the virtual machine is used to perform functions such as object life cycle management, stack management, thread management, security and exception management, and garbage collection.
  • a system library can include multiple function modules. For example: surface manager (surface manager), media library (media libraries), 3D graphics processing library (eg: OpenGL ES), 2D graphics engine (eg: SGL), etc.
  • the surface manager is used to manage the display subsystem and provides the fusion of 2D and 3D layers for multiple applications.
  • the media library supports playback and recording of various commonly used audio and video formats, as well as still image files, etc.
  • the media library can support a variety of audio and video encoding formats, such as: MPEG4, H.264, MP3, AAC, AMR, JPG, PNG, etc.
  • the 3D graphics processing library is used to implement 3D graphics drawing, image rendering, compositing, and layer processing, etc.
  • 2D graphics engine is a drawing engine for 2D drawing.
  • the kernel layer is the layer between hardware and software.
  • the kernel layer includes at least a display driver, a camera driver, an audio driver, and a sensor driver.
  • the processor of the electronic device may support multiple cores, such as 4 cores or 8 cores. At this time, the processor may be called a multi-core processor.
  • the operating system of the electronic device may also support multi-core.
  • the operating system may be called a multi-core operating system.
  • a multi-core processor or a multi-core operating system can execute multiple threads in parallel. That is, multiple threads can execute on multiple processors during the same time period.
  • a thread is the smallest unit that an operating system can perform operation scheduling. It is included in the process and is the actual operating unit in the process.
  • a thread refers to a single sequential flow of control in a process. Multiple threads can run concurrently in a process, and each thread performs different tasks in parallel. Multiple threads in the same process will share all system resources in the process, such as virtual address space, file descriptors, signal processing, and so on.
  • a process is a running activity of a program in a computer on a certain data set. It is the basic unit for resource allocation and scheduling of the system and the basis of the operating system structure.
  • a secure boot function is usually added to the electronic device. In this way, after the electronic device is started, it will verify the integrity of the software package of the software system of the electronic device. However, the efficiency of the secure boot verification of the existing electronic equipment is low, and the boot time is long, resulting in poor user experience.
  • the embodiment of the present application provides a method for secure boot verification, which can be implemented in a single-threaded running scenario.
  • the method can improve the efficiency of safe startup inspection, reduce the startup time of electronic equipment, and improve user experience.
  • the method for secure boot verification can not only be applied to IoT devices, such as smart door locks, smart cat-eye Bluetooth headsets, etc., but also can be applied to other electronic devices other than IoT devices .
  • the execution body of the method for secure boot verification may be the processor of the electronic device.
  • the processor may call an operating system boot program of the electronic device such as a universal boot loader (uboot) to implement the secure boot verification method.
  • uboot universal boot loader
  • FIG. 4 is a schematic flowchart of a method 300 for secure boot verification provided by an embodiment of the present application.
  • the execution subject of the method 300 may be the processor 110 shown in FIG. 1 or the processor 220 shown in FIG. 2 .
  • the flash memory controller involved in the method 300 may be the flash memory controller 230 shown in FIG. 2 .
  • the hash calculation module involved in the method 300 may be the hash calculation module 240 shown in FIG. 2 .
  • the memory involved in the method 300 may be the memory 210 shown in FIG. 2 .
  • the method 300 includes S301 to S315.
  • S301 to S315 will be specifically introduced.
  • the processor data reading parameters include the step size of the processor data reading, the starting address and the data volume of all data.
  • the step size of data read by the processor represents the amount of data read each time.
  • the step size for reading data by the processor is 64k, that is, the processor reads 64k of data each time.
  • the step size of reading the number of processors is 128k, that is, the processor reads 128k of data each time.
  • the embodiment of the present application does not limit the unit of the data amount.
  • the unit of the data amount may be kilobyte (k), bit (bit), or mega (M).
  • the starting address of data read by the processor means the starting address of the data read by the processor in the storage space.
  • the step size and start address of processor data reading may be preset.
  • N is greater than or equal to 2.
  • S302. Determine the reading parameters of the data read by the flash memory controller according to the step size of the data read by the flash memory controller and the processor data reading parameters.
  • the flash controller Since the step size for reading data of the flash controller is a hardware parameter of the flash controller, the flash controller does not need to obtain the step size for reading data of the flash controller. Then the read parameter of the flash memory controller to read data includes the start address of the flash memory controller to read data.
  • the step size of data read by the flash memory controller may be acquired in advance or acquired now, which is not limited in this application.
  • the flash memory controller needs to read the amount of data read by the processor once in n times. In this way, for the flash memory controller, all data needs to be read N ⁇ n times. Therefore, the read parameters determined in S302 for the flash controller to read data include the start address of the flash controller for N ⁇ n times of data reading.
  • the starting address of flash memory controller data reading is divided into N groups, and each group includes n starting addresses of data reading, and the starting addresses of n data reading included in each group are respectively It is the starting address of n data reads by the flash memory controller.
  • the starting addresses for data reading of the flash memory controller may be divided into N groups, or may not be divided into N groups, which is not limited in this embodiment of the present application.
  • n is determined according to the step size of the flash memory controller data read and the step size of the processor data read. Specifically, n satisfies the following formula (1):
  • M1 is the step size of data read by the processor
  • M2 is the step size of data read by the flash memory controller
  • start addresses for reading data of N groups of flash memory controllers may be determined once, or the starting addresses for reading data of N groups of flash memory controllers may be determined N times respectively.
  • the starting address L i of the i-th data read of the flash memory controller satisfies the following formula:
  • the start address of group flash memory controller data reading; ...; L (N-1) ⁇ n+1 , L (N-1) ⁇ n+2 , ..., L (N-1) ⁇ n+n They are the starting addresses for reading data of the flash memory controller of group N respectively.
  • the work of the flash memory controller can be controlled through multiple registers.
  • Each register in the plurality of registers plays a different role, that is, each register has a different purpose.
  • the operation of the flash memory controller can be controlled through four registers such as a first register, a second register and a third register.
  • the first register is used for storing the starting address of the flash memory controller for reading data.
  • the second register is used to control the flash controller to start reading data.
  • the third register is used to monitor the working state of the flash memory controller, for example, the third register can monitor whether the data of the flash memory controller has been read completely and/or the step size of accumulated data read by the flash memory controller. When the data of the flash memory controller has been read, the third register is in an idle state.
  • registers may be provided in the processor.
  • mapping relationship involved in this embodiment of the present application may be predefined.
  • S303 may be performed N times.
  • the read parameter of the flash memory controller to read data includes a set of start addresses for reading data of the flash memory controller.
  • S303 may be performed only once.
  • the read parameters of the flash memory controller to read data include N groups of start addresses for reading data of the flash memory controller.
  • writing the read parameter of the data read by the flash memory controller into the first target address means writing the read parameter of the data read by the flash memory controller into a register corresponding to the first target address, that is, the first register.
  • the flash memory controller can obtain the read parameters of the flash memory controller data read.
  • writing the start command into the second target address means writing the start command into a register corresponding to the second target address, that is, the second register.
  • the flash memory controller can start to read data, and the specific process is described in S305.
  • the flash memory controller divides Read the jth group of data n times.
  • the amount of data read by the flash memory controller each time is the data amount corresponding to the step size of the data read by the flash memory controller
  • the total data amount read by the flash memory controller n times is the data amount corresponding to the step size of the processor data read.
  • the third register has been monitoring the read status of the flash memory controller.
  • the processor keeps cyclically accessing the third register so as to execute S306.
  • S306 may be implemented by judging whether the third register is in an idle state. If the third register is in an idle state, execute S307. If the third register is not in the idle state, continue to execute S306 until it is determined that the third register is in the idle state.
  • the flash memory controller may first cache the jth group of data to a direct memory access (direct memory access, DMA) controller, and then the DMA controller copies the jth group of data into RAM, and notifies the processor that the The address and length of the jth group of data in RAM.
  • DMA direct memory access
  • the work of the hash calculation module can also be controlled through multiple registers.
  • Each register in the plurality of registers plays a different role, that is, each register has a different purpose.
  • the operation of the flash memory controller can be controlled through two registers such as the fourth register and the fifth register.
  • the fourth register is used to store the address of the jth group of data in the RAM and the length to be written into the third target address.
  • the fifth register is used to monitor the working status of the hash calculation module, for example, the fifth register can monitor whether the hash value of the hash calculation module has been calculated. When the hash value of the hash calculation module has been calculated, the fifth register is in an idle state.
  • writing the address and length of the jth group of data in the RAM into the third target address means writing the address and length of the jth group of data in the RAM into the register corresponding to the third target address, that is, the fourth register.
  • the hash calculation module can obtain the jth group of data from the RAM, that is, S309.
  • the hash calculation module After the hash calculation module reads the jth group of data, it is judged whether the hash calculation module has completed the last hash value calculation, ie S310.
  • S310 may be implemented by judging whether the fifth register is in an idle state. When the fifth register is in an idle state, start to calculate the jth hash value, that is, execute S311 and S312. If the fifth register is not in the idle state, continue to execute S310 until it is determined that the fifth register is in the idle state.
  • S310 may not be executed.
  • the j-1th hash value calculation result is acquired, ie S311.
  • the hash value calculation data performed by the hash calculation module each time includes two parts: one part is the calculation result of the j-1th hash value, and the other part is the jth group of data.
  • the data volume of the jth group of data corresponds to the data volume of n data reads by the flash memory controller, that is, the data volume of one data read by the processor (ie, the data volume corresponding to the step size of the processor's data read).
  • S313 can also be executed to determine whether the flash memory controller continues to read the j+1th group data or end the operation of reading data.
  • S313 may be implemented by judging whether the step size of the accumulated data read by the flash memory controller reaches the length of the data volume of all the data described in S301.
  • the step size of the accumulative data read by the flash memory controller may be obtained through the third register to acquire the step size of the accumulative data read by the flash memory controller.
  • the flash memory controller starts to read the j+1th group of data, that is, executes S305 to S308.
  • the hash value calculation module starts the j+1th hash value calculation, that is, executes S309 to S312, wherein j in S309 to S312 is j plus 1 in the previous round.
  • the flash memory controller completes the reading of all data in N ⁇ n times, and transfers the data volume of n times of reading to the RAM.
  • the hash value module completes the hash value calculation of all data in N times.
  • the first time in order to better reduce the waiting time of the processor, improve the efficiency of the security startup check, and reduce the startup time of the electronic device, the first time can be realized by adjusting the step size of the processor data reading. greater than the second time.
  • the first time includes the time when the flash memory controller reads the jth group of data from the third register and the time when the flash memory controller loads the jth group of data into the RAM.
  • the second time includes the time when the hash calculation module calculates the hash value of the jth group of data.
  • the hash calculation module can complete the calculation of the jth hash value during the process of the flash memory controller reading the j+1th group of data (that is, the amount of data read by the processor at one time) from the memory. Therefore, the hash calculation module can start the calculation of the j+1th hash value without waiting time.
  • control hash value calculation module when the control hash value calculation module starts to calculate the hash value, it is not necessary to consider whether the data that needs to calculate the hash value has been loaded into RAM by the flash memory controller, that is, when the control hash value calculation module After the module starts to calculate the hash value, the operation of controlling the hash value calculation module to calculate the hash value no longer depends on the operation of the flash memory controller, that is, the operation of the flash memory controller and the operation of the hash value calculation module are two parallel and independent operation.
  • signature verification can also be performed. For details, refer to the description in S315.
  • the calculation result of the Nth hash value is matched with the target hash value.
  • the target hash value is the hash value configured by the data corresponding to the software package of the software system.
  • the matching of the calculation result of the Nth hash value with the target hash value may be interpreted as passing the secure boot verification or passing the signature verification.
  • a first preset operation may be performed, and the first preset operation is to pass the security boot verification or to pass the signature verification. corresponding actions, such as starting an electronic device.
  • the mismatch between the calculation result of the Nth hash value and the target hash value may be interpreted as a failure (or failure) of the secure boot verification or a failure (or failure) of the signature verification.
  • a second preset operation may be performed, and the second preset operation is that the secure boot verification fails (or does not pass) or the corresponding operation when the signature verification fails (or fails), for example, do not start the electronic device or use another secure boot verification method to re-verify.
  • the hash calculation module can start the jth hash value calculation, so as to realize the reading of the jth group of data by the flash memory controller
  • the combination of the time of +1 group of data and the time of the jth hash value calculation by the hash calculation module will not wait for the processor to completely complete all the data corresponding to the software package of the software system in the flash memory controller as in the existing solution
  • the hash calculation module can calculate the hash value of all the data corresponding to the software package, thereby reducing the waiting time of the processor, improving the efficiency of the security boot inspection, reducing the startup time of the electronic device, and improving the user experience.
  • Table 1 shows the time-consuming data reading through the method 300 and the existing solution for three cases of data to be read.
  • the step size of processor data reading is 128k
  • the step size of flash memory controller data reading is 2k.
  • the solution of method 300 has the following advantages: 1. For the same size of data to be read, it takes less time to perform secure boot verification through method 300 . 2. The optimization effect of the method 300 is above 90%. 3. The larger the amount of data to be read, the more time-consuming it is to perform the security boot verification in the existing solution, but the time-consuming to perform the security boot verification through the method 300 is basically stable.
  • the processing waiting time of other peripheral devices can also be merged to minimize the situation where the processor alone waits for a certain peripheral device to complete execution , improve the execution efficiency of the whole process.
  • peripheral devices may include encryption and decryption devices, data compression devices, etc., to implement hash calculation while reading and decrypting or hash calculation while reading and decompressing, so as to improve the execution efficiency of the whole process.
  • FIG. 5 is another example of a method 400 for secure boot verification provided by an embodiment of the present application.
  • the method 400 can be applied to electronic devices, such as but not limited to IoT devices.
  • the execution subject of the method 400 may be a processor or a processing unit of an electronic device.
  • the method 400 includes:
  • the target data includes the data corresponding to the software package of the software system of the electronic device, and the N is greater than or equal to 2.
  • the target step size may be the step size M1 of processor data reading described in the method 300 above.
  • the start address of the target data may be the start address of the processor data reading described in the method 300 above.
  • the electronic device includes a flash memory controller
  • reading the target data in N times according to the target step size and the start address of the target data includes: according to the flash memory controller
  • the step size, the target step size and the start address of the target data determine N start address sets, and each start address set in the N start address sets includes n start addresses, so Said n is the ratio of the target step size to the step size of the flash controller; the flash controller is controlled to divide n times the The jth group of data is read.
  • the flash memory controller for each data read in N times, the flash memory controller needs to read in n times. In this way, the flash memory controller needs to read the target data N ⁇ n times.
  • n starting addresses can be understood as the starting addresses of n data reads by the flash memory controller.
  • the N sets of starting addresses may be the starting addresses for reading data of the N groups of flash memory controllers described in the method 300 above.
  • the n start addresses included in each start address set in the N start address sets can be determined according to the above formula (2). That is, the first set of start addresses in the N set of start addresses includes the start addresses L 0 , L 1 , ..., L n of the first group of flash memory controller data read described above, and the second The starting address set includes the starting addresses L n+1 , L n+2 , ..., L 2n , ... of the second group of flash memory controller data reading described above, and the Nth starting address set includes The starting address L (N-1) ⁇ n+1 , L (N-1) ⁇ n+2 ,..., L (N-1) ⁇ n+n .
  • the flash memory controller can also load the jth group of data into RAM.
  • the above j may also be an integer greater than or equal to 1 and less than or equal to N. At this time, when j is equal to 1, the result of the 0th hash value calculation is 0.
  • S402 is not executed after the N times of data reading are completed in S401, but after the first data reading out of the N times of S401 is completed in S401. Therefore, in the process of reading the j+1th group of data, the calculation of the jth hash value can be started, and the time to read the j+1th group of data and the time to calculate the jth hash value can be realized merging, thereby reducing the waiting time of the electronic device, improving the efficiency of the security startup inspection, reducing the startup time of the electronic device, and improving the user experience.
  • the electronic device includes a hash calculation module, and after the j-time data reading, according to the j-th group of data read for the j-th time and the j-1th hash value calculation As a result, performing the jth hash value calculation includes: after the flash memory controller performs the jth data reading, controlling the hash calculation module according to the jth group of the jth read The data and the result of the j-1th hash value calculation are performed for the jth hash value calculation.
  • the hash calculation module may first read the jth group of data from the RAM, and then perform the jth hash value calculation.
  • the target hash value is obtained, and the target hash value is the hash value configured for the data corresponding to the software package of the software system; by comparing the target hash value with the Nth The calculation result of the hash value is used for secure boot verification.
  • the secure boot check passes; or, when the target hash value and the Nth hash value If the calculation results of the secondary hash values are inconsistent, the secure boot check fails.
  • the method 400 also includes:
  • FIG. 6 is another example of a method 500 for secure boot verification provided by an embodiment of the present application.
  • the method 500 can be applied to electronic devices, such as but not limited to IoT devices.
  • the subject of execution of the method 500 may be a processor or a processing unit of an electronic device.
  • the method 500 includes:
  • the target step size and the start address of the target data read a first group of data from the target data, where the target data includes data corresponding to a software package of the software system of the electronic device.
  • the target step size may be the step size M1 of processor data reading described in the method 300 above.
  • the start address of the target data may be the start address of the processor data reading described in the method 300 above.
  • the electronic device includes a flash memory controller
  • reading the first group of data from the target data according to the target step size and the start address of the target data includes: according to the step of the flash memory controller length, the target step size and the start address of the target data, determine the first start address set, the first start address set includes n start addresses, and the n is the target step size and the The ratio of the step size of the flash controller; controlling the flash controller to read the first set of data from the target data in n times according to the first set of starting addresses and the step size of the flash controller .
  • n starting addresses can be understood as the starting addresses of n data reads by the flash memory controller.
  • the flash memory controller can also load the first set of data into RAM.
  • S502. Perform a first hash value calculation according to the first set of data, and read a second set of data from the target data according to the target step size and the starting address of the target data, The second set of data and the first set of data are different data in the target data.
  • the electronic device includes a flash memory controller
  • reading the second group of data from the target data according to the target step size and the start address of the target data includes: according to the The step size of the flash memory controller, the target step size and the start address of the target data determine a second start address set, the second start address set includes n start addresses, and the second The starting address set is different from the first starting address set; the flash controller is controlled to read from the target data in n times according to the step size of the second starting address set and the flash controller The second set of data.
  • the n starting addresses respectively included in the first starting address set and the second starting address may be determined according to the above formula (2). That is, the first set of starting addresses includes the starting addresses L 0 , L 1 , ..., L n of the first group of flash memory controller data read described above, and the second starting address set includes the first set of starting addresses mentioned above.
  • the starting addresses L n+1 , L n+2 , . . . , L 2n for data reading of the two flash memory controllers.
  • the flash controller can also load the second set of data into RAM.
  • the electronic device includes a hash calculation module, and performing the first hash value calculation according to the first set of data includes: controlling the hash calculation module to calculate the hash value according to the first set of data Data, for the first hash value calculation.
  • the hash calculation module may first read the first set of data from the RAM, and then perform the first hash value calculation.
  • the electronic device includes a hash calculation module, and performing the second hash value calculation according to the second set of data and the result of the first hash value calculation includes: controlling The hash calculation module performs a second hash value calculation according to the second set of data and the result of the first hash value calculation.
  • the hash calculation module can also first read the second set of data from the RAM, and then perform the second hash value calculation.
  • the target hash value is obtained, and the target hash value is the hash value configured for the data corresponding to the software package of the software system; by comparing the target hash value with the second The calculation result of the hash value is used for secure boot verification.
  • the secure boot check passes; or, when the target hash value and the second hash value If the calculation results of the secondary hash values are inconsistent, the secure boot check fails.
  • the method 500 also includes:
  • the electronic device in FIG. 7 includes corresponding hardware structures and/or software modules for performing various functions.
  • the present application can be implemented in the form of hardware or a combination of hardware and computer software with reference to the units and method steps of the examples described in the embodiments disclosed in the present application. Whether a certain function is executed by hardware or computer software drives the hardware depends on the specific application scenario and design constraints of the technical solution.
  • FIG. 7 is a schematic structural diagram of an example of an electronic device provided by an embodiment of the present application.
  • the electronic device 700 includes: a reading unit 701 , a processing unit 702 and a checking unit 703 .
  • the electronic device 700 may be an IoT device.
  • the reading unit 701 is configured to read the target data N times according to the target step size and the start address of the target data, and the target data includes the The data corresponding to the software package of the software system, the N is greater than or equal to 2; the processing unit 702 is configured to, after the data is read for the jth time, according to the jth group of data read for the jth time and the j-1th The result of the second hash value calculation is to perform the jth hash value calculation, wherein the j is an integer greater than 1 and less than or equal to N; the checking unit 703 is used to calculate the result according to the Nth hash value , to perform a secure boot check.
  • the electronic device 700 includes a flash memory controller
  • the processing unit 702 is further configured to: determine according to the step size of the flash memory controller, the target step size, and the start address of the target data N starting address sets, each starting address set in the N starting address sets includes n starting addresses, and the n is the ratio of the target step size to the step size of the flash memory controller
  • the reading unit 701 is specifically configured to: control the flash memory controller to read the jth group of data in n times according to the jth start address set and the step size of the flash memory controller.
  • the electronic device 700 includes a hash calculation module
  • the verification unit 703 is specifically configured to: after the flash memory controller performs the jth data reading, control the hash calculation module according to The jth group of data read for the jth time and the result of the j-1th hash value calculation are used for the jth hash value calculation.
  • the electronic device 700 further includes an adjustment unit, configured to adjust the target step size so that the first time is greater than the second time, and the first time includes the time required for reading the jth data.
  • the second time includes the time required to calculate the jth hash value.
  • the verification unit 703 is further specifically configured to: obtain a target hash value, the target hash value is the hash value configured for the data corresponding to the software package of the software system; by comparing the The target hash value and the calculation result of the Nth hash value are checked for secure startup.
  • the secure boot check passes; or, when the target hash value and the Nth hash value If the calculation results of the secondary hash values are inconsistent, the secure boot check fails.
  • the reading unit 701 is configured to read the first group of data from the target data according to the target step size and the start address of the target data, the target data including the The data corresponding to the software package of the software system; the processing unit 702 is configured to perform the first hash value calculation according to the first set of data, and the reading unit 701 is also configured to calculate the hash value according to the target step size and the start address of the target data, read the second group of data from the target data, the second group of data and the first group of data are different data in the target data; the processing unit 702 also uses Performing a second hash value calculation based on the second set of data and the result of the first hash value calculation; the checking unit 703 is configured to perform a second hash value calculation based on the second hash value calculation result Secure Boot Verification.
  • the electronic device 700 includes a flash memory controller
  • the processing unit 702 is further configured to: determine according to the step size of the flash memory controller, the target step size, and the start address of the target data
  • a first start address set, the first start address set includes n start addresses, where n is the ratio of the target step size to the step size of the flash memory controller
  • the read unit 701 is specifically used to : controlling the flash memory controller to read the first group of data from the target data in n times according to the first start address set and the step size of the flash memory controller.
  • the processing unit 702 is further configured to: determine a second start address set according to the step size of the flash memory controller, the target step size, and the start address of the target data, the The second start address set includes n start addresses, and the second start address set is different from the first start address set; the reading unit 701 is further specifically configured to: control the flash memory controller according to the Read the second group of data from the target data in n times according to the second start address set and the step size of the flash memory controller.
  • the electronic device includes a hash calculation module
  • the processing unit 702 is further configured to: control the hash calculation module to perform the first hash value calculation according to the first set of data;
  • the hash calculation module performs a second hash value calculation according to the second set of data and the result of the first hash value calculation.
  • the electronic device 700 further includes an adjustment unit, configured to adjust the target step size so that the first time is greater than the second time, and the first time includes the time required to read the second set of data. time, the second time includes the time required to calculate the first hash value.
  • the verification unit 703 is further specifically configured to: obtain a target hash value, the target hash value is the hash value configured for the data corresponding to the software package of the software system; by comparing the The target hash value and the calculation result of the second hash value are subjected to a secure boot verification.
  • the secure boot check passes; or, when the target hash value and the second hash value If the calculation results of the secondary hash values are inconsistent, the secure boot check fails.
  • the embodiment of the present application also provides an electronic device, including: one or more processors; one or more memories; the one or more memories store one or more computer programs, and the one or more computer programs include instructions , when the instruction is executed by one or more processors, the method as above is executed.
  • the electronic device is an IoT device.
  • the embodiment of the present application also provides a computer-readable storage medium, the computer-readable storage medium has program instructions, and when the program instructions are directly or indirectly executed, the foregoing method is realized.
  • the embodiment of the present application also provides a computer program product containing instructions, which, when run on a computing device, causes the computing device to execute the aforementioned method, or enables the computing device to realize the functions of the aforementioned electronic device.
  • the embodiment of the present application also provides a chip, including at least one processor and an interface circuit, the interface circuit is used to provide program instructions or data for the at least one processor, and the at least one processor is used to execute the program instructions , so that the above method can be realized.
  • the above-mentioned embodiments may be implemented in whole or in part by software, hardware, firmware or other arbitrary combinations.
  • the above-described embodiments may be implemented in whole or in part in the form of computer program products.
  • the computer program product comprises one or more computer instructions or computer programs.
  • the processes or functions according to the embodiments of the present application will be generated in whole or in part.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website, computer, server or data center Transmission to another website site, computer, server or data center by wired (such as infrared, wireless, microwave, etc.).
  • the computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center that includes one or more sets of available media.
  • the available media may be magnetic media (eg, floppy disk, hard disk, magnetic tape), optical media (eg, DVD), or semiconductor media.
  • the semiconductor medium may be a solid state drive.
  • the disclosed systems, devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the functions described above are realized in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disc and other media that can store program codes. .

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Abstract

一种安全启动校验的方法及电子设备(100,700)。方法包括：根据目标步长和目标数据的起始地址，分N次对目标数据进行读取，目标数据包括电子设备的软件系统的软件包对应的数据，N≥2(S401)；在第j次数据读取后，根据第j次读取的第j组数据和第j-1次哈希值计算的结果，进行第j次哈希值计算，其中，j为大于1，且小于或等于N的整数(S402)；根据第N次哈希值的计算结果，进行安全启动校验(S403)。这样，可以在读取第j+1组数据的过程中，便可以开始对第j次哈希值计算，实现将读取第j+1组数据的时间和对第j次哈希值计算的时间的合并，进而减少处理器等待的时间，提高了安全启动检验的效率，降低了电子设备的启动时间，提高了用户体验。

Description

安全启动校验的方法及电子设备
本申请要求于2021年8月26日提交中国专利局、申请号为202110985283.X、申请名称为“安全启动校验的方法及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子技术领域，并且更具体地，涉及一种安全启动校验的方法及电子设备。
背景技术
为了避免电子设备受到黑客攻击，造成电子设备上的信息存在安全隐患问题，通常在电子设备上增加安全启动功能。这样，电子设备在启动后，会对电子设备的软件系统的软件包进行安全启动校验。但是，现有的电子设备的安全启动校验的效率较低，启动时间较长，导致用户体验较差。
发明内容
本申请提供一种安全启动校验的方法及电子设备，可以提高安全启动校验的效率，进而缩短电子设备的启动时间，提高用户体验。
第一方面，提供了一种安全启动校验的方法，所述方法应用于电子设备，所述方法包括：根据目标步长和目标数据的起始地址，分N次对所述目标数据进行读取，所述目标数据包括所述电子设备的软件系统的软件包对应的数据，所述N大于或等于2；在第j次数据读取后，根据所述第j次读取的第j组数据和第j-1次哈希值计算的结果，进行第j次哈希值计算，其中，所述j为大于1，且小于或等于N的整数；根据第N次哈希值的计算结果，进行安全启动校验。
示例性地，所述电子设备为物联网(internet of things，IoT)设备。
在一种可实现的方式中，上述j还可以为大于或等于1，且小于或等于N的整数。此时，在j等于1的情况下，第0次哈希值计算的结果为0。
通过上述技术方案，在读取第j+1组数据的过程中，便可以开始对第j次哈希值计算，实现将读取第j+1组数据的时间和对第j次哈希值计算的时间的合并，进而减少电子设备等待的时间，提高了安全启动检验的效率，降低了电子设备的启动时间，提高了用户体验。
结合第一方面，在一种可实现的方式中，所述电子设备包括闪存控制器，所述根据目标步长和目标数据的起始地址，分N次对所述目标数据进行读取，包括：根据所述闪存控制器的步长、所述目标步长和所述目标数据的起始地址，确定N个起始地址集合，所述N个起始地址集合中的每个起始地址集合包括n个起始地址，所述n为所述目标步长与所述闪存控制器的步长的比值；控制所述闪存控制器根据第j个起始地址集合和所述闪存控制器的步长，分n次对所述第j组数据进行读取。
结合第一方面，在一种可实现的方式中，所述电子设备包括哈希计算模块，所述在第j次数据读取后，根据所述第j次读取的第j组数据和第j-1次哈希值计算的结果，进行第j次哈希值计算，包括：在所述闪存控制器进行所述第j次数据读取后，控制所述哈希计算模块根据所述第j次读取的第j组数据和第j-1次哈希值计算的结果，进行第j次哈希值计算。
通过上述技术方案，在闪存控制器读取第j+1组数据的过程中，哈希计算模块便可以开始对第j次哈希值计算，实现将读取第j+1组数据的时间和对第j次哈希值计算的时间的合并，进而减少电子设备等待的时间，提高了安全启动检验的效率，降低了电子设备的启动时间，提高了用户体验。
结合第一方面，在一种可实现的方式中，所述方法还包括：调整所述目标步长，以使第一时间大于第二时间，所述第一时间包括所述第j次数据读取所需的时间，所述第二时间包括所述第j次哈希值计算所需的时间。
通过调整目标步长，以使第j次数据读取所需的时间大于第j次哈希值计算所需的时间，进而保证读取第j+1组数据的过程中，可以完成对第j组数据的哈希值计算。从而更好的减少电子设备等待的时间，提高了安全启动检验的效率，降低了电子设备的启动时间，提高了用户体验。
结合第一方面，在一种可实现的方式中，所述根据第N次哈希值的计算结果，进行安全启动校验，包括：获取目标哈希值，所述目标哈希值为所述软件系统的软件包对应的数据所配置的哈希值；通过比较所述目标哈希值和所述第N次哈希值的计算结果，进行安全启动校验。
结合第一方面，在一种可实现的方式中，所述通过比较所述目标哈希值和所述第N次哈希值的计算结果，进行安全启动校验，包括：在所述目标哈希值和所述第N次哈希值的计算结果一致的情况下，安全启动校验通过；或，在所述目标哈希值和所述第N次哈希值的计算结果不一致的情况下，安全启动校验不通过。
第二方面，提供了一种安全启动校验的方法，所述方法应用于电子设备，所述方法包括：根据目标步长和目标数据的起始地址，从目标数据中读取第一组数据，所述目标数据包括所述电子设备的软件系统的软件包对应的数据；根据所述第一组数据，进行第一次哈希值计算，以及，根据所述目标步长和所述目标数据的起始地址，从所述目标数据中读取第二组数据，所述第二组数据和所述第一组数据是所述目标数据中不同的数据；根据所述第二组数据和所述第一次哈希值计算的结果，进行第二次哈希值计算；根据所述第二次哈希值的计算结果，进行安全启动校验。
示例性地，所述电子设备为IoT设备。
通过上述技术方案，在读取第二组数据的过程中，便可以开始对第一组数据进行第一次哈希值计算，实现将读取第二组数据的时间和对第一组数据进行第一次哈希值计算的时间的合并，进而减少电子设备等待的时间，提高了安全启动检验的效率，降低了电子设备的启动时间，提高了用户体验。
结合第二方面，在一种可实现的方式中，所述电子设备包括闪存控制器，所述根据目标步长和目标数据的起始地址，从目标数据中读取第一组数据，包括：根据所述闪存控制器的步长、所述目标步长和所述目标数据的起始地址，确定第一起始地址集合，所述第一 起始地址集合包括n个起始地址，所述n为所述目标步长与所述闪存控制器的步长的比值；控制所述闪存控制器根据所述第一起始地址集合和所述闪存控制器的步长，分n次从所述目标数据中读取所述第一组数据。
结合第二方面，在一种可实现的方式中，所述根据所述目标步长和所述目标数据的起始地址，从所述目标数据中读取第二组数据，包括：根据所述闪存控制器的步长、所述目标步长和所述目标数据的起始地址，确定第二起始地址集合，所述第二起始地址集合包括n个起始地址，所述第二起始地址集合和所述第一起始地址集合不同；控制所述闪存控制器根据所述第二起始地址集合和所述闪存控制器的步长，分n次从所述目标数据中读取所述第二组数据。
结合第二方面，在一种可实现的方式中，所述电子设备包括哈希计算模块，所述根据所述第一组数据，进行第一次哈希值计算，包括：控制所述哈希计算模块根据所述第一组数据，进行第一次哈希值计算；所述根据所述第二组数据和所述第一次哈希值计算的结果，进行第二次哈希值计算，包括：控制所述哈希计算模块根据所述第二组数据和所述第一次哈希值计算的结果，进行第二次哈希值计算。
通过上述技术方案，在闪存控制器读取第二组数据的过程中，哈希计算模块便可以开始对第一组数据进行第一次哈希值计算，实现将读取第二组数据的时间和对第一组数据进行第一次哈希值计算的时间的合并，进而减少电子设备等待的时间，提高了安全启动检验的效率，降低了电子设备的启动时间，提高了用户体验。
结合第二方面，在一种可实现的方式中，所述方法还包括：调整所述目标步长，以使第一时间大于第二时间，所述第一时间包括读取所述第二组数据所需的时间，所述第二时间包括所述第一次哈希值计算所需的时间。
通过调整目标步长，以使读取第二组数据所需的时间大于第二次哈希值计算所需的时间，进而保证读取第二组数据的过程中，可以完成对第一组数据的哈希值计算。从而更好的减少电子设备等待的时间，提高了安全启动检验的效率，降低了电子设备的启动时间，提高了用户体验。
结合第二方面，在一种可实现的方式中，所述根据第二次哈希值的计算结果，进行安全启动校验，包括：获取目标哈希值，所述目标哈希值为所述软件系统的软件包对应的数据所配置的哈希值；通过比较所述目标哈希值和所述第二次哈希值的计算结果，进行安全启动校验。
结合第二方面，在一种可实现的方式中，所述通过比较所述目标哈希值和所述第二次哈希值的计算结果，进行安全启动校验，包括：在所述目标哈希值和所述第二次哈希值的计算结果一致的情况下，安全启动校验通过；或，在所述目标哈希值和所述第二次哈希值的计算结果不一致的情况下，安全启动校验不通过。
第三方面，提供了一种电子设备，包括：一个或多个处理器；一个或多个存储器；该一个或多个存储器存储有一个或多个计算机程序，该一个或多个计算机程序包括指令，当该指令被一个或多个处理器执行时，使得如第一方面及其任一种可能的实现方式中所述的安全启动校验的方法被执行。
示例性地，所述电子设备为IoT设备。
第四方面，提供了一种计算机可读存储介质，包括计算机指令，当所述计算机指令在 电子设备上运行时，使得所述电子设备执行如第一方面及其任一种可能的实现方式中所述的安全启动校验的方法。
第五方面，提供了一种芯片，包括至少一个处理器和接口电路，所述接口电路用于为所述至少一个处理器提供程序指令或者数据，所述至少一个处理器用于执行所述程序指令，以实现如第一方面及其任一种可能的实现方式中所述的安全启动校验的方法。
第六方面，提供一种计算机程序产品，包括计算机指令，当所述计算机指令在电子设备上运行时，使得如第一方面及其任一种可能的实现方式中所述的安全启动校验的方法被执行。
附图说明
图1是本申请实施例提供的一例电子设备的结构示意图。
图2是本申请实施例提供的另一例电子设备的结构示意图。
图3是本申请实施例提供的一例电子设备的软件结构示意图。
图4是本申请实施例提供的一例安全启动校验的方法的流程示意图。
图5是本申请实施例提供的另一例安全启动校验的方法的流程示意图。
图6是本申请实施例提供的又一例安全启动校验的方法的流程示意图。
图7是本申请实施例提供的又一例电子设备的结构示意图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
本申请实施例中涉及的电子设备可以指用户设备、接入终端、用户单元、用户站、移动站、移动台、远方站、远程终端、移动设备、用户终端、终端、无线通信设备、用户代理或用户装置。终端设备还可以是蜂窝电话、无绳电话、会话启动协议(Session Initiation Protocol，SIP)电话、无线本地环路(Wireless Local Loop，WLL)站、个人数字处理(Personal Digital Assistant，PDA)、具有无线通信功能的手持设备、计算设备或连接到无线调制解调器的其它处理设备、车载设备、可穿戴设备(例如蓝牙耳机或智能手表)、家居设备(例如智能门锁或智能猫眼)，未来5G网络中的终端设备或者未来演进的公用陆地移动通信网络(Public Land Mobile Network，PLMN)中的终端设备等，本申请实施例对此并不限定。
示例性的，图1示出了本申请实施例提供的一例电子设备100的结构示意图。
例如，如图1所示，电子设备100可以包括处理器110，外部存储器接口120，内部存储器121，通用串行总线(universal serial bus，USB)接口130，充电管理模块140，电源管理模块141，电池142，天线1，天线2，移动通信模块150，无线通信模块160，音频模块170，扬声器170A，受话器170B，麦克风170C，耳机接口170D，传感器模块180，按键190，马达191，指示器192，摄像头193，显示屏194，以及用户标识模块(subscriber identification module，SIM)卡接口195等。其中传感器模块180可以包括压力传感器180A，陀螺仪传感器180B，气压传感器180C，磁传感器180D，加速度传感器180E，距离传感器180F，接近光传感器180G，指纹传感器180H，温度传感器180J，触摸传感器180K，环境光传感器180L，骨传导传感器180M等。
可以理解的是，本申请实施例示意的结构并不构成对电子设备100的具体限定。在本申请另一些实施例中，电子设备100可以包括比图示更多或更少的部件，或者组合某些部件，或者拆分某些部件，或者不同的部件布置。图示的部件可以以硬件，软件或软件和硬件的组合实现。
处理器110可以包括一个或多个处理单元，例如：处理器110可以包括应用处理器(application processor，AP)，调制解调处理器，图形处理器(graphics processing unit，GPU)，图像信号处理器(image signal processor，ISP)，控制器，存储器，视频编解码器，数字信号处理器(digital signal processor，DSP)，基带处理器，和/或神经网络处理器(neural-network processing unit，NPU)等。其中，不同的处理单元可以是独立的器件，也可以集成在一个或多个处理器中。
其中，控制器可以是电子设备100的神经中枢和指挥中心。控制器可以根据指令操作码和时序信号，产生操作控制信号，完成取指令和执行指令的控制。
处理器110中还可以设置存储器，用于存储指令和数据。在一些实施例中，处理器110中的存储器为高速缓冲存储器。该存储器可以保存处理器110刚用过或循环使用的指令或数据。如果处理器110需要再次使用该指令或数据，可从所述存储器中直接调用。避免了重复存取，减少了处理器110的等待时间，因而提高了系统的效率。
在一些实施例中，处理器110可以包括一个或多个接口。接口可以包括集成电路(inter-integrated circuit，I2C)接口，集成电路内置音频(inter-integrated circuit sound，I2S)接口，脉冲编码调制(pulse code modulation，PCM)接口，通用异步收发传输器(universal asynchronous receiver/transmitter，UART)接口，移动产业处理器接口(mobile industry processor interface，MIPI)，通用输入输出(general-purpose input/output，GPIO)接口，用户标识模块(subscriber identity module，SIM)接口，和/或通用串行总线(universal serial bus，USB)接口等。其中，I2C接口是一种双向同步串行总线，包括一根串行数据线(serial data line，SDA)和一根串行时钟线(derail clock line，SCL)。I2S接口可以用于音频通信。在一些实施例中，处理器110可以包含多组I2S总线。处理器110可以通过I2S总线与音频模块170耦合，实现处理器110与音频模块170之间的通信。PCM接口也可以用于音频通信，将模拟信号抽样，量化和编码。在一些实施例中，音频模块170与无线通信模块160可以通过PCM总线接口耦合。UART接口是一种通用串行数据总线，用于异步通信。该总线可以为双向通信总线。它将要传输的数据在串行通信与并行通信之间转换。在一些实施例中，UART接口通常被用于连接处理器110与无线通信模块160。MIPI接口可以被用于连接处理器110与显示屏194，摄像头193等外围器件。GPIO接口可以通过软件配置。GPIO接口可以被配置为控制信号，也可被配置为数据信号。在一些实施例中，GPIO接口可以用于连接处理器110与摄像头193，显示屏194，无线通信模块160，音频模块170，传感器模块180等。USB接口130是符合USB标准规范的接口，具体可以是Mini USB接口，Micro USB接口，USB Type C接口等。USB接口130可以用于连接充电器为电子设备100充电，也可以用于电子设备100与外围设备之间传输数据。
可以理解的是，本申请实施例示意的各模块间的接口连接关系，只是示意性说明，并不构成对电子设备100的结构限定。在本申请另一些实施例中，电子设备100也可以采用上述实施例中不同的接口连接方式，或多种接口连接方式的组合。
充电管理模块140用于从充电器接收充电输入。其中，充电器可以是无线充电器，也可以是有线充电器。在一些有线充电的实施例中，充电管理模块140可以通过USB接口130接收有线充电器的充电输入。在一些无线充电的实施例中，充电管理模块140可以通过电子设备100的无线充电线圈接收无线充电输入。充电管理模块140为电池142充电的同时，还可以通过电源管理模块141为电子设备供电。电源管理模块141用于连接电池142，充电管理模块140与处理器110。
电子设备100的无线通信功能可以通过天线1，天线2，移动通信模块150，无线通信模块160，调制解调处理器以及基带处理器等实现。
移动通信模块150可以提供应用在电子设备100上的包括2G/3G/4G/5G等无线通信的解决方案。
在一些实施例中，调制解调处理器可以是独立的器件。在另一些实施例中，调制解调处理器可以独立于处理器110，与移动通信模块150或其他功能模块设置在同一个器件中。
无线通信模块160可以提供应用在电子设备100上的包括无线局域网(wireless local area networks，WLAN)(如无线保真(wireless fidelity，Wi-Fi)网络)，蓝牙(bluetooth，BT)，全球导航卫星系统(global navigation satellite system，GNSS)，调频(frequency modulation，FM)，近距离无线通信技术(near field communication，NFC)，红外技术(infrared，IR)等无线通信的解决方案。
在一些实施例中，电子设备100的天线1和移动通信模块150耦合，天线2和无线通信模块160耦合，使得电子设备100可以通过无线通信技术与网络以及其他设备通信。
电子设备100通过GPU，显示屏194，以及应用处理器等实现显示功能。GPU为图像处理的微处理器，连接显示屏194和应用处理器。GPU用于执行数学和几何计算，用于图形渲染。处理器110可包括一个或多个GPU，其执行程序指令以生成或改变显示信息。
显示屏194用于显示图像，视频等。显示屏194包括显示面板。显示面板可以采用液晶显示屏(liquid crystal display，LCD)，也可以采用有机发光二极管(organic light-emitting diode，OLED)、有源矩阵有机发光二极体或主动矩阵有机发光二极体(active-matrix organic light emitting diode，AMOLED)、柔性发光二极管(flex light-emitting diode，FLED)、Miniled、MicroLed、Micro-oLed或量子点发光二极管(quantum dot light emitting diodes，QLED)等材料中的一种所制作的显示面板。在一些实施例中，电子设备100可以包括1个或N个显示屏194，N为大于1的正整数。
电子设备100可以通过ISP，摄像头193，视频编解码器，GPU，显示屏194以及应用处理器等实现拍摄功能。
外部存储器接口120可以用于连接外部存储卡，例如Micro SD卡，实现扩展电子设备100的存储能力。内部存储器121可以用于存储计算机可执行程序代码，所述可执行程序代码包括指令。处理器110通过运行存储在内部存储器121的指令，从而执行电子设备100的各种功能应用以及数据处理。
电子设备100可以通过音频模块170，扬声器170A，受话器170B，麦克风170C，耳机接口170D，以及应用处理器等实现音频功能。例如音乐播放，录音等。音频模块170用于将数字音频信息转换成模拟音频信号输出，也用于将模拟音频输入转换为数字音频信 号。扬声器170A，也称“喇叭”，用于将音频电信号转换为声音信号。受话器170B，也称“听筒”，用于将音频电信号转换成声音信号。麦克风170C，也称“话筒”，“传声器”，用于将声音信号转换为电信号。耳机接口170D用于连接有线耳机。
压力传感器180A用于感受压力信号，可以将压力信号转换成电信号。在一些实施例中，压力传感器180A可以设置于显示屏194。陀螺仪传感器180B可以用于确定电子设备100的运动姿态。气压传感器180C用于测量气压。在一些实施例中，电子设备100通过气压传感器180C测得的气压值计算海拔高度，辅助定位和导航。加速度传感器180E可检测电子设备100在各个方向上(一般为三轴)加速度的大小。距离传感器180F，用于测量距离。指纹传感器180H用于采集指纹。触摸传感器180K，也称“触控面板”。触摸传感器180K可以设置于显示屏194，由触摸传感器180K与显示屏194组成触摸屏，也称“触控屏”。骨传导传感器180M可以获取振动信号。在一些实施例中，骨传导传感器180M可以获取人体声部振动骨块的振动信号。骨传导传感器180M也可以接触人体脉搏，接收血压跳动信号。
按键190包括开机键，音量键等。马达191可以产生振动提示。指示器192可以是指示灯，可以用于指示充电状态，电量变化，也可以用于指示消息，未接来电，通知等。SIM卡接口195用于连接SIM卡。
示例性的，图2示出了本申请实施例提供的另一例电子设备100的结构示意图。如图2所示，电子设备100包括存储器210以及处理器220。存储器210用于存储计算机程序，该计算机程序包括应用程序、操作系统程序和操作系统引导程序等。处理器220用于读取存储器210中的计算机程序，然后执行计算机程序定义的方法，例如处理器220读取操作系统引导程序从而在该电子设备100上引导操作系统的运行，或读取操作系统程序从而在该电子设备100上运行操作系统以及实现操作系统的各种功能，或读取一种或多种应用程序，从而在该电子设备100上运行应用。
关于处理器220的其他描述可以参考上文中关于处理器110的描述，这里不再赘述。
存储器210还存储有除计算机程序之外的其他数据，其他数据可包括操作系统程序或应用程序被运行后产生的数据，该数据包括系统数据(例如操作系统的配置参数、操作系统的软件包对应的数据等)和用户数据。
存储器210一般包括内存和外存。内存可以为随机存储器(random access memory，RAM)，只读存储器(read-only memory，ROM)，以及高速缓存(cache)等。外存可以为硬盘、光盘、通用串行总线(universal serial bus，USB)盘、软盘或磁带机等。计算机程序例如应用程序可以被存储在外存上，处理器在执行处理前会将计算机程序从外存加载到内存，操作系统可以存储于内存中。这样，内存可以存储计算机可执行程序代码，该可执行程序代码包括指令。处理器220通过运行存储在内存的指令，从而执行电子设备100的各种功能应用以及数据处理。
示例性地，操作系统引导程序中包含了可实现本申请实施例提供的安全启动校验的方法的计算机程序，从而使得处理器220读取到该操作系统引导程序后，启动电子设备100的安全启动校验的功能。
示例性地，在一些实施例中，电子设备100还可以包括接口电路，该接口电路用于为存储器210提供该操作系统引导程序。
示例性地，接口电路可以使用例如但不限于收发器一类的收发装置，来实现装置与其他设备或通信网络之间的通信。该接口电路例如还可以是通信接口。
电子设备100还可以包括闪存(flash)控制器230，用于存储与电子设备100的软件系统的软件包相关的数据。其中，闪存控制器230可以是独立的器件，也可以集成在存储器210中。
电子设备100还可以包括哈希计算模块240，用于对闪存控制器230中存储的与电子设备200的软件系统的软件包相关的数据进行哈希值计算。其中，哈希计算模块240可以是独立的器件，也可以集成在处理器220中。
示例性地，图2所示的电子设备100的各个部件通过总线连接在一起。
可以理解的是，本申请实施例示意的如图2所示的电子设备100的结构并不构成对电子设备100的具体限定。
示例性地，在一些实施例中，电子设备100可以包括比图2所示更多的部件。例如，电子设备100还可以包括显示模块、电源模块、传感器模块、音频模块、充电管理模块、通信模块、电池、指示灯、输入模块(例如触控面板、物理键盘、功能按键等)等。
示例性地，在一些实施例中，电子设备100可以包括组合图2所示某些部件，或者拆分图2所示某些部件，或者不同的部件布置。图示的部件可以以硬件，软件或软件和硬件的组合实现。
图1或图2所述的电子设备100的软件系统可以采用分层架构，事件驱动架构，微核架构，微服务架构，或云架构。
本申请实施例对该软件系统不作限定。例如，该软件系统可以为
Figure PCTCN2022111184-appb-000001
系统、
Figure PCTCN2022111184-appb-000002
系统或
Figure PCTCN2022111184-appb-000003
系统等。
下面结合图3，以分层架构的
Figure PCTCN2022111184-appb-000004
系统为例，示例性说明电子设备100的软件结构。
图3是本申请实施例的电子设备100的软件结构框图。分层架构将软件分成若干个层，每一层都有清晰的角色和分工。层与层之间通过软件接口通信。在一些实施例中，将Android系统分为四层，从上至下分别为应用程序层，应用程序框架层和系统库，以及内核层。应用程序层可以包括一系列应用程序包。
如图3所示，应用程序包可以包括相机，图库，日历，通话，地图，导航，WLAN，蓝牙，音乐，视频，短信息等应用程序。
应用程序框架层为应用程序层的应用程序提供应用编程接口(application programming interface，API)和编程框架。应用程序框架层包括一些预先定义的函数。
如图3所示，应用程序框架层可以包括窗口管理器，内容提供器，视图系统，电话管理器，资源管理器，通知管理器等。
窗口管理器用于管理窗口程序。窗口管理器可以获取显示屏大小，判断是否有状态栏，锁定屏幕，截取屏幕等。
内容提供器用来存放和获取数据，并使这些数据可以被应用程序访问。所述数据可以包括视频，图像，音频，拨打和接听的电话，浏览历史和书签，电话簿等。
视图系统包括可视控件，例如显示文字的控件，显示图片的控件等。视图系统可用于构建应用程序。显示界面可以由一个或多个视图组成的。例如，包括短信通知图标的显示 界面，可以包括显示文字的视图以及显示图片的视图。
电话管理器用于提供电子设备100的通信功能。例如通话状态的管理(包括接通，挂断等)。
资源管理器为应用程序提供各种资源，比如本地化字符串，图标，图片，布局文件，视频文件等等。
通知管理器使应用程序可以在状态栏中显示通知信息，可以用于传达告知类型的消息，可以短暂停留后自动消失，无需用户交互。比如通知管理器被用于告知下载完成，消息提醒等。通知管理器还可以是以图表或者滚动条文本形式出现在系统顶部状态栏的通知，例如后台运行的应用程序的通知，还可以是以对话窗口形式出现在屏幕上的通知。例如在状态栏提示文本信息，发出提示音，电子设备振动，指示灯闪烁等。
应用程序层和应用程序框架层运行在虚拟机中。虚拟机将应用程序层和应用程序框架层的java文件执行为二进制文件。虚拟机用于执行对象生命周期的管理，堆栈管理，线程管理，安全和异常的管理，以及垃圾回收等功能。
系统库可以包括多个功能模块。例如：表面管理器(surface manager)，媒体库(media libraries)，三维图形处理库(例如：OpenGL ES)，2D图形引擎(例如：SGL)等。
表面管理器用于对显示子系统进行管理，并且为多个应用程序提供了2D和3D图层的融合。
媒体库支持多种常用的音频，视频格式回放和录制，以及静态图像文件等。媒体库可以支持多种音视频编码格式，例如：MPEG4，H.264，MP3，AAC，AMR，JPG，PNG等。
三维图形处理库用于实现三维图形绘图，图像渲染，合成，和图层处理等。
2D图形引擎是2D绘图的绘图引擎。
内核层是硬件和软件之间的层。内核层至少包含显示驱动，摄像头驱动，音频驱动，传感器驱动。
示例性地，电子设备的处理器可以支持多核，例如4核或8核等。此时，该处理器可以称为多核处理器。
示例性地，电子设备的操作系统也可以支持多核。此时，该操作系统可以称为多核操作系统。
多核处理器或多核操作系统可以并行执行多个线程(thread)。即同一时间段内，多个线程可以在多个处理器上执行。
其中，线程是操作系统能够进行运算调度的最小单位。它被包含在进程之中，是进程中的实际运作单位。一条线程指的是进程中一个单一顺序的控制流，一个进程中可以并发多个线程，每条线程并行执行不同的任务。同一进程中的多条线程将共享该进程中的全部系统资源，如虚拟地址空间，文件描述符和信号处理等等。
进程(process)是计算机中的程序关于某数据集合上的一次运行活动，是系统进行资源分配和调度的基本单位，是操作系统结构的基础。
为了避免电子设备受到黑客攻击，造成电子设备上的信息存在安全隐患问题，通常在电子设备上增加安全启动功能。这样，电子设备在启动后，会对电子设备的软件系统的软件包的完整性进行校验。但是，现有的电子设备的安全启动校验的效率较低，启动时间较长，导致用户体验较差。
因此，本申请实施例提供了一种安全启动校验的方法，该方法可以实现在单线程运行的场景下。该方法可以提高了安全启动检验的效率，降低电子设备的启动时间，提高了用户体验。
示例性地，该安全启动校验的方法不仅可以应用于IoT设备，例如智能门锁、智能猫眼蓝牙耳机等，该安全启动校验的方法也可以应用于除IoT设备之外的其他电子设备中。
示例性地，该安全启动校验的方法的执行主体可以是电子设备的处理器。例如，处理器可以调用电子设备的操作系统引导程序如通用引导加载程序(universal boot loader，uboot)实现该安全启动校验方法。
图4为本申请实施例提供的一例安全启动校验的方法300的流程示意图。
示例性地，该方法300的执行主体可以是如图1所示的处理器110或如图2所示的处理器220。方法300中涉及的闪存控制器可以是如图2所示的闪存控制器230。方法300中涉及的哈希计算模块可以是如图2所示的哈希计算模块240。方法300中涉及的存储器可以是如图2所示的存储器210。
例如，如图4所示，该方法300包括S301至S315。下面，将具体介绍S301至S315。
S301，获取处理器数据读取参数。其中，处理器数据读取参数包括处理器数据读取的步长、起始地址和全部数据的数据量。
应理解，处理器数据读取的步长表示每次读取的数据量。例如，处理器数据读取的步长为64k，即处理器每次读取64k的数据量。又例如，处理器数量读取的步长为128k，即处理器每次读取128k的数据量。
本申请实施例对数据量的单位不作限定。例如，数据量的单位可以是千字节(k)、比特(bit)或兆(M)等。
应理解，处理器数据读取的起始地址表示处理器读取的数据在存储空间中的起始地址。
示例性地，处理器数据读取的步长和起始地址可以是预先设定的。
由于全部数据的数据量比较大，因此，针对处理器而言，处理器需要分N次，才能完成全部数据的读取。其中N大于或等于2。
在获取处理器数据读取参数之后，需控制闪存控制器进行数据的读取。故在控制闪存控制进行数据的读取之前，需将处理器数据读取参数转换为闪存控制器的读取参数，具体过程详见S302中的描述。
S302，根据闪存控制器数据读取的步长和处理器数据读取参数，确定闪存控制器读取数据的读取参数。
由于闪存控制器数据读取的步长是闪存控制器的硬件参数，故闪存控制器不需要获取闪存控制器数据读取的步长。则闪存控制器读取数据的读取参数包括闪存控制器数据读取的起始地址。
示例性地，闪存控制器数据读取的步长可以是预先获取的或现获取的，本申请对此不作限定。
进一步地，由于处理器数据读取的步长一般大于闪存控制器数据读取的步长，因此，处理器一次数据读取的数据量，闪存控制器需要分n次读取。这样，对于闪存控制器而言，全部数据需分N×n次读取。因此，S302中确定的闪存控制器读取数据的读取参数包括闪存控制器N×n次数据读取的起始地址。
以下，为了方便描述，将闪存控制器数据读取的起始地址分为N组，每组包括n个数据读取的起始地址，且每组包括的n个数据读取的起始地址分别为闪存控制器n次数据读取的起始地址。在具体实现中，闪存控制器数据读取的起始地址可以分为N组，也可以不分为N组，本申请实施例对此不作限定。
在S302中，首先，根据闪存控制器数据读取的步长和处理器数据读取的步长，确定上文所述的n。具体的，n满足以下公式(1)：
Figure PCTCN2022111184-appb-000005
其中，M1为处理器数据读取的步长，M2为闪存控制器数据读取的步长。
例如，若处理器数据读取的步长为128k，即M1＝128k；闪存控制器数据读取的步长为2k，即M2＝2k，则闪存控制器需要分64次(即n＝64)读取处理器一个步长对应的数据量。
其次，确定N组闪存控制器数据读取的起始地址。
应理解，在S320中，可以一次性确定N组闪存控制器数据读取的起始地址，也可以分N次分别确定N组闪存控制器数据读取的起始地址。
具体的，闪存控制器第i次数据读取的起始地址L i满足以下公式：
L i＝L 0+(i-1)×M2  (2)
其中，L 0为处理器数据读取的起始步长，i＝1，2，……，n，n+1，……，n×N。L 0，L 1，……，L n分别为第一组闪存控制器数据读取的起始地址；L n+1，L n+2，……，L 2n分别为第二组闪存控制器数据读取的起始地址；……；L (j-1)×n+1，L (j-1)×n+2，……，L (j-1)×n+n分别为第j组闪存控制器数据读取的起始地址；……；L (N-1)×n+1，L (N-1)×n+2，……，L (N-1)×n+n分别为第N组闪存控制器数据读取的起始地址。
在确定闪存控制器读取数据的读取参数后，需要触发闪存控制器工作。具体过程详见S303和S304中的描述。
在本申请实施例中，可以通过多个寄存器控制闪存控制器的工作。该多个寄存器中的每个寄存器扮演着不同的角色，即每个寄存器的用途不同。示例性地，可以通过四个寄存器如第一寄存器、第二寄存器和第三寄存器，控制闪存控制器的工作。其中，第一寄存器用于存储闪存控制器数据读取的起始地址。第二寄存器用于控制闪存控制器开始读取数据。第三寄存器用于监视闪存控制器的工作状态，例如第三寄存器可以监视闪存控制器数据是否读取完毕和/或闪存控制器累积数据读取的步长等。在闪存控制器数据已读取完毕的情况下，第三寄存器为空闲状态。
本申请实施例对寄存器设置的位置不作限定。例如，寄存器可以设置在处理器中。
S303，将闪存控制器读取数据的读取参数写入第一目标地址。其中，第一目标地址和第一寄存器存在映射关系，第一目标地址和闪存控制器存在映射关系。
示例性地，本申请实施例中涉及的映射关系可以是预先定义好的。
在一些实施例中，可以分N次执行S303。此时，闪存控制器读取数据的读取参数包括一组闪存控制器数据读取的起始地址。
在另一些实施例中，S303可以只执行一次。此时，闪存控制器读取数据的读取参数包括N组闪存控制器数据读取的起始地址。
应理解，将闪存控制器读取数据的读取参数写入第一目标地址即为将闪存控制器读取数据的读取参数写入该第一目标地址对应的寄存器，即第一寄存器。
通过S303，闪存控制器即可获知闪存控制器数据读取的读取参数。
进一步地，在将闪存控制器读取数据的读取参数写入第一目标地址之后，需要触发闪存控制器开始进行数据读取，具体过程详见S304中的描述。
S304，将开始指令写入第二目标地址。其中，第二目标地址和第二寄存器存在映射关系，第二目标地址和闪存控制器存在映射关系。
应理解，将开始指令写入第二目标地址即为将开始指令写入第二目标地址对应的寄存器，即第二寄存器。
通过S304，闪存控制器即可开始读取数据，具体过程详见S305中的描述。
S305，控制闪存控制器按照第一目标地址中存储的读取参数，从存储器中读取第j组数据。其中，j＝1，2，……，N。
具体的，闪存控制器根据存储器对应的起始地址L (j-1)×n+1，L (j-1)×n+2，……，L (j-1)×n+n，分n次读取第j组数据。其中，闪存控制器每次读取数据量为闪存控制器数据读取的步长对应的数据量，闪存控制器n次读取的总数据量为处理器数据读取步长对应的数据量。
此时，即在S305执行过程中，第三寄存器一直监视着闪存控制器的读取状态。同时，即在S305执行过程中，处理器一直循环访问第三寄存器，以便执行S306。
S306，判断闪存控制器是否完成第j组数据的读取。
示例性地，可以通过判断第三寄存器是否处于空闲状态来实现S306。在第三寄存器为空闲状态的情况下，执行S307。在第三寄存器不为空闲状态的情况下，继续执行S306，直到判断第三寄存器为空闲状态。
S307，将第j组数据加载至RAM。即以闪存控制器n次读取的数据量为单位传输至RAM中。
示例性地，闪存控制器可以将第j组数据先缓存至直接存储器访问(direct memory access，DMA)控制器，DMA控制器再将该第j组数据复制到RAM中，并通知处理器，该第j组数据在RAM中的地址以及长度。
本申请实施例中，也可以通过多个寄存器控制哈希计算模块的工作。该多个寄存器中的每个寄存器扮演着不同的角色，即每个寄存器的用途不同。示例性地，可以通过两个寄存器如第四寄存器和第五寄存器，控制闪存控制器的工作。其中，第四寄存器用于存储第j组数据在RAM中的地址以及长度写入第三目标地址。第五寄存器用于监视哈希计算模块的工作状态，例如第五寄存器可以监视哈希计算模块哈希值是否计算完毕。在哈希计算模块哈希值已计算完毕的情况下，第五寄存器为空闲状态。
S308，将第j组数据在RAM中的地址以及长度写入第三目标地址。其中，第三目标地址和第四寄存器存在映射关系。该第三目标地址和哈希计算模块存在映射关系。
应理解，将第j组数据在RAM中的地址以及长度写入第三目标地址即为将第j组数据在RAM中的地址以及长度写入第三目标地址对应的寄存器，即第四寄存器。
通过S308，哈希计算模块即可从RAM中获知第j组数据，即S309。
S309，控制哈希计算模块按照第三目标地址中存储的第j组数据在RAM中的地址以及长度，从RAM中读取第j组数据。
在哈希计算模块读取第j组数据后，判断哈希计算模块是否完成上次哈希值计算，即S310。
S310，判断是否完成第j-1次哈希值计算。
示例性地，可以通过判断第五寄存器是否处于空闲状态来实现S310。在第五寄存器为空闲状态的情况下，开始进行第j次哈希值的计算，即执行S311和S312。在第五寄存器不为空闲状态的情况下，继续执行S310，直到判断第五寄存器为空闲状态。
应理解，当j＝1时，第0次哈希值的计算结果为0。
可选地，当j＝1时，可以不用执行S310。
在完成第j-1次哈希值计算后，获取第j-1次哈希值的计算结果，即S311。
S312，控制哈希计算模块根据第j组数据和第j-1次哈希值的计算结果，进行第j次哈希值计算。
应理解，哈希计算模块每次进行哈希值计算数据包括两部分：一部分为第j-1次哈希值的计算结果，另一部分为第j组数据。
其中，第j组数据的数据量对应于闪存控制器n次数据读取的数据量，也即处理器一次数据读取的数据量(即处理器数据读取的步长对应的数据量)。例如，若处理器数据读取的步长为128k；闪存控制器数据读取的步长为2k，则第j组数据的数据量对应于闪存控制器分64(此时根据公式(1)可得n＝64)次读取的数据量(128k)，也即处理器一个步长对应的数据量(128k)。
通过S312，可实现用第j次哈希值的计算结果覆盖第j-1次哈希值的计算结果。
此外，在控制哈希值计算模块进行第j次哈希值计算的过程，即执行S309至S312的过程中，同时，也可以执行S313，以便确定闪存控制器是继续读取第j+1组数据还是结束读取数据的操作。
S313，判断闪存控制器是否完成全部数据的读取。
示例性地，可以通过判断闪存控制器累积数据读取的步长是否达到S301中所述的全部数据的数据量的长度来实现S313。
示例性地，闪存控制累积数据读取的步长可以通过第三寄存器来获取闪存控制器累积数据读取的步长。
在闪存控制器未完成全部数据的读取的情况下，将j加1，并循环执行S305至S313。此时，j＜N，闪存控制器开始第j+1组数据的读取，即执行S305至S308。此外，哈希值计算模块开始第j+1次哈希值计算，即执行S309至S312，其中，S309至S312中的j为上一轮j加1。
直到S313判断闪存控制器已完成全部数据的读取。在闪存控制器完成全部数据的读取的情况下，结束闪存控制器读取数据的操作，即S314，此时，j＝N。
通过S301至S314，当j从1取值到N，闪存控制器分N×n次完成全部数据的读取，且以n次读取的数据量为单位传输至RAM中。此外，哈希值模块分N次完成全部数据的哈希值计算。
在一些实施例中，为了更好的减少处理器等待的时间，提高了安全启动检验的效率，降低了电子设备的启动时间，可以通过调整处理器数据读取的步长，来实现第一时间大于第二时间。其中，第一时间包括闪存控制器从第三寄存器读取第j组数据的时间和闪存控 制器将第j组数据加载到RAM中的时间。第二时间包括哈希计算模块对第j组数据进行哈希值计算的时间。这样，可以保证闪存控制器在从存储器中读取第j+1组数据(即处理器一次数据读取的数据量)的过程中，哈希计算模块可以完成第j次哈希值的计算。因此，哈希计算模块不需要等待时间，便可以开始第j+1次哈希值的计算。在具体实现的过程中，当控制哈希值计算模块开始进行哈希值计算之后，便可以不用去考虑需要计算哈希值的数据是否闪存控制器已加载至RAM，即当控制哈希值计算模块开始进行哈希值计算之后，控制哈希值计算模块进行哈希值计算的操作不再依赖闪存控制器的操作，即闪存控制器的操作和哈希值计算模块的操作是两个并行且独立的操作。
在一些实施例中，在闪存控制器完成全部数据的读取和哈希计算模块完成全部数据的哈希值计算后，还可以进行签名验证，具体过程详见S315中的描述。
S315，获取第N次哈希值的计算结果，并进行签名验证。
示例性地，将第N次哈希值的计算结果与目标哈希值进行匹配。其中，目标哈希值为软件系统的软件包对应的数据所配置的哈希值。
将第N次哈希值的计算结果与目标哈希值进行匹配，可以得到匹配结果，该匹配结果包括第N次哈希值的计算结果与目标哈希值匹配，以及第N次哈希值的计算结果与目标哈希值不匹配。
第N次哈希值的计算结果与目标哈希值匹配可以理解为该安全启动校验通过或签名验证通过。
在一些实施例中，在第N次哈希值的计算结果与目标哈希值匹配的情况下，可以执行第一预设操作，该第一预设操作为安全启动校验通过或签名验证通过时对应的操作，例如启动电子设备。
第N次哈希值的计算结果与目标哈希值不匹配可以理解为该安全启动校验失败(或不通过)或签名验证失败(或不通过)。
在一些实施例中，在第N次哈希值的计算结果与目标哈希值不匹配的情况下，可以执行第二预设操作，该第二预设操作为安全启动校验失败(或不通过)或签名验证失败(或不通过)时对应的操作，例如不启动电子设备或采用另一种安全启动检验方法重新进行校验。
通过方法300，可以在闪存控制器在读取全部数据中的第j+1组数据的过程中，哈希计算模块便可以开始第j次哈希值计算，实现将闪存控制器读取第j+1组数据的时间和哈希计算模块对第j次哈希值计算的时间的合并，不会像现有方案中必须等处理器将闪存控制器中软件系统的软件包对应的全部数据完全加载到RAM之后，哈希计算模块才能够对软件包对应的全部数据进行哈希值计算，进而减少处理器等待的时间，提高了安全启动检验的效率，降低了电子设备的启动时间，提高了用户体验。
表1示出了针对三例待读取的数据，分别通过方法300和现有方案进行数据读取耗时情况。其中，处理器数据读取的步长为128k，闪存控制器数据读取的步长为2k。例如，如表1所示，与现有方案相比，方法300的方案具有以下优点：1、对于相同的待读取的数据大小，通过方法300进行安全启动校验耗时较短。2、方法300的优化效果在90％以上。3、待读取的数据量越大，现有方案进行安全启动校验耗时明显越大，而通过该方法300进行安全启动校验耗时基本保持稳定。
表1
待读取的数据大小 现有方案耗时 方法300耗时 优化时间 优化比例
10MB 219ms 9ms 210ms 95.8％
20MB 306ms 11ms 295ms 96.4％
30MB 392ms 12ms 380ms 97.1％
在一些实施例中，在单核或单线程模式下，还可以将其他外围器件(除处理器之外的器件)处理等待时间合并，尽可能减少处理器单独等某一外围设备执行完成的情况，提高全流程的执行效率。
示例性地，外围器件可以包括加解密器件、数据压缩器件等，实现边读边解密边哈希计算或边读边解压边哈希计算，提高全流程的执行效率。
图5为本申请实施例提供的另一例安全启动校验的方法400。该方法400可以应用于电子设备，例如但不限于是IoT设备。示例性地，方法400的执行主体可以是电子设备的处理器或处理单元。
例如，如图5所示，该方法400包括：
S401，根据目标步长和目标数据的起始地址，分N次对所述目标数据进行读取，所述目标数据包括所述电子设备的软件系统的软件包对应的数据，所述N大于或等于2。
示例性地，该目标步长可以是上文方法300中所述的处理器数据读取的步长M1。
示例性地，该目标数据的起始地址可以是上文方法300中所述的处理器数据读取的起始地址。
在一些实施例中，所述电子设备包括闪存控制器，所述根据目标步长和目标数据的起始地址，分N次对所述目标数据进行读取，包括：根据所述闪存控制器的步长、所述目标步长和所述目标数据的起始地址，确定N个起始地址集合，所述N个起始地址集合中的每个起始地址集合包括n个起始地址，所述n为所述目标步长与所述闪存控制器的步长的比值；控制所述闪存控制器根据第j个起始地址集合和所述闪存控制器的步长，分n次对所述第j组数据进行读取。
应理解，对于闪存控制器而言，针对N次中的每次数据读取，闪存控制器需要再分n次读取。这样，闪存控制器需分N×n次读取目标数据。
应理解，n个起始地址可以理解为闪存控制器n次数据读取的起始地址。
示例性地，N个起始地址集合可以是上文方法300中所述的N组闪存控制器数据读取的起始地址。则N个起始地址集合中的每个起始地址集合包括的n个起始地址可以根据上述公式(2)确定。即N个起始地址集合中的第一个起始地址集合包括上文所述的第一组闪存控制器数据读取的起始地址L 0，L 1，……，L n，第二个起始地址集合包括上文所述的第二组闪存控制器数据读取的起始地址L n+1，L n+2，……，L 2n，……，第N个起始地址集合包括上文所述的第N组闪存控制器数据读取的起始地址L (N-1)×n+1，L (N-1)×n+2，……，L (N-1)×n+n。
在一些实施例中，闪存控制器还可以将第j组数据加载至RAM。
S402，在第j次数据读取后，根据所述第j次读取的第j组数据和第j-1次哈希值计算的结果，进行第j次哈希值计算，其中，所述j为大于1，且小于或等于N的整数。
在一些实施例中，上述j还可以为大于或等于1，且小于或等于N的整数。此时，在 j等于1的情况下，第0次哈希值计算的结果为0。
应理解，S402并不是在S401中完成N次数据读取之后执行，而是在S401中完成N次中的第1次数据读取之后便可执行。从而可以在读取第j+1组数据的过程中，便可以开始对第j次哈希值计算，实现将读取第j+1组数据的时间和对第j次哈希值计算的时间的合并，进而减少电子设备等待的时间，提高了安全启动检验的效率，降低了电子设备的启动时间，提高了用户体验。
在一些实施例中，所述电子设备包括哈希计算模块，所述在第j次数据读取后，根据所述第j次读取的第j组数据和第j-1次哈希值计算的结果，进行第j次哈希值计算，包括：在所述闪存控制器进行所述第j次数据读取后，控制所述哈希计算模块根据所述第j次读取的第j组数据和第j-1次哈希值计算的结果，进行第j次哈希值计算。
在一些实施例中，哈希计算模块还可以先从RAM中读取第j组数据，然后再进行第j次哈希值计算。
S403，根据第N次哈希值的计算结果，进行安全启动校验。
在一些实施例中，获取目标哈希值，所述目标哈希值为所述软件系统的软件包对应的数据所配置的哈希值；通过比较所述目标哈希值和所述第N次哈希值的计算结果，进行安全启动校验。
在一些实施例中，在所述目标哈希值和所述第N次哈希值的计算结果一致的情况下，安全启动校验通过；或，在所述目标哈希值和所述第N次哈希值的计算结果不一致的情况下，安全启动校验不通过。
在一些实施例中，所述方法400还包括：
S404，调整所述目标步长，以使第一时间大于第二时间，所述第一时间包括所述第j次数据读取所需的时间，所述第二时间包括所述第j次哈希值计算所需的时间。进而保证读取第j+1组数据的过程中，可以完成对第j组数据的哈希值计算。从而更好的减少电子设备等待的时间，提高了安全启动检验的效率，降低了电子设备的启动时间，提高了用户体验。
图6为本申请实施例提供的另一例安全启动校验的方法500。该方法500可以应用于电子设备，例如但不限于是IoT设备。示例性地，方法500的执行主体可以是电子设备的处理器或处理单元。
例如，如图6所示，该方法500包括：
S501，根据目标步长和目标数据的起始地址，从目标数据中读取第一组数据，所述目标数据包括所述电子设备的软件系统的软件包对应的数据。
示例性地，该目标步长可以是上文方法300中所述的处理器数据读取的步长M1。
示例性地，该目标数据的起始地址可以是上文方法300中所述的处理器数据读取的起始地址。
在一些实施例中，所述电子设备包括闪存控制器，所述根据目标步长和目标数据的起始地址，从目标数据中读取第一组数据，包括：根据所述闪存控制器的步长、所述目标步长和所述目标数据的起始地址，确定第一起始地址集合，所述第一起始地址集合包括n个起始地址，所述n为所述目标步长与所述闪存控制器的步长的比值；控制所述闪存控制器根据所述第一起始地址集合和所述闪存控制器的步长，分n次从所述目标数据中读取所述 第一组数据。
应理解，n个起始地址可以理解为闪存控制器n次数据读取的起始地址。
在一些实施例中，闪存控制器还可以将第一组数据加载至RAM。
S502，根据所述第一组数据，进行第一次哈希值计算，以及，根据所述目标步长和所述目标数据的起始地址，从所述目标数据中读取第二组数据，所述第二组数据和所述第一组数据是所述目标数据中不同的数据。
在一些实施例中，所述电子设备包括闪存控制器，所述根据所述目标步长和所述目标数据的起始地址，从所述目标数据中读取第二组数据，包括：根据所述闪存控制器的步长、所述目标步长和所述目标数据的起始地址，确定第二起始地址集合，所述第二起始地址集合包括n个起始地址，所述第二起始地址集合和所述第一起始地址集合不同；控制所述闪存控制器根据所述第二起始地址集合和所述闪存控制器的步长，分n次从所述目标数据中读取所述第二组数据。
示例性地，第一起始地址集合和第二起始地址分别包括的n个起始地址可以根据上述公式(2)确定。即第一起始地址集合包括上文所述的第一组闪存控制器数据读取的起始地址L 0，L 1，……，L n，第二起始地址集合包括上文所述的第二组闪存控制器数据读取的起始地址L n+1，L n+2，……，L 2n。
在一些实施例中，闪存控制器还可以将第二组数据加载至RAM。
在一些实施例中，所述电子设备包括哈希计算模块，所述根据所述第一组数据，进行第一次哈希值计算，包括：控制所述哈希计算模块根据所述第一组数据，进行第一次哈希值计算。
在一些实施例中，哈希计算模块还可以先从RAM中读取第一组数据，然后再进行第一次哈希值计算。
S503，根据所述第二组数据和所述第一次哈希值计算的结果，进行第二次哈希值计算。
在一些实施例中，所述电子设备包括哈希计算模块，所述根据所述第二组数据和所述第一次哈希值计算的结果，进行第二次哈希值计算，包括：控制所述哈希计算模块根据所述第二组数据和所述第一次哈希值计算的结果，进行第二次哈希值计算。
在一些实施例中，哈希计算模块还可以先从RAM中读取第二组数据，然后再进行第二次哈希值计算。
S504，根据所述第二次哈希值的计算结果，进行安全启动校验。
在一些实施例中，获取目标哈希值，所述目标哈希值为所述软件系统的软件包对应的数据所配置的哈希值；通过比较所述目标哈希值和所述第二次哈希值的计算结果，进行安全启动校验。
在一些实施例中，在所述目标哈希值和所述第二次哈希值的计算结果一致的情况下，安全启动校验通过；或，在所述目标哈希值和所述第二次哈希值的计算结果不一致的情况下，安全启动校验不通过。
在一些实施例中，所述方法500还包括：
S505，调整所述目标步长，以使第一时间大于第二时间，所述第一时间包括读取所述第二组数据所需的时间，所述第二时间包括所述第一次哈希值计算所需的时间。
上文结合图4至图6，详细描述了本申请提供的安全启动检验的方法，下面将结合图 7，详细描述本申请的电子设备的实施例。可以理解的是，为了实现上述实施例中功能，图7中的电子设备包括了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本申请中所公开的实施例描述的各示例的单元及方法步骤，本申请能够以硬件或硬件和计算机软件相结合的形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用场景和设计约束条件。
图7为本申请的实施例提供的一例电子设备的结构示意图。
例如，如图7所示，该电子设备700包括：读取单元701、处理单元702和检验单元703。
示例性地，该电子设备700可以是IoT设备。
在一种可能实现的方式中，读取单元701，用于根据目标步长和目标数据的起始地址，分N次对所述目标数据进行读取，所述目标数据包括所述电子设备的软件系统的软件包对应的数据，所述N大于或等于2；处理单元702，用于在第j次数据读取后，根据所述第j次读取的第j组数据和第j-1次哈希值计算的结果，进行第j次哈希值计算，其中，所述j为大于1，且小于或等于N的整数；检验单元703，用于根据第N次哈希值的计算结果，进行安全启动校验。
在一些实施例中，该电子设备700包括闪存控制器，所述处理单元702还用于：根据所述闪存控制器的步长、所述目标步长和所述目标数据的起始地址，确定N个起始地址集合，所述N个起始地址集合中的每个起始地址集合包括n个起始地址，所述n为所述目标步长与所述闪存控制器的步长的比值；所述读取单元701具体用于：控制所述闪存控制器根据第j个起始地址集合和所述闪存控制器的步长，分n次对所述第j组数据进行读取。
在一些实施例中，该电子设备700包括哈希计算模块，所述检验单元703具体用于：在所述闪存控制器进行所述第j次数据读取后，控制所述哈希计算模块根据所述第j次读取的第j组数据和第j-1次哈希值计算的结果，进行第j次哈希值计算。
在一些实施例中，该电子设备700还包括调整单元，用于调整所述目标步长，以使第一时间大于第二时间，所述第一时间包括读取所述第j次数据所需的时间，所述第二时间包括计算所述第j次哈希值所需的时间。
在一些实施例中，所述检验单元703还具体用于：获取目标哈希值，所述目标哈希值为所述软件系统的软件包对应的数据所配置的哈希值；通过比较所述目标哈希值和所述第N次哈希值的计算结果，进行安全启动校验。
在一些实施例中，在所述目标哈希值和所述第N次哈希值的计算结果一致的情况下，安全启动校验通过；或，在所述目标哈希值和所述第N次哈希值的计算结果不一致的情况下，安全启动校验不通过。
在另一种可能实现的方式中，读取单元701，用于根据目标步长和目标数据的起始地址，从目标数据中读取第一组数据，所述目标数据包括所述电子设备的软件系统的软件包对应的数据；处理单元702，用于根据所述第一组数据，进行第一次哈希值计算，以及，所述读取单元701，还用于根据所述目标步长和目标数据的起始地址，从目标数据中读取第二组数据，所述第二组数据和所述第一组数据是所述目标数据中不同的数据；所述处理单元702，还用于根据所述第二组数据和所述第一次哈希值计算的结果，进行第二次哈希值计算；检验单元703，用于根据所述第二次哈希值的计算结果，进行安全启动校验。
在一些实施例中，该电子设备700包括闪存控制器，所述处理单元702还用于：根据所述闪存控制器的步长、所述目标步长和所述目标数据的起始地址，确定第一起始地址集合，所述第一起始地址集合包括n个起始地址，所述n为所述目标步长与所述闪存控制器的步长的比值；所述读取单元701具体用于：控制所述闪存控制器根据所述第一起始地址集合和所述闪存控制器的步长，分n次从所述目标数据中读取所述第一组数据。
在一些实施例中，所述处理单元702还用于：根据所述闪存控制器的步长、所述目标步长和所述目标数据的起始地址，确定第二起始地址集合，所述第二起始地址集合包括n个起始地址，所述第二起始地址集合和所述第一起始地址集合不同；所述读取单元701还具体用于：控制所述闪存控制器根据所述第二起始地址集合和所述闪存控制器的步长，分n次从所述目标数据中读取所述第二组数据。
在一些实施例中，该电子设备包括哈希计算模块，所述处理单元702还用于：控制所述哈希计算模块根据所述第一组数据，进行第一次哈希值计算；控制所述哈希计算模块根据所述第二组数据和所述第一次哈希值计算的结果，进行第二次哈希值计算。
在一些实施例中，该电子设备700还包括调整单元，用于调整所述目标步长，以使第一时间大于第二时间，所述第一时间包括读取所述第二组数据所需的时间，所述第二时间包括计算所述第一次哈希值所需的时间。
在一些实施例中，所述检验单元703还具体用于：获取目标哈希值，所述目标哈希值为所述软件系统的软件包对应的数据所配置的哈希值；通过比较所述目标哈希值和所述第二次哈希值的计算结果，进行安全启动校验。
在一些实施例中，在所述目标哈希值和所述第二次哈希值的计算结果一致的情况下，安全启动校验通过；或，在所述目标哈希值和所述第二次哈希值的计算结果不一致的情况下，安全启动校验不通过。
上述各个附图对应的流程的描述各有侧重，某个流程中没有详述的部分，可以参见其他流程的相关描述。
本申请实施例还提供一种电子设备，包括：一个或多个处理器；一个或多个存储器；该一个或多个存储器存储有一个或多个计算机程序，该一个或多个计算机程序包括指令，当该指令被一个或多个处理器执行时，使得如前文中的方法被执行。
示例性地，该电子设备为IoT设备。
本申请实施例还提供一种计算机可读存储介质，所述计算机可读存储介质具有程序指令，当所述程序指令被直接或者间接执行时，使得前文中的方法得以实现。
本申请实施例还提供了一种包含指令的计算机程序产品，当其在计算设备上运行时，使得计算设备执行前文中的方法，或者使得所述计算设备实现前文中的电子设备的功能。
本申请实施例还提供一种芯片，包括至少一个处理器和接口电路，所述接口电路用于为所述至少一个处理器提供程序指令或者数据，所述至少一个处理器用于执行所述程序指令，使得前文中的方法得以实现。
上述实施例，可以全部或部分地通过软件、硬件、固件或其他任意组合来实现。当使用软件实现时，上述实施例可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令或计算机程序。在计算机上加载或执行所述计算机指令或计算机程序时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机 可以为通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集合的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质。半导体介质可以是固态硬盘。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种安全启动校验的方法，其特征在于，所述方法应用于电子设备，所述方法包括：
    根据目标步长和目标数据的起始地址，分N次对所述目标数据进行读取，所述目标数据包括所述电子设备的软件系统的软件包对应的数据，所述N大于或等于2；
    在第j次数据读取后，根据所述第j次读取的第j组数据和第j-1次哈希值计算的结果，进行第j次哈希值计算，其中，所述j为大于1，且小于或等于N的整数；
    根据第N次哈希值的计算结果，进行安全启动校验。
  2. 根据权利要求1所述的方法，其特征在于，所述电子设备包括闪存控制器，所述根据目标步长和目标数据的起始地址，分N次对所述目标数据进行读取，包括：
    根据所述闪存控制器的步长、所述目标步长和所述目标数据的起始地址，确定N个起始地址集合，所述N个起始地址集合中的每个起始地址集合包括n个起始地址，所述n为所述目标步长与所述闪存控制器的步长的比值；
    控制所述闪存控制器根据第j个起始地址集合和所述闪存控制器的步长，分n次对所述第j组数据进行读取。
  3. 根据权利要求2所述的方法，其特征在于，所述电子设备包括哈希计算模块，所述在第j次数据读取后，根据所述第j次读取的第j组数据和第j-1次哈希值计算的结果，进行第j次哈希值计算，包括：
    在所述闪存控制器进行所述第j次数据读取后，控制所述哈希计算模块根据所述第j次读取的第j组数据和第j-1次哈希值计算的结果，进行第j次哈希值计算。
  4. 根据权利要求1至3中任一项所述的方法，其特征在于，所述方法还包括：
    调整所述目标步长，以使第一时间大于第二时间，所述第一时间包括所述第j次数据读取所需的时间，所述第二时间包括所述第j次哈希值计算所需的时间。
  5. 根据权利要求1至4中任一项所述的方法，其特征在于，所述根据第N次哈希值的计算结果，进行安全启动校验，包括：
    获取目标哈希值，所述目标哈希值为所述软件系统的软件包对应的数据所配置的哈希值；
    通过比较所述目标哈希值和所述第N次哈希值的计算结果，进行安全启动校验。
  6. 根据权利要求5所述的方法，其特征在于，所述通过比较所述目标哈希值和所述第N次哈希值的计算结果，进行安全启动校验，包括：
    在所述目标哈希值和所述第N次哈希值的计算结果一致的情况下，安全启动校验通过；或，
    在所述目标哈希值和所述第N次哈希值的计算结果不一致的情况下，安全启动校验不通过。
  7. 一种安全启动校验的方法，其特征在于，所述方法应用于电子设备，所述方法包括：
    根据目标步长和目标数据的起始地址，从目标数据中读取第一组数据，所述目标数据 包括所述电子设备的软件系统的软件包对应的数据；
    根据所述第一组数据，进行第一次哈希值计算，以及，根据所述目标步长和所述目标数据的起始地址，从所述目标数据中读取第二组数据，所述第二组数据和所述第一组数据是所述目标数据中不同的数据；
    根据所述第二组数据和所述第一次哈希值计算的结果，进行第二次哈希值计算；
    根据所述第二次哈希值的计算结果，进行安全启动校验。
  8. 根据权利要求7所述的方法，其特征在于，所述电子设备包括闪存控制器，所述根据目标步长和目标数据的起始地址，从目标数据中读取第一组数据，包括：
    根据所述闪存控制器的步长、所述目标步长和所述目标数据的起始地址，确定第一起始地址集合，所述第一起始地址集合包括n个起始地址，所述n为所述目标步长与所述闪存控制器的步长的比值；
    控制所述闪存控制器根据所述第一起始地址集合和所述闪存控制器的步长，分n次从所述目标数据中读取所述第一组数据。
  9. 根据权利要求8所述的方法，其特征在于，所述根据所述目标步长和所述目标数据的起始地址，从所述目标数据中读取第二组数据，包括：
    根据所述闪存控制器的步长、所述目标步长和所述目标数据的起始地址，确定第二起始地址集合，所述第二起始地址集合包括n个起始地址，所述第二起始地址集合和所述第一起始地址集合不同；
    控制所述闪存控制器根据所述第二起始地址集合和所述闪存控制器的步长，分n次从所述目标数据中读取所述第二组数据。
  10. 根据权利要求8或9所述的方法，其特征在于，所述电子设备包括哈希计算模块，
    所述根据所述第一组数据，进行第一次哈希值计算，包括：
    控制所述哈希计算模块根据所述第一组数据，进行第一次哈希值计算；
    所述根据所述第二组数据和所述第一次哈希值计算的结果，进行第二次哈希值计算，包括：
    控制所述哈希计算模块根据所述第二组数据和所述第一次哈希值计算的结果，进行第二次哈希值计算。
  11. 根据权利要求7至10中任一项所述的方法，其特征在于，所述方法还包括：
    调整所述目标步长，以使第一时间大于第二时间，所述第一时间包括读取所述第二组数据所需的时间，所述第二时间包括所述第一次哈希值计算所需的时间。
  12. 根据权利要求7至11中任一项所述的方法，其特征在于，所述根据第二次哈希值的计算结果，进行安全启动校验，包括：
    获取目标哈希值，所述目标哈希值为所述软件系统的软件包对应的数据所配置的哈希值；
    通过比较所述目标哈希值和所述第二次哈希值的计算结果，进行安全启动校验。
  13. 根据权利要求12所述的方法，其特征在于，所述通过比较所述目标哈希值和所述第二次哈希值的计算结果，进行安全启动校验，包括：
    在所述目标哈希值和所述第二次哈希值的计算结果一致的情况下，安全启动校验通过；或，
    在所述目标哈希值和所述第二次哈希值的计算结果不一致的情况下，安全启动校验不通过。
  14. 一种电子设备，其特征在于，所述电子设备包括一个或多个处理器；一个或多个存储器；所述一个或多个存储器存储有一个或者多个计算机程序，所述一个或者多个计算机程序包括指令，当所述指令被所述一个或多个处理器执行时，使得所述电子设备执行如权利要求1至13中任一项所述的安全启动校验的方法。
  15. 根据权利要求14所述的电子设备，其特征在于，所述电子设备为物联网IoT设备。
  16. 一种计算机可读存储介质，其特征在于，包括计算机指令，当所述计算机指令在电子设备上运行时，使得所述电子设备执行如权利要求1至13中任一项所述的安全启动校验的方法。
  17. 一种芯片，其特征在于，包括至少一个处理器和接口电路，所述接口电路用于为所述至少一个处理器提供程序指令或者数据，所述至少一个处理器用于执行所述程序指令，以实现如权利要求1至13中任一项所述的安全启动校验的方法。
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