WO2023019889A1 - 报文处理方法、装置、设备及计算机可读存储介质 - Google Patents

报文处理方法、装置、设备及计算机可读存储介质 Download PDF

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Publication number
WO2023019889A1
WO2023019889A1 PCT/CN2022/075530 CN2022075530W WO2023019889A1 WO 2023019889 A1 WO2023019889 A1 WO 2023019889A1 CN 2022075530 W CN2022075530 W CN 2022075530W WO 2023019889 A1 WO2023019889 A1 WO 2023019889A1
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Prior art keywords
message
key feature
group
chip
same
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PCT/CN2022/075530
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English (en)
French (fr)
Inventor
徐华东
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华为技术有限公司
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Priority claimed from CN202111278136.5A external-priority patent/CN115914103A/zh
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2023019889A1 publication Critical patent/WO2023019889A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/74—Address processing for routing
    • H04L45/745—Address table lookup; Address filtering
    • H04L45/7453—Address table lookup; Address filtering using hashing

Definitions

  • the present application relates to the technical field of communications, and in particular to a message processing method, device, equipment, and computer-readable storage medium.
  • the forwarding device In the process of message-based communication, after receiving the message, the forwarding device will process the received message based on the message characteristics of the message. In the related art, the forwarding device acquires the message characteristics of the received message, performs table entry search and business logic processing corresponding to the message based on the message feature, and obtains the processed message.
  • the forwarding device will perform the process of obtaining message characteristics, and performing table entry search and business logic processing corresponding to the message based on the message characteristics.
  • the device resources used by the forwarding device to perform packet processing tend to become the bottleneck of packet processing.
  • the present application proposes a message processing method, device, device, and computer-readable storage medium, which are used to reduce resource requirements for message processing and improve message processing efficiency.
  • a message processing method includes: a first chip acquires multiple messages with the same key feature; group the multiple messages to obtain at least one message group; for at least one Each packet group in the packet group executes processing corresponding to the key feature for each packet belonging to the same packet group.
  • the number of key features is at least one.
  • the method can reduce the device resources required by the first chip for processing each message by performing processing corresponding to the key feature for each message belonging to the same message group and having the same key feature.
  • the first chip can perform processing corresponding to the key feature on each message in one processing process, and the efficiency of message processing is high.
  • each packet in the same packet group includes complete packet header data
  • the complete packet header data includes key features. Since each message of the same message group includes complete message header data, the first chip subsequently performs the processing corresponding to the key features and the data required for the processing corresponding to the non-key features of each message, and there is no need to obtain it again Execute the data required for processing, and the message processing efficiency is high.
  • the first message in the same message group includes complete message header data
  • the second message in the same message group includes message header difference data
  • the first message is the same Any message in the message group
  • the second message is other messages in the same message group except the first message; wherein, the complete message header data includes key features, and the message header difference data is based on the first message
  • the difference between the header data of the second message and the header data of the first message is determined. Since the second message includes header difference data, and the amount of data included in the message group is less than the amount of data including complete header data in the second message, the first chip subsequently transmits the message group to the first chip When processed by the processing module, the device resources required for transmission are low.
  • the first message in the same message group includes complete message header data
  • the second message in the same message group includes a descriptor
  • the first message is the same message group
  • Any message in the same message group, the second message is other messages except the first message in the same message group; wherein, the complete message header data includes key features, and the descriptor is used to obtain the second message including The complete packet header data. Since the second message includes the descriptor, the amount of data included in the message group is smaller than the amount of data included in the second message including the header difference data, and even smaller than the amount of data included in the second message including the complete header data.
  • the method further includes: the first chip performs processing corresponding to non-key features on each packet, where the non-key features are other data in the complete packet header data except the key features.
  • the method further includes: the first chip performs processing corresponding to non-key features on the first message, where the non-key features are data other than key features in the complete message header data; A chip executes processing corresponding to the difference data in the header of the second packet.
  • the method further includes: the first chip performs processing corresponding to a first non-key feature on the first message, where the first non-key feature is a complete message header of the first message Other data in the data except the key features; the first chip obtains the complete message header data of the second message based on the descriptor, wherein the complete message header data of the second message includes the key features and the second non-key feature feature, the second non-key feature is data other than the key feature in the complete message header data of the second message; the first chip performs processing corresponding to the second non-key feature on the second message.
  • the first chip acquires multiple messages with the same key feature, including: the first chip acquires multiple messages, and acquires the characteristics of each key feature of each message in the multiple messages value; the first chip obtains the hash value of each message based on the feature value of each key feature of each message; the first chip determines whether the key features of each message are the same based on the hash value of each message.
  • the first chip obtains the hash value of each message based on the feature value of each key feature of each message, including: the first chip based on the feature value of each key feature of each message and The first hash algorithm obtains the first hash value of each message; the first chip obtains the second hash value of each message based on the feature value of each key feature of each message and the second hash algorithm; the second A chip uses the first hash value of each message and the second hash value of each message as the hash value of each message. Since the hash value of each message includes the first hash value of each message and the second hash value of each message, the first chip subsequently determines whether the key features of each message are consistent based on the hash value of each message. At the same time, the accuracy is higher.
  • the first chip obtains the hash value of each message based on the feature value of each key feature of each message, including: the first chip based on the feature value of each key feature of each message and The third hash algorithm obtains the third hash value of each message; for each key feature of each message, the first chip obtains the fourth hash value of each key feature based on the feature value of each key feature and the fourth hash algorithm.
  • Hash value the first chip uses the third hash value of each message and the fourth hash value of each key feature of each message as the hash value of each message. Since the hash value of each message includes the third hash value and the fourth hash value of each key feature, the first chip subsequently determines whether the key features of each message are the same based on the hash value of each message, accurately Sex is higher.
  • the first chip determines whether the key features of each message are the same based on the hash value of each message, including: the first chip obtains at least one Cache group: For each cache group in at least one cache group, the first chip determines whether the key features of each message belonging to the same cache group are the same based on the second hash value of each message belonging to the same cache group. Since the method can obtain at least one cache group based on the first hash value of each message, and determine whether the key feature of each message belonging to the same cache group is based on the second hash value of each message belonging to the same cache group Similarly, while the accuracy of determining whether the key features of each message are the same is high, the determination efficiency is also high.
  • the first chip determines whether the key features of each message are the same based on the hash value of each message, including: the first chip obtains at least one Cache group; for each cache group in at least one cache group, the first chip determines whether the key features of each message belonging to the same cache group are based on the fourth hash value of each key feature of each message belonging to the same cache group same. Because the method can obtain at least one cache group based on the third hash value of each message, and determine the number of each message belonging to the same cache group based on the fourth hash value of the key feature of each message belonging to the same cache group Whether the key features are the same, while determining whether the key features of each message are the same, the accuracy is high, and the determination efficiency is also high.
  • the key feature includes at least one of an ingress port number, a destination media access control MAC address, a destination Internet Protocol IP address, a source IP address, and a source MAC address.
  • the type of key features in this method is more flexible.
  • the resource used by the first chip to perform processing corresponding to the key feature for any message is based on the performance of the first chip 1.
  • the number of packets included in the packet group in which any packet belongs and the cost of performing the processing corresponding to the key feature are determined.
  • the resources used by the first chip to perform processing corresponding to key features for any message are based on the performance of the first chip, the number of messages included in the message group in which any message belongs, and the execution key
  • the cost of the processing corresponding to the feature is determined according to the following formula:
  • R1 is the resource used by the first chip to perform the processing corresponding to the key feature for any message
  • P is the performance of the first chip
  • N is the number of messages included in the message group where any message is located
  • A is The cost of performing the processing corresponding to the key feature. Since the number of messages belonging to the same message group is larger, for any message in the messages of the same message group, the resources used by the first chip to perform processing corresponding to key features on any message are more Low. Therefore, compared with the method in the related art, the method requires less device resources to process the same number of packets.
  • a message processing device in a second aspect, includes:
  • An acquisition module configured to acquire multiple messages with the same key feature, wherein the number of key features is at least one;
  • a grouping module configured to group multiple messages to obtain at least one message group
  • the processing module is configured to, for each packet group in at least one packet group, perform processing corresponding to key features on each packet belonging to the same packet group.
  • each packet in the same packet group includes complete packet header data, and the complete packet header data includes key features.
  • the first message in the same message group includes complete message header data
  • the second message in the same message group includes message header difference data
  • the first message is the same Any message in the message group
  • the second message is other messages in the same message group except the first message;
  • the complete message header data includes key features
  • the message header difference data is based on the first message The difference between the header data of the second message and the header data of the first message is determined.
  • the first message in the same message group includes complete message header data
  • the second message in the same message group includes a descriptor
  • the first message is the same message group
  • Any message in the same message group, the second message is other messages except the first message in the same message group; wherein, the complete message header data includes key features, and the descriptor is used to obtain the second message including The complete packet header data.
  • the processing module is further configured to perform processing corresponding to non-key features on each packet, where the non-key features are data other than the key features in the complete packet header data.
  • the processing module is further configured to perform processing corresponding to non-key features on the first message, where the non-key features are data other than key features in the complete message header data; The message performs the processing corresponding to the difference data in the message header.
  • the processing module is further configured to perform processing corresponding to the first non-key feature on the first message, where the first non-key feature is in the complete message header data of the first message Other data except the key features; obtain the complete message header data of the second message based on the descriptor, wherein the complete message header data of the second message includes the key feature and the second non-key feature, and the second non-key feature
  • the key feature is data other than the key feature in the complete packet header data of the second packet; the processing corresponding to the second non-key feature is performed on the second packet.
  • the acquiring module is configured to acquire multiple messages, and acquire the feature values of each key feature of each message in the multiple messages; based on the feature value of each key feature of each message, Obtain the hash value of each message; determine whether the key features of each message are the same based on the hash value of each message.
  • the obtaining module is configured to obtain the first hash value of each message based on the characteristic value of each key feature of each message and the first hash algorithm;
  • the feature value of the feature and the second hash algorithm are used to obtain the second hash value of each message;
  • the first hash value of each message and the second hash value of each message are used as the hash value of each message .
  • the obtaining module is configured to obtain the third hash value of each message based on the characteristic value of each key feature of each message and the third hash algorithm; for each key of each message feature, based on the feature value of each key feature and the fourth hash algorithm, the fourth hash value of each key feature is obtained; the third hash value of each message and the fourth hash value of each key feature of each message The value is used as the hash value of each message.
  • the obtaining module is configured to obtain at least one cache group based on the first hash value of each message; for each cache group in the at least one cache group, based on each message belonging to the same cache group The second hash value of the text is used to determine whether the key features of the packets belonging to the same cache group are the same.
  • the obtaining module is configured to obtain at least one cache group based on the third hash value of each message; for each cache group in the at least one cache group, based on each message belonging to the same cache group The fourth hash value of each key feature of the document, and determine whether the key features of the messages belonging to the same cache group are the same.
  • the key feature includes at least one of an ingress port number, a destination media access control MAC address, a destination Internet Protocol IP address, a source IP address, and a source MAC address.
  • the resource used by the processing module to process any message corresponding to the key feature is based on the performance of the processing module, any The number of messages included in the message group to which a message belongs and the cost of performing the processing corresponding to the key feature are determined.
  • the resources used by the processing module to perform processing corresponding to key features for any message are based on the performance of the processing module, the number of messages included in the message group in which any message belongs, and the execution key feature correspondence
  • the processing cost of is determined according to the following formula:
  • R1 is the resource used by the processing module to perform the processing corresponding to the key feature of any message
  • P is the performance of the processing module
  • N is the number of messages included in the message group of any message
  • A is the execution key The cost of the processing corresponding to the feature.
  • a network device in a third aspect, includes: a processor, the processor is coupled to a memory, at least one program instruction or code is stored in the memory, and at least one program instruction or code is loaded and executed by the processor to The network device is made to implement any packet processing method in the first aspect above.
  • a computer-readable storage medium is provided. At least one program instruction or code is stored in the computer-readable storage medium. When the program instruction or code is loaded and executed by a processor, the computer can realize the Any packet processing method.
  • a computer program product including a computer program.
  • the computer program When the computer program is executed by a computer, the computer implements the message processing method in any one of the above first aspects.
  • a communication device includes: a communication interface, a memory, and a processor.
  • the memory and the processor communicate with each other through an internal connection path, the memory is used to store instructions, and the processor is used to execute the instructions stored in the memory to control the communication interface to receive data and control the communication interface to send data, and when the When the processor executes the instructions stored in the memory, the processor is made to execute the first aspect or the method in any possible implementation manner of the first aspect.
  • processors there are one or more processors, and one or more memories.
  • the memory may be integrated with the processor, or the memory may be separated from the processor.
  • the memory can be a non-transitory (non-transitory) memory, for example, a read-only memory (read only memory, ROM), which can be integrated with the processor on the same chip, or can be set in different On the chip, the application does not limit the type of the memory and the arrangement of the memory and the processor.
  • a non-transitory memory for example, a read-only memory (read only memory, ROM), which can be integrated with the processor on the same chip, or can be set in different On the chip, the application does not limit the type of the memory and the arrangement of the memory and the processor.
  • a chip including a processor, which is used to call and execute instructions stored in the memory from the memory, so that the communication device installed with the chip executes any one of the above-mentioned first aspect or any possible method of the first aspect. method in the implementation.
  • another chip including: an input interface, an output interface, a processor, and a memory, the input interface, the output interface, the processor, and the memory are connected through an internal connection path, and the processor is used to execute the code in the memory , when the code is executed, the processor is configured to execute the method in the foregoing first aspect or any possible implementation manner of the first aspect.
  • a device including any chip in the above solution.
  • FIG. 1 is a schematic diagram of an implementation environment of a message processing method provided in an embodiment of the present application
  • FIG. 2 is a flow chart of a message processing method provided in an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a message processing process provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a message processing device provided in an embodiment of the present application.
  • Fig. 5 is a schematic structural diagram of a network device provided by an embodiment of the present application.
  • the embodiment of the present application provides a packet processing method, and the implementation environment of the method may be shown in the packet processing architecture diagram in FIG. 1 .
  • the packet processing architecture shown in FIG. 1 is applied to a chip, and the chip is set in a device such as a terminal, a network device, or a server.
  • the message processing architecture includes a control module 101 , an analysis module 102 and a processing module 103 , and information transmission can be performed between the control module 101 , the analysis module 102 and the processing module 103 .
  • control module 101 is used to send configuration information, for example, the control module 101 sends configuration information to the analysis module 102, and the configuration information is used to indicate the type of key information; the analysis module 102 is used to obtain the message header data of the message, based on The key features included in the message header data group multiple messages with the same key feature; the processing module 103 is used to process the messages.
  • the processing module 103 includes at least one submodule.
  • the processing module 103 includes an interface submodule 1031 , a tunnel termination submodule 1032 , a forwarding submodule 1033 and a modification submodule 1034 .
  • the interface sub-module 1031 is used to perform interface processing, for example, check the maximum transmission unit (maximum transmission unit, MTU) of the message, and control the committed access rate (committed access rate, CAR) of the message;
  • the tunnel termination sub-module 1032 It is used to perform tunnel termination processing when the message is a tunnel type message and needs to be terminated locally;
  • the forwarding submodule 1033 is used to perform forwarding processing based on the processing results of the interface submodule 1031 and the tunnel termination submodule 1032, for example, perform Routing forwarding;
  • the modifying submodule 1034 is used to modify the message and send it to the egress port.
  • different modules can be set according to actual message processing requirements, and the message processing architecture can include more additional modules than the shown modules or omit some of the shown modules. This embodiment of the present application does not limit it.
  • the message processing method provided by the embodiment of the present application includes but is not limited to S201 to S203. Wherein, the method is executed by the first chip, and the application does not limit the type of the first chip.
  • the first chip acquires multiple packets with the same key feature.
  • the number of key features is at least one.
  • the type of the key feature is the type indicated by the configuration information.
  • the key features include ingress port number, destination media access control (media access control address, MAC) address, destination Internet protocol (internet protocol, IP) address, source IP address, source MAC at least one of the addresses.
  • the types of key features in the embodiments of the present application are relatively flexible. It should be noted that the embodiment of the present application does not limit the manner of indicating the type of key information through the configuration information.
  • the acquisition by the first chip of multiple packets having the same key feature includes but is not limited to S2011 to S2013.
  • the first chip acquires a plurality of packets, and acquires characteristic values of key features of each packet in the plurality of packets.
  • the multiple packets acquired by the first chip are packets received by the first chip and sent by other devices, or multiple packets generated by the first chip.
  • the key features are included in the packet header data, and the first chip obtains the characteristic values of each key feature of each message, including: the first chip obtains each of the message header data of each message The eigenvalues of the key features.
  • the key feature includes a destination MAC address and a destination IP address
  • the characteristic value of the key feature of the any message includes the destination MAC address and the destination IP address of the any message .
  • the first chip obtains the characteristic value of each key feature in the message header data of each message, including: the first chip obtains the message header data of each message The destination MAC address and destination IP address of each packet in the
  • the process of obtaining multiple packets may refer to the process of receiving packets by the parsing module shown in FIG. 3 .
  • the first chip acquires a hash value of each message based on the feature value of each key feature of each message.
  • the first chip acquires the hash value of each message based on the feature value of each key feature of each message, including but not limited to the following two ways.
  • the first chip obtains the hash value of each message based on one hash calculation.
  • the first chip acquires the hash value of each message based on the feature value of each key feature of each message and a reference hash algorithm.
  • the first chip calculates a hash value based on the feature value of each key feature of each message and a reference hash algorithm, and uses the hash value as the hash value of the message.
  • the key features include the destination MAC address and the destination IP address.
  • the first chip obtains two messages, namely message 1 and message 2. For message 1, the first chip based on the destination MAC address of message 1 1.
  • the destination IP address 1 and the reference hash algorithm are calculated to obtain a hash value 1, and the hash value 1 is used as the hash value of message 1; for message 2, the first chip is based on the destination MAC of message 2
  • the address 2, the destination IP address 2, and the hash algorithm are used to calculate a hash value 2, and the hash value 2 is used as the hash value of the message 2.
  • the reference hash algorithm includes but is not limited to any one of a cyclic redundancy check (cyclic redundancy check, CRC) algorithm or a folded XOR algorithm, wherein the CRC algorithm includes but is not limited to the CRC-32 algorithm, CRC Either of the -16 algorithm or the CRC-8 algorithm.
  • CRC cyclic redundancy check
  • each message Since the hash value of each message is obtained based on one hash calculation, each message has only one hash value. Therefore, when the first chip subsequently determines whether the key features of each message are the same based on the hash value of each message, the determination efficiency is relatively high.
  • the first chip obtains the hash value of each packet based on two hash calculations.
  • the first chip acquires the hash value of each message based on the feature value of each key feature of each message, including but not limited to mode 2A and mode 2B.
  • the first chip acquires the first hash value of each message based on the feature value of each key feature of each message and the first hash algorithm.
  • the first chip acquires a second hash value of each message based on the feature value of each key feature of each message and the second hash algorithm.
  • the second hash algorithm includes but is not limited to any one of the CRC algorithm or the folding XOR algorithm, wherein the CRC algorithm includes but is not limited to CRC-32 algorithm, CRC-16 algorithm or CRC-8 algorithm any kind.
  • the second hash algorithm is a different algorithm from the first hash algorithm.
  • the first chip obtains the second hash value of each message based on the eigenvalues of each key feature of each message and the second hash algorithm, which is the same as the principle of the related process in the above method 1, and will not be repeated here.
  • the first chip uses the first hash value of each message and the second hash value of each message as the hash value of each message.
  • the first chip uses the first hash value of the message 2 and the second hash value of the message 2 as the hash value of the message 2.
  • the first chip realizes obtaining the hash value of each packet.
  • the first chip Since the hash value of each message includes the first hash value of each message and the second hash value of each message, the first chip subsequently determines whether the key features of each message are consistent based on the hash value of each message. At the same time, the accuracy is higher.
  • way 2B includes but is not limited to S20124 to S20126.
  • the first chip acquires a third hash value of each message based on the feature value of each key feature of each message and the third hash algorithm.
  • the third hash algorithm includes but is not limited to any one of the CRC algorithm or the folding XOR algorithm, wherein the CRC algorithm includes but is not limited to CRC-32 algorithm, CRC-16 algorithm or CRC-8 algorithm any kind.
  • the first chip obtains the third hash value of each message based on the eigenvalues of each key feature of each message and the third hash algorithm.
  • the first chip acquires a fourth hash value of each key feature based on the feature value of each key feature and the fourth hash algorithm.
  • the fourth hash algorithm includes but is not limited to any one of the CRC algorithm or the folding XOR algorithm, wherein the CRC algorithm includes but is not limited to CRC-32 algorithm, CRC-16 algorithm or CRC-8 algorithm any kind. It should be noted that the fourth hash algorithm may be the same as or different from the third hash algorithm, which is not limited in this embodiment of the present application.
  • the first chip obtains the fourth hash value of each key feature based on the feature value of each key feature and the fourth hash algorithm, including: the first chip based on the feature value of each key feature and the fourth hash algorithm, calculate a hash value, and use the hash value as the fourth hash value of the key feature.
  • the key features include the destination MAC address and the destination IP address.
  • the first chip obtains two messages, namely message 1 and message 2. For message 1, the first chip based on the destination MAC address of message 1 and the fourth hash algorithm, calculate the fourth hash value of the destination MAC address of message 1, and calculate the fourth hash value of the destination IP address of message 1 based on the destination IP address of message 1 and the fourth hash algorithm Hash value; for message 2, the first chip calculates the fourth hash value of the destination MAC address of message 2 based on the destination MAC address of message 2 and the fourth hash algorithm, based on the destination IP address of message 2 The address and the fourth hash algorithm are used to calculate the fourth hash value of the destination IP address of the message 2.
  • the first chip uses the third hash value of each message and the fourth hash value of each key feature of each message as the hash value of each message.
  • the first chip obtains two packets, namely packet 1 and packet 2, as an example for illustration.
  • the first chip calculates the third hash value of message 1, the fourth hash value of the destination MAC address of message 1, and the destination IP address of message 1.
  • the hash value of message 1 includes: the third hash value of message 1, the fourth hash value of the destination MAC address of message 1, and the fourth hash value of the destination IP address of message 1 value.
  • the first chip uses the third hash value of message 2, the fourth hash value of the destination MAC address of message 2, and the fourth hash value of the destination IP address of message 2 as the hash value of message 2. Greek value.
  • the first chip realizes obtaining the hash value of each packet.
  • the first chip subsequently determines whether the key features of each message are the same based on the hash value of each message, accurately Sex is higher.
  • the first chip may also obtain the hash value of each message based on triple hash calculation. For example, the first chip obtains the first hash value of each message based on the feature value of each key feature of each message and the first hash algorithm; based on the feature value of each key feature of each message and the second hash The algorithm is used to obtain the second hash value of each message; based on the characteristic value of each key feature of each message and the fifth hash algorithm, the fifth hash value of each message is obtained.
  • the first hash algorithm, the second hash algorithm and the fifth hash algorithm are different algorithms respectively. The first hash value, the second hash value and the fifth hash value of each message are used as the hash value of each message.
  • the accuracy of the first chip is relatively high when subsequently determining whether the key features of each message are the same based on the hash value of each message.
  • the first chip may also use more hash calculations to obtain each hash value, so as to further improve the accuracy of determining whether the key features of each message are the same.
  • the first chip determines whether the key features of each message are the same based on the hash value of each message.
  • the first chip determines whether the key features of each message are the same based on the hash value of each message, including but not limited to the following three Way.
  • the first chip determines whether the key features of each message are the same based on the hash value of each message.
  • the method 1 can be used to determine whether the key features of the packets are the same. Wherein, in response to the hash values of the two messages being the same, the key features of the two messages are the same; in response to the hash values of the two messages being different, the key features of the two messages are different.
  • the first chip can determine whether the key features of the packets are the same.
  • the first chip determines whether the key features of each message are the same based on the first hash value of each message and the second hash value of each message.
  • the method 2 can be used to determine whether the key features of the packets are the same.
  • the first chip determines whether the key features of each message are the same based on the hash value of each message in the multiple messages, including but not limited to S20131 and S20132.
  • the first chip acquires at least one cache group based on the first hash value of each message.
  • the first chip has at least one set of caches, and the first chip stores each message in the first At least one cache group is obtained from the caches with the mapping relationship between the hash values.
  • the embodiment of the present application does not limit the manner in which the first chip obtains the mapping relationship between the hash value and the cache.
  • the first chip stores the mapping relationship between the hash value and the cache, or the first chip obtains the hash The mapping relationship between hash value and cache.
  • packets with the same first hash value will be stored in the same cache group, and the first chip determines the packets with the same first hash value as packets belonging to the same cache group.
  • the key features include the destination MAC address and the destination IP address
  • the multiple packets acquired by the first chip include packet 1, packet 2, and packet 3, wherein the first hash value of packet 1 is the same as the first hash value of packet 2.
  • the first hash value of message 1 is the same, the first hash value of message 1 is different from the first hash value of message 3, and the first chip is based on the first hash value of message 1 and the first hash value of message 2.
  • Hash value and the first hash value of message 3 two cache groups are obtained, message 1 and message 2 belong to one of the two cache groups, and message 3 belongs to the cache group of the two cache groups Another cache group.
  • the first chip determines whether the key features of the packets belonging to the same cache group are the same based on the second hash values of the packets belonging to the same cache group.
  • the first chip can determine whether the key features of the packets belonging to the same cache group are the same.
  • the first chip is based on the second hash value of message 1 and the second hash value of message 2 value to determine whether the key features of message 1 and message 2 are the same.
  • the first chip determines whether the key features of each message are the same based on the hash value of each message, including: get at least one cache group; for each cache group in at least one cache group, based on the rest of the three hash values of the packets belonging to the same cache group value to determine whether the key characteristics of the packets belonging to the same cache group are the same.
  • the hash value of each message includes a first hash value, a second hash value and a fifth hash value
  • the first chip obtains at least one cache group based on the first hash value of each message; for at least Each cache group in a cache group determines whether the key features of the packets belonging to the same cache group are the same based on the second hash value and the fifth hash value of the packets belonging to the same cache group. If the second hash values of two messages belonging to the same cache group are the same, and the fifth hash values of the two messages are the same, then the key features of the two messages are the same. It should be noted that if the hash value of each message includes more hash values, the process of the first chip determining whether the key features of each message are the same is the same as the principle of the above process, and will not be repeated here.
  • the first chip determines whether the key features of the messages are the same based on the third hash value of the messages and the fourth hash value of the key features of the messages.
  • the method 3 can be used to determine whether the key features of the packets are the same.
  • the first chip determines whether the key features of each message are the same based on the hash value of each message in the multiple messages, including but not limited to S20133 and S20134.
  • the first chip acquires at least one cache group based on the third hash value of each message.
  • the first chip determines whether the key features of each message belonging to the same cache group are the same based on the fourth hash value of each key feature of each message belonging to the same cache group .
  • the first chip can determine whether the key features of the packets belonging to the same cache group are the same.
  • the first chip is based on the fourth hash value of the destination MAC address of message 1 and the fourth hash value of the destination IP address, and the fourth hash value of the destination MAC address of message 2 and the fourth hash value of the destination IP address. Hash value, to determine whether the key features of message 1 and message 2 are the same.
  • the first chip determines whether the fourth hash value of the destination MAC address of message 1 is the same as the fourth hash value of the destination MAC address of message 2, and the fourth hash value of the destination IP address of message 1 Whether the value is the same as the fourth hash value of the destination IP address of the message 2; the fourth hash value of the destination MAC address of the response message 1 is the same as the fourth hash value of the destination MAC address of the message 2, and The fourth hash value of the destination IP address of message 1 is the same as the fourth hash value of the destination IP address of message 2, and the first chip determines that the key features of message 1 and message 2 are the same; in response to message 1
  • the fourth hash value of the destination MAC address of packet 2 is different from the fourth hash value of the destination MAC address of packet 2, and/or the fourth hash value of the destination IP address of packet 1 is different from the fourth hash value of the destination IP address of packet 2.
  • the fourth hash value of the address is different, and the first chip determines that the key features
  • the first chip groups the multiple packets to obtain at least one packet group.
  • the grouping of the multiple messages by the first chip includes: grouping the multiple messages by the first chip according to the reference number; in response to the remaining messages being less than the reference number, grouping the remaining Messages are grouped together.
  • the reference number may be determined according to experience or actual requirements, which is not limited in this embodiment of the present application. For example, if the first chip obtains 10 messages with the same key feature, and the reference number is 4, then the first chip will group the 10 messages according to a group of 4 messages, and the remaining 2 messages as a group.
  • the first chip may also obtain a packet group based on the multiple packets, that is, the multiple packets all belong to the same packet group.
  • the data included in each packet in at least one packet group includes but is not limited to the following three situations.
  • each message in the same message group includes complete message header data.
  • the complete packet header data includes key features.
  • the first chip obtains at least one message group, including: the first chip determines at least one message group based on multiple messages with the same key feature, wherein each message in the same message group includes a complete header data.
  • the multiple messages with the same key feature acquired by the first chip include message 1 and message 2, and the first chip determines a message group based on the message 1 and the message 2, and the message group includes message 1 and message 2.
  • a message 1 and a message 2; wherein, both the message 1 and the message 2 include complete message header data.
  • the complete packet header data also includes non-key features, where the non-key features are data other than the key features in the complete packet header data, and the non-key features are used in the first A chip performs processing corresponding to the non-key feature on the message including the non-key feature.
  • the complete message header data of the message 1 also includes non-key features, and the non-key features included in the message header data of the message 1 are used for the first chip to perform processing corresponding to the non-key features on the message 1
  • the complete header data of the message 2 also includes non-key features, and the non-key features included in the message header data of the message 2 are used by the first chip to perform processing corresponding to the non-key features on the message 2.
  • each message of the same message group includes complete message header data
  • the first chip subsequently performs the processing corresponding to the key features and the data required for the processing corresponding to the non-key features of each message, and there is no need to obtain it again Execute the data required for processing, and the message processing efficiency is high.
  • the first packet in the same packet group includes complete packet header data
  • the second packet in the same packet group includes packet header difference data
  • the first message is any message in the same message group
  • the second message is other messages in the same message group except the first message.
  • the complete packet header data includes key features
  • the packet header difference data is determined based on the difference between the packet header data of the second packet and the packet header data of the first packet.
  • the complete packet header data also includes non-key features.
  • non-key features please refer to the relevant description of the non-key features in Case 1, which will not be repeated here.
  • the manners for the first chip to determine the packet header difference data included in the second packet include but are not limited to the following manners A and B.
  • the first chip obtains the difference between the header data of the first message and the header data of the second message; based on the difference between the header data of the first message and the header data of the second message The difference is to determine the packet header difference data of the second packet.
  • the message header data of the first message includes the incoming port number, source IP address, destination MAC address and destination IP address
  • the message header data of the second message includes the source IP address, destination MAC address and destination IP address
  • the difference between the header data of the first message and the header data of the second message includes the ingress port number and the source IP address
  • the message header data of the second message Header difference data includes ingress port number and source IP address
  • the first chip obtains the configuration information, the header data of the first message and the header data of the second message; based on the header data of the first message and the header data of the second message , to obtain the difference between the header data of the first message and the header data of the second message; based on the difference between the header data of the first message and the header data of the second message and the configuration information , to determine the packet header difference data included in the second packet.
  • the configuration information is the configuration information sent by the control module 101 shown in FIG. 1 , and the configuration information is used to indicate data included in the message except key data.
  • the configuration information indicates that the packet includes the source port number, the key features include the destination MAC address and the destination IP address, the header data of the first packet includes the ingress port number, the source IP address, the destination MAC address, and the destination IP address, and the second
  • the header data of the second message includes the source IP address, the destination MAC address and the destination IP address, and the difference between the header data of the first message and the header data of the second message includes the ingress port number and the source IP Address;
  • the difference data of the packet header of the second packet determined based on the difference between the packet header data of the first packet and the packet header data of the second packet and the configuration information includes the source IP address.
  • the first chip subsequently transmits the message group to the second When the processing module of one chip performs processing, the device resources required for transmission are relatively low.
  • the first packet in the same packet group includes complete packet header data
  • the second packet in the same packet group includes a descriptor
  • the first message is any message in the same message group
  • the second message is other messages in the same message group except the first message.
  • the complete packet header data includes key features
  • the descriptor is used to obtain the complete packet header data included in the second packet.
  • the complete packet header data also includes non-key features.
  • the descriptor is a message identification number (identity document, ID).
  • the amount of data included in the message group is less than the amount of data that the second message includes in the header difference data, and is even smaller than the amount of data that the second message includes in the complete header data, so , when the first chip subsequently transmits the packet group to the processing module of the first chip for processing, the device resources required for transmission are relatively low.
  • the process of S202 may refer to the process of obtaining the packet group by the parsing module shown in FIG. 3 .
  • each message in a message group may also include message body data, which is not included in this embodiment of the present application. limited.
  • the first chip For each packet group in at least one packet group, the first chip performs processing corresponding to the key feature for each packet belonging to the same packet group.
  • the processing corresponding to the key feature performed by the first chip on the multiple messages is also the same.
  • the first chip performs processing corresponding to the key feature on each message belonging to the same message group, the first chip can Each message is processed corresponding to the key feature, and the efficiency of message processing is high.
  • the key feature includes the destination MAC address and the destination IP address, and a packet group obtained includes message 1 and message 2, and the corresponding processing of the key feature includes: determining whether the destination MAC address included in the message is the same as that of the first chip
  • the MAC addresses of the devices are the same; in response to the fact that the destination MAC address is the same as the MAC address of the device where the first chip is located, the outgoing port number and the new destination MAC address are obtained based on the destination IP address included in the message.
  • the first chip when the first chip performs the processing corresponding to the key feature on the message 1 and message 2 included in the message group, it may be based on the destination MAC address and the destination MAC address included in any message in the message 1 or message 2.
  • the IP address performs the processing corresponding to the destination MAC address and the destination IP address on the message 1 and the message 2, and the result of the processing is that the first chip performs the destination MAC address and the destination IP address on the message 1 and the message 2.
  • the processing result of the corresponding processing That is, the first chip performs processing corresponding to the destination MAC address and the destination IP address of the packet 1 and the packet 2 included in the packet group during one processing.
  • the processing corresponding to the above key features is only an example process described in the embodiment of the present application, and the processing corresponding to the key features may also be other processing, which is not limited in the embodiment of the present application.
  • the processing corresponding to the key feature includes determining whether the destination MAC address included in the message is the same as the MAC address corresponding to the port where the first chip is located, or whether the destination MAC address included in the message is It is the same as the MAC address corresponding to the logical port where the first chip is located.
  • the resource used by the first chip to perform processing corresponding to the key feature for any message is based on the performance of the first chip, the any The number of packets included in the packet group to which the packet belongs and the cost of performing the processing corresponding to the key feature are determined.
  • the resource used by the first chip to process any message corresponding to the key feature is based on the performance of the first chip, the number of messages included in the message group where any message belongs, and The cost of performing the processing corresponding to the key feature is determined according to the following formula 1:
  • R 1 is the resource used by the first chip to perform the processing corresponding to the key feature of any message
  • P is the performance of the first chip
  • N is the number of messages included in the message group where any message is located
  • A is the cost of performing the processing corresponding to the key feature.
  • the first chip is used to perform the processing corresponding to the key feature of any message
  • R 1 is the resource used by the first chip to perform the processing corresponding to the key feature of any message
  • P is the performance of the first chip
  • A is the cost of performing the processing corresponding to the key feature.
  • the packet processing method provided by the embodiment of the present application requires less device resources to process the same number of packets.
  • each message belonging to the same message group can also include other data than key features.
  • the first chip can perform processing corresponding to other data on each packet.
  • each message in the same message group includes complete message header data, wherein the complete message header data also includes non-key features.
  • the method further includes: the first chip performs processing corresponding to non-key features on each packet.
  • a message group includes message 1 and message 2
  • non-key features include ingress port number and source IP address
  • the first chip executes the ingress port included in the complete message header data of message 1 for message 1 number and the source IP address
  • the first chip performs the processing corresponding to the inbound port number and the source IP address included in the complete header data of the message 2 for the message 2.
  • the first message in the same message group includes complete message header data
  • the second message in the same message group includes message header difference data, wherein the complete message header data also includes non-critical feature.
  • the method further includes S1-1 and S1-2.
  • the first chip performs processing corresponding to non-key features on the first packet.
  • the principle of the first chip performing the processing corresponding to the non-key feature on the first packet is the same as that of the related process in the above case A, and will not be repeated here.
  • the first chip performs processing corresponding to the packet header difference data on the second packet.
  • the first chip performs processing corresponding to the source IP address on the second packet.
  • the first chip performs processing corresponding to key features on each message, performs processing corresponding to non-key features on the first message, and performs message header difference data correspondence on the second message by the first chip
  • the sequence of processing is not limited by this application.
  • the first packet in the same packet group includes complete packet header data
  • the second packet in the same packet group includes a descriptor, wherein the complete packet header data also includes non-key features.
  • the method further includes S2-1 to S2-3.
  • the first chip performs processing corresponding to the first non-key feature on the first packet.
  • the first non-key feature is other data in the complete header data of the first packet except the key feature.
  • the principle of the first chip performing the processing corresponding to the first non-key feature on the first packet is the same as that of the relevant process in the foregoing case A, and details are not repeated here.
  • the first chip acquires complete packet header data of the second packet based on the descriptor.
  • the complete packet header data of the second message includes a key feature and a second non-key feature
  • the second non-key feature is other data in the complete message header data of the second message except the key feature
  • the first chip stores a plurality of obtained messages, and the first chip obtains the complete message header data of the second message based on the descriptor, including: the first chip obtains based on the descriptor included in the second message For the stored second message, complete message header data of the second message is acquired.
  • the first chip performs processing corresponding to the second non-key feature on the second packet.
  • the process of the first chip performing processing corresponding to the second non-key feature on the second message is the same as the process of the first chip performing processing corresponding to the first non-key feature on the first message, and will not be repeated here. repeat.
  • the first chip is used to process any message
  • the resource is determined based on the performance of the first chip, the number of packets included in the packet group where any packet is located, the cost of executing the processing corresponding to the key feature, and the cost of executing the processing corresponding to other data.
  • the resource used by the first chip to process any message is based on the performance of the first chip, the number of messages included in the message group to which any message belongs, the cost of performing the processing corresponding to the key feature, and The cost of performing processing corresponding to other data is determined according to the following formula 2:
  • R2 is the resource used by the first chip to process any message
  • P is the performance of the first chip
  • N is the number of messages included in the message group where any message is located
  • A is the execution key The cost of the processing corresponding to the feature
  • B is the cost of performing the processing corresponding to other data.
  • the resource used by the first chip to process any message is based on the performance of the first chip, the message group in which any message belongs The number of included packets, the cost of executing the processing corresponding to the key feature and the cost of executing the processing corresponding to the non-key feature are determined.
  • the resources used by the first chip to process the first message are based on the performance of the first chip, and the message group where the first message is located includes The number of packets, the cost of performing processing corresponding to key features, and the cost of performing processing corresponding to non-key features are determined.
  • the resources used by the first chip to process the second message are based on the performance of the first chip, the number of messages included in the message group where the second message belongs, and the key features of execution The corresponding processing cost and the cost of executing the processing corresponding to the packet header difference data are determined.
  • the resources used by the first chip to process the first message are based on the performance of the first chip, and the message group in which the first message belongs includes The number of packets, the cost of executing the processing corresponding to the key feature, and the cost of executing the processing corresponding to the first non-key feature are determined.
  • the resources used by the first chip to process the second message are based on the performance of the first chip, the number of messages included in the message group where the second message belongs, and the key features of execution The corresponding processing cost, the cost of obtaining the complete packet header data of the second packet, and the cost of performing the processing corresponding to the second non-key feature are determined.
  • the method provided by the embodiment of the present application can reduce the device resources required by the first chip to process each message by performing processing corresponding to the key feature for each message belonging to the same message group and having the same key feature.
  • the first chip can perform processing corresponding to key features on each message in one processing process, the efficiency of message processing is relatively high.
  • Fig. 4 is a schematic structural diagram of a message processing device provided by an embodiment of the present application. Based on the following multiple modules shown in FIG. 4 , the messaging device shown in FIG. 4 can perform all or part of the operations performed by the first chip. It should be understood that the device may include more additional modules than those shown or omit some of the modules shown therein, which is not limited in this embodiment of the present application. As shown in Figure 4, the device includes:
  • An acquisition module 401 configured to acquire multiple messages having the same key feature, where the number of key features is at least one;
  • the processing module 403 is configured to, for each packet group in at least one packet group, perform processing corresponding to key features on each packet belonging to the same packet group.
  • each packet in the same packet group includes complete packet header data, and the complete packet header data includes key features.
  • the first message in the same message group includes complete message header data
  • the second message in the same message group includes message header difference data
  • the first message is the same Any message in the message group
  • the second message is other messages in the same message group except the first message;
  • the complete message header data includes key features
  • the message header difference data is based on the first message The difference between the header data of the second message and the header data of the first message is determined.
  • the first message in the same message group includes complete message header data
  • the second message in the same message group includes a descriptor
  • the first message is the same message group
  • Any message in the same message group, the second message is other messages except the first message in the same message group; wherein, the complete message header data includes key features, and the descriptor is used to obtain the second message including The complete packet header data.
  • the processing module 403 is further configured to perform processing corresponding to non-key features on each packet, where the non-key features are data other than the key features in the complete packet header data.
  • the processing module 403 is further configured to perform processing corresponding to non-key features on the first message, where the non-key features are data other than key features in the complete message header data;
  • the second message performs processing corresponding to the difference data in the message header.
  • the processing module 403 is further configured to perform processing corresponding to the first non-key feature on the first message, where the first non-key feature is the complete message header data of the first message other data except the key features; obtain the complete message header data of the second message based on the descriptor, wherein the complete message header data of the second message includes the key feature and the second non-key feature, and the second The non-key feature is data other than the key feature in the complete packet header data of the second packet; the processing corresponding to the second non-key feature is performed on the second packet.
  • the acquisition module 401 is configured to acquire multiple messages, and acquire the feature value of each key feature of each message in the multiple messages; based on the feature value of each key feature of each message , to obtain the hash value of each message; based on the hash value of each message, determine whether the key features of each message are the same.
  • the obtaining module 401 is configured to obtain the first hash value of each message based on the feature value of each key feature of each message and the first hash algorithm; The eigenvalue of the key feature and the second hash algorithm are used to obtain the second hash value of each message; the first hash value of each message and the second hash value of each message are used as the hash of each message value.
  • the obtaining module 401 is configured to obtain the third hash value of each message based on the characteristic value of each key feature of each message and the third hash algorithm; for each The key feature is to obtain the fourth hash value of each key feature based on the feature value of each key feature and the fourth hash algorithm; the third hash value of each message and the fourth hash value of each key feature of each message The hash value is used as the hash value of each message.
  • the obtaining module 401 is configured to obtain at least one cache group based on the first hash value of each message; for each cache group in at least one cache group, based on each The second hash value of the message determines whether the key features of the messages belonging to the same cache group are the same.
  • the obtaining module 401 is configured to obtain at least one cache group based on the third hash value of each message; for each cache group in at least one cache group, based on each The fourth hash value of each key feature of the message determines whether the key features of the messages belonging to the same cache group are the same.
  • the key feature includes at least one of an ingress port number, a destination media access control MAC address, a destination Internet Protocol IP address, a source IP address, and a source MAC address.
  • the resource used by the processing module 403 to perform processing corresponding to the key feature on any message is based on the performance of the processing module 403 1.
  • the number of packets included in the packet group in which any packet belongs and the cost of performing the processing corresponding to the key feature are determined.
  • R1 is the resource that the processing module 403 is used to perform the processing corresponding to the key feature for any message
  • P is the performance of the processing module 403
  • N is the number of messages included in the message group where any message is located
  • A is The cost of performing the processing corresponding to the key feature.
  • An embodiment of the present application provides a network device, which includes: a processor, the processor is coupled to a memory, and at least one program instruction or code is stored in the memory, and the at least one program instruction or code is loaded by the processor and Execute, so that the network device implements the methods in the foregoing method embodiments.
  • FIG. 5 shows a schematic structural diagram of a network device 1100 provided by an exemplary embodiment of the present application.
  • the network device 1100 is a sending-side/receiving-side device.
  • the network device 1100 shown in FIG. 5 is configured to perform operations involved in the packet processing method shown in FIG. 2 above.
  • the network device 1100 is, for example, a network device such as a switch, a router, and other devices (such as a server, a personal computer PC, etc.) including such a chip cascading mode.
  • the hardware structure of the network device 1100 includes a communication interface 1101 and a processor 1102 .
  • the communication interface 1101 and the processor 1102 are connected through a bus 1104 .
  • the communication interface 1101 is used to receive messages sent by other devices, and the processor may store instructions or program codes, and execute the functions performed by the above-mentioned first chip by calling the instructions or program codes.
  • the network device further includes a memory 1103, and the memory 1103 stores instructions or program codes, and the processor 1102 is used to call the instructions or program codes in the memory 1103 so that the network device performs the relevant processing of the first chip in the above method embodiment step.
  • the network device 1100 in the embodiment of the present application may include the first chip in each of the above method embodiments, and the processor 1102 in the network device 1100 reads the instructions or program codes in the memory 1103, so that the The illustrated network device 1100 is capable of performing all or part of the operations performed by the first chip.
  • the processor 1102 is, for example, a general-purpose central processing unit (central processing unit, CPU), a digital signal processor (digital signal processor, DSP), a network processor (network processor, NP), a graphics processing unit (graphics processing unit , GPU), neural-network processing units (neural-network processing units, NPU), data processing unit (data processing unit, DPU), microprocessor or one or more integrated circuits for implementing the solution of this application.
  • the processor 1102 includes an application-specific integrated circuit (application-specific integrated circuit, ASIC), a programmable logic device (programmable logic device, PLD) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof.
  • ASIC application-specific integrated circuit
  • PLD programmable logic device
  • the PLD is, for example, a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), a general array logic (generic array logic, GAL) or any combination thereof. It can realize or execute various logical blocks, modules and circuits described in conjunction with the disclosure of the embodiments of the present invention.
  • the processor can also be a combination of computing functions, for example, a combination of one or more microprocessors, a combination of DSP and a microprocessor, and so on.
  • the network device 1100 further includes a bus.
  • the bus is used to transfer information between the various components of the network device 1100 .
  • the bus may be a peripheral component interconnect standard (PCI for short) bus or an extended industry standard architecture (EISA for short) bus or the like.
  • PCI peripheral component interconnect standard
  • EISA extended industry standard architecture
  • the bus can be divided into address bus, data bus, control bus and so on. For ease of representation, only one thick line is used in FIG. 5 , but it does not mean that there is only one bus or one type of bus.
  • the components of the network device 1100 in FIG. 5 may be connected in other ways besides the bus connection, and the embodiment of the present invention does not limit the connection mode of the components.
  • the memory 1103 is, for example, a read-only memory (read-only memory, ROM) or other types of static storage devices that can store static information and instructions, or a random access memory (random access memory, RAM) or a memory that can store information and instructions.
  • Other types of dynamic storage devices such as electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc Storage (including Compact Disc, Laser Disc, Optical Disc, Digital Versatile Disc, Blu-ray Disc, etc.), magnetic disk storage medium, or other magnetic storage device, or is capable of carrying or storing desired program code in the form of instructions or data structures and capable of Any other medium accessed by a computer, but not limited to.
  • the memory 1103 exists independently, for example, and is connected to the processor 1102 via a bus.
  • the memory 1103 can also be integrated with the processor 1102 .
  • the communication interface 1101 uses any device such as a transceiver to communicate with other devices or a communication network.
  • the communication network can be Ethernet, radio access network (RAN) or wireless local area networks (wireless local area networks, WLAN).
  • the communication interface 1101 may include a wired communication interface, and may also include a wireless communication interface.
  • the communication interface 1101 can be an Ethernet (ethernet) interface, a fast ethernet (fast ethernet, FE) interface, a gigabit ethernet (gigabit ethernet, GE) interface, an asynchronous transfer mode (asynchronous transfer mode, ATM) interface, a wireless local area network ( wireless local area networks, WLAN) interface, cellular network communication interface or a combination thereof.
  • the Ethernet interface can be an optical interface, an electrical interface or a combination thereof.
  • the communication interface 1101 may be used for the network device 1100 to communicate with other devices.
  • the processor 1102 may include one or more processors. Each of these processors may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor.
  • a processor herein may refer to one or more devices, circuits, and/or processing cores for processing data (eg, computer program instructions).
  • the network device 1100 may further include an output device and an input device.
  • Output devices are in communication with processor 1102 and can display information in a variety of ways.
  • the output device may be a liquid crystal display (liquid crystal display, LCD), a light emitting diode (light emitting diode, LED) display device, a cathode ray tube (cathode ray tube, CRT) display device, or a projector (projector).
  • the input device is in communication with the processor 1102 and can receive user input in a variety of ways.
  • the input device may be a mouse, a keyboard, a touch screen device, or a sensing device, among others.
  • the memory 1103 is used to store program codes for implementing the solutions of the present application, and the processor 1102 can execute the program codes stored in the memory 1103 . That is, the network device 1100 can implement the packet processing method provided by the method embodiment through the processor 1102 and the program codes in the memory 1103 . One or more software modules may be included in the program code.
  • the processor 1102 itself may also store program codes or instructions for executing the solutions of the present application.
  • the network device 1100 in the embodiment of the present application may include the first chip in each of the above method embodiments, and the processor 1102 in the network device 1100 reads the program code in the memory 1103 or the program code stored in the processor 1102 itself.
  • the program codes or instructions enable the network device 1100 shown in FIG. 5 to perform all or part of the operations performed by the first chip.
  • the network device 1100 may also correspond to the apparatus shown in FIG. 4 above, and each functional module in the apparatus shown in FIG. 4 is implemented by software of the network device 1100 .
  • the functional modules included in the apparatus shown in FIG. 4 are generated after the processor 1102 of the network device 1100 reads the program code stored in the memory 1103 .
  • each step of the packet processing method shown in FIG. 2 is completed by an integrated logic circuit of hardware in the processor of the network device 1100 or an instruction in the form of software.
  • the steps of the methods disclosed in connection with the embodiments of the present application may be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor.
  • the software module can be located in a mature storage medium in the field such as random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, register.
  • the storage medium is located in the memory, and the processor reads the information in the memory, and completes the steps of the above method in combination with its hardware. To avoid repetition, no detailed description is given here.
  • processor may be a central processing unit (CPU), and may also be other general-purpose processors, digital signal processing (digital signal processing, DSP), application specific integrated circuit (application specific integrated circuit, ASIC), field-programmable gate array (field-programmable gate array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • DSP digital signal processing
  • ASIC application specific integrated circuit
  • FPGA field-programmable gate array
  • a general purpose processor may be a microprocessor or any conventional processor or the like. It should be noted that the processor may be a processor supporting advanced RISC machines (ARM) architecture.
  • ARM advanced RISC machines
  • the above-mentioned memory may include a read-only memory and a random-access memory, and provide instructions and data to the processor.
  • Memory may also include non-volatile random access memory.
  • the memory may also store device type information.
  • the memory can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory.
  • the non-volatile memory can be read-only memory (read-only memory, ROM), programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically programmable Erases programmable read-only memory (electrically EPROM, EEPROM) or flash memory.
  • Volatile memory can be random access memory (RAM), which acts as external cache memory. By way of illustration and not limitation, many forms of RAM are available.
  • static random access memory static random access memory
  • dynamic random access memory dynamic random access memory
  • DRAM dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • double data rate synchronous dynamic random access Memory double data date SDRAM, DDR SDRAM
  • enhanced synchronous dynamic random access memory enhanced SDRAM, ESDRAM
  • synchronous link dynamic random access memory direct memory bus random access memory (direct rambus) RAM, DR RAM).
  • the present application provides a computer program.
  • the processor or the computer can execute the corresponding steps and/or processes in the above method embodiments.
  • a chip including a processor, configured to call from a memory and execute instructions stored in the memory, so that a device equipped with the chip executes the methods in the above aspects.
  • Another chip including: an input interface, an output interface, a processor, and a memory, the input interface, the output interface, the processor, and the memory are connected through an internal connection path, and the processor is used to execute the codes in the memory, and when the codes are executed, the processor is configured to perform the methods in the above aspects.
  • a device including any chip in the above solution.
  • the first chip may be a sending side/receiving side device, such as a physical layer (PHY) chip in a router, a switch, or a server, and the first chip may be an interface of a sending side/receiving side device, such as an optical module
  • the chip in or CDR/retimer chip can be a chip located on a single board of a computing device, and the chip can be a CPU, a network processor (network processor, NP), a neural network processing unit (neural network processing unit, NPU), an FPGA, a programmable logic control One or any combination of PLC (programmable logic controller, PLC) etc.
  • PLC programmable logic controller
  • all or part of them may be implemented by software, hardware, firmware or any combination thereof.
  • software When implemented using software, it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions according to the present application will be generated in whole or in part.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website, computer, server or data center Transmission to another website site, computer, server, or data center by wired (eg, coaxial cable, optical fiber, DSL) or wireless (eg, infrared, wireless, microwave, etc.) means.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center integrated with one or more available media.
  • the available medium may be a magnetic medium (such as a floppy disk, a hard disk, or a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk, solid state disk), etc.
  • the computer program product includes one or more computer program instructions.
  • the methods of embodiments of the present application may be described in the context of machine-executable instructions, such as program modules included in a device executed on a real or virtual processor of a target.
  • program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform particular tasks or implement particular abstract data structures.
  • the functionality of the program modules may be combined or divided between the described program modules.
  • Machine-executable instructions for program modules may be executed locally or in distributed devices. In a distributed device, program modules may be located in both local and remote storage media.
  • Computer program codes for implementing the methods of the embodiments of the present application may be written in one or more programming languages. These computer program codes can be provided to processors of general-purpose computers, special-purpose computers, or other programmable data processing devices, so that when the program codes are executed by the computer or other programmable data processing devices, The functions/operations specified in are implemented.
  • the program code may execute entirely on the computer, partly on the computer, as a stand-alone software package, partly on the computer and partly on a remote computer or entirely on the remote computer or server.
  • computer program codes or related data may be carried by any appropriate carrier, so that a device, apparatus or processor can perform various processes and operations described above.
  • Examples of carriers include signals, computer readable media, and the like.
  • Examples of signals may include electrical, optical, radio, sound, or other forms of propagated signals, such as carrier waves, infrared signals, and the like.
  • a machine-readable medium may be any tangible medium that contains or stores a program for or related to an instruction execution system, apparatus, or device.
  • a machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium.
  • a machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More detailed examples of machine-readable storage media include electrical connections with one or more wires, portable computer diskettes, hard disks, random storage access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash), optical storage, magnetic storage, or any suitable combination thereof.
  • the disclosed systems, devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the modules is only a logical function division. In actual implementation, there may be other division methods.
  • multiple modules or components can be combined or can be Integrate into another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices or modules, and may also be electrical, mechanical or other forms of connection.
  • the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place, or may be distributed to multiple network modules. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the embodiment of the present application.
  • each functional module in each embodiment of the present application may be integrated into one processing module, each module may exist separately physically, or two or more modules may be integrated into one module.
  • the above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules.
  • the integrated module is realized in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of software products, and the computer software products are stored in a storage medium
  • several instructions are included to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods in the various embodiments of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (read-only memory, ROM), random access memory (random access memory, RAM), magnetic disk or optical disc and other media that can store program codes. .
  • first and second are used to distinguish the same or similar items with basically the same function and function. It should be understood that “first”, “second” and “nth” There are no logical or timing dependencies, nor are there restrictions on quantity or order of execution. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, a first network device could be termed a second network device, and, similarly, a second network device could be termed a first network device, without departing from the scope of the various described examples. Both the first network and device and the second network device may be network devices, and in some cases, may be separate and distinct network devices.
  • if and “if” may be construed to mean “when” ("when” or “upon”) or “in response to determining” or “in response to detecting”.
  • phrases “if it is determined" or “if [the stated condition or event] is detected” may be construed to mean “when determining” or “in response to determining... ” or “upon detection of [stated condition or event]” or “in response to detection of [stated condition or event]”.
  • determining B according to A does not mean determining B only according to A, and B may also be determined according to A and/or other information.

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Abstract

一种报文处理方法、装置、设备及计算机可读存储介质。该报文处理方法包括：第一芯片获取具有相同关键特征的多个报文（S201）；第一芯片对该多个报文进行分组，得到至少一个报文组（S202）；对于至少一个报文组中的各个报文组，第一芯片对属于同一报文组的各个报文执行关键特征对应的处理（S203）。其中，关键特征的数量为至少一个。该方法通过对属于同一报文组的各个具有相同关键特征的报文执行关键特征对应的处理，能够降低第一芯片对各个报文执行处理所需的设备资源。此外，由于属于同一报文组的各个报文具有相同的关键特征，第一芯片能够在一次处理过程中对各个报文执行关键特征对应的处理，报文处理的效率较高。

Description

报文处理方法、装置、设备及计算机可读存储介质
本申请要求于2021年08月16日提交的申请号为202110937645.8、发明名称为“报文处理方法、处理器及设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。本申请还要求2021年10月30日提交的申请号为202111278136.5、发明名称为“报文处理方法、装置、设备及计算机可读存储介质”的中国专利申请，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，特别涉及报文处理方法、装置、设备及计算机可读存储介质。
背景技术
在基于报文通信的过程中，转发设备接收到报文后，将基于报文的报文特征对接收的报文进行处理。相关技术中，转发设备获取接收的报文的报文特征，基于报文特征执行该报文对应的表项查找和业务逻辑处理，得到处理后的报文。
然而，由于相关技术中对于接收到的各个报文，转发设备均会执行获取报文特征，基于报文特征执行报文对应的表项查找和业务逻辑处理的过程，在传输报文的带宽和报文的业务复杂度不断提高的情况下，转发设备用于执行报文处理的设备资源容易成为报文处理的瓶颈。
发明内容
本申请提出一种报文处理方法、装置、设备及计算机可读存储介质，用于降低报文处理的资源要求，提高报文处理的效率。
第一方面，提供了一种报文处理方法，该方法包括：第一芯片获取具有相同关键特征的多个报文；对该多个报文进行分组，得到至少一个报文组；对于至少一个报文组中的各个报文组，对属于同一报文组的各个报文执行关键特征对应的处理。其中，关键特征的数量为至少一个。
该方法通过对属于同一报文组的各个具有相同关键特征的报文执行关键特征对应的处理，能够降低第一芯片对各个报文执行处理所需的设备资源。此外，由于属于同一报文组的各个报文具有相同的关键特征，第一芯片能够在一次处理过程中对各个报文执行关键特征对应的处理，报文处理的效率较高。
在一种可能的实现方式中，同一报文组中的各个报文均包括完整的报文头数据，完整的报文头数据包括关键特征。由于同一报文组的各个报文均包括完整的报文头数据，第一芯片后续对各个报文执行关键特征对应的处理以及非关键特征对应的处理所需的数据均已包括，无需重新获取执行处理所需的数据，报文处理效率较高。
在一种可能的实现方式中，同一报文组中的第一报文包括完整的报文头数据，同一报文组中的第二报文包括报文头差异数据，第一报文为同一报文组中的任一报文，第二报文为同一报文组中除第一报文外的其他报文；其中，完整的报文头数据包括关键特征，报文头差异数据基于第二报文的报文头数据和第一报文的报文头数据的差异确定。由于第二报文包括报文头差异数据，该报文组包括的数据量小于第二报文包括完整的报文头数据的数据量，第一 芯片后续将该报文组传输至第一芯片的处理模块进行处理时，传输所需的设备资源较低。
在一种可能的实现方式中，同一报文组中的第一报文包括完整的报文头数据，同一报文组中的第二报文包括描述符，第一报文为同一报文组中的任一报文，第二报文为同一报文组中除第一报文外的其他报文；其中，完整的报文头数据包括关键特征，描述符用于获取第二报文包括的完整的报文头数据。由于第二报文包括描述符，该报文组包括的数据量小于第二报文包括报文头差异数据的数据量，更小于第二报文包括完整的报文头数据的数据量，第一芯片后续将该报文组传输至第一芯片的处理模块进行处理时，传输所需的设备资源较低。
在一种可能的实现方式中，该方法还包括：第一芯片对各个报文执行非关键特征对应的处理，非关键特征为完整的报文头数据中除关键特征外的其他数据。
在一种可能的实现方式中，该方法还包括：第一芯片对第一报文执行非关键特征对应的处理，非关键特征为完整的报文头数据中除关键特征外的其他数据；第一芯片对第二报文执行报文头差异数据对应的处理。
在一种可能的实现方式中，该方法还包括：第一芯片对第一报文执行第一非关键特征对应的处理，其中，第一非关键特征为第一报文的完整的报文头数据中除关键特征外的其他数据；第一芯片基于描述符获取第二报文的完整的报文头数据，其中，第二报文的完整的报文头数据包括关键特征和第二非关键特征，第二非关键特征为第二报文的完整的报文头数据中除关键特征外的其他数据；第一芯片对第二报文执行第二非关键特征对应的处理。
在一种可能的实现方式中，第一芯片获取具有相同关键特征的多个报文，包括：第一芯片获取多个报文，获取多个报文中的各个报文的各个关键特征的特征值；第一芯片基于各个报文的各个关键特征的特征值，获取各个报文的哈希值；第一芯片基于各个报文的哈希值，确定各个报文的关键特征是否相同。
在一种可能的实现方式中，第一芯片基于各个报文的各个关键特征的特征值，获取各个报文的哈希值，包括：第一芯片基于各个报文的各个关键特征的特征值和第一哈希算法，获取各个报文的第一哈希值；第一芯片基于各个报文的各个关键特征的特征值和第二哈希算法，获取各个报文的第二哈希值；第一芯片将各个报文的第一哈希值和各个报文的第二哈希值作为各个报文的哈希值。由于各个报文的哈希值包括各个报文的第一哈希值和各个报文第二哈希值，第一芯片后续在基于各个报文的哈希值确定各个报文的关键特征是否相同时，准确性较高。
在一种可能的实现方式中，第一芯片基于各个报文的各个关键特征的特征值，获取各个报文的哈希值，包括：第一芯片基于各个报文的各个关键特征的特征值和第三哈希算法，获取各个报文的第三哈希值；对于各个报文的各个关键特征，第一芯片基于各个关键特征的特征值和第四哈希算法，获取各个关键特征的第四哈希值；第一芯片将各个报文的第三哈希值和各个报文的各个关键特征的第四哈希值作为各个报文的哈希值。由于各个报文的哈希值包括第三哈希值和各个关键特征的第四哈希值，第一芯片后续在基于各个报文的哈希值确定各个报文的关键特征是否相同时，准确性较高。
在一种可能的实现方式中，第一芯片基于各个报文的哈希值，确定各个报文的关键特征是否相同，包括：第一芯片基于各个报文的第一哈希值，获取至少一个缓存组；对于至少一个缓存组中的各个缓存组，第一芯片基于属于同一缓存组的各个报文的第二哈希值，确定属于同一缓存组的各个报文的关键特征是否相同。由于该方法能够基于各个报文的第一哈希值，获取至少一个缓存组，基于属于同一缓存组的各个报文的第二哈希值，确定属于同一缓存组 的各个报文的关键特征是否相同，在确定各个报文的关键特征是否相同的准确性较高的同时，确定效率也较高。
在一种可能的实现方式中，第一芯片基于各个报文的哈希值，确定各个报文的关键特征是否相同，包括：第一芯片基于各个报文的第三哈希值，获取至少一个缓存组；对于至少一个缓存组中的各个缓存组，第一芯片基于属于同一缓存组的各个报文的各个关键特征的第四哈希值，确定属于同一缓存组的各个报文的关键特征是否相同。由于该方法能够基于各个报文的第三哈希值，获取至少一个缓存组，基于属于同一缓存组的各个报文的关键特征的第四哈希值，确定属于同一缓存组的各个报文的关键特征是否相同，在确定各个报文的关键特征是否相同的准确性较高的同时，确定效率也较高。
在一种可能的实现方式中，关键特征包括入端口号、目的媒体接入控制MAC地址、目的网际互连协议IP地址、源IP地址、源MAC地址中的至少一种。该方法中关键特征的类型较为灵活。
在一种可能的实现方式中，对于属于同一报文组的各个报文中的任一报文，第一芯片用于对任一报文执行关键特征对应的处理的资源基于第一芯片的性能、任一报文所在报文组包括的报文数量和执行关键特征对应的处理的代价确定。
在一种可能的实现方式中，第一芯片用于对任一报文执行关键特征对应的处理的资源基于第一芯片的性能、任一报文所在报文组包括的报文数量和执行关键特征对应的处理的代价按照如下公式确定：
Figure PCTCN2022075530-appb-000001
其中，R 1为第一芯片用于对任一报文执行关键特征对应的处理的资源，P为第一芯片的性能，N为任一报文所在报文组包括的报文数量，A为执行关键特征对应的处理的代价。由于属于同一报文组的报文数量越多，对于该同一报文组的各个报文中的任一报文，第一芯片用于对该任一报文执行关键特征对应的处理的资源越低。因此，相较于相关技术的方法，该方法处理相同数量的报文所需的设备资源较低。
第二方面，提供了一种报文处理装置，该装置包括：
获取模块，用于获取具有相同关键特征的多个报文，其中，关键特征的数量为至少一个；
分组模块，用于对多个报文进行分组，得到至少一个报文组；
处理模块，用于对于至少一个报文组中的各个报文组，对属于同一报文组的各个报文执行关键特征对应的处理。
在一种可能的实现方式中，同一报文组中的各个报文均包括完整的报文头数据，完整的报文头数据包括关键特征。
在一种可能的实现方式中，同一报文组中的第一报文包括完整的报文头数据，同一报文组中的第二报文包括报文头差异数据，第一报文为同一报文组中的任一报文，第二报文为同一报文组中除第一报文外的其他报文；其中，完整的报文头数据包括关键特征，报文头差异数据基于第二报文的报文头数据和第一报文的报文头数据的差异确定。
在一种可能的实现方式中，同一报文组中的第一报文包括完整的报文头数据，同一报文组中的第二报文包括描述符，第一报文为同一报文组中的任一报文，第二报文为同一报文组中除第一报文外的其他报文；其中，完整的报文头数据包括关键特征，描述符用于获取第二 报文包括的完整的报文头数据。
在一种可能的实现方式中，处理模块，还用于对各个报文执行非关键特征对应的处理，非关键特征为完整的报文头数据中除关键特征外的其他数据。
在一种可能的实现方式中，处理模块，还用于对第一报文执行非关键特征对应的处理，非关键特征为完整的报文头数据中除关键特征外的其他数据；对第二报文执行报文头差异数据对应的处理。
在一种可能的实现方式中，处理模块，还用于对第一报文执行第一非关键特征对应的处理，其中，第一非关键特征为第一报文的完整的报文头数据中除关键特征外的其他数据；基于描述符获取第二报文的完整的报文头数据，其中，第二报文的完整的报文头数据包括关键特征和第二非关键特征，第二非关键特征为第二报文的完整的报文头数据中除关键特征外的其他数据；对第二报文执行第二非关键特征对应的处理。
在一种可能的实现方式中，获取模块，用于获取多个报文，获取多个报文中的各个报文的各个关键特征的特征值；基于各个报文的各个关键特征的特征值，获取各个报文的哈希值；基于各个报文的哈希值，确定各个报文的关键特征是否相同。
在一种可能的实现方式中，获取模块，用于基于各个报文的各个关键特征的特征值和第一哈希算法，获取各个报文的第一哈希值；基于各个报文的各个关键特征的特征值和第二哈希算法，获取各个报文的第二哈希值；将各个报文的第一哈希值和各个报文的第二哈希值作为各个报文的哈希值。
在一种可能的实现方式中，获取模块，用于基于各个报文的各个关键特征的特征值和第三哈希算法，获取各个报文的第三哈希值；对于各个报文的各个关键特征，基于各个关键特征的特征值和第四哈希算法，获取各个关键特征的第四哈希值；将各个报文的第三哈希值和各个报文的各个关键特征的第四哈希值作为各个报文的哈希值。
在一种可能的实现方式中，获取模块，用于基于各个报文的第一哈希值，获取至少一个缓存组；对于至少一个缓存组中的各个缓存组，基于属于同一缓存组的各个报文的第二哈希值，确定属于同一缓存组的各个报文的关键特征是否相同。
在一种可能的实现方式中，获取模块，用于基于各个报文的第三哈希值，获取至少一个缓存组；对于至少一个缓存组中的各个缓存组，基于属于同一缓存组的各个报文的各个关键特征的第四哈希值，确定属于同一缓存组的各个报文的关键特征是否相同。
在一种可能的实现方式中，关键特征包括入端口号、目的媒体接入控制MAC地址、目的网际互连协议IP地址、源IP地址、源MAC地址中的至少一种。
在一种可能的实现方式中，对于属于同一报文组的各个报文中的任一报文，处理模块用于对任一报文执行关键特征对应的处理的资源基于处理模块的性能、任一报文所在报文组包括的报文数量和执行关键特征对应的处理的代价确定。
在一种可能的实现方式中，处理模块用于对任一报文执行关键特征对应的处理的资源基于处理模块的性能、任一报文所在报文组包括的报文数量和执行关键特征对应的处理的代价按照如下公式确定：
Figure PCTCN2022075530-appb-000002
其中，R 1为处理模块用于对任一报文执行关键特征对应的处理的资源，P为处理模块的性能，N为任一报文所在报文组包括的报文数量，A为执行关键特征对应的处理的代价。
第三方面，提供了一种网络设备，该网络设备包括：处理器，处理器与存储器耦合，存储器中存储有至少一条程序指令或代码，至少一条程序指令或代码由处理器加载并执行，以使该网络设备实现如上第一方面中任一的报文处理方法。
第四方面，提供了一种计算机可读存储介质，该计算机可读存储介质中存储有至少一条程序指令或代码，程序指令或代码由处理器加载并执行时以使计算机实现如第一方面中任一的报文处理方法。
第五方面，提供了一种计算机程序产品，包括计算机程序，计算机程序被计算机执行时，以使计算机实现如上第一方面中任一的报文处理方法。
第六方面，提供了一种通信装置，该装置包括：通信接口、存储器和处理器。其中，该存储器和该处理器通过内部连接通路互相通信，该存储器用于存储指令，该处理器用于执行该存储器存储的指令，以控制通信接口接收数据，并控制通信接口发送数据，并且当该处理器执行该存储器存储的指令时，使得该处理器执行第一方面或第一方面的任一种可能的实施方式中的方法。
在一种可能的实现方式中，处理器为一个或多个，存储器为一个或多个。
在一种可能的实现方式中，存储器可以与处理器集成在一起，或者存储器与处理器分离设置。
在具体实现过程中，存储器可以为非瞬时性(non-transitory)存储器，例如，只读存储器(read only memory，ROM)，其可以与处理器集成在同一块芯片上，也可以分别设置在不同的芯片上，本申请对存储器的类型以及存储器与处理器的设置方式不做限定。
第七方面，提供了一种芯片，包括处理器，用于从存储器中调用并运行存储器中存储的指令，使得安装有芯片的通信设备执行上述第一方面或第一方面的任一种可能的实施方式中的方法。
第八方面，提供了另一种芯片，包括：输入接口、输出接口、处理器和存储器，输入接口、输出接口、处理器以及存储器之间通过内部连接通路相连，处理器用于执行存储器中的代码，当代码被执行时，处理器用于执行上述第一方面或第一方面的任一种可能的实施方式中的方法。
第九方面，提供了一种设备，包括上述方案中的任一芯片。
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图1是本申请实施例提供的一种报文处理方法的实施环境示意图；
图2是本申请实施例提供的一种报文处理方法的流程图；
图3是本申请实施例提供的一种报文处理过程的示意图；
图4是本申请实施例提供的一种报文处理装置的结构示意图；
图5是本申请实施例提供的一种网络设备的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
本申请实施例提供了一种报文处理方法，该方法的实施环境可如图1中的报文处理架构 图所示。在一种可能的实现方式中，图1示出的报文处理架构应用于芯片，该芯片设置于终端、网络设备或者服务器等设备中。如图1所示，该报文处理架构包括控制模块101、解析模块102和处理模块103，控制模块101、解析模块102以及处理模块103之间能够进行信息传输。其中，控制模块101用于发送配置信息，例如，控制模块101向解析模块102发送配置信息，该配置信息用于指示关键信息的类型；解析模块102用于获取报文的报文头数据，基于报文头数据包括的关键特征对具有相同关键特征的多个报文进行分组；处理模块103用于对报文进行处理。
示例性地，该处理模块103包括至少一个子模块。例如，如图1所示，该处理模块103包括接口子模块1031、隧道终结子模块1032、转发子模块1033和修改子模块1034。其中，接口子模块1031用于执行接口处理，例如，检查报文的最大传输单元(maximum transmission unit，MTU)，控制报文的承诺接入速率(committed access rate，CAR)；隧道终结子模块1032用于在报文为隧道类报文且需要本地终结的情况下，进行隧道终结处理；转发子模块1033用于基于接口子模块1031和隧道终结子模块1032的处理结果进行转发处理，例如，进行路由转发；修改子模块1034用于进行报文的修改处理并发送到出端口。
图1示出的系统架构中，不同模块可以根据实际报文处理需求进行设置，该报文处理架构可以包括比所示模块更多的附加模块或者省略其中所示的一部分模块。本申请实施例对此不加以限定。
结合图1所示的实施环境，对本申请实施例提供的报文处理方法进行说明。如图2所示，本申请实施例提供的报文处理方法包括但不限于S201至S203。其中，该方法由第一芯片执行，本申请不对该第一芯片的类型加以限定。
S201，第一芯片获取具有相同关键特征的多个报文。
其中，关键特征的数量为至少一个。示例性地，关键特征的类型为配置信息指示的类型。在一种可能的实现方式中，关键特征包括入端口号、目的媒体接入控制(media access control address，MAC)地址、目的网际互连协议(internet protocol，IP)地址、源IP地址、源MAC地址中的至少一种。本申请实施例中的关键特征的类型较为灵活。需要说明的是，关于通过配置信息指示关键信息的类型的方式，本申请实施例对此不加以限定。
在一种可能的实现方式中，第一芯片获取具有相同关键特征的多个报文包括但不限于S2011至S2013。
S2011，第一芯片获取多个报文，获取多个报文中的各个报文的各个关键特征的特征值。
示例性地，第一芯片获取的多个报文为第一芯片接收的其他设备发送的报文，或第一芯片生成的多个报文。在一种可能的实现方式中，关键特征包括在报文头数据中，第一芯片获取各个报文的各个关键特征的特征值，包括：第一芯片获取各个报文的报文头数据中各个关键特征的特征值。
例如，关键特征包括目的MAC地址和目的IP地址，则对于各个报文中的任一报文，该任一报文的关键特征的特征值包括该任一报文的目的MAC地址和目的IP地址。则在关键特征包括目的MAC地址和目的IP地址的情况下，第一芯片获取各个报文的报文头数据中各个关键特征的特征值，包括：第一芯片获取各个报文的报文头数据中各个报文的目的MAC地址和目的IP地址。
示例性地，该获取多个报文的过程可参照图3示出的解析模块接收报文的过程。
S2012，第一芯片基于各个报文的各个关键特征的特征值，获取各个报文的哈希值。
在一种可能的实现方式中，第一芯片基于各个报文的各个关键特征的特征值，获取各个报文的哈希值，包括但不限于如下两种方式。
方式一，第一芯片基于一次哈希计算获取各个报文的哈希值。
在一种可能的实现方式中，第一芯片基于各个报文的各个关键特征的特征值和参考哈希算法，获取各个报文的哈希值。示例性地，第一芯片基于每个报文的各个关键特征的特征值和参考哈希算法，计算得到一个哈希值，将该哈希值作为该报文的哈希值。
例如，关键特征包括目的MAC地址和目的IP地址，第一芯片获取到两个报文，分别为报文1和报文2，则对于报文1，第一芯片基于报文1的目的MAC地址1、目的IP地址1和参考哈希算法，计算得到一个哈希值1，将该哈希值1作为报文1的哈希值；对于报文2，第一芯片基于报文2的目的MAC地址2、目的IP地址2和参考哈希算法，计算得到一个哈希值2，将该哈希值2作为报文2的哈希值。
示例性地，参考哈希算法包括但不限于循环冗余校验(cyclic redundancy check，CRC)算法或折叠异或算法中的任一种，其中，CRC算法包括但不限于CRC-32算法、CRC-16算法或CRC-8算法中的任一种。
由于各个报文的哈希值为基于一次哈希计算得到的，各个报文仅具有一个哈希值。因此，第一芯片后续在基于各个报文的哈希值确定各个报文的关键特征是否相同时，确定效率较高。
方式二，第一芯片基于两次哈希计算获取各个报文的哈希值。
示例性地，第一芯片基于各个报文的各个关键特征的特征值，获取各个报文的哈希值，包括但不限于方式二A和方式二B。
示例性地，方式二A包括但不限于S20121至S20123。
S20121，第一芯片基于各个报文的各个关键特征的特征值和第一哈希算法，获取各个报文的第一哈希值。
示例性地，第一哈希算法包括但不限于CRC算法或折叠异或算法中的任一种，其中，CRC算法包括但不限于CRC-32算法、CRC-16算法或CRC-8算法中的任一种。第一芯片基于各个报文的各个关键特征的特征值和第一哈希算法，获取各个报文的第一哈希值的方式与上述方式一中的相关过程原理相同，此处不再赘述。
S20122，第一芯片基于各个报文的各个关键特征的特征值和第二哈希算法，获取各个报文的第二哈希值。
示例性地，第二哈希算法包括但不限于CRC算法或折叠异或算法中的任一种，其中，CRC算法包括但不限于CRC-32算法、CRC-16算法或CRC-8算法中的任一种。
第二哈希算法为与第一哈希算法不同的算法。第一芯片基于各个报文的各个关键特征的特征值和第二哈希算法，获取各个报文的第二哈希值的方式与上述方式一中的相关过程原理相同，此处不再赘述。
S20123，第一芯片将各个报文的第一哈希值和各个报文的第二哈希值作为各个报文的哈希值。
仍以关键特征包括目的MAC地址和目的IP地址，第一芯片获取到两个报文，分别为报文1和报文2为例进行说明。根据上述S20121和S20122的内容，第一芯片计算得到报文1的第一哈希值和该报文1的第二哈希值后，将该报文1的第一哈希值和第二哈希值作为该报文1的哈希值。也就是说，该报文1的哈希值包括：报文1的第一哈希值和报文1的第二哈 希值。
同理，第一芯片将报文2的第一哈希值和该报文2的第二哈希值作为报文2的哈希值。由此，第一芯片实现获取各个报文的哈希值。
由于各个报文的哈希值包括各个报文的第一哈希值和各个报文第二哈希值，第一芯片后续在基于各个报文的哈希值确定各个报文的关键特征是否相同时，准确性较高。
示例性地，方式二B包括但不限于S20124至S20126。
S20124，第一芯片基于各个报文的各个关键特征的特征值和第三哈希算法，获取各个报文的第三哈希值。
示例性地，第三哈希算法包括但不限于CRC算法或折叠异或算法中的任一种，其中，CRC算法包括但不限于CRC-32算法、CRC-16算法或CRC-8算法中的任一种。第一芯片基于各个报文的各个关键特征的特征值和第三哈希算法，获取各个报文的第三哈希值的方式与上述方式一中的相关过程原理相同，此处不再赘述。
S20125，对于各个报文的各个关键特征，第一芯片基于各个关键特征的特征值和第四哈希算法，获取各个关键特征的第四哈希值。
示例性地，第四哈希算法包括但不限于CRC算法或折叠异或算法中的任一种，其中，CRC算法包括但不限于CRC-32算法、CRC-16算法或CRC-8算法中的任一种。需要说明的是，第四哈希算法可以为与第三哈希算法相同或不同的算法，本申请实施例对此不加以限定。
示例性地，第一芯片基于各个关键特征的特征值和第四哈希算法，获取各个关键特征的第四哈希值，包括：第一芯片基于每个关键特征的特征值和第四哈希算法，计算得到一个哈希值，将该哈希值作为该关键特征的第四哈希值。
例如，关键特征包括目的MAC地址和目的IP地址，第一芯片获取到两个报文，分别为报文1和报文2，则对于报文1，第一芯片基于报文1的目的MAC地址和第四哈希算法，计算得到报文1的目的MAC地址的第四哈希值，基于报文1的目的IP地址和第四哈希算法，计算得到报文1的目的IP地址的第四哈希值；对于报文2，第一芯片基于报文2的目的MAC地址和第四哈希算法，计算得到报文2的目的MAC地址的第四哈希值，基于报文2的目的IP地址和第四哈希算法，计算得到报文2的目的IP地址的第四哈希值。
S20126，第一芯片将各个报文的第三哈希值和各个报文的各个关键特征的第四哈希值作为各个报文的哈希值。
仍以关键特征包括目的MAC地址和目的IP地址，第一芯片获取到两个报文，分别为报文1和报文2为例进行说明。根据上述S20124和S20125的内容，对于报文1，第一芯片计算得到报文1的第三哈希值、报文1的目的MAC地址的第四哈希值和报文1的目的IP地址的第四哈希值后，将报文1的第三哈希值、报文1的目的MAC地址的第四哈希值和报文1的目的IP地址的第四哈希值作为该报文1的哈希值。也就是说，该报文1的哈希值包括：报文1的第三哈希值、报文1的目的MAC地址的第四哈希值和报文1的目的IP地址的第四哈希值。
同理，第一芯片将报文2的第三哈希值、报文2的目的MAC地址的第四哈希值和报文2的目的IP地址的第四哈希值作为报文2的哈希值。由此，第一芯片实现获取各个报文的哈希值。
由于各个报文的哈希值包括第三哈希值和各个关键特征的第四哈希值，第一芯片后续在基于各个报文的哈希值确定各个报文的关键特征是否相同时，准确性较高。
第一芯片还可以基于三次哈希计算获取各个报文的哈希值。例如，第一芯片基于各个报文的各个关键特征的特征值和第一哈希算法，获取各个报文的第一哈希值；基于各个报文的各个关键特征的特征值和第二哈希算法，获取各个报文的第二哈希值；基于各个报文的各个关键特征的特征值和第五哈希算法，获取各个报文的第五哈希值。其中，该第一哈希算法、第二哈希算法和第五哈希算法分别为不同的算法。将各个报文的第一哈希值、第二哈希值和第五哈希值作为各个报文的哈希值。由于各个报文的哈希值能够包括多个哈希值，第一芯片后续在基于各个报文的哈希值确定各个报文的关键特征是否相同时，准确性较高。示例性地，第一芯片还可以采用更多次的哈希计算获取各个哈希值，以进一步提高确定各个报文的关键特征是否相同的准确性。
S2013，第一芯片基于各个报文的哈希值，确定各个报文的关键特征是否相同。
在一种可能的实现方式中，针对获取各个报文的哈希值的不同方式，第一芯片基于各个报文的哈希值，确定各个报文的关键特征是否相同包括但不限于如下三种方式。
方式1，第一芯片基于各个报文的哈希值，确定各个报文的关键特征是否相同。
示例性地，针对以上述方式一获取的各个报文的哈希值，可以采用该方式1确定各个报文的关键特征是否相同。其中，响应于两个报文的哈希值相同，则该两个报文的关键特征相同；响应于两个报文的哈希值不同，则该两个报文的关键特征不同。通过确定各个报文的哈希值是否相同，第一芯片能够确定各个报文的关键特征是否相同。
方式2，第一芯片基于各个报文的第一哈希值和各个报文的第二哈希值，确定各个报文的关键特征是否相同。
示例性地，针对以上述方式二A获取的各个报文的哈希值，可以采用该方式2确定各个报文的关键特征是否相同。
在一种可能的实现方式中，第一芯片基于多个报文中的各个报文的哈希值，确定各个报文的关键特征是否相同，包括但不限于S20131和S20132。
S20131，第一芯片基于各个报文的第一哈希值，获取至少一个缓存组。
示例性地，第一芯片具有至少一组缓存，第一芯片根据哈希值与缓存的映射关系以及各个报文的第一哈希值，将各个报文存储在与该各个报文的第一哈希值具有映射关系的缓存中，得到至少一个缓存组。关于第一芯片获取哈希值与缓存的映射关系的方式，本申请实施例不加以限定，例如，第一芯片中存储有哈希值与缓存的映射关系，或第一芯片获取用户输入的哈希值与缓存的映射关系。
示例性地，第一哈希值相同的报文将存储在同一缓存组中，第一芯片将第一哈希值相同的各个报文确定为属于同一缓存组的报文。例如，关键特征包括目的MAC地址和目的IP地址，第一芯片获取的多个报文包括报文1、报文2和报文3，其中，报文1的第一哈希值与报文2的第一哈希值相同，报文1的第一哈希值与报文3的第一哈希值不同，第一芯片基于报文1的第一哈希值、报文2的第一哈希值和报文3的第一哈希值，获取到两个缓存组，报文1和报文2属于该两个缓存组中的一个缓存组，报文3属于该两个缓存组中的另一个缓存组。
S20132，对于至少一个缓存组中的各个缓存组，第一芯片基于属于同一缓存组的各个报文的第二哈希值，确定属于同一缓存组的各个报文的关键特征是否相同。
示例性地，对于属于同一缓存组的各个报文中的任意两个报文，响应于两个报文的第二哈希值相同，该两个报文的关键特征相同；响应于两个报文的第二哈希值不同，该两个报文的关键特征不同。由此，第一芯片能够确定属于同一缓存组的各个报文的关键特征是否相同。
仍以上述S20131中获取的缓存组为例进行说明，其中，报文1和报文2属于同一缓存组；第一芯片基于报文1的第二哈希值和报文2的第二哈希值，确定报文1和报文2的关键特征是否相同。
通过基于各个报文的第一哈希值，获取至少一个缓存组，进而基于属于同一缓存组的各个报文的第二哈希值，确定属于同一缓存组的各个报文的关键特征是否相同，在确定各个报文的关键特征是否相同的准确性较高的同时，确定效率也较高。
示例性地，若各个报文的哈希值包括三个哈希值，第一芯片基于各个报文的哈希值，确定各个报文的关键特征是否相同，包括：第一芯片基于各个报文的三个哈希值中的一个哈希值，获取至少一个缓存组；对于至少一个缓存组中的各个缓存组，基于属于同一缓存组的各个报文的三个哈希值中的其余哈希值，确定属于同一缓存组的各个报文的关键特征是否相同。例如，各个报文的哈希值包括第一哈希值、第二哈希值和第五哈希值，第一芯片基于各个报文的第一哈希值，获取至少一个缓存组；对于至少一个缓存组中的各个缓存组，基于属于同一缓存组的各个报文的第二哈希值和第五哈希值，确定属于同一缓存组的各个报文的关键特征是否相同。若属于同一缓存组的两个报文的第二哈希值相同，且该两个报文的第五哈希值相同，则该两个报文的关键特征相同。需要说明的是，若各个报文的哈希值包括更多个哈希值，第一芯片确定各个报文的关键特征是否相同的过程与上述过程原理相同，此处不再赘述。
方式3，第一芯片基于各个报文的第三哈希值和各个报文的各个关键特征的第四哈希值，确定各个报文的关键特征是否相同。
示例性地，针对以上述方式二B获取的各个报文的哈希值，可以采用该方式3确定各个报文的关键特征是否相同。
在一种可能的实现方式中，第一芯片基于多个报文中的各个报文的哈希值，确定各个报文的关键特征是否相同，包括但不限于S20133和S20134。
S20133，第一芯片基于各个报文的第三哈希值，获取至少一个缓存组。
该S20133的实现过程与S20131中的相关过程原理相同，此处不再赘述。
S20134，对于至少一个缓存组中的各个缓存组，第一芯片基于属于同一缓存组的各个报文的各个关键特征的第四哈希值，确定属于同一缓存组的各个报文的关键特征是否相同。
示例性地，对于属于同一缓存组的各个报文中的任意两个报文，响应于两个报文的各个关键特征的第四哈希值均相同，该两个报文的关键特征相同；响应于两个报文的各个关键特征的第四哈希值中存在至少一个关键特征的第四哈希值不同，该两个报文的关键特征不同。由此，第一芯片能够确定属于同一缓存组的各个报文的关键特征是否相同。
仍以报文1和报文2为属于同一缓存组的两个报文为例进行说明。第一芯片基于报文1的目的MAC地址的第四哈希值和目的IP地址的第四哈希值，以及报文2的目的MAC地址的第四哈希值和目的IP地址的第四哈希值，确定报文1和报文2的关键特征是否相同。
示例性地，第一芯片确定报文1的目的MAC地址的第四哈希值与报文2的目的MAC地址的第四哈希值是否相同，报文1的目的IP地址的第四哈希值与报文2的目的IP地址的第四哈希值是否相同；响应于报文1的目的MAC地址的第四哈希值与报文2的目的MAC地址的第四哈希值相同，且报文1的目的IP地址的第四哈希值与报文2的目的IP地址的第四哈希值相同，第一芯片确定报文1和报文2的关键特征相同；响应于报文1的目的MAC地址的第四哈希值与报文2的目的MAC地址的第四哈希值不同，和/或，报文1的目的IP地址的第四哈希值与报文2的目的IP地址的第四哈希值不同，第一芯片确定报文1和报文2的关键 特征不同。
通过基于各个报文的第三哈希值，获取至少一个缓存组，进而基于属于同一缓存组的各个报文的关键特征的第四哈希值，确定属于同一缓存组的各个报文的关键特征是否相同，在确定各个报文的关键特征是否相同的准确性较高的同时，确定效率也较高。
S202，第一芯片对该多个报文进行分组，得到至少一个报文组。
在一种可能实现方式中，第一芯片对该多个报文进行分组，包括：第一芯片按照参考数量对该多个报文进行分组；响应于剩余的报文小于参考数量，将剩余的报文作为一组。需要说明的是，该参考数量可以根据经验或实际需求确定，本申请实施例对此不加以限定。例如，第一芯片获取到10个具有相同关键特征的报文，参考数量为4，则第一芯片按照一组4个报文的方式对该10个报文进行分组，剩余的2个报文为一组。当然，第一芯片也可以基于该多个报文得到一个报文组，也即，该多个报文均属于同一个报文组。
在一种可能的实现方式中，至少一个报文组中的各个报文所包括的数据包括但不限于如下三种情况。
情况1，同一报文组中的各个报文均包括完整的报文头数据。
其中，完整的报文头数据包括关键特征。示例性地，第一芯片得到至少一个报文组，包括：第一芯片基于具有相同关键特征的多个报文确定至少一个报文组，其中，同一报文组中的各个报文均包括完整的报文头数据。例如，第一芯片获取的具有相同关键特征的多个报文包括报文1和报文2，第一芯片基于该报文1和该报文2确定一个报文组，该报文组包括报文1和报文2；其中，该报文1和该报文2均包括完整的报文头数据。
在一种可能的实现方式中，该完整的报文头数据还包括非关键特征，该非关键特征为该完整的报文头数据中除关键特征外的其他数据，该非关键特征用于第一芯片对包括该非关键特征的报文执行该非关键特征对应的处理。例如，报文1的完整的报文头数据还包括非关键特征，该报文1的报文头数据包括的非关键特征用于第一芯片对该报文1执行该非关键特征对应的处理；报文2的完整的报文头数据还包括非关键特征，该报文2的报文头数据包括的非关键特征用于第一芯片对该报文2执行该非关键特征对应的处理。
由于同一报文组的各个报文均包括完整的报文头数据，第一芯片后续对各个报文执行关键特征对应的处理以及非关键特征对应的处理所需的数据均已包括，无需重新获取执行处理所需的数据，报文处理效率较高。
情况2，同一报文组中的第一报文包括完整的报文头数据，同一报文组中的第二报文包括报文头差异数据。
其中，第一报文为同一报文组中的任一报文，第二报文为同一报文组中除第一报文外的其他报文。示例性地，完整的报文头数据包括关键特征，报文头差异数据基于第二报文的报文头数据和第一报文的报文头数据的差异确定。在一种可能的实现方式中，该完整的报文头数据还包括非关键特征，该非关键特征的说明请参照情况1中非关键特征的相关说明，此处不再赘述。
示例性地，第一芯片确定第二报文包括的报文头差异数据的方式包括但不限于如下方式A和方式B。
方式A，第一芯片获取第一报文的报文头数据和第二报文的报文头数据的差异；基于第一报文的报文头数据和第二报文的报文头数据的差异，确定第二报文的报文头差异数据。
例如，第一报文的报文头数据包括入端口号、源IP地址、目的MAC地址和目的IP地址， 第二报文的报文头数据包括源IP地址、目的MAC地址和目的IP地址，其中目的MAC地址和目的IP地址为关键特征，则第一报文的报文头数据和第二报文的报文头数据的差异包括入端口号和源IP地址，第二报文的报文头差异数据包括入端口号和源IP地址。
方式B，第一芯片获取配置信息、第一报文的报文头数据和第二报文的报文头数据；基于第一报文的报文头数据和第二报文的报文头数据，获取第一报文的报文头数据和第二报文的报文头数据的差异；基于该第一报文的报文头数据和第二报文的报文头数据的差异以及配置信息，确定第二报文包括的报文头差异数据。
示例性地，该配置信息为图1中示出的控制模块101发送的配置信息，该配置信息用于指示报文包括的数据中除关键数据外的其他数据。例如，配置信息指示报文包括源端口号，关键特征包括目的MAC地址和目的IP地址，第一报文的报文头数据包括入端口号、源IP地址、目的MAC地址和目的IP地址，第二报文的报文头数据包括源IP地址、目的MAC地址和目的IP地址，则第一报文的报文头数据和第二报文的报文头数据的差异包括入端口号和源IP地址；基于第一报文的报文头数据和第二报文的报文头数据的差异以及配置信息确定的第二报文的报文头差异数据包括源IP地址。
由于第二报文包括报文头差异数据，该报文组包括的数据量小于第二报文包括完整的报文头数据的数据量，因此，第一芯片后续将该报文组传输至第一芯片的处理模块进行处理时，传输所需的设备资源较低。
情况3，同一报文组中的第一报文包括完整的报文头数据，同一报文组中的第二报文包括描述符。
其中，第一报文为同一报文组中的任一报文，第二报文为同一报文组中除第一报文外的其他报文。示例性地，完整的报文头数据包括关键特征，描述符用于获取第二报文包括的完整的报文头数据。在一种可能的实现方式中，该完整的报文头数据还包括非关键特征，该非关键特征的说明请参照情况1中非关键特征的相关说明，此处不再赘述。示例性地，描述符为报文身份标识号(identity document，ID)。
由于第二报文包括描述符，该报文组包括的数据量小于第二报文包括报文头差异数据的数据量，更小于第二报文包括完整的报文头数据的数据量，因此，第一芯片后续将该报文组传输至第一芯片的处理模块进行处理时，传输所需的设备资源较低。
示例性地，S202的过程可参照图3示出的由解析模块得到报文组的过程。
无论至少一个报文组中的各个报文所包括的数据为上述情况1-3中的哪种情况，报文组中的各个报文还可以包括报文体数据，本申请实施例对此不加以限定。
S203，对于至少一个报文组中的各个报文组，第一芯片对属于同一报文组的各个报文执行关键特征对应的处理。
对于具有相同关键特征的多个报文，第一芯片对该多个报文执行的关键特征对应的处理也相同。在此基础上，由于属于同一报文组的各个报文具有相同的关键特征，第一芯片对属于同一报文组的各个报文执行关键特征对应的处理时，第一芯片能够在一次处理过程中对各个报文执行关键特征对应的处理，报文处理的效率较高。
例如，关键特征包括目的MAC地址和目的IP地址，得到的一个报文组包括报文1和报文2，该关键特征对应的处理包括：确定报文包括的目的MAC地址是否与第一芯片所在设备的MAC地址相同；响应于目的MAC地址与第一芯片所在设备的MAC地址相同，基于报文包括的目的IP地址获取出端口号和新的目的MAC地址。
则第一芯片对该报文组包括的报文1和报文2执行该关键特征对应的处理时，可以基于该报文1或报文2中的任一报文包括的目的MAC地址和目的IP地址对该报文1和报文2执行该目的MAC地址和目的IP地址对应的处理，处理得到的结果即为第一芯片对该报文1和报文2执行目的MAC地址和目的IP地址对应的处理的处理结果。也即，第一芯片在一次处理过程中对该报文组包括的报文1和报文2执行了目的MAC地址和目的IP地址对应的处理。需要说明的是，上述关键特征对应的处理仅为本申请实施例举例说明的过程，关键特征对应的处理还可以为其他处理，本申请实施例对此不加以限定。例如，在关键特征包括目的MAC地址的情况下，该关键特征对应的处理包括确定报文包括的目的MAC地址是否与第一芯片所在端口对应的MAC地址相同，或报文包括的目的MAC地址是否与第一芯片所在逻辑端口对应的MAC地址相同。
示例性地，对于属于同一报文组的各个报文中的任一报文，第一芯片用于对该任一报文执行关键特征对应的处理的资源基于第一芯片的性能、该任一报文所在报文组包括的报文数量和执行关键特征对应的处理的代价确定。
在一种可能的实现方式中，第一芯片用于对该任一报文执行关键特征对应的处理的资源基于第一芯片的性能、该任一报文所在报文组包括的报文数量和执行关键特征对应的处理的代价按照如下公式1确定：
Figure PCTCN2022075530-appb-000003
其中，R 1为第一芯片用于对该任一报文执行关键特征对应的处理的资源，P为第一芯片的性能，N为该任一报文所在报文组包括的报文数量，A为执行关键特征对应的处理的代价。
仍以上述包括报文1和报文2的报文组为例进行说明，则对于该报文组包括的任一报文，第一芯片用于对该任一报文执行关键特征对应的处理的资源为R 1＝(P/3)*A。其中，R 1为第一芯片用于对该任一报文执行关键特征对应的处理的资源，P为第一芯片的性能，A为执行关键特征对应的处理的代价。
基于上述公式1可知，属于同一报文组的报文数量越多，对于该同一报文组的各个报文中的任一报文，第一芯片用于对该任一报文执行关键特征对应的处理的资源越低。因此，相较于相关技术中的报文处理方法，本申请实施例提供的报文处理方法处理相同数量的报文所需的设备资源较低。
在一些实施例中，如上述S202中所提及的，属于同一报文组的各个报文还能够包括关键特征以外的其他数据。示例性地，在属于同一报文组的各个报文还包括其他数据的情况下，第一芯片能够对各个报文执行其他数据对应的处理。接下来，分别对各个报文包括其他数据的情况，以及第一芯片对各个报文执行其他数据对应的处理的情况加以说明。
情况A，同一报文组中的各个报文均包括完整的报文头数据，其中，完整的报文头数据还包括非关键特征。
在一种可能的实现方式中，针对情况A，该方法还包括：第一芯片对各个报文执行非关键特征对应的处理。
例如，一个报文组包括报文1和报文2，非关键特征包括入端口号和源IP地址，则第一芯片对报文1执行报文1的完整的报文头数据包括的入端口号和源IP地址对应的处理，第一芯片对报文2执行报文2的完整的报文头数据包括的入端口号和源IP地址对应的处理。需要说明的是，关于第一芯片对各个报文执行关键特征对应的处理和执行非关键特征对应的处理的顺序，以及第一芯片分别对各个报文执行非关键特征对应的处理的顺序，本申请对此不加 以限定。
情况B，同一报文组中的第一报文包括完整的报文头数据，同一报文组中的第二报文包括报文头差异数据，其中，完整的报文头数据还包括非关键特征。
在一种可能的实现方式中，针对情况B，该方法还包括S1-1和S1-2。
S1-1，第一芯片对第一报文执行非关键特征对应的处理。
示例性地，第一芯片对第一报文执行非关键特征对应的处理的过程与上述情况A中的相关过程原理相同，此处不再赘述。
S1-2，第一芯片对第二报文执行报文头差异数据对应的处理。
例如，第二报文包括的报文头差异数据为源IP地址，则第一芯片对该第二报文执行源IP地址对应的处理。
在一些实施例中，关于第一芯片对各个报文执行关键特征对应的处理、对第一报文执行非关键特征对应的处理，以及第一芯片对第二报文执行报文头差异数据对应的处理的顺序，本申请对此不加以限定。
情况C，同一报文组中的第一报文包括完整的报文头数据，同一报文组中的第二报文包括描述符，其中，完整的报文头数据还包括非关键特征。
在一种可能的实现方式中，针对情况C，该方法还包括S2-1至S2-3。
S2-1，第一芯片对第一报文执行第一非关键特征对应的处理。
其中，第一非关键特征为第一报文的完整的报文头数据中除关键特征外的其他数据。示例性地，第一芯片对第一报文执行第一非关键特征对应的处理的过程与上述情况A中的相关过程原理相同，此处不再赘述。
S2-2，第一芯片基于描述符获取第二报文的完整的报文头数据。
其中，第二报文的完整的报文头数据包括关键特征和第二非关键特征，第二非关键特征为第二报文的完整的报文头数据中除关键特征外的其他数据。
示例性地，第一芯片存储有获取的多个报文，第一芯片基于描述符获取第二报文的完整的报文头数据，包括：第一芯片基于第二报文包括的描述符获取存储的第二报文，获取该第二报文的完整的报文头数据。
S2-3，第一芯片对第二报文执行第二非关键特征对应的处理。
示例性地，第一芯片对第二报文执行第二非关键特征对应的处理的过程与第一芯片对第一报文执行第一非关键特征对应的处理的过程原理相同，此处不再赘述。
在一种可能的实现方式中，针对同一报文组中的各个报文包括其他数据的情况，对于该各个报文中的任一报文，第一芯片用于对该任一报文进行处理的资源基于第一芯片的性能、该任一报文所在报文组包括的报文数量、执行关键特征对应的处理的代价和执行其他数据对应的处理的代价确定。
示例性地，第一芯片用于对该任一报文进行处理的资源基于第一芯片的性能、该任一报文所在报文组包括的报文数量、执行关键特征对应的处理的代价和执行其他数据对应的处理的代价按照如下公式2确定：
Figure PCTCN2022075530-appb-000004
其中，R 2为第一芯片用于对该任一报文进行处理的资源，P为第一芯片的性能，N为该任一报文所在报文组包括的报文数量，A为执行关键特征对应的处理的代价，B为执行其他数据对应的处理的代价。基于公式2可知，在任一报文的报文头数据包括关键特征和非关键 特征的情况下，该关键特征占报文头数据的比例越高，第一芯片用于对该任一报文执行处理的资源越低。因此，相较于相关技术中的报文处理方法，本申请实施例提供的报文处理方法处理相同数量的报文所需的设备资源较低。
例如，针对上述情况A，对于同一报文组中的任一报文，第一芯片用于对该任一报文进行处理的资源基于第一芯片的性能、该任一报文所在报文组包括的报文数量，执行关键特征对应的处理的代价和执行非关键特征对应的处理的代价确定。
又例如，针对上述情况B，对于同一报文组中的第一报文，第一芯片用于对第一报文进行处理的资源基于第一芯片的性能、第一报文所在报文组包括的报文数量、执行关键特征对应的处理的代价和执行非关键特征对应的处理的代价确定。对于同一报文组中的第二报文，第一芯片用于对第二报文进行处理的资源基于第一芯片的性能、第二报文所在报文组包括的报文数量、执行关键特征对应的处理的代价和执行报文头差异数据对应的处理的代价确定。
又例如，针对上述情况C，对于同一报文组中的第一报文，第一芯片用于对第一报文进行处理的资源基于第一芯片的性能、第一报文所在报文组包括的报文数量、执行关键特征对应的处理的代价和执行第一非关键特征对应的处理的代价确定。对于同一报文组中的第二报文，第一芯片用于对第二报文进行处理的资源基于第一芯片的性能、第二报文所在报文组包括的报文数量、执行关键特征对应的处理的代价、获取第二报文的完整的报文头数据的代价和执行第二非关键特征对应的处理的代价确定。
本申请实施例提供的方法，通过对属于同一报文组的各个具有相同关键特征的报文执行关键特征对应的处理，能够降低第一芯片对各个报文执行处理所需的设备资源。此外，由于第一芯片能够在一次处理过程中对各个报文执行关键特征对应的处理，报文处理的效率较高。
本申请实施例还提供了一种报文处理装置。图4是本申请实施例提供的一种报文处理装置的结构示意图。基于图4所示的如下多个模块，该图4所示的报文装置能够执行第一芯片所执行的全部或部分操作。应理解到，该装置可以包括比所示模块更多的附加模块或者省略其中所示的一部分模块，本申请实施例对此并不进行限制。如图4所示，该装置包括：
获取模块401，用于获取具有相同关键特征的多个报文，其中，关键特征的数量为至少一个；
分组模块402，用于对多个报文进行分组，得到至少一个报文组；
处理模块403，用于对于至少一个报文组中的各个报文组，对属于同一报文组的各个报文执行关键特征对应的处理。
在一种可能的实现方式中，同一报文组中的各个报文均包括完整的报文头数据，完整的报文头数据包括关键特征。
在一种可能的实现方式中，同一报文组中的第一报文包括完整的报文头数据，同一报文组中的第二报文包括报文头差异数据，第一报文为同一报文组中的任一报文，第二报文为同一报文组中除第一报文外的其他报文；其中，完整的报文头数据包括关键特征，报文头差异数据基于第二报文的报文头数据和第一报文的报文头数据的差异确定。
在一种可能的实现方式中，同一报文组中的第一报文包括完整的报文头数据，同一报文组中的第二报文包括描述符，第一报文为同一报文组中的任一报文，第二报文为同一报文组中除第一报文外的其他报文；其中，完整的报文头数据包括关键特征，描述符用于获取第二报文包括的完整的报文头数据。
在一种可能的实现方式中，处理模块403，还用于对各个报文执行非关键特征对应的处理，非关键特征为完整的报文头数据中除关键特征外的其他数据。
在一种可能的实现方式中，处理模块403，还用于对第一报文执行非关键特征对应的处理，非关键特征为完整的报文头数据中除关键特征外的其他数据；对第二报文执行报文头差异数据对应的处理。
在一种可能的实现方式中，处理模块403，还用于对第一报文执行第一非关键特征对应的处理，其中，第一非关键特征为第一报文的完整的报文头数据中除关键特征外的其他数据；基于描述符获取第二报文的完整的报文头数据，其中，第二报文的完整的报文头数据包括关键特征和第二非关键特征，第二非关键特征为第二报文的完整的报文头数据中除关键特征外的其他数据；对第二报文执行第二非关键特征对应的处理。
在一种可能的实现方式中，获取模块401，用于获取多个报文，获取多个报文中的各个报文的各个关键特征的特征值；基于各个报文的各个关键特征的特征值，获取各个报文的哈希值；基于各个报文的哈希值，确定各个报文的关键特征是否相同。
在一种可能的实现方式中，获取模块401，用于基于各个报文的各个关键特征的特征值和第一哈希算法，获取各个报文的第一哈希值；基于各个报文的各个关键特征的特征值和第二哈希算法，获取各个报文的第二哈希值；将各个报文的第一哈希值和各个报文的第二哈希值作为各个报文的哈希值。
在一种可能的实现方式中，获取模块401，用于基于各个报文的各个关键特征的特征值和第三哈希算法，获取各个报文的第三哈希值；对于各个报文的各个关键特征，基于各个关键特征的特征值和第四哈希算法，获取各个关键特征的第四哈希值；将各个报文的第三哈希值和各个报文的各个关键特征的第四哈希值作为各个报文的哈希值。
在一种可能的实现方式中，获取模块401，用于基于各个报文的第一哈希值，获取至少一个缓存组；对于至少一个缓存组中的各个缓存组，基于属于同一缓存组的各个报文的第二哈希值，确定属于同一缓存组的各个报文的关键特征是否相同。
在一种可能的实现方式中，获取模块401，用于基于各个报文的第三哈希值，获取至少一个缓存组；对于至少一个缓存组中的各个缓存组，基于属于同一缓存组的各个报文的各个关键特征的第四哈希值，确定属于同一缓存组的各个报文的关键特征是否相同。
在一种可能的实现方式中，关键特征包括入端口号、目的媒体接入控制MAC地址、目的网际互连协议IP地址、源IP地址、源MAC地址中的至少一种。
在一种可能的实现方式中，对于属于同一报文组的各个报文中的任一报文，处理模块403用于对任一报文执行关键特征对应的处理的资源基于处理模块403的性能、任一报文所在报文组包括的报文数量和执行关键特征对应的处理的代价确定。
在一种可能的实现方式中，处理模块403用于对任一报文执行关键特征对应的处理的资源基于处理模块403的性能、任一报文所在报文组包括的报文数量和执行关键特征对应的处理的代价按照如下公式确定：
Figure PCTCN2022075530-appb-000005
其中，R 1为处理模块403用于对任一报文执行关键特征对应的处理的资源，P为处理模块403的性能，N为任一报文所在报文组包括的报文数量，A为执行关键特征对应的处理的代价。
应理解的是，上述图4提供的装置在实现其功能时，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将设备的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。另外，上述实施例提供的装置与方法实施例属于同一构思，其具体实现过程详见方法实施例，这里不再赘述。
本申请实施例提供了一种网络设备，该设备包括：处理器，该处理器与存储器耦合，该存储器中存储有至少一条程序指令或代码，该至少一条程序指令或代码由该处理器加载并执行，以使该网络设备实现如上述方法实施例中的方法。
参见图5，图5示出了本申请一个示例性实施例提供的网络设备1100的结构示意图，该网络设备1100为发送侧/接收侧设备。图5所示的网络设备1100用于执行上述图2所示的报文处理方法所涉及的操作。该网络设备1100例如是交换机、路由器等网络设备以及其他包含这种芯片级联模式的设备(例如服务器、个人电脑PC等)。该网络设备1100的硬件结构包括通信接口1101和处理器1102。可选地，通信接口1101和处理器1102之间通过总线1104连接。其中，通信接口1101用于接收其他设备发送的报文，处理器可存储有指令或程序代码，通过调用该指令或程序代码来执行上述第一芯片所执行的功能。可选地，该网络设备还包括存储器1103，由存储器1103存放指令或程序代码，处理器1102用于调用存储器1103中的指令或程序代码使得网络设备执行上述方法实施例中第一芯片的相关处理步骤。在具体实施例中，本申请实施例的网络设备1100可包括上述各个方法实施例中的第一芯片，网络设备1100中的处理器1102读取存储器1103中的指令或程序代码，使图5所示的网络设备1100能够执行第一芯片所执行的全部或部分操作。
示例性地，处理器1102例如是通用中央处理器(central processing unit，CPU)、数字信号处理器(digital signal processor，DSP)、网络处理器(network processer，NP)、图形处理器(graphics processing unit，GPU)、神经网络处理器(neural-network processing units，NPU)、数据处理单元(data processing unit，DPU)、微处理器或者一个或多个用于实现本申请方案的集成电路。例如，处理器1102包括专用集成电路(application-specific integrated circuit，ASIC)，可编程逻辑器件(programmable logic device，PLD)或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合。PLD例如是复杂可编程逻辑器件(complex programmable logic device，CPLD)、现场可编程逻辑门阵列(field-programmable gate array，FPGA)、通用阵列逻辑(generic array logic，GAL)或其任意组合。其可以实现或执行结合本发明实施例公开内容所描述的各种逻辑方框、模块和电路。处理器也可以是实现计算功能的组合，例如包括一个或多个微处理器组合，DSP和微处理器的组合等等。
可选的，网络设备1100还包括总线。总线用于在网络设备1100的各组件之间传送信息。总线可以是外设部件互连标准(peripheral component interconnect，简称PCI)总线或扩展工业标准结构(extended industry standard architecture，简称EISA)总线等。总线可以分为地址总线、数据总线、控制总线等。为便于表示，图5中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。图5中网络设备1100的各组件之间除了采用总线连接，还可采用其他方式连接，本发明实施例不对各组件的连接方式进行限定。
存储器1103例如是只读存储器(read-only memory，ROM)或可存储静态信息和指令的其它类型的静态存储设备，又如是随机存取存储器(random access memory，RAM)或者可存储信息和指令的其它类型的动态存储设备，又如是电可擦可编程只读存储器(electrically  erasable programmable read-only memory，EEPROM)、只读光盘(compact disc read-only memory，CD-ROM)或其它光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其它磁存储设备，或者是能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其它介质，但不限于此。存储器1103例如是独立存在，并通过总线与处理器1102相连接。存储器1103也可以和处理器1102集成在一起。
通信接口1101使用任何收发器一类的装置，用于与其它设备或通信网络通信，通信网络可以为以太网、无线接入网(RAN)或无线局域网(wireless local area networks，WLAN)等。通信接口1101可以包括有线通信接口，还可以包括无线通信接口。具体的，通信接口1101可以为以太(ethernet)接口、快速以太(fast ethernet，FE)接口、千兆以太(gigabit ethernet，GE)接口，异步传输模式(asynchronous transfer mode，ATM)接口，无线局域网(wireless local area networks，WLAN)接口，蜂窝网络通信接口或其组合。以太网接口可以是光接口，电接口或其组合。在本申请实施例中，通信接口1101可以用于网络设备1100与其他设备进行通信。
在具体实现中，作为一种实施例，处理器1102可以包括一个或多个处理器。这些处理器中的每一个可以是一个单核(single-CPU)处理器，也可以是一个多核(multi-CPU)处理器。这里的处理器可以指一个或多个设备、电路、和/或用于处理数据(例如计算机程序指令)的处理核。
在具体实现中，作为一种实施例，网络设备1100还可以包括输出设备和输入设备。输出设备和处理器1102通信，可以以多种方式来显示信息。例如，输出设备可以是液晶显示器(liquid crystal display，LCD)、发光二级管(light emitting diode，LED)显示设备、阴极射线管(cathode ray tube，CRT)显示设备或投影仪(projector)等。输入设备和处理器1102通信，可以以多种方式接收用户的输入。例如，输入设备可以是鼠标、键盘、触摸屏设备或传感设备等。
在一些实施例中，存储器1103用于存储执行本申请方案的程序代码，处理器1102可以执行存储器1103中存储的程序代码。也即是，网络设备1100可以通过处理器1102以及存储器1103中的程序代码，来实现方法实施例提供的报文处理方法。程序代码中可以包括一个或多个软件模块。可选地，处理器1102自身也可以存储执行本申请方案的程序代码或指令。
在具体实施例中，本申请实施例的网络设备1100可包括上述各个方法实施例中的第一芯片，网络设备1100中的处理器1102读取存储器1103中的程序代码或处理器1102自身存储的程序代码或指令，使图5所示的网络设备1100能够执行第一芯片所执行的全部或部分操作。
网络设备1100还可以对应于上述图4所示的装置，图4所示的装置中的每个功能模块采用网络设备1100的软件实现。换句话说，图4所示的装置包括的功能模块为网络设备1100的处理器1102读取存储器1103中存储的程序代码后生成的。
其中，图2所示的报文处理方法的各步骤通过网络设备1100的处理器中的硬件的集成逻辑电路或者软件形式的指令完成。结合本申请实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤，为避免重复，这里不再详细描述。
应理解的是，上述处理器可以是中央处理器(central processing unit，CPU)，还可以是其他通用处理器、数字信号处理器(digital signal processing，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field-programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者是任何常规的处理器等。值得说明的是，处理器可以是支持进阶精简指令集机器(advanced RISC machines，ARM)架构的处理器。
进一步地，在一种可选的实施例中，上述存储器可以包括只读存储器和随机存取存储器，并向处理器提供指令和数据。存储器还可以包括非易失性随机存取存储器。例如，存储器还可以存储设备类型的信息。
该存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用。例如，静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(dynamic random access memory，DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data date SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM，DR RAM)。
还提供了一种计算机可读存储介质，存储介质中存储有至少一条程序指令或代码，所述程序指令或代码由处理器加载并执行时以使计算机实现如上图2所示的报文处理方法。
本申请提供了一种计算机程序，当计算机程序被计算机执行时，可以使得处理器或计算机执行上述方法实施例中对应的各个步骤和/或流程。
提供了一种芯片，包括处理器，用于从存储器中调用并运行所述存储器中存储的指令，使得安装有所述芯片的设备执行上述各方面中的方法。
提供另一种芯片，包括：输入接口、输出接口、处理器和存储器，所述输入接口、输出接口、所述处理器以及所述存储器之间通过内部连接通路相连，所述处理器用于执行所述存储器中的代码，当所述代码被执行时，所述处理器用于执行上述各方面中的方法。
提供一种设备，包括上述方案中的任一芯片。
在一些实施例中，第一芯片可以是发送侧/接收侧设备，比如路由器、交换机、服务器中的物理层(PHY)芯片，第一芯片可以是发送侧/接收侧设备的接口，比如光模块中的芯片或者CDR/retimer芯片。该PHY芯片可以是位于计算设备的单板上的芯片，该芯片可以是CPU、网络处理器(network processor，NP)、神经网络处理单元(neural network processing unit,NPU)、FPGA、可编程逻辑控制器(programmable logic controller，PLC)等中的一个或其任意组合。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算 机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线)或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘，solid state disk)等。
以上所述的具体实施方式，对本申请的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本申请的具体实施方式而已，并不用于限定本申请的保护范围，凡在本申请的技术方案的基础之上，所做的任何修改、等同替换、改进等，均应包括在本申请的保护范围之内。
本领域普通技术人员可以意识到，结合本文中所公开的实施例中描述的各方法步骤和模块，能够以软件、硬件、固件或者其任意组合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各实施例的步骤及组成。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。本领域普通技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，该程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。该计算机程序产品包括一个或多个计算机程序指令。作为示例，本申请实施例的方法可以在机器可执行指令的上下文中被描述，机器可执行指令诸如包括在目标的真实或者虚拟处理器上的器件中执行的程序模块中。一般而言，程序模块包括例程、程序、库、对象、类、组件、数据结构等，其执行特定的任务或者实现特定的抽象数据结构。在各实施例中，程序模块的功能可以在所描述的程序模块之间合并或者分割。用于程序模块的机器可执行指令可以在本地或者分布式设备内执行。在分布式设备中，程序模块可以位于本地和远程存储介质二者中。
用于实现本申请实施例的方法的计算机程序代码可以用一种或多种编程语言编写。这些计算机程序代码可以提供给通用计算机、专用计算机或其他可编程的数据处理装置的处理器，使得程序代码在被计算机或其他可编程的数据处理装置执行的时候，引起在流程图和/或框图中规定的功能/操作被实施。程序代码可以完全在计算机上、部分在计算机上、作为独立的软件包、部分在计算机上且部分在远程计算机上或完全在远程计算机或服务器上执行。
在本申请实施例的上下文中，计算机程序代码或者相关数据可以由任意适当载体承载，以使得设备、装置或者处理器能够执行上文描述的各种处理和操作。载体的示例包括信号、计算机可读介质等等。
信号的示例可以包括电、光、无线电、声音或其它形式的传播信号，诸如载波、红外信号等。
机器可读介质可以是包含或存储用于或有关于指令执行系统、装置或设备的程序的任何有形介质。机器可读介质可以是机器可读信号介质或机器可读存储介质。机器可读介质可以包括但不限于电子的、磁的、光学的、电磁的、红外的或半导体系统、装置或设备，或其任意合适的组合。机器可读存储介质的更详细示例包括带有一根或多根导线的电气连接、便携 式计算机磁盘、硬盘、随机存储存取器(RAM)、只读存储器(ROM)、可擦除可编程只读存储器(EPROM或闪存)、光存储设备、磁存储设备，或其任意合适的组合。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的系统、设备和模块的具体工作过程，可以参见前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、设备和方法，可以通过其它的方式实现。例如，以上所描述的设备实施例仅仅是示意性的，例如，该模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个模块或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、设备或模块的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
该作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理模块，即可以位于一个地方，或者也可以分布到多个网络模块上。可以根据实际的需要选择其中的部分或者全部模块来实现本申请实施例方案的目的。
另外，在本申请各个实施例中的各功能模块可以集成在一个处理模块中，也可以是各个模块单独物理存在，也可以是两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。
该集成的模块如果以软件功能模块的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分，或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例中方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read-only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
本申请中术语“第一”“第二”等字样用于对作用和功能基本相同的相同项或相似项进行区分，应理解，“第一”、“第二”、“第n”之间不具有逻辑或时序上的依赖关系，也不对数量和执行顺序进行限定。还应理解，尽管以下描述使用术语第一、第二等来描述各种元素，但这些元素不应受术语的限制。这些术语只是用于将一元素与另一元素区别分开。例如，在不脱离各种所述示例的范围的情况下，第一网络设备可以被称为第二网络设备，并且类似地，第二网络设备可以被称为第一网络设备。第一网络和设备和第二网络设备都可以是网络设备，并且在某些情况下，可以是单独且不同的网络设备。
还应理解，在本申请的各个实施例中，各个过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
本申请中术语“至少一个”的含义是指一个或多个，本申请中术语“多个”的含义是指两个或两个以上，例如，多个第二报文是指两个或两个以上的第二报文。本文中术语“系统”和“网络”经常可互换使用。
应理解，在本文中对各种所述示例的描述中所使用的术语只是为了描述特定示例，而并非旨在进行限制。如在对各种所述示例的描述和所附权利要求书中所使用的那样，单数形式“一个(“a”，“an”)”和“该”旨在也包括复数形式，除非上下文另外明确地指示。
还应理解，术语“包括”(也称“includes”、“including”、“comprises”和/或“comprising”)当 在本说明书中使用时指定存在所陈述的特征、整数、步骤、操作、元素、和/或部件，但是并不排除存在或添加一个或多个其他特征、整数、步骤、操作、元素、部件、和/或其分组。
还应理解，术语“若”和“如果”可被解释为意指“当...时”(“when”或“upon”)或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“若确定...”或“若检测到[所陈述的条件或事件]”可被解释为意指“在确定...时”或“响应于确定...”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
应理解，根据A确定B并不意味着仅仅根据A确定B，还可以根据A和/或其它信息确定B。
还应理解，说明书通篇中提到的“一个实施例”、“一实施例”、“一种可能的实现方式”意味着与实施例或实现方式有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”、“一种可能的实现方式”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。

Claims (33)

  1. 一种报文处理方法，其特征在于，所述方法包括：
    第一芯片获取具有相同关键特征的多个报文，其中，所述关键特征的数量为至少一个；
    所述第一芯片对所述多个报文进行分组，得到至少一个报文组；
    对于所述至少一个报文组中的各个报文组，所述第一芯片对属于同一报文组的各个报文执行所述关键特征对应的处理。
  2. 根据权利要求1所述的方法，其特征在于，所述同一报文组中的各个报文均包括完整的报文头数据，所述完整的报文头数据包括所述关键特征。
  3. 根据权利要求1所述的方法，其特征在于，所述同一报文组中的第一报文包括完整的报文头数据，所述同一报文组中的第二报文包括报文头差异数据，所述第一报文为所述同一报文组中的任一报文，所述第二报文为所述同一报文组中除所述第一报文外的其他报文；
    其中，所述完整的报文头数据包括所述关键特征，所述报文头差异数据基于所述第二报文的报文头数据和所述第一报文的报文头数据的差异确定。
  4. 根据权利要求1所述的方法，其特征在于，所述同一报文组中的第一报文包括完整的报文头数据，所述同一报文组中的第二报文包括描述符，所述第一报文为所述同一报文组中的任一报文，所述第二报文为所述同一报文组中除所述第一报文外的其他报文；
    其中，所述完整的报文头数据包括所述关键特征，所述描述符用于获取所述第二报文包括的完整的报文头数据。
  5. 根据权利要求2所述的方法，其特征在于，所述方法还包括：
    所述第一芯片对所述各个报文执行非关键特征对应的处理，所述非关键特征为所述完整的报文头数据中除所述关键特征外的其他数据。
  6. 根据权利要求3所述的方法，其特征在于，所述方法还包括：
    所述第一芯片对所述第一报文执行非关键特征对应的处理，所述非关键特征为所述完整的报文头数据中除所述关键特征外的其他数据；
    所述第一芯片对所述第二报文执行所述报文头差异数据对应的处理。
  7. 根据权利要求4所述的方法，其特征在于，所述方法还包括：
    所述第一芯片对所述第一报文执行第一非关键特征对应的处理，其中，所述第一非关键特征为所述第一报文的完整的报文头数据中除所述关键特征外的其他数据；
    所述第一芯片基于所述描述符获取所述第二报文的完整的报文头数据，其中，所述第二报文的完整的报文头数据包括所述关键特征和第二非关键特征，所述第二非关键特征为所述第二报文的完整的报文头数据中除所述关键特征外的其他数据；
    所述第一芯片对所述第二报文执行所述第二非关键特征对应的处理。
  8. 根据权利要求1-7任一所述的方法，其特征在于，所述第一芯片获取具有相同关键特征的多个报文，包括：
    所述第一芯片获取多个报文，获取所述多个报文中的各个报文的各个关键特征的特征值；
    所述第一芯片基于所述各个报文的各个关键特征的特征值，获取所述各个报文的哈希值；
    所述第一芯片基于所述各个报文的哈希值，确定所述各个报文的关键特征是否相同。
  9. 根据权利要求8所述的方法，其特征在于，所述第一芯片基于所述各个报文的各个关键特征的特征值，获取所述各个报文的哈希值，包括：
    所述第一芯片基于所述各个报文的各个关键特征的特征值和第一哈希算法，获取所述各个报文的第一哈希值；
    所述第一芯片基于所述各个报文的各个关键特征的特征值和第二哈希算法，获取所述各个报文的第二哈希值；
    所述第一芯片将所述各个报文的第一哈希值和所述各个报文的第二哈希值作为所述各个报文的哈希值。
  10. 根据权利要求8所述的方法，其特征在于，所述第一芯片基于所述各个报文的各个关键特征的特征值，获取所述各个报文的哈希值，包括：
    所述第一芯片基于所述各个报文的各个关键特征的特征值和第三哈希算法，获取所述各个报文的第三哈希值；
    对于所述各个报文的各个关键特征，所述第一芯片基于所述各个关键特征的特征值和第四哈希算法，获取所述各个关键特征的第四哈希值；
    所述第一芯片将所述各个报文的第三哈希值和所述各个报文的各个关键特征的第四哈希值作为所述各个报文的哈希值。
  11. 根据权利要求9所述的方法，其特征在于，所述第一芯片基于所述各个报文的哈希值，确定所述各个报文的关键特征是否相同，包括：
    所述第一芯片基于所述各个报文的第一哈希值，获取至少一个缓存组；
    对于所述至少一个缓存组中的各个缓存组，所述第一芯片基于属于同一缓存组的各个报文的第二哈希值，确定所述属于同一缓存组的各个报文的关键特征是否相同。
  12. 根据权利要求10所述的方法，其特征在于，所述第一芯片基于所述各个报文的哈希值，确定所述各个报文的关键特征是否相同，包括：
    所述第一芯片基于所述各个报文的第三哈希值，获取至少一个缓存组；
    对于所述至少一个缓存组中的各个缓存组，所述第一芯片基于属于同一缓存组的各个报文的各个关键特征的第四哈希值，确定所述属于同一缓存组的各个报文的关键特征是否相同。
  13. 根据权利要求1-12任一所述的方法，其特征在于，所述关键特征包括入端口号、目的媒体接入控制MAC地址、目的网际互连协议IP地址、源IP地址、源MAC地址中的至少一种。
  14. 根据权利要求1-13任一所述的方法，其特征在于，对于所述属于同一报文组的各个报 文中的任一报文，所述第一芯片用于对所述任一报文执行所述关键特征对应的处理的资源基于所述第一芯片的性能、所述任一报文所在报文组包括的报文数量和执行所述关键特征对应的处理的代价确定。
  15. 根据权利要求14所述的方法，其特征在于，所述第一芯片用于对所述任一报文执行所述关键特征对应的处理的资源基于所述第一芯片的性能、所述任一报文所在报文组包括的报文数量和执行所述关键特征对应的处理的代价按照如下公式确定：
    Figure PCTCN2022075530-appb-100001
    其中，所述R 1为所述第一芯片用于对所述任一报文执行所述关键特征对应的处理的资源，所述P为所述第一芯片的性能，所述N为所述任一报文所在报文组包括的报文数量，所述A为所述执行所述关键特征对应的处理的代价。
  16. 一种报文处理装置，其特征在于，所述装置包括：
    获取模块，用于获取具有相同关键特征的多个报文，其中，所述关键特征的数量为至少一个；
    分组模块，用于对所述多个报文进行分组，得到至少一个报文组；
    处理模块，用于对于所述至少一个报文组中的各个报文组，对属于同一报文组的各个报文执行所述关键特征对应的处理。
  17. 根据权利要求16所述的装置，其特征在于，所述同一报文组中的各个报文均包括完整的报文头数据，所述完整的报文头数据包括所述关键特征。
  18. 根据权利要求16所述的装置，其特征在于，所述同一报文组中的第一报文包括完整的报文头数据，所述同一报文组中的第二报文包括报文头差异数据，所述第一报文为所述同一报文组中的任一报文，所述第二报文为所述同一报文组中除所述第一报文外的其他报文；其中，所述完整的报文头数据包括所述关键特征，所述报文头差异数据基于所述第二报文的报文头数据和所述第一报文的报文头数据的差异确定。
  19. 根据权利要求16所述的装置，其特征在于，所述同一报文组中的第一报文包括完整的报文头数据，所述同一报文组中的第二报文包括描述符，所述第一报文为所述同一报文组中的任一报文，所述第二报文为所述同一报文组中除所述第一报文外的其他报文；其中，所述完整的报文头数据包括所述关键特征，所述描述符用于获取所述第二报文包括的完整的报文头数据。
  20. 根据权利要求17所述的装置，其特征在于，所述处理模块，还用于对所述各个报文执行非关键特征对应的处理，所述非关键特征为所述完整的报文头数据中除所述关键特征外的其他数据。
  21. 根据权利要求18所述的装置，其特征在于，所述处理模块，还用于对所述第一报文执 行非关键特征对应的处理，所述非关键特征为所述完整的报文头数据中除所述关键特征外的其他数据；对所述第二报文执行所述报文头差异数据对应的处理。
  22. 根据权利要求19所述的装置，其特征在于，所述处理模块，还用于对所述第一报文执行第一非关键特征对应的处理，其中，所述第一非关键特征为所述第一报文的完整的报文头数据中除所述关键特征外的其他数据；基于所述描述符获取所述第二报文的完整的报文头数据，其中，所述第二报文的完整的报文头数据包括所述关键特征和第二非关键特征，所述第二非关键特征为所述第二报文的完整的报文头数据中除所述关键特征外的其他数据；对所述第二报文执行所述第二非关键特征对应的处理。
  23. 根据权利要求16-22任一所述的装置，其特征在于，所述获取模块，用于获取多个报文，获取所述多个报文中的各个报文的各个关键特征的特征值；基于所述各个报文的各个关键特征的特征值，获取所述各个报文的哈希值；基于所述各个报文的哈希值，确定所述各个报文的关键特征是否相同。
  24. 根据权利要求23所述的装置，其特征在于，所述获取模块，用于基于所述各个报文的各个关键特征的特征值和第一哈希算法，获取所述各个报文的第一哈希值；基于所述各个报文的各个关键特征的特征值和第二哈希算法，获取所述各个报文的第二哈希值；将所述各个报文的第一哈希值和所述各个报文的第二哈希值作为所述各个报文的哈希值。
  25. 根据权利要求23所述的装置，其特征在于，所述获取模块，用于基于所述各个报文的各个关键特征的特征值和第三哈希算法，获取所述各个报文的第三哈希值；对于所述各个报文的各个关键特征，基于所述各个关键特征的特征值和第四哈希算法，获取所述各个关键特征的第四哈希值；将所述各个报文的第三哈希值和所述各个报文的各个关键特征的第四哈希值作为所述各个报文的哈希值。
  26. 根据权利要求24所述的装置，其特征在于，所述获取模块，用于基于所述各个报文的第一哈希值，获取至少一个缓存组；对于所述至少一个缓存组中的各个缓存组，基于属于同一缓存组的各个报文的第二哈希值，确定所述属于同一缓存组的各个报文的关键特征是否相同。
  27. 根据权利要求25所述的装置，其特征在于，所述获取模块，用于基于所述各个报文的第三哈希值，获取至少一个缓存组；对于所述至少一个缓存组中的各个缓存组，基于属于同一缓存组的各个报文的各个关键特征的第四哈希值，确定所述属于同一缓存组的各个报文的关键特征是否相同。
  28. 根据权利要求16-27任一所述的装置，其特征在于，所述关键特征包括入端口号、目的媒体接入控制MAC地址、目的网际互连协议IP地址、源IP地址、源MAC地址中的至少一种。
  29. 根据权利要求16-28任一所述的装置，其特征在于，对于所述属于同一报文组的各个报 文中的任一报文，所述处理模块用于对所述任一报文执行所述关键特征对应的处理的资源基于所述处理模块的性能、所述任一报文所在报文组包括的报文数量和执行所述关键特征对应的处理的代价确定。
  30. 根据权利要求29所述的装置，其特征在于，所述处理模块用于对所述任一报文执行所述关键特征对应的处理的资源基于所述处理模块的性能、所述任一报文所在报文组包括的报文数量和执行所述关键特征对应的处理的代价按照如下公式确定：
    Figure PCTCN2022075530-appb-100002
    其中，所述R 1为所述处理模块用于对所述任一报文执行所述关键特征对应的处理的资源，所述P为所述处理模块的性能，所述N为所述任一报文所在报文组包括的报文数量，所述A为所述执行所述关键特征对应的处理的代价。
  31. 一种网络设备，其特征在于，所述网络设备包括：处理器，所述处理器与存储器耦合，所述存储器中存储有至少一条程序指令或代码，所述至少一条程序指令或代码由所述处理器加载并执行，以使所述网络设备实现权利要求1-15任一所述的报文处理方法。
  32. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有至少一条程序指令或代码，所述程序指令或代码由处理器加载并执行，以使计算机实现如权利要求1-15中任一所述的报文处理方法。
  33. 一种计算机程序产品，其特征在于，所述计算机程序产品包括计算机程序，所述计算机程序被计算机执行，以使所述计算机实现如权利要求1-15中任一所述的报文处理方法。
PCT/CN2022/075530 2021-08-16 2022-02-08 报文处理方法、装置、设备及计算机可读存储介质 WO2023019889A1 (zh)

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