WO2023018476A1 - A circuit and system for a very high throughput true random number generator (trng) for next generation secure hardware and communication systems - Google Patents

A circuit and system for a very high throughput true random number generator (trng) for next generation secure hardware and communication systems Download PDF

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Publication number
WO2023018476A1
WO2023018476A1 PCT/US2022/033332 US2022033332W WO2023018476A1 WO 2023018476 A1 WO2023018476 A1 WO 2023018476A1 US 2022033332 W US2022033332 W US 2022033332W WO 2023018476 A1 WO2023018476 A1 WO 2023018476A1
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Prior art keywords
entropy
source blocks
random number
output signals
number generator
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PCT/US2022/033332
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French (fr)
Inventor
Rashad RAMZAN
Hasiq ROHAIL
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Wi-LAN Research Inc.
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Priority to AU2022327059A priority Critical patent/AU2022327059A1/en
Publication of WO2023018476A1 publication Critical patent/WO2023018476A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/588—Random number generators, i.e. based on natural stochastic processes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
    • H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
    • H04L9/0662—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/84—Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators

Definitions

  • the invention described herein discloses a system of circuits for a very' high throughput True Random Number Generator (TRNG).
  • TRNG True Random Number Generator
  • the system of circuits utilizes multiple classes of entropy sources including but not limited to metastability, chaos, power supply noise and perturbations. Further disclosed are the components and modules that implement the TRNG invention, as is evident from the embodiments and aspects described herein and from the accompanying drawings.
  • Random Numbers are an essential part of any modern communication system to ensure encryption and security wherein they are used to generate and manage secure keys for encryption algorithms.
  • devices currently communicate at several Mbps up to Gbps. These systems include satellites and base stations that form the core of the network and communicate with hundreds of devices simultaneously and will require the generation of random numbers at very high data rates.
  • MMIMO Massive Multiple Input Multiple Output
  • the number of these devices is expected to exponentially grow, as billions of Internet of Things (loT) devices/ sensors get connected to the cloud systems, thereby requiring very high data rate random numbers.
  • the generated random numbers must be statistically independent to pass the randomness tests, and the generation systems must be robust against different types of hardware attacks.
  • Some examples of these attacks are: initial condition determination by rigorous statistical analysis, forced biasing using environment tampering attacks such as EMI, temperature manipulation, etc.; and other methods that empower an attacker to predict the next bit. by analyzing the previous ones. Last but not least, these random number generators must also be able to easily integrate into the current microchip technology without requiring extra cost or manufacturing steps.
  • Random numbers are generated either from hardware-based True Random Number Generators (TRNGs) or software-based Pseudo-Random Number Generators (PRNGs), where the output of a TRNG is the seed for a PRNG.
  • TRNGs that use various entropy sources are available in the prior art including the ones that use thermal/shot noise of resistors with amplifiers, sampling jitter of the oscillator(s), deterministic but unpredictable chaos, metastability, quantum entropy sources, just to name few. However, all of them have their strengths and weaknesses.
  • the metastability and thermal noise based TRNGs are relatively less sensitive to initial conditions, but they are susceptible to environmental attacks such as EMI that enhance or suppress the circuit noise or bias the average voltages more towards one side, or manipulate temperature, pressure, humidity, etc.
  • the chaos-based TRNGs are immune to voltage biasing or EMI based attacks, but their outputs can be tracked given the initial conditions.
  • the chaos-based TRNGs generally operate in the discrete domain and have relatively low generation rates, due to the limitation of the buffer and sample-and-hold circuits involved.
  • the jitter-based oscillator sampling method is widely used because it can be implemented both in a semi-customized digital circuit and a fully customized digital -analog hybrid one, but it cannot provide very high data rates without compromising the randomness of the generated stream.
  • TRNGs that incorporate weak random sources and use post-processing to reduce the bias in the output stream, such as the Von Neumann scheme, are prone to data rate fluctuations with time due to the bits that they discard.
  • a new set of TRNGs based on quantum noise sources use entropy sources such as single- photon detection or the variations in the intensity of a light source, etc.
  • QRNGs Quantum Random Number Generators
  • QRNGs Quantum Random Number Generators
  • these QRNGs are difficult to implement in the Bulk CMOS technology since they typically require additional and costly manufacturing steps.
  • a known class of TRNGs combines the output streams of multiple entropy sources to get a single stream using functions such as XOR, etc. Although the generation of the streams is independent in these TNRGs, they use the same type of generation source, i.e., taking the output of two different instances of the same TRNG. In comparison, the design of the disclosed invention set forth below combines output of different classes of entropy sources so that, the output of one source directly affects that of the other to increase the randomness of the output steam.
  • the TRNGs in prior art generate multiple independent streams from different sources and then combine them.
  • Our invention as set forth below, in comparison, changes the input or biasing or initial conditions of one entropy source based on the output of other entropy sources.
  • the invention described herein combines different classes of entropy sources in a novel way and makes it less susceptible to different types of above-mentioned attacks. Accordingly, since all of the entropy sources send analog voltages to the subsequent stages instead of the digital bits, therefore, their entropy remains preserved until the final sampling.
  • a novel ring oscillator constitutes a significant aspect of our invention thereby enabling it to achieve very high generation rates with a small on-chip area.
  • the generation rate of one randomness source is significantly higher than the others, then their output approximately stays constant for a short time period during which only that source generates random numbers.
  • some of the generated output bits get discarded by a post-processing technique to remove bias by analyzing the previous output. bit(s).
  • the Von-Neumann technique compares a pair of bits for similarity; it uses only one of them if they are different or discards both of them if they are the same.
  • the Random Number Generator allows the Random Number Generator to use multiple entropy sources even when the generation rates of some sources are significantly higher than the other ones.
  • the random bits of the TRNG are generated at the rate of the fastest source in the system, but its output is still affected by the entropy of the slower randomness sources.
  • the invention described herein mangles the generated bits, by using bit order multiplexers, to remove the bias. Since the system described herein does not process the outputs of all entropy sources in a single stage to determine the most random bit in comparison with the previous output bit, as a result, the output bits become less dependent on the earlier bits.
  • the novel TRNG described herein is also scalable as it can be manufactured by using any IC technology and can be optimized for performance, speed, power consumption, area, etc. as the usage scenario demands.
  • the novel TRNG described herein can be implemented for a variety of processors ranging from low-power microcontrollers that are used in embedded systems to high throughput multicore server processors, GPUs, etc.
  • Figure 1 is a system level depiction of the novel True Random Number Generator where each entropy source acts as a series stage and controls the input or biasing conditions of the subsequent stage according to aspects to the invention
  • Figure 2 is a system level depiction of the prior True Random Number Generators where all entropy sources act as a single, parallel stage and the outputs of all sources are passed through an entropy combiner module according to aspects to the invention;
  • Figure 3 is a novel Taie Random Number Generator acting as a seed for Pseudo-Random Number Generator to generate random numbers at a higher data rate according to aspects to the invention
  • Figure 4 is a block diagram of a True Random Number Generator with different entropy sources according to aspects to the invention.
  • Figure 5 is a block diagram of the ring oscillator with a variable delay and support for metastability according to aspects to the invention;
  • Figure 6 is a variable delay cell with delay control transistors and pull up switches for metastability according to aspects to the invention
  • Figure 7 is a variable delay ring oscillator circuit with a bandwidth extension inductor to achieve higher generation rates according to aspects to the invention; [0015].
  • Figure 8 is a differential amplifier circuit with additional pull down transistors for faster transition to the metastable state according to aspects to the invention; [0016].
  • Figure 9 i s a three transistor based non-linear tent map circuit with four bias voltages for bifurcation control according to aspects to the invention;
  • Figure 10 is a block diagram of the discrete time chaotic generator circuit In which the non-linear chaotic map circuit can be tent map, chua’s circuit, gauss map, etc. or any other similar circuit according to aspects to the invention,
  • Figure 11 show's normalized power supply variations due to noise including a combination of thermal, 1/f, and switching noise of transistors according to aspects to the invention
  • Figure 12 shows normalized input/output characteristics of the non-linear tent map circuit according to aspects to the invention
  • Figure 13 is a normalized chaotic signal generated for controlling the delay path of the ring oscillator circuit according to aspects to the invention.
  • Figure 14 show's a normalized nieta-stable response of the ring oscillator circuit of Figure 5 according to aspects to the invention
  • Figure 15 is a Taie Random Number Generator with only one output bit for reduced area and power, wherein the XOR gate and delay element are used to remove the bias according to aspects to the invention;
  • Figure 16 is a multicore TRNG using N different instances of the TRNG 100 of Figure 1 for generating random numbers at a faster rate according to aspects to the invention
  • Figure 17 is a flowchart depicting the generation of True Random Numbers using different entropy sources according to aspects to the invention.
  • Figure 18 is a flowchart depicting the generation of True Random Numbers using different entropy sources according to aspects to the invention. [0026].
  • Figure 19 is an embodiment of the delay cell shown in Figure 6 with an additional transistor to improve the operation of the oscillator circuit in its metastable state.
  • Figure 20 is an embodiment of the delay cell shown in Figure 7 with an additional transistor to improve the operation of the oscillator circuit in its metastable state.
  • FIG. 1 shows a system-level embodiment of a novel TRNG 100 based on aspects of the present invention in which each entropy source acts as a block, and its output controls the input/bias of the next block and that next block again may be a different type of entropy source.
  • the various entropy sources 102 can include power supply noise or perturbations 104, deterministic chaos sources (generator) 106, metastability circuits (generator) 110, oscillator jitter-based circuits (generator) 108, or quantum noise extraction circuits, or any other systems, circuits, or sub-circuits that can be the source of the entropy that are not explicitly mentioned in this disclosure but are known to one skilled in the art.
  • the TRNG 100 extracts the maximum entropy, as most of the sources are combined in a series fashion, from the final bit generation stage 112 and subsequently generates the random bit stream as its output 114.
  • Figure 2 shows a typical known TRNG 200 (disclosed in the prior art) where the outputs of all entropy sources 202 are combined at a single bit generation stage 214 to generate the random output bits.
  • the entropy sources 204, 206, 208, and 210 of the typical TRNG 200 may be the same as entropy sources 104, 106, 108, and 110 of novel TRNG 100 but the output of the entropy sources are combined differently.
  • the entropy sources 204, 206, 208, and 210 of typical TRNG 200 are combined in parallel and hence one source cannot affect the output of others.
  • the outputs of all entropy sources are processed digitally at the bit generation 214, which acts as an entropy extractor, to create the random number string which is the TRNG Output 216 of the typical TRNG 200.
  • FIG. 3 shows a system 300 incorporating an embodiment of the invention in which the TRNG 308 is an instance of TRNG 100 of Figure 1 and provides one or more seeds (or secure keys) 304 for the user application 302.
  • the user application 302 generates the output random bit stream 310 using seed or secure keys 304 and an encryption software method or algorithm 306 to achieve even higher generation rates, albeit requiring more processing power.
  • FIG. 4 shows a detailed schematic description of TRNG 400 which is one possible implementation of novel TRNG 100, according to aspects of the invention.
  • the Ring Oscillator 406 of TRNG 400 has a variable delay and supports metastability. Both characteristics are controlled via separate voltage signals: ‘V stage Ctrl’ 422 and ‘Metastability Ctrl’ 420. These voltage sources are controlled via the ‘Chaotic Entropy Source 1’ 404 and ‘V_clk’ 402 signals.
  • the ‘V_clk’ 402 signal is from a predetermined clock source that controls the TRNG’s 400 generation rate.
  • the ‘Chaotic Entropy Source 1 ’ 404 signal is from a chaotic entropy source with a slow varying entropy and controls the oscillation frequency of the ring oscillator circuit 406 that is a fast-varying entropy source.
  • Different possible incarnations of source 404 are: Chua’s circuit implementation or a chaotic circuit based on a non-linear map such as the tent map, logistic map, etc., or any source capable of generating chaotic signals.
  • the ring oscillator 406 utilizes power supply noise perturbations (Entropy Source 2) 408, which are inherent to the circuit and can also be generated using transistors.
  • ring oscillator 406 generates five random outputs, since it has five delay cells as shown in Figure 5 as Delay Cells 524, Output 2 526, 528, 530 and 532.
  • this number of delay cells and random outputs can be changed to any other number depending on the application requirements.
  • Ring oscillator 406 also supports using an even number of delay cells by changing the polarity of the differential signals. Using five outputs is beneficial because it allows for two different oscillation frequencies, one with all five delay cells active and the other with only three of them active. Although increasing the number of delay cells 524, 526, 528, 530, and 532 would give an increased number of outputs, it would also reduce the ring oscillator’s frequency.
  • the output signals of ring oscillator 406 are fed to the sampling circuit 412 through buffers (and/or amplifiers) 410. Subsequently they pass through the multiplexer (bit order multiplexers)) 416 to remove bias.
  • the sampling circuit 412 changes its sampling instance because of input from jitter source (entropy source 3) 414 that is external or may be a part of the circuit.
  • the order of five signals is controlled by the voltage signal of the chaotic source (entropy source 4) 418 as an input to multiplexer(s) 416 that further enhances the entropy of the system.
  • the output of 416 is sent as a five-digit random stream 422 through optional parallel in/serial out shift register 420.
  • some, or all, of the chaotic sources 404 and 418, the jitter source 414, and the power supply variations source 408 are replaced by other entropy sources.
  • the bit order multiplexer 416 and chaotic source 418 are removed to thereby produce the generated bits in a fixed order.
  • FIG. 5 show's a schematic block diagram 500 of ring oscillator 502 which is an embodiment of ring oscillator 406 that is a component of novel TRNG 100 according to an aspect of the invention.
  • Ring oscillator 502 has two different delayed paths, and hence two oscillation frequencies.
  • the first path consists of the delay cells 524, 526 and 528, and switch 536.
  • the second path consists of the delay cells 524, 526 and 528, the switch 538, and also the delay cells 532 and 530.
  • the two switches (such as transistors) 536 and 538 are controlled by the two complementary signals ‘V_fast’ 510 and ‘V_slow’ 512.
  • the switch 536 When the switch 536 is ON, the signal propagates through the first delay path with a corresponding delay.
  • Each delay cell can be a simple inverter-based delay cell, a transmission line-based delay cell, the delay cell 600 of Figure 6 described below, the delay cell 700 of Figure 7 described below, etc., or any other type of known delay cell not explicitly mentioned herein.
  • Q Pull up transistor 534 represents one of the transistors which connect all five of the outputs 514, 516, 518, 520 and 522 to the supply ‘VDD’ 504 thereby enforcing metastability. Multiple Q Pull up transistors 534 may be used based on the design requirements as would be known to one skilled in the art. These Q Pull up transistors 534 are controlled through ‘V_meta_stability’ signal 506 which also determines the bit generation rate of TRNG 500.
  • the circuit instead of pulling the output nodes up to VDD, the circuit can also pull them down to GND without altering the circuit’s functionality and operation.
  • the delay cells 524, 526, 528, 530, and 532 of ring oscillator 502 can be implemented with the delay cell schematic circuit 600 shown in Figure 6.
  • the transistors/switches 536 and 538 of Figure 5 are not needed, as the delay path controlling feature is incorporated within the delay cell 600.
  • the input signals ‘V_fast’ 616 and ‘ V_slow’ 618 are connected to the base transistors 624 and 626 respectively.
  • the base transistors 624 and 626 act as the current sources and do not need to be in a single transistor configuration, i.e., any other form of current source is also suitable for this circuit.
  • the input signals ‘V fast’ 616 and 'V slow” 618 analogous to the input signals ‘ V_fast’ 510 and ‘V_slow’ 512 of the two delay paths of ring oscillator 500 of Figure 5, are applied at the inputs of two differential pairs even though the output is common.
  • the first, input is at ‘Vin n 3’ 608 and ‘Vin p 3’ 610, while the second input is at ‘Vin_n_5’ 612 and ‘‘Vin_p_5’ 614, and the output at ‘Vout_n’ 620 and ‘Vout p’ 622, respectively.
  • the transistor 624 turns ON, thereby enabling the differential pair 1 consisting of transistors 628 and 630 which propagates the input in the delay path 1 of ring oscillator 500
  • the transistor 626 turns ON thereby enabling the differential pair 2 consisting of transistors 632 and 634 enabling the input in the delay path 2 of ring oscillator 500.
  • the ‘Q_Pull up’ transistors 638 and 636 which act as switches, are used to force the delay cell into the nieta-stable state.
  • the Q Pull up transistors 636 and 638 can also be replaced with Q Pull down transistors (NMOS) that pull the output nodes 620 and 622 to GND 604.
  • the circuit can also be modified to have a PMOS differential pair and an NMOS cross coupled pair or it can also be altered in other ways, not described herein but known or understood to the persons skilled in the art, by retaining its basic functionality.
  • the resistors can be implemented by active loads.
  • an inductor 702 can be placed between the output nodes Vout n 620 and Vout p 622.
  • the inductor 702 is used for bandwidth extension. It resonates out the parasitic capacitances of the transistors in the delay cell, thereby reducing the delay cell’s delay and increasing the frequency of the ring oscillator.
  • the inductor 702 increases the TRNG’s generation rates up by to 30 percent but may occupy more area on the chip. Further, it also makes the circuit’s delay independent of the resistors used which thereby enables a greater signal strength.
  • the buffers/amplifiers 410 can be replaced with Flip Flops. In other embodiments, they can be implemented using any inverting or non-inverting single stage amplifiers, or amplifier-based buffers, or any other similar components not mentioned herein but which are known or understood to one skilled in the art.
  • the buffers/amplifiers 410 are replaced with a modified differential amplifier 800, as shown in Figure 8, for improving its performance.
  • Modified differential amplifier 800 consists of a differential pair 812 and 814 with resistive/active loads 816 and 818, a current source 810, and a pair of pull-down transistors 808 and 806,
  • the control signals ‘V Pull down’ 802 and ‘V Pull down_inv’ 804 are used to switch the circuit between the normal and metastable states.
  • the amplifier needs to be pulled into the metastable state because it has an inherent slew rate. When the input signals enter their meta-stable state (both high), the differential pair of transistors pulls down both output nodes.
  • this pull-down speed is limited by the current in the amplifier’s base transistor 810, which slows the circuit’s operation.
  • the high current is passed through the two pull-down transistors 808 and 806. These high current carrying transistors are turned ON only for a fraction of the time during the meta-stable state and therefore do not have to stay in the conduction mode all the time.
  • the resistors 816 and 818 of 800 can also be implemented with active loads.
  • the pull-down operation can also be replaced with a pull-up operation without altering the circuit’s functionality and operation.
  • Figure 9 depicts a three-transistor tent map circuit 900 that has a non-linear response and is used to generate the chaotic signals in chaotic entropy source 404 or 418 of Figure 4.
  • the tent map circuit 900’ s response is controlled by changing the size of the transistors 920 and 922, the voltage ’ V__gate’ 906, and the body bias voltages 908, 910 and 912 of transistors 918, 920, and 922, respectively.
  • the transistor 918 acts as a current source, and the transistors 920 and 922 act as the pull-down transistors.
  • the circuit achieves the desired non-linear characteristics by leveraging the opposite operation regions of the NMOS and PMOS transistors 920 and 922, respectively.
  • the PMOS transistor 920 turns ON thereby pulling the output 916 to the ground 904.
  • the NMOS transistor 922 turns ON that pulls the output low.
  • both transistors are partially OFF which causes the output to be pulled towards the supply ‘VDD’ 902.
  • the non-linear tent map circuit 900 may be used to generate discrete-time chaotic signals as an embodiment of the chaotic map circuit 1002 in chaotic source 1000 of Figure 10.
  • the number of bifurcations of the generated chaotic signal, and hence its chaotic nature, is controlled by varying the gate voltage of transistor 918 and the body bias voltages of the transistors 920 and 922, or transistor sizes, as mentioned above in the description of non-linear tent map circuit 900.
  • chaotic source 1000 may be implemented with other chaotic map circuits that provide the desired non-linear response such as the Logistic map, Gauss map, Lorenz system, etc., or any other similar systems well known to the one skilled in the art.
  • the buffers 1012, 1014 and 1016 can also be implemented in any other suitable way.
  • the chaotic output at the hold capacitor 1010 is inverted using inverter 1008 to generate two signals ‘V fast’ 1004 and ‘V slow' 1006. These two signals can be used as chaotic signals 510 and 512, respectively, in the embodiment 500 of Figure 5 for chaotically switching the number of stages therein.
  • the circuit’s speed is controlled by switching speed of the swatches 1018 and 1020 and is a much lower speed than that of the ring oscillator 406 of Figure 4.
  • the chaotic sources 404 and 418 of Figure 4 both can be implemented with the chaotic circuit 1000 of Figure 10, or with any other chaotic source known to the one skilled in the art.
  • Figure 11 shows a graph 1 100 of the normalized power supply noise perturbations in the voltage VDD 1102 with time.
  • This noise is a combination of thermal, 1/E and switching noise of transistors. It is well known that, these noise sources are inherent and provide maximum randomness in their behavior and attributes. If required, this noise can also be generated.
  • Figure 12 show's a graph 1200 of the non-linear transfer characteristics of the tent map circuit 900 of Figure 9.
  • the horizontal axis 1218 and the vertical axis 1216 show the normalized input voltage and the normalized output voltage, respectively.
  • the sign of the slope changes at the graphs’ peak 1206, and the two regions of operation before and after this point are 1202 and 1204, respectively.
  • Region 1202 is the region of operation of the PMOS transistor 920 of tent map circuit 900
  • region 1204 is the region of operation of the NMOS transistor 922 of tent map circuit 900.
  • Figure 13 show's a graph 1300 of the chaotic signal 1302 as the normalized output voltage of the chaotic signal generator block of chaotic source 1000 of Figure 10 in which the non-linear chaotic map circuit 1002 is the tent map circuit 900 of Figure 9.
  • Figure 14 shows a graph 1400 of the normalized differential signal 1402 and 1404 as one of the differential outputs of the ring oscillator 500 of Figure 5, in w'hich the delay cell is the circuit 600 of Figure 6.
  • the differential signal shifts between two operating states: the meta-stable state 1420 with zero differential voltage and the oscillation state 1414 with a dominant differential voltage.
  • the rate of this shift is controlled using the standard clock signal ‘V_meta stability’ 506 which is input to ring oscillator 500 of Figure 5.
  • V_meta stability’ 506 which is input to ring oscillator 500 of Figure 5.
  • the randomness of this polarity /phase is further enhanced at the sampling instances 1406, 1408, 1410, and 1412 as the oscillation frequency shifts between different oscillation states that are controlled by the chaotic signals 510 and 512 from chaotic source 508 of Figure 5. This is further supplemented by varying the sampling instances 1406, 1408, 1410, and 1412 and introducing jitter to sampling circuit 412 of Figure 4 with the jitter source 414.
  • the circuit 400 of Figure 4 generates five such outputs, one of which is shown in 1400 which are further processed as earlier described.
  • the five random outputs can be combined to generate a single random stream.
  • Figure 15 shows another embodiment of a TRNG 1500, according to aspects of the invention, in which the TRNG circuit 400 of Figure 4 can be modified to generate less than 5 outputs as well and they may be combined to get a single random bit stream. Though this reduces the generation rate, the chip area and power consumption are also significantly reduced. Moreover, in case of one output bit, the bit order multiplexer 416 of TRNG 400 is replaced by a delay element 1506 and an XORgate 1504 for removing the bias; as a result, only one buffer 1502 is needed.
  • the total on-chip area of the complete circuit of TRNG 400 including the bit order multiplexers, parallel/in serial out shift register, and the biasing circuitry may be calculated to be about 85x85 gm 2 in 65-nm CMOS.
  • TRNG’s generation rate can go up to 20 Gbps with a power consumption of less than 15W.
  • Figure 16 show's another embodiment of the invention wherein the multicore TRNG 1602 is composed of multiple TRNG core units 1604, 1606, 1608, and 1610.
  • the cores 1604, 1606, 1618, and 1610 are all separate instances of the TRNG 400 of Figure 4, and they generate the output bits Do --- DN (1612-1618).
  • This is exceptionally beneficial when using multiple cores of the TRNG that use the delay cell 600 of the embodiment of Figure 6.
  • N such TRNG cores
  • 20* N Gbps can be generated using on-chip area of approximately Nx85x85 pm 2 and a power of N*15 W,
  • 10 such TRNG cores will only require a total area of 270x270 ⁇ m 2 yet deliver a rate of 200 Gbps by consuming only 150 W.
  • the TRNG circuit described herein can be modified to operate at even lower frequencies of a few Mbps to enable use of the invention for low power devices and applications. Furthermore, the TRNG circuit described herein can be modified to provide high data rate at expense of large area and power or low data rates with low power and small area.
  • This aspect of the invention makes it a unit block that is suitable for a wide range of electronics and communication systems.
  • the low frequency, single core TRNG embodiment described herein makes it ideal for low powered microcontrollers based embedded systems, loT devices and smart dust.
  • the multicore, high frequency TRNG embodiment described herein makes it. suitable for high generation rate demanding GPUs, servers, 5G gNB etc., or any other similar circuits or communication systems.
  • FIG. 17 is a flowchart 1700 depicting a method for generating true random numbers at a high frequency rate according to aspects of the invention.
  • Step 1702 is the step of generating an entropy output signal from each of a plurality of entropy source blocks, wherein the entropy output signal of each entropy source block being used as an input condition for each next entropy source block in the plurality of entropy source blocks.
  • the next step in step 1704 is sampling the entropy output signals from the plurality of entropy source blocks, followed by combining the sampled entropy output signals into a combined entropy output signal in step 1706.
  • step 1708 is using the combined entropy output signal to generate a plurality of random output bits. It should be appreciated that any of the vari ations and features described above with respect to the other fi gures can be utilized in the above method, either alone or in any combination.
  • FIG. 18 is a flowchart 1800 depicting a method for generating true random numbers at a high frequency rate according to aspects of the invention.
  • Step 1802 is the step of generating an entropy output signal from each of a plurality of entropy source blocks, wherein the entropy output signals of at least some of the plurality of entropy source blocks affect the entropy output signals of at least some others of the plurality of entropy source blocks.
  • Step 1804 is receiving, at a ring oscillator, the entropy output signals of two of the plurality of entropy source blocks and a clock signal and outputting a plurality of random output signals from the ring oscillator.
  • step 1808 is sampling, by a sampling circuit that receives the entropy output signal of a third one of the plurality of entropy source blocks, the plurality of buffered random output signals from the plurality of buffers and outputting a plurality of sampled random output signals from the sampling circuit.
  • the delay cells 524, 526, 528, and 532 of the ring oscillator 502 can be implemented with the delay cell schematic circuit 1900 shown in Figure 19.
  • this embodiment uses an additional transistor 1902 under the base transistors 624 and 626.
  • the transistor 1902 is a control transistor that is used to turn OFF the base transistors 624 and 626, and consequently, the differential pair transistors 628, 630, 632 and 634, during the metastable state. It receives the same control signal 606 'V metastable' as the pull-up transistors 636 and 638.
  • control transistor 1902 can also be used in the delay cell 700 of Figure 7, to get the delay cell 2000 of Figure 20.
  • the operation principle of the control transistor 1902 remains the same in this embodiment with only the addition of the inductor 702 which enables higher frequency operation of the ring oscillator 502.
  • the pull function in the illustrated exemplary embodiment of Figure 19 is performed by one PMOS transistor (on each side), it will be understood that the pull function may also be performed by a complete transmission gate (NMOS-PMOS pair). In other words, a complete transmission gate can also be used in place of this single PMOS pull-up to achieve the same functionality.

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Abstract

A True Random Number Generator circuit compatible with all chip manufacturing technologies including CMOS, using the different types of multiple entropy sources to enhance the different parameters of a single circuit which generates the random numbers, wherein the output of a preceding entropy source affects the entropy of the succeeding entropy source. The entropy sources include metastability supporting ring oscillator, chaos circuit, sampling jitter etc., and even more number of entropy sources. The chaos source controls the oscillation frequency of the ring oscillator and the ring oscillator's output is sampled using an independent clock source with jitter. The multiple cores of TRNGs provides up to hundreds of Gbps rate for random numbers and may form an essential component of next generation of secure hardware and communication systems.

Description

A CIRCUIT AND SYSTEM FORA VERY HIGH THROUGHPUT TRUE RANDOM NUMBER GENERATOR (TRNG) FOR NEXT GENERATION SECURE HARDWARE AND COMMUNICATION SYSTEMS
FIELD OF THE INVENTION
[0001]. The invention described herein discloses a system of circuits for a very' high throughput True Random Number Generator (TRNG). The system of circuits utilizes multiple classes of entropy sources including but not limited to metastability, chaos, power supply noise and perturbations. Further disclosed are the components and modules that implement the TRNG invention, as is evident from the embodiments and aspects described herein and from the accompanying drawings.
BACKGROUND
[0002]. Random Numbers are an essential part of any modern communication system to ensure encryption and security wherein they are used to generate and manage secure keys for encryption algorithms. In communication systems, devices currently communicate at several Mbps up to Gbps. These systems include satellites and base stations that form the core of the network and communicate with hundreds of devices simultaneously and will require the generation of random numbers at very high data rates. In 5G and Massive Multiple Input Multiple Output (MMIMO) technologies, the number of these devices is expected to exponentially grow, as billions of Internet of Things (loT) devices/ sensors get connected to the cloud systems, thereby requiring very high data rate random numbers. Moreover, the generated random numbers must be statistically independent to pass the randomness tests, and the generation systems must be robust against different types of hardware attacks. Some examples of these attacks are: initial condition determination by rigorous statistical analysis, forced biasing using environment tampering attacks such as EMI, temperature manipulation, etc.; and other methods that empower an attacker to predict the next bit. by analyzing the previous ones. Last but not least, these random number generators must also be able to easily integrate into the current microchip technology without requiring extra cost or manufacturing steps.
[0003]. Random numbers are generated either from hardware-based True Random Number Generators (TRNGs) or software-based Pseudo-Random Number Generators (PRNGs), where the output of a TRNG is the seed for a PRNG. TRNGs that use various entropy sources are available in the prior art including the ones that use thermal/shot noise of resistors with amplifiers, sampling jitter of the oscillator(s), deterministic but unpredictable chaos, metastability, quantum entropy sources, just to name few. However, all of them have their strengths and weaknesses. The metastability and thermal noise based TRNGs are relatively less sensitive to initial conditions, but they are susceptible to environmental attacks such as EMI that enhance or suppress the circuit noise or bias the average voltages more towards one side, or manipulate temperature, pressure, humidity, etc. On the other hand, the chaos-based TRNGs are immune to voltage biasing or EMI based attacks, but their outputs can be tracked given the initial conditions. Moreover, the chaos-based TRNGs generally operate in the discrete domain and have relatively low generation rates, due to the limitation of the buffer and sample-and-hold circuits involved. Therefore, the jitter-based oscillator sampling method is widely used because it can be implemented both in a semi-customized digital circuit and a fully customized digital -analog hybrid one, but it cannot provide very high data rates without compromising the randomness of the generated stream. TRNGs that incorporate weak random sources and use post-processing to reduce the bias in the output stream, such as the Von Neumann scheme, are prone to data rate fluctuations with time due to the bits that they discard. A new set of TRNGs based on quantum noise sources use entropy sources such as single- photon detection or the variations in the intensity of a light source, etc. The benefit of these Quantum Random Number Generators (QRNGs) is that the quantum noise is highly unpredictable and is an excellent source for entropy. However, these QRNGs are difficult to implement in the Bulk CMOS technology since they typically require additional and costly manufacturing steps.
[0004]. A known class of TRNGs combines the output streams of multiple entropy sources to get a single stream using functions such as XOR, etc. Although the generation of the streams is independent in these TNRGs, they use the same type of generation source, i.e., taking the output of two different instances of the same TRNG. In comparison, the design of the disclosed invention set forth below combines output of different classes of entropy sources so that, the output of one source directly affects that of the other to increase the randomness of the output steam.
[0005]. The TRNGs in prior art generate multiple independent streams from different sources and then combine them. Our invention as set forth below, in comparison, changes the input or biasing or initial conditions of one entropy source based on the output of other entropy sources. As a result, the invention described herein combines different classes of entropy sources in a novel way and makes it less susceptible to different types of above-mentioned attacks. Accordingly, since all of the entropy sources send analog voltages to the subsequent stages instead of the digital bits, therefore, their entropy remains preserved until the final sampling. Moreover, a novel ring oscillator constitutes a significant aspect of our invention thereby enabling it to achieve very high generation rates with a small on-chip area.
SUMMARY OF THE INVENTON
[0006]. Aspects of the invention described herein describe a TRNG system of circuits that are compatible with all modern IC design and manufacturing technologies, and a random number generation method, capable of generating random numbers in the order of hundreds of Gbps by combining various classes of entropy sources in a novel way to make them robust against the above-mentioned attacks. The conventional TRNGs that combine the outputs of different randomness sources (such as ring oscillators, etc.) use these sources as the first input stage and then select the output of the most random among them using Von-Neumann or XOR type post processing techniques. But this conventional method requires that all entropy sources must have a comparable generation rate to maximize randomness in the output stream of the TRNG. If the generation rate of one randomness source is significantly higher than the others, then their output approximately stays constant for a short time period during which only that source generates random numbers. Moreover, in the conventional method, some of the generated output bits get discarded by a post-processing technique to remove bias by analyzing the previous output. bit(s). For example, the Von-Neumann technique compares a pair of bits for similarity; it uses only one of them if they are different or discards both of them if they are the same. Our invention as described herein, in comparison, uses multiple randomness sources in a novel way that, by varying the input characteristics or biasing conditions of one source with respect to the output of the other source, generates a random number stream that is less susceptible to external attacks. This allows the Random Number Generator to use multiple entropy sources even when the generation rates of some sources are significantly higher than the other ones. The random bits of the TRNG are generated at the rate of the fastest source in the system, but its output is still affected by the entropy of the slower randomness sources. Instead of discarding any generated bits, the invention described herein mangles the generated bits, by using bit order multiplexers, to remove the bias. Since the system described herein does not process the outputs of all entropy sources in a single stage to determine the most random bit in comparison with the previous output bit, as a result, the output bits become less dependent on the earlier bits. The novel TRNG described herein is also scalable as it can be manufactured by using any IC technology and can be optimized for performance, speed, power consumption, area, etc. as the usage scenario demands. The novel TRNG described herein can be implemented for a variety of processors ranging from low-power microcontrollers that are used in embedded systems to high throughput multicore server processors, GPUs, etc.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007]. The accompanying drawings, which are incorporated in and constitute part of this specification, illustrate aspects and embodiments of the invention and together with the description, serve to explain the principles of the invention. The aspects and embodiments illustrated herein are presently preferred, it being understood by those skilled in the art, however, that, the invention is not limited to the precise aspects, arrangements and instrumentalities shown, wherein:
[0008]. Figure 1 is a system level depiction of the novel True Random Number Generator where each entropy source acts as a series stage and controls the input or biasing conditions of the subsequent stage according to aspects to the invention;
[0009]. Figure 2 is a system level depiction of the prior True Random Number Generators where all entropy sources act as a single, parallel stage and the outputs of all sources are passed through an entropy combiner module according to aspects to the invention;
[0010]. Figure 3 is a novel Taie Random Number Generator acting as a seed for Pseudo-Random Number Generator to generate random numbers at a higher data rate according to aspects to the invention;
[0011]. Figure 4 is a block diagram of a True Random Number Generator with different entropy sources according to aspects to the invention; [0012] . Figure 5 is a block diagram of the ring oscillator with a variable delay and support for metastability according to aspects to the invention;
[0013]. Figure 6 is a variable delay cell with delay control transistors and pull up switches for metastability according to aspects to the invention;
[0014]. Figure 7 is a variable delay ring oscillator circuit with a bandwidth extension inductor to achieve higher generation rates according to aspects to the invention; [0015]. Figure 8 is a differential amplifier circuit with additional pull down transistors for faster transition to the metastable state according to aspects to the invention; [0016]. Figure 9 i s a three transistor based non-linear tent map circuit with four bias voltages for bifurcation control according to aspects to the invention;
[0017]. Figure 10 is a block diagram of the discrete time chaotic generator circuit In which the non-linear chaotic map circuit can be tent map, chua’s circuit, gauss map, etc. or any other similar circuit according to aspects to the invention,
[0018]. Figure 11 show's normalized power supply variations due to noise including a combination of thermal, 1/f, and switching noise of transistors according to aspects to the invention;
[0019]. Figure 12 shows normalized input/output characteristics of the non-linear tent map circuit according to aspects to the invention;
[0020]. Figure 13 is a normalized chaotic signal generated for controlling the delay path of the ring oscillator circuit according to aspects to the invention;
[0021]. Figure 14 show's a normalized nieta-stable response of the ring oscillator circuit of Figure 5 according to aspects to the invention;
[0022]. Figure 15 is a Taie Random Number Generator with only one output bit for reduced area and power, wherein the XOR gate and delay element are used to remove the bias according to aspects to the invention;
[0023]. Figure 16 is a multicore TRNG using N different instances of the TRNG 100 of Figure 1 for generating random numbers at a faster rate according to aspects to the invention;
[0024], Figure 17 is a flowchart depicting the generation of True Random Numbers using different entropy sources according to aspects to the invention; and
[0025]. Figure 18 is a flowchart depicting the generation of True Random Numbers using different entropy sources according to aspects to the invention. [0026]. Figure 19 is an embodiment of the delay cell shown in Figure 6 with an additional transistor to improve the operation of the oscillator circuit in its metastable state. [0027]. Figure 20 is an embodiment of the delay cell shown in Figure 7 with an additional transistor to improve the operation of the oscillator circuit in its metastable state.
DETAILED DESCRIPTION OF THE INVENTION
[0028]. The figures and their corresponding aspects and embodiments provided in this disclosure are explained in detail for a thorough understanding of the invention and the accompanying embodiments. All such figures are schematic or block diagrams, hence they are not drawn to the scale. The simulation results such as transfer characteristics of components, node voltages, generated outputs, etc. shown are also normalized and can be scaled according to the technology used. Further, the schematics and block diagrams are drawn to clarify the details of the invention. One skilled in the art can understand that only the core components of the circuits are shown in the aspects and embodiments set forth herein for a better enablement, and hence, any biasing transistors or such circuitry that would be included in these circuits for implementation is implicitly a part of this disclosure. Henceforth, the figures, voltages, transfer characteristics, and aspects and embodiments depicted herein are for the sole purpose of clarity and enablement and do not by any way- limit the scope of the invention. Any theories of operation, circuit explanations, design techniques followed, output results depicted are to facilitate enablement, and the disclosed systems, methods, and circuits are not limited to any one of them only. All aspects, embodiments, systems, schematics, circuits, and subcircuits that utilize the fundamental principles of the invention or have elements of the invention are hereby treated to be under the complete protection of the disclosed invention.
[0029]. Figure 1 shows a system-level embodiment of a novel TRNG 100 based on aspects of the present invention in which each entropy source acts as a block, and its output controls the input/bias of the next block and that next block again may be a different type of entropy source. The various entropy sources 102 can include power supply noise or perturbations 104, deterministic chaos sources (generator) 106, metastability circuits (generator) 110, oscillator jitter-based circuits (generator) 108, or quantum noise extraction circuits, or any other systems, circuits, or sub-circuits that can be the source of the entropy that are not explicitly mentioned in this disclosure but are known to one skilled in the art. The TRNG 100 extracts the maximum entropy, as most of the sources are combined in a series fashion, from the final bit generation stage 112 and subsequently generates the random bit stream as its output 114.
[0030]. Figure 2 shows a typical known TRNG 200 (disclosed in the prior art) where the outputs of all entropy sources 202 are combined at a single bit generation stage 214 to generate the random output bits. Here, in known TRNG 200, the entropy sources 204, 206, 208, and 210 of the typical TRNG 200 may be the same as entropy sources 104, 106, 108, and 110 of novel TRNG 100 but the output of the entropy sources are combined differently. The entropy sources 204, 206, 208, and 210 of typical TRNG 200 are combined in parallel and hence one source cannot affect the output of others. The outputs of all entropy sources are processed digitally at the bit generation 214, which acts as an entropy extractor, to create the random number string which is the TRNG Output 216 of the typical TRNG 200.
[0031]. In certain scenarios, application layer programs prefer using their own encryption algorithms to provide peer to peer encryption. The TRNG as described herein can provide a seed and secure keys to such applications at high rates. Figure 3 shows a system 300 incorporating an embodiment of the invention in which the TRNG 308 is an instance of TRNG 100 of Figure 1 and provides one or more seeds (or secure keys) 304 for the user application 302. The user application 302 generates the output random bit stream 310 using seed or secure keys 304 and an encryption software method or algorithm 306 to achieve even higher generation rates, albeit requiring more processing power.
[0032]. Figure 4 shows a detailed schematic description of TRNG 400 which is one possible implementation of novel TRNG 100, according to aspects of the invention. The Ring Oscillator 406 of TRNG 400 has a variable delay and supports metastability. Both characteristics are controlled via separate voltage signals: ‘V stage Ctrl’ 422 and ‘Metastability Ctrl’ 420. These voltage sources are controlled via the ‘Chaotic Entropy Source 1’ 404 and ‘V_clk’ 402 signals. The ‘V_clk’ 402 signal is from a predetermined clock source that controls the TRNG’s 400 generation rate. The ‘Chaotic Entropy Source 1 ’ 404 signal is from a chaotic entropy source with a slow varying entropy and controls the oscillation frequency of the ring oscillator circuit 406 that is a fast-varying entropy source. Different possible incarnations of source 404 are: Chua’s circuit implementation or a chaotic circuit based on a non-linear map such as the tent map, logistic map, etc., or any source capable of generating chaotic signals. The ring oscillator 406 utilizes power supply noise perturbations (Entropy Source 2) 408, which are inherent to the circuit and can also be generated using transistors. In an aspect, ring oscillator 406 generates five random outputs, since it has five delay cells as shown in Figure 5 as Delay Cells 524, Output 2 526, 528, 530 and 532. However, this number of delay cells and random outputs can be changed to any other number depending on the application requirements. Ring oscillator 406 also supports using an even number of delay cells by changing the polarity of the differential signals. Using five outputs is beneficial because it allows for two different oscillation frequencies, one with all five delay cells active and the other with only three of them active. Although increasing the number of delay cells 524, 526, 528, 530, and 532 would give an increased number of outputs, it would also reduce the ring oscillator’s frequency. The output signals of ring oscillator 406 are fed to the sampling circuit 412 through buffers (and/or amplifiers) 410. Subsequently they pass through the multiplexer (bit order multiplexers)) 416 to remove bias. The sampling circuit 412 changes its sampling instance because of input from jitter source (entropy source 3) 414 that is external or may be a part of the circuit. In one aspect of the invention, the order of five signals is controlled by the voltage signal of the chaotic source (entropy source 4) 418 as an input to multiplexer(s) 416 that further enhances the entropy of the system. Finally, the output of 416 is sent as a five-digit random stream 422 through optional parallel in/serial out shift register 420.
[0033]. In another aspect of the invention some, or all, of the chaotic sources 404 and 418, the jitter source 414, and the power supply variations source 408 are replaced by other entropy sources. In another aspect, the bit order multiplexer 416 and chaotic source 418 are removed to thereby produce the generated bits in a fixed order.
[0034]. Figure 5 show's a schematic block diagram 500 of ring oscillator 502 which is an embodiment of ring oscillator 406 that is a component of novel TRNG 100 according to an aspect of the invention. Ring oscillator 502 has two different delayed paths, and hence two oscillation frequencies. The first path consists of the delay cells 524, 526 and 528, and switch 536. The second path consists of the delay cells 524, 526 and 528, the switch 538, and also the delay cells 532 and 530. The two switches (such as transistors) 536 and 538 are controlled by the two complementary signals ‘V_fast’ 510 and ‘V_slow’ 512. When the switch 536 is ON, the signal propagates through the first delay path with a corresponding delay. When the switch 538 is ON, it goes through the second delay path with a different delay. The signals 510 and 512 come from the chaotic source 508. Each delay cell can be a simple inverter-based delay cell, a transmission line-based delay cell, the delay cell 600 of Figure 6 described below, the delay cell 700 of Figure 7 described below, etc., or any other type of known delay cell not explicitly mentioned herein. Q Pull up transistor 534 represents one of the transistors which connect all five of the outputs 514, 516, 518, 520 and 522 to the supply ‘VDD’ 504 thereby enforcing metastability. Multiple Q Pull up transistors 534 may be used based on the design requirements as would be known to one skilled in the art. These Q Pull up transistors 534 are controlled through ‘V_meta_stability’ signal 506 which also determines the bit generation rate of TRNG 500.
[0035]. In another embodiment, instead of pulling the output nodes up to VDD, the circuit can also pull them down to GND without altering the circuit’s functionality and operation.
[0036]. In an embodiment, the delay cells 524, 526, 528, 530, and 532 of ring oscillator 502 can be implemented with the delay cell schematic circuit 600 shown in Figure 6. In this embodiment, the transistors/switches 536 and 538 of Figure 5 are not needed, as the delay path controlling feature is incorporated within the delay cell 600. For the said purpose, the input signals ‘V_fast’ 616 and ‘ V_slow’ 618 are connected to the base transistors 624 and 626 respectively. The base transistors 624 and 626 act as the current sources and do not need to be in a single transistor configuration, i.e., any other form of current source is also suitable for this circuit. The input signals ‘V fast’ 616 and 'V slow" 618, analogous to the input signals ‘ V_fast’ 510 and ‘V_slow’ 512 of the two delay paths of ring oscillator 500 of Figure 5, are applied at the inputs of two differential pairs even though the output is common. The first, input is at ‘Vin n 3’ 608 and ‘Vin p 3’ 610, while the second input is at ‘Vin_n_5’ 612 and ‘‘Vin_p_5’ 614, and the output at ‘Vout_n’ 620 and ‘Vout p’ 622, respectively. Note that, in the delay cell 600, if the input signal ‘V fast’ 616 is high, the transistor 624 turns ON, thereby enabling the differential pair 1 consisting of transistors 628 and 630 which propagates the input in the delay path 1 of ring oscillator 500, Similarly, if the input, signal ‘Vjslow’ 618 is high, the transistor 626 turns ON thereby enabling the differential pair 2 consisting of transistors 632 and 634 enabling the input in the delay path 2 of ring oscillator 500. The ‘Q_Pull up’ transistors 638 and 636, which act as switches, are used to force the delay cell into the nieta-stable state. When the control signal ‘V meta stable’ 606 is low', the transistors 638 and 636 are turned ON thereby pulling both output nodes 620 and 622 to VDD 602. When ’ V_meta stable’ 606 turns high, both transistors are turned OFF which leaves the output nodes 620 and 622 floating. At this point, the inevitable noise in the circuit causes one of the outputs to go higher than the other which generates a small differential signal. The cross-coupled transistors 640 and 642 then amplify this signal to generate oscillations with a random phase due to the initial noise. This signal can then be sampled and sent to the buffers/amplifiers 410 of TRNG 400 of Figure 4.
[0037]. In another embodiment of the delay cell 600, the Q Pull up transistors 636 and 638 (PMOS) can also be replaced with Q Pull down transistors (NMOS) that pull the output nodes 620 and 622 to GND 604. In other embodiments, the circuit can also be modified to have a PMOS differential pair and an NMOS cross coupled pair or it can also be altered in other ways, not described herein but known or understood to the persons skilled in the art, by retaining its basic functionality.
[0038]. In another embodiment of the delay cell 600, the resistors can be implemented by active loads.
[0039]. In another embodiment 700, shown in Figure 7, of the delay cell 600, an inductor 702 can be placed between the output nodes Vout n 620 and Vout p 622. The inductor 702 is used for bandwidth extension. It resonates out the parasitic capacitances of the transistors in the delay cell, thereby reducing the delay cell’s delay and increasing the frequency of the ring oscillator. The inductor 702 increases the TRNG’s generation rates up by to 30 percent but may occupy more area on the chip. Further, it also makes the circuit’s delay independent of the resistors used which thereby enables a greater signal strength.
[0040]. In another embodiment of TRNG 400 of Figure 4, the buffers/amplifiers 410 can be replaced with Flip Flops. In other embodiments, they can be implemented using any inverting or non-inverting single stage amplifiers, or amplifier-based buffers, or any other similar components not mentioned herein but which are known or understood to one skilled in the art.
[0041]. In another embodiment of TRNG 400 of Figure 4, the buffers/amplifiers 410 are replaced with a modified differential amplifier 800, as shown in Figure 8, for improving its performance. Modified differential amplifier 800 consists of a differential pair 812 and 814 with resistive/active loads 816 and 818, a current source 810, and a pair of pull-down transistors 808 and 806, The control signals ‘V Pull down’ 802 and ‘V Pull down_inv’ 804 are used to switch the circuit between the normal and metastable states. The amplifier needs to be pulled into the metastable state because it has an inherent slew rate. When the input signals enter their meta-stable state (both high), the differential pair of transistors pulls down both output nodes. However, this pull-down speed is limited by the current in the amplifier’s base transistor 810, which slows the circuit’s operation. Instead, in this embodiment, to increase the circuit’s operation speed, the high current is passed through the two pull-down transistors 808 and 806. These high current carrying transistors are turned ON only for a fraction of the time during the meta-stable state and therefore do not have to stay in the conduction mode all the time.
[0042]. In another embodiment, the resistors 816 and 818 of 800 can also be implemented with active loads. Furthermore, the pull-down operation can also be replaced with a pull-up operation without altering the circuit’s functionality and operation.
[0043]. Figure 9 depicts a three-transistor tent map circuit 900 that has a non-linear response and is used to generate the chaotic signals in chaotic entropy source 404 or 418 of Figure 4. The tent map circuit 900’ s response is controlled by changing the size of the transistors 920 and 922, the voltage ’ V__gate’ 906, and the body bias voltages 908, 910 and 912 of transistors 918, 920, and 922, respectively. The transistor 918 acts as a current source, and the transistors 920 and 922 act as the pull-down transistors. The circuit achieves the desired non-linear characteristics by leveraging the opposite operation regions of the NMOS and PMOS transistors 920 and 922, respectively. For lower input voltages at the input 914, the PMOS transistor 920 turns ON thereby pulling the output 916 to the ground 904. For higher input voltages, the NMOS transistor 922 turns ON that pulls the output low. However, for voltages in between the two ranges both transistors are partially OFF which causes the output to be pulled towards the supply ‘VDD’ 902. By selecting the size and body biases of the transistors, one skilled in the art can achieve the non-linear transfer characteristics of a well-known tent map.
[0044]. The non-linear tent map circuit 900 may be used to generate discrete-time chaotic signals as an embodiment of the chaotic map circuit 1002 in chaotic source 1000 of Figure 10. The number of bifurcations of the generated chaotic signal, and hence its chaotic nature, is controlled by varying the gate voltage of transistor 918 and the body bias voltages of the transistors 920 and 922, or transistor sizes, as mentioned above in the description of non-linear tent map circuit 900. Further, chaotic source 1000 may be implemented with other chaotic map circuits that provide the desired non-linear response such as the Logistic map, Gauss map, Lorenz system, etc., or any other similar systems well known to the one skilled in the art.. Similarly, the buffers 1012, 1014 and 1016 can also be implemented in any other suitable way. The chaotic output at the hold capacitor 1010 is inverted using inverter 1008 to generate two signals ‘V fast’ 1004 and ‘V slow' 1006. These two signals can be used as chaotic signals 510 and 512, respectively, in the embodiment 500 of Figure 5 for chaotically switching the number of stages therein. The circuit’s speed is controlled by switching speed of the swatches 1018 and 1020 and is a much lower speed than that of the ring oscillator 406 of Figure 4. The chaotic sources 404 and 418 of Figure 4 both can be implemented with the chaotic circuit 1000 of Figure 10, or with any other chaotic source known to the one skilled in the art.
[0045]. Figure 11 shows a graph 1 100 of the normalized power supply noise perturbations in the voltage VDD 1102 with time. This noise is a combination of thermal, 1/E and switching noise of transistors. It is well known that, these noise sources are inherent and provide maximum randomness in their behavior and attributes. If required, this noise can also be generated.
[0046]. Figure 12 show's a graph 1200 of the non-linear transfer characteristics of the tent map circuit 900 of Figure 9. The horizontal axis 1218 and the vertical axis 1216 show the normalized input voltage and the normalized output voltage, respectively. The sign of the slope changes at the graphs’ peak 1206, and the two regions of operation before and after this point are 1202 and 1204, respectively. Region 1202 is the region of operation of the PMOS transistor 920 of tent map circuit 900 whereas region 1204 is the region of operation of the NMOS transistor 922 of tent map circuit 900.
[004'7]. Figure 13 show's a graph 1300 of the chaotic signal 1302 as the normalized output voltage of the chaotic signal generator block of chaotic source 1000 of Figure 10 in which the non-linear chaotic map circuit 1002 is the tent map circuit 900 of Figure 9.
[0048]. Figure 14 shows a graph 1400 of the normalized differential signal 1402 and 1404 as one of the differential outputs of the ring oscillator 500 of Figure 5, in w'hich the delay cell is the circuit 600 of Figure 6. As depicted in graph 1400, the differential signal shifts between two operating states: the meta-stable state 1420 with zero differential voltage and the oscillation state 1414 with a dominant differential voltage. The rate of this shift is controlled using the standard clock signal ‘V_meta stability’ 506 which is input to ring oscillator 500 of Figure 5. When the circuit is released from the meta-stable state, the differential signal’s initial polarity /phase is random due to the circuit’s inherent noise. The randomness of this polarity /phase is further enhanced at the sampling instances 1406, 1408, 1410, and 1412 as the oscillation frequency shifts between different oscillation states that are controlled by the chaotic signals 510 and 512 from chaotic source 508 of Figure 5. This is further supplemented by varying the sampling instances 1406, 1408, 1410, and 1412 and introducing jitter to sampling circuit 412 of Figure 4 with the jitter source 414.
[0049]. In an embodiment, the circuit 400 of Figure 4 generates five such outputs, one of which is shown in 1400 which are further processed as earlier described. The five random outputs can be combined to generate a single random stream.
[0050], Figure 15 shows another embodiment of a TRNG 1500, according to aspects of the invention, in which the TRNG circuit 400 of Figure 4 can be modified to generate less than 5 outputs as well and they may be combined to get a single random bit stream. Though this reduces the generation rate, the chip area and power consumption are also significantly reduced. Moreover, in case of one output bit, the bit order multiplexer 416 of TRNG 400 is replaced by a delay element 1506 and an XORgate 1504 for removing the bias; as a result, only one buffer 1502 is needed.
[0051]. The total on-chip area of the complete circuit of TRNG 400 including the bit order multiplexers, parallel/in serial out shift register, and the biasing circuitry may be calculated to be about 85x85 gm2 in 65-nm CMOS. As a result, TRNG’s generation rate can go up to 20 Gbps with a power consumption of less than 15W.
[0052]. Figure 16 show's another embodiment of the invention wherein the multicore TRNG 1602 is composed of multiple TRNG core units 1604, 1606, 1608, and 1610. The cores 1604, 1606, 1618, and 1610 are all separate instances of the TRNG 400 of Figure 4, and they generate the output bits Do --- DN (1612-1618). This is exceptionally beneficial when using multiple cores of the TRNG that use the delay cell 600 of the embodiment of Figure 6. By using N such TRNG cores, 20* N Gbps can be generated using on-chip area of approximately Nx85x85 pm2 and a power of N*15 W, For example, 10 such TRNG cores will only require a total area of 270x270 μm2 yet deliver a rate of 200 Gbps by consuming only 150 W. All these cores would be separate hardware blocks, and therefore, their outputs would all be not only highly uncorrelated, but also random and independent of one another. If the delay cell 700 of Figure 7 with the bandwidth extension inductor 702 is used, the overall area of the complete core increases to only 400x400 μm2 but with a 30% increase in the data rate and no additional static power consumption.
[0053]. This area, power and speed described above are limited only to the 65-nm technology and is expected to be better in advanced nodes that enable shorter gate length nodes. For instance, the expected area for the 45-nm node would be approximately 30% lower, and the area for the 32-nm node would be approximately 50% lower, and the data rates would increase with similar ratios accordingly.
[0054]. In an embodiment the TRNG circuit described herein can be modified to operate at even lower frequencies of a few Mbps to enable use of the invention for low power devices and applications. Furthermore, the TRNG circuit described herein can be modified to provide high data rate at expense of large area and power or low data rates with low power and small area. This aspect of the invention makes it a unit block that is suitable for a wide range of electronics and communication systems. The low frequency, single core TRNG embodiment described herein makes it ideal for low powered microcontrollers based embedded systems, loT devices and smart dust. The multicore, high frequency TRNG embodiment described herein makes it. suitable for high generation rate demanding GPUs, servers, 5G gNB etc., or any other similar circuits or communication systems.
[0055]. Figure 17 is a flowchart 1700 depicting a method for generating true random numbers at a high frequency rate according to aspects of the invention. Step 1702 is the step of generating an entropy output signal from each of a plurality of entropy source blocks, wherein the entropy output signal of each entropy source block being used as an input condition for each next entropy source block in the plurality of entropy source blocks. The next step in step 1704 is sampling the entropy output signals from the plurality of entropy source blocks, followed by combining the sampled entropy output signals into a combined entropy output signal in step 1706. Lastly, step 1708 is using the combined entropy output signal to generate a plurality of random output bits. It should be appreciated that any of the vari ations and features described above with respect to the other fi gures can be utilized in the above method, either alone or in any combination.
[0056]. Figure 18 is a flowchart 1800 depicting a method for generating true random numbers at a high frequency rate according to aspects of the invention. Step 1802 is the step of generating an entropy output signal from each of a plurality of entropy source blocks, wherein the entropy output signals of at least some of the plurality of entropy source blocks affect the entropy output signals of at least some others of the plurality of entropy source blocks. Step 1804 is receiving, at a ring oscillator, the entropy output signals of two of the plurality of entropy source blocks and a clock signal and outputting a plurality of random output signals from the ring oscillator. Next is receiving, at a plurality of buffers, the plurality of random output signals from the ring oscillator, respectively, and outputting a plurality of buffered random output, signals from the plurality of buffers in step 1806. Lastly, step 1808 is sampling, by a sampling circuit that receives the entropy output signal of a third one of the plurality of entropy source blocks, the plurality of buffered random output signals from the plurality of buffers and outputting a plurality of sampled random output signals from the sampling circuit. It should be appreciated that, any of the variations and features described above with respect to the other figures can be utilized in the above method, either alone or in any combination.
[0057]. In another embodiment of the invention, the delay cells 524, 526, 528, and 532 of the ring oscillator 502 can be implemented with the delay cell schematic circuit 1900 shown in Figure 19. In contrast to the delay cell 600 of Figure 6, this embodiment uses an additional transistor 1902 under the base transistors 624 and 626. The transistor 1902 is a control transistor that is used to turn OFF the base transistors 624 and 626, and consequently, the differential pair transistors 628, 630, 632 and 634, during the metastable state. It receives the same control signal 606 'V metastable' as the pull-up transistors 636 and 638. When 'V _metastable' 606 is low, the PMOS transistors 636 and 638 are turned ON and the NMOS transistor 1902 is turned OFF. In the opposite state, when 'V _metastable' 606 is high, the PMOS transistors 636 and 638 are turned OFF and the NMOST transistor 1902 is turned ON. This ensures that the pull-up transistors and the differential pair transistors operate in a complementary fashion, i.e., only one of them is ON at a time. By doing so, this embodiment saves power consumed by the differential pairs and their base transistors during the metastable state and also makes it easier for the pull- up transistors to achieve the nietastable state.
[0058]. In another embodiment of the invention, the control transistor 1902 can also be used in the delay cell 700 of Figure 7, to get the delay cell 2000 of Figure 20. The operation principle of the control transistor 1902 remains the same in this embodiment with only the addition of the inductor 702 which enables higher frequency operation of the ring oscillator 502.
[0059]. In addition, the pull function in the illustrated exemplary embodiment of Figure 19 is performed by one PMOS transistor (on each side), it will be understood that the pull function may also be performed by a complete transmission gate (NMOS-PMOS pair). In other words, a complete transmission gate can also be used in place of this single PMOS pull-up to achieve the same functionality.
[0060]. Those of skill in the art wall appreciate that the various examples, aspects, logical and functional blocks, components, devices, graphs, modules and units described in connection with the aspects disclosed herein can be implemented as hardware blocks inside an application specific integrated chip (ASIC) or in discrete blocks in 3D integrated circuits or in multichip modules or hybrids or reconfigurable modules of software defined radios (implemented in any known technology). To clearly illustrate this interchangeability of hardware and functionality, various illustrative aspects, devices, components, blocks, modules, and/or steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software, or a combination thereof, depends upon the particular constraints imposed on the overall system and devices. Skilled persons can implement the described functionality in varying ways for each particular system, but such implementation decisions should not be interpreted as causing a departure from the scope of the invention as described herein. In addition, the grouping of functions, components or devices within a unit, module, block, or step is for ease of description. Specific functions, components or steps can be moved from one unit, module, or block without departing from the invention.
[0061]. The above description of the disclosed aspects, and that provided in the accompanying figures, is provided to enable any person skilled in the art to make or use the invention. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles described herein, and in the accompanying figures, can be applied to other aspects without departing from the spirit or scope of the invention. Thus, it is to be understood that the description and drawings presented herein, and presented in the accompanying documents, represent particular aspects of the invention and are therefore representative examples of the subject matter that is broadly contemplated by the present invention. It is further understood that the scope of the present invention fully encompasses other aspects that are, or may become, understood to those skilled in the art based on the descriptions presented herein and that the scope of the present invention is accordingly not limited by the descriptions of aspects presented herein, or by the descriptions of aspects presented in the accompanying figures.

Claims

CLAIMS What we claim is:
1. A true random number generator for generating true random numbers at a high frequency rate, the true random number generator comprising: a plurality of entropy source blocks, each entropy source block having an input condition and providing an entropy output signal, wherein the entropy output signal of a first one of the entropy source blocks is used as the input condition for a next one of entropy source blocks and the entropy output signal of the next one of the entropy source blocks is used as the input condition for a subsequent next one of the entropy source blocks; and a bit generation block that samples the entropy output signals of the plurality of entropy source blocks and combines the sampled entropy output signals into a combined entropy output signal and uses the combined entropy output signal to generate a plurality of random output bits,
2. The true random number generator of Claim 1, wherein the input condition of each entropy source block is a bias condition.
3. The true random number generator of Claim 1, wherein the plurality of entropy source blocks include two or more of a chaos generator block, a power supply noise source block, a metastability generator block, an oscillator jitter generator block, a quantum noise source block, and a thermal/shot noise source block,
4. The true random number generator of Claim 1, wherein all of the plurality of entropy source blocks operate at different rates.
5. The true random number generator of Claim 1, wherein some of the plurality of entropy source blocks operate at different rates.
6. The true random number generator of Claim 1, wh erein all of the plurality of entropy source blocks operate at the same rate.
7. The true random number generator of Claim 1, wherein at least one of the plurality of entropy source blocks operates synchronously and at least one other of the plurality of entropy source blocks operates asynchronously.
8. The true random number generator of Claim 1 , wherein all of the plurality of entropy source blocks operate synchronously.
9. The true random number generator of Claim 1, wherein all of the plurality of entropy source blocks operate asynchronously.
10. The true random number generator of Claim 1, wherein the plurality of entropy source blocks are arranged in a predetermined order, and wherein a precedent group of the plurality of entropy source blocks are positioned before a juncture in the predetermined order and a subsequent group of the plurality of entropy source blocks are positioned after a juncture in the predetermined order.
11. The true random number generator of Claim 10, wherein all of the precedent entropy source blocks affect the entropy output signals of the subsequent group of the plurality of entropy source blocks.
12. The true random number generator of Claim 10, wherein some of the precedent entropy source blocks affect the entropy output signals of the subsequent group of the plurality of entropy source blocks.
13. The true random number generator of Claim 1, w'herein at least one of the plurality of entropy source blocks produces an analog signal as its entropy output signal and at least one other of the plurality of entropy source blocks produces a digital signal as its entropy output signal.
14. The true random number generator of Claim 1, wherein all of the plurality of entropy source blocks produce an analog signal as their respective entropy output signals.
15. The true random number generator of Claim 1, wherein all of the plurality of entropy source blocks produce a digital signal as their respective entropy output signals.
16. The true random number generator of Claim 1 , wherein at least one of the plurality of entropy source blocks has a differential confi guration and at least one other of the plurality of entropy source blocks has a single-ended configuration.
17. The true random number generator of Claim 1 , wherein all of the plurality of entropy source blocks have a differential configuration.
18. The true random number generator of Claim 1, wherein all of the plurality of entropy source blocks have a single-ended configuration.
19. The true random number generator of Claim 1, wherein the bit generation block samples the entropy output signals of all of the plurality of entropy source blocks and combines them into the combined entropy output signal.
20. The true random number generator of Claim 1, wherein the bit generation block samples the entropy output signals of only some of the plurality of entropy source blocks and combines them into the combined entropy output signal.
21. A time random number generator for generating true random numbers at a high frequency rate, the true random number generator comprising: a plurality of entropy source blocks, each entropy source block having an input condition and providing an entropy output signal, wherein the entropy output signals of at least some of the plurality of entropy source blocks affect the entropy output signals of at least some other of the plurality of entropy source blocks; a ring oscillator that receives the entropy output signals of at least two of the plurality of entropy source blocks along with a clock signal and outputs a plurality of random output signals; a plurality of buffers that receive the plurality of random output signals from the ring oscillator, respectively, and output a plurality of buffered random output signals; and a sampling circuit that receives the entropy output signal of a third one of the plurality of entropy source blocks, samples the plurality of buffered random output signals from the plurality of buffers and outputs a plurality of sampled random output signals.
22. The true random number generator of Claim 21, wherein the plurality of entropy source blocks include two or more of a chaos generator block, a power supply noise source block, a metastability generator block, an oscillator jitter generator block, a quantum noise source block, and a thermal/shot noise source block.
23. The true random number generator of Claim 21, wherein the entropy output signals of the at least two of the plurality of entropy source blocks received by the ring oscillator are from a chaos generator block and a power supply noise source block.
24. The true random number generator of Claim 23, wherein the entropy output signal of the chaos generator block is used as a delay control signal by the ring oscillator to adjust a variable delay of the ring oscillator.
25. The true random number generator of Claim 23, wherein the entropy output signal of the chaos generator block is used by the ring oscillator to control an oscillation frequency of the ring oscillator.
26. The true random number generator of Claim 21, wherein the clock signal is used as a metastability control signal by the ring oscillator to adjust an output frequency of the plurality of random output signals.
27. The true random number generator of Claim 23, wherein the chaos generator block is based on a non-linear map chaotic circuit configuration.
28. The true random number generator of Claim 23, wherein the chaos generator block is based on a Chua circuit configuration.
29. The true random number generator of Claim 21, wherein the ring oscillator comprises a plurality of delay cells that correspond to the plurality of random output signals, respectively.
30. The true random number generator of Claim 29, wherein the plurality of delay cells comprises five delay cells and the plurality of random output signals comprises five random output signals.
31. The true random number generator of Claim 21, wherein the plurality of buffers are a plurality of amplifiers that, amplify the plurality of random output signals from the ring oscillator to output the plurality of buffered random output signals.
32. The true random number generator of Claim 21, wherein the third one of the plurality of entropy source blocks is an oscillator jitter generator block and the entropy output signal of the oscillator jitter generator block controls a sample rate at which the sampling circuit samples the plurality of buffered random output signals from the plurality of buffers.
33. The true random number generator of Claim 21, further comprising a bit order multiplexer that receives the entropy output signal of a fourth one of the plurality of entropy source blocks, receives the plurality of sampled random output signals from the sampling circuit and outputs a plurality of multiplexed random output signals.
34. The true random number generator of Claim 33, wherein the fourth one of the plurality- of entropy source blocks is a chaos generator block and the entropy output signal of the chaos generator block controls an output order in which the bit order multiplexer outputs the plurality of multiplexed random output signals.
35. The time random number generator of Claim 21, wherein the ring oscillator comprises two delay paths, the first delay path comprising a first plurality of delay paths and operating at a first oscillator frequency and the second delay path comprising a second plurality of delay paths and operating at a second oscillator frequency.
36. The true random number generator of Claim 35, wherein the ring oscillator further comprises a first switch that controls whether the ring oscillator operates via the first delay path, and a second switch that controls whether the ring oscillator operates via the second delay path.
37. The true random number generator of Claim 36, wherein a first control input signal is used by the ring oscillator to control operation of the first switch and a second control input, signal is used by the ring oscillator to control operation of the second switch.
38. The true random number generator of Claim 37, wherein the first control input signal and the second control input signal are provided by a chaos generator block.
39. The true random number generator of Claim 21, wherein the ring oscillator further comprises a voltage supply signal ( VDD) and a pull-up transistor, wherein the pull-up transistor connects the plurality of random output signals to the voltage supply signal (VDD) in order to enhance metastability of the plurality of random output signals of the ring oscillator.
40. The true random number generator of Claim 21, wherein the ring oscillator further comprises a ground connection and a pull-down transistor which connects the plurality of random output signals to the ground connection in order to enhance metastability of the plurality of random output signals of the ring oscillator.
41. The true random number generator of Claim 29, wherein each of the plurality of delay cells includes a first differential pair of transistors and a second differential pair of transistors, and wherein the first differential pair of transistors and the second differential pair of transistors are used within the respective delay cell to determine whether the delay cell is operational within a delay path of the ring oscillator.
42. The true random number generator of Claim 29, wherein each of the plurality of delay cells includes a cross-coupled pair of transistors that are used to amplify a differential signal in order to generate a random output signal of the delay cell, the random output signal having oscillations with a random phase.
43. The true random number generator of Claim 29, wherein each of the plurality of delay cells includes an inductor disposed between two output nodes of the respective delay cell, wherein the inductor reduces a delay of the respective delay cell thereby increasing a frequency bandwidth of the ring oscillator.
44. The true random number generator of Claim 21, wherein each of the plurality of buffers is a modified differential amplifier that comprises a differential pair of transistors each of which is connected to a resistive load, a current source, and a pair of control signals that are used to control the differential pair of transistors in order to switch operation of the modified differential amplifier between a normal state and a metastable state.
45. The true random number generator of Claim 23, wherein the chaos generator block is a tent-map circuit comprised of three transistors that has a non-linear response.
46. The true random number generator of Claim 45, wherein the non-linear response of the tent-map circuit varies in relation to a size and a body bias voltage of each of three transistors.
47. The true random number generator of Claim 46, wherein a first transistor of the three transistors operates as a current source and a second transistor and a third transistor of the three transistors operate as pull-down transistors, and wherein multiple input voltage signals are used to control the three transistors in order to pull an output signal of the tent-map circuit towards a ground connection or towards a voltage supply signal (VDD).
48. A multi-core true random number generator comprising a plurality of the true random number generators of Claim 21, wherein each of the plurality of true random number generators outputs a separate independent plurality of sampled random output signals.
49. The hue random number generator of Claim 48 which is implemented by a CMOS chip manufacturing technology.
50. The true random number generator of Claim 49 which is implemented by a 65-nanometer CMOS chip manufacturing technology.
51. The true random number generator of Claim 33, further comprising a parallel-in serial-out shift register that receives the plurality of multiplexed random output signals from the bit order multiplexer and outputs a multi-digit random output stream.
52. A true random number generator for generating true random numbers at a high frequency rate, the true random number generator comprising: a plurality of entropy source blocks, each entropy source block having an input condition and providing an entropy output signal, wherein the entropy output signals of at least some of the plurality of entropy source blocks affect, the entropy output signals of at least some other of the plurality of entropy source blocks; a ring oscillator that receives the entropy output signals of at least two of the plurality of entropy source blocks along with a clock signal and outputs a random output signal; a buffer that receives the random output signal from the ring oscillator and outputs a buffered random output signal; and a sampling circuit that receives the entropy output signal of a third one of the plurality of entropy source blocks, samples the buffered random output signal from the buffer and outputs a sampled random output signal.
53. The true random number generator of Claim 52, further comprising a delay element and an XOR gate that are used to remove a bias from the sampled random output signal.
54. A method for generating true random numbers at a high frequency rate, the method comprising the steps of: generating an entropy output signal from each of a plurality of entropy source blocks, each entropy source block having an input condition, wherein the entropy output signal of a first one of the entropy source blocks is used as the input condition for a next one of entropy source blocks and the entropy output signal of the next one of the entropy source blocks is used as the input, condition for a subsequent next one of the entropy source blocks; sampling the entropy output signals from the plurality of entropy source blocks; combining the sampled entropy output signals into a combined entropy output signal; and using the combined entropy output signal to generate a plurality of random output bits.
55. The method of Claim 54, wherein the input condition of each entropy source block is a bias condition.
56. The method generator of Claim 54, wherein the plurality of entropy source blocks include two or more of a chaos generator block, a power supply noise source block, a metastability generator block, an oscillator jitter generator block, a quantum noise source block, and a thermal/ shot noise source block.
57. The method of Claim 54, wherein all of the plurality of entropy source blocks operate at different rates.
58. The method of Claim 54, wherein some of the plurality of entropy source blocks operate at different rates.
59. The method of Claim 54, wherein all of the plurality of entropy source blocks operate at the same rate,
60. The method of Claim 54, wherein at least one of the plurality of entropy source blocks operates synchronously and at least one other of the plurality of entropy source blocks operates asynchronously.
61. The method of Claim 54, wherein all of the plurality of entropy source blocks operate synchronously.
62. The method of Claim 54, wherein all of the plurality of entropy source blocks operate asynchronously.
63. The method of Claim 54, wherein the plurality of entropy source blocks are arranged in a predetermined order, and wherein a precedent group of the plurality of entropy source blocks are positioned before a juncture in the predetermined order and a subsequent group of the plurality of entropy source blocks are positioned after a juncture in the predetermined order.
64. The method of Claim 63, wherein all of the precedent entropy source blocks affect the entropy output signals of the subsequent group of the plurality of entropy source blocks.
65. The method of Claim 63, wherein some of the precedent entropy source blocks affect the entropy output signals of the subsequent group of the plurality of entropy source blocks.
66. The method of Claim 54, wherein at least one of the plurality of entropy source blocks produces an analog signal as its entropy output signal and at least one other of the plurality of entropy source blocks produces a digital signal as its entropy output signal.
6'7. The method of Claim 54, wherein all of the plurality of entropy source blocks produce an analog signal as their respective entropy output signals.
68. The method of Claim 54, wherein all of the plurality of entropy source blocks produce a digital signal as their respective entropy output signals.
69. The method of Claim 54, wherein at least one of the plurality of entropy source blocks has a differential configuration and at least one other of the plurality of entropy source blocks has a single-ended configuration.
70. The method of Claim 54, wherein all of the plurality of entropy source blocks have a differential configuration.
71. The method of Claim 54, wherein all of the plurality of entropy source blocks have a single-ended configuration.
72. A method for generating true random numbers at a high frequency rate, the method comprising the steps of generating an entropy output signal from each of a plurality of entropy source blocks, wherein the entropy output signals of at least some of the plurality of entropy source blocks affect the entropy output signals of at least some others of the plurality of entropy source blocks; receiving, at a ring oscillator, the entropy output, signals of at least two of the plurality of entropy source blocks and a clock signal and outputting a plurality of random output signals from the ring oscillator; receiving, at a plurality of buffers, the plurality of random output signals from the ring oscillator, respectively, and outputting a plurality of buffered random output signals from the plurality of buffers; and sampling, by a sampling circuit that receives the entropy output signal of a third one of the plurality of entropy source blocks, the plurality of buffered random output signals from the plurality of buffers and outputting a plurality of sampled random output signals from the sampling circuit.
73. The method of Claim 72, wherein the plurality of entropy source blocks include two or more of a chaos generator block, a power supply noise source block, a metastability generator block, an oscillator jitter generator block, a quantum noise source block, and a thermal/shot noise source block.
74. The method of Claim 72, wherein the entropy output signals of the at least two of the plurality of entropy source blocks received by the ring oscillator are from a chaos generator block and a power supply noise source block.
75. The method of Claim 74, wherein the entropy output signal of the chaos generator block is used as a delay control signal by the ring oscillator to adjust a variable delay of the ring oscillator.
76. The method of Claim 74, wherein the entropy output signal of the chaos generator block is used by the ring oscillator to control an oscillation frequency of the ring oscillator.
77. The method of Claim 72, wherein the clock signal is used as a metastability control signal by the ring oscillator to adjust an output frequency of the plurality of random output signals.
78. The method of Claim 74, wherein the chaos generator block is based on a non-linear map chaotic circuit configuration.
79. The method of Claim 74, wherein the chaos generator block is based on a Chua circuit configuration.
80. The method of Claim 72, wherein the ring oscillator comprises a plurality of delay cells that correspond to the plurality of random output signals, respectively.
81. The method of Claim 80, wherein the plurality of delay cells comprises five delay cells and the plurality of random output signals comprises five random output signals.
82. The method of Claim 72, wherein the plurality of buffers are a plurality of amplifiers that amplify the plurality of random output signals from the ring oscillator to output the plurality of buffered random output signals.
83. The method of Claim 72, wherein the third one of the plurality of entropy source blocks is an oscillator jitter generator block and the entropy output signal of the oscillator jitter generator block controls a sample rate at which the sampling circuit samples the plurality of buffered random output signals from the plurality of buffers.
84. The method of Claim 72, further comprising receiving in a bit order the entropy output signal of a fourth one of the plurality of entropy source blocks, receiving the plurality of sampled random output signals from the sampling circuit and outputting a plurality of multiplexed random output signals.
85. The method of Claim 84, wherein the fourth one of the plurality of entropy source blocks is a chaos generator block and the entropy output signal of the chaos generator block controls an output order of the plurality of multiplexed random output signals.
86. The method of Claim 72, wherein the ring oscillator comprises two delay paths, the first delay path comprising a first plurality of delay paths and operating at a first oscillator frequency and the second delay path comprising a second plurality of delay paths and operating at a second oscillator frequency.
87. The method of Claim 86, wherein the ring oscillator further comprises a first switch that controls whether the ring oscillator operates via the first delay path, and a second switch that controls whether the ring oscillator operates via the second delay path.
88. The method of Claim 87, wherein a first control input signal is used by the ring oscillator to control operation of the first switch and a second control input signal is used by the ring oscillator to control operation of the second switch.
89. The method of Claim 88, wherein the first control input signal and the second control input signal are provided by a chaos generator block.
90. The method of Claim 72, wherein the ring oscillator further comprises a voltage supply signal (VDD) and a pull-up transistor, wherein the pull-up transistor connects the plurality of random output signals to the voltage supply signal (VDD) in order to enhance metastability of the plurality of random output signals of the ring oscillator.
91. The method of Claim 72, wherein the ring oscillator further comprises a ground connection and a pull-down transistor which connects the plurality of random output signals to the ground connection in order to enhance metastability of the plurality of random output signals of the ring oscillator.
92. The method of Claim 80, wherein each of the plurality of delay cells includes a first differential pair of transistors and a second differential pair of transistors, and wherein the first differential pair of transistors and the second differential pair of transistors are used within the respective delay cell to determine whether the delay cell is operational within a delay path of the ring oscillator.
93. The method of Claim 80, wherein each of the plurality of delay cells includes a cross-coupled pair of transistors that are used to amplify a differential signal in order to generate a random output signal of the delay cell, the random output signal having oscillations with a random phase.
94. The method of Claim 80, wherein each of the plurality of delay cells includes an inductor disposed between two output nodes of the respective delay cell, wherein the inductor reduces a delay of the respective delay cell thereby increasing a frequency bandwidth of the ring oscillator.
95. The method of Ciaim 72, wherein each of the plurality of buffers is a modified differential amplifier that comprises a differential pair of transistors each of which is connected to a resistive load, a current source, and a pair of control signals that are used to control the differential pair of transistors in order to switch operation of the modified differential amplifier between a normal state and a metastable state.
96. The method of Claim 74, wherein the chaos generator block is a tent-map circuit comprised of three transistors that has a non-linear response.
97. The method of Claim 96, wherein the non-linear response of the tent-map circuit varies in relation to a size and a body bias voltage of each of three transistors.
98. The method of Claim 97, wherein a first transistor of the three transistors operates as a current source and a second transistor and a third transistor of the three transistors operate as pull-down transistors, and wherein multiple input voltage signals are used to control the three transistors in order to pull an output signal of the tent-map circuit towards a ground connection or towards a voltage supply signal (VDD).
99. The true random number generator of Claim 41, wherein each of the plurality of delay cells includes an additional transistor structured and configured to turn OFF the first the first differential pair of transistors and the second differential pair of transistors during a metastable state.
100. The method of Claim 92, wherein each of the plurality of delay cells includes an additional transistor structured and configured to turn OFF the first the first differential pair of transistors and the second differential pair of transistors during a metastable state.
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