WO2023014355A1

WO2023014355A1 - Power management circuit supporting fast voltage switching with reduced rush current

Info

Publication number: WO2023014355A1
Application number: PCT/US2021/044596
Authority: WO
Inventors: Nadim Khlat; Jeffrey D. Potts
Original assignee: Qorvo US Inc
Current assignee: Qorvo US Inc
Priority date: 2021-08-05
Filing date: 2021-08-05
Publication date: 2023-02-09
Anticipated expiration: 2024-02-05
Also published as: US20250096746A1

Abstract

A power management circuit supporting fast voltage switching with reduced rush current is provided. The power management circuit is configured to provide an average power tracking (APT) voltage to a power amplifier circuit for amplifying an analog signal. Moreover, the power management circuit must be able to adapt the APT voltage frequently and rapidly to enable such application as dynamic power control. In embodiments disclosed herein, the power management circuit can be configured to opportunistically activate a voltage amplifier, which is typically used to generate an envelope tracking (ET) voltage, at an appropriate time to help support fast switching of the APT voltage. As a result, the power management circuit is able to adapt the APT voltage frequently and rapidly. Furthermore, by utilizing the voltage amplifier to support fast switching of the APT voltage, it is also possible to reduce rush current in the power management circuit.

Description

POWER MANAGEMENT CIRCUIT SUPPORTING FAST VOLTAGE SWITCHING WITH REDUCED RUSH CURRENT

Field of the Disclosure

[0001] The technology of the disclosure relates generally to an envelope tracking (ET) and/or average power tracking (APT) power management circuit.

Background

[0002] Fifth-generation (5G) new radio (NR) (5G-NR) has been widely regarded as the next generation of wireless communication technology beyond the current third-generation (3G) and fourth-generation (4G) technologies. In this regard, a wireless communication device capable of supporting the 5G-NR wireless communication technology is expected to achieve higher data rates, improved coverage range, enhanced signaling efficiency, and reduced latency across a wide range of radio frequency (RF) bands, which include a low-band (below 1 GHz), a mid-band (1 GHz to 6 GHz), and a high-band (above 24 GHz). [0003] Downlink and uplink transmissions in a 5G-NR system are widely based on orthogonal frequency division multiplexing (OFDM). In this regard, Figure 1 is a schematic diagram of an exemplary OFDM time-frequency grid 10 illustrating at least one reserve block (RB 12) for physical resource allocation in the 5G-NR system. The OFDM time-frequency grid 10 includes a frequency axis 14 representing a frequency domain and a time axis 16 representing a time domain. Along the frequency axis 14, there are a number of subcarriers 18(1 )- 18(M). The subcarriers 18(1 )-18(M) are orthogonally separated from each other by a subcarrier spacing (SCS) of 15 KHz, for example. Along the time axis 16, there are a number of OFDM symbols 20(1 )-20(N). Each of the OFDM symbols 20(1 )-20(N) is separated by a cyclic prefix (CP) (not shown) configured to act as a guard band to help overcome inter-symbol interference (ISI) between the OFDM symbols 20(1 )-20(N). In the OFDM time-frequency grid 10, each intersection of the subcarriers 18(1 )-18M) and the OFDM symbols 20(1 )-20(N) defines a resource element (RE) 22. [0004] In a 5G-NR communication system, an RF signal 24 can be modulated into multiple subcarriers among the subcarriers 18(1 )-18(N) in the frequency domain (along the frequency axis 14) and multiple OFDM symbols among the OFDM symbols 20(1 )-20(N) in the time domain (along the time axis 16). The table (Table 1 ) below summarizes OFDM configurations supported by the 5G-NR communication system.

Table 1

[0005] In the 5G-NR communication system, the RF signal 24 is typically modulated with a high modulation bandwidth in excess of 200 MHz. In this regard, according to Table 1 , the SCS will be 120 KHz and a transition settling time between two consecutive OFDM symbols among the OFDM symbols 20(1 )- 20(N) (e.g., amplitude change of the RF signal) needs to be less than or equal to the CP duration of 0.59 ps.

[0006] In addition, the wireless communication device may also need to support such internet-of-things (loT) applications as keyless car entry, remote garage door opening, contactless payment, mobile boarding pass, and so on. Needless to say, the wireless communication device must also always make 911/E911 service accessible under emergency situations. As such, it is critical that the wireless communication device remains operable whenever needed. [0007] Notably, the wireless communication device relies on a battery cell (e.g., Li-Ion battery) to power its operations and services. Despite recent advancement in battery technologies, the wireless communication device can run into a low battery situation from time to time. In this regard, it is desirable to prolong battery life concurrent to enabling fast voltage changes between the OFDM symbols 20(1)-20(N).

[0008] Embodiments of the disclosure relate to a power management circuit supporting fast voltage switching with reduced rush current. The power management circuit is configured to provide an average power tracking (APT) voltage to a power amplifier circuit for amplifying an analog signal. Moreover, the power management circuit must be able to adapt the APT voltage frequently and rapidly to enable such application as dynamic power control. In embodiments disclosed herein, the power management circuit can be configured to opportunistically activate a voltage amplifier, which is typically used to generate an envelope tracking (ET) voltage, at an appropriate time to help support fast switching of the APT voltage. As a result, the power management circuit is able to adapt the APT voltage frequently and rapidly. Furthermore, by utilizing the voltage amplifier to support fast switching of the APT voltage, it is also possible to reduce rush current in the power management circuit to help prolong battery life.

[0009] In one aspect, a power management circuit is provided. The power management circuit includes a voltage output that outputs an APT voltage to a power amplifier circuit for amplifying an analog signal. The power management circuit also includes a voltage amplifier coupled to the voltage output and configured to generate an ET voltage based on an ET target voltage and a supply voltage. The power management circuit also includes a control circuit. The control circuit is configured to receive a target voltage indicating that the APT voltage will change from a present voltage level in a present time interval to a future voltage level in an upcoming time interval. The control circuit is also configured to activate the voltage amplifier prior to a start of the upcoming time interval to thereby cause the APT voltage to change to the target voltage within a defined temporal limit from the start of the upcoming time interval. [0010] In another aspect, a power management apparatus is provided. The power management apparatus includes a power amplifier circuit configured to amplify an analog signal based on an APT voltage. The power management apparatus also includes a power management circuit. The power management circuit includes a voltage output that outputs the APT voltage to the power amplifier circuit. The power management circuit also includes a voltage amplifier coupled to the voltage output and configured to generate an ET voltage based on an ET target voltage and a supply voltage. The power management circuit also includes a control circuit. The control circuit is configured to receive a target voltage indicating that the APT voltage will change from a present voltage level in a present time interval to a future voltage level in an upcoming time interval. The control circuit is also configured to activate the voltage amplifier prior to a start of the upcoming time interval to thereby cause the APT voltage to change to the target voltage within a defined temporal limit from the start of the upcoming time interval.

[0011] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

Brief Description of the Drawing Figures

[0012] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0013] Figure 1 is a schematic diagram of an exemplary orthogonal frequency division multiplexing (OFDM) time-frequency grid illustrating at least one reserve block (RB) for physical resource allocation;

[0014] Figure 2 is a schematic diagram of an exemplary conventional power management circuit that can draw a large rush current during voltage switching; [0015] Figure 3 is a schematic diagram of an exemplary power management circuit configured according to an embodiment of the present disclosure to support fast voltage switching in a power management apparatus with reduced rush current;

[0016] Figure 4 is a timing diagram providing an exemplary illustration of the power management circuit of Figure 3 configured to increase an average power tracking (APT) voltage from a present voltage level in a present OFDM symbol to a future voltage level in an upcoming OFDM symbol; and

[0017] Figure 5 is a timing diagram providing an exemplary illustration of the power management circuit of Figure 3 configured to decrease an APT voltage from a present voltage level in a present OFDM symbol to a future voltage level in an upcoming OFDM symbol.

Detailed Description

[0018] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0019] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. [0020] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0021] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0024] Embodiments of the disclosure relate to a power management circuit supporting fast voltage switching with reduced rush current. The power management circuit is configured to provide an average power tracking (APT) voltage to a power amplifier circuit for amplifying an analog signal. Moreover, the power management circuit must be able to adapt the APT voltage frequently and rapidly to enable such application as dynamic power control. In embodiments disclosed herein, the power management circuit can be configured to opportunistically activate a voltage amplifier, which is typically used to generate an envelope tracking (ET) voltage, at an appropriate time to help support fast switching of the APT voltage. As a result, the power management circuit is able to adapt the APT voltage frequently and rapidly. Furthermore, by utilizing the voltage amplifier to support fast switching of the APT voltage, it is also possible to reduce rush current in the power management circuit to help prolong battery life.

[0025] Before discussing the power management circuit according to the present disclosure, starting at Figure 3, an overview of a conventional power management circuit that can draw a lager rush current during voltage switching is first provided with reference to Figure 2.

[0026] Figure 2 is a schematic diagram of an exemplary conventional power management circuit 26 that can draw a large rush current IRUSH during voltage switching. The conventional power management circuit 26 includes a voltage source 28 and a power management integrated circuit (PMIC) 30. The voltage source 28 includes a battery 32 (e.g., a Li-Ion battery) that supplies a battery voltage VBAT at a coupling node 34, which may be coupled to a ground (GND) via a capacitor CBYP and a resistor RBYP. The PMIC 30 is coupled to the coupling node 34 to receive the battery voltage VBAT and draw a battery current IBAT. Accordingly, the PMIC 30 is configured to generate an APT voltage Vcc based on the battery voltage VBAT and provide the APT voltage Vcc to a power amplifier circuit 36 for amplifying an analog signal 38.

[0027] The analog signal 38 may be modulated across a wide modulation bandwidth, which can cause a large variation of RF current at the power amplifier circuit 36. As such, it is necessary to present a low impedance to the power amplifier circuit 36 to help reduce ripple in the APT voltage Vcc caused by the RF current. In this regard, the conventional power management circuit 26 typically includes an offset capacitor COFF to help reduce the impedance seen by the power amplifier circuit 36.

[0028] In addition to impedance matching, the offset capacitor COFF is also used to maintain the APT voltage Vcc at a desired voltage level. In this regard, the offset capacitor COFF needs to be charged whenever the APT voltage Vcc increases and discharged whenever the APT voltage Vcc decreases. As such, as shown in the equation (Eq. 1 ) below, a change rate (dVcc/dt) of the APT voltage Vcc is dependent on how fast the offset capacitor COFF can be charged or discharged. dVcc/dt = IRUSH I COFF (Eq. 1 )

[0029] In the equation (Eq. 1 ) above, I USH represents a rush current associated with charging/discharging of the offset capacitor COFF and COFF represents a capacitance of the offset capacitor COFF. Particularly, when the offset capacitor COFF is charged in response to an increase of the APT voltage Vcc, the offset capacitor COFF draws the rush current IRUSH from the battery 32. Given that the capacitance COFF is typically fixed and relatively large (e.g., 2.2 /zF), the only way to reduce switching time of the APT voltage Vcc is to increase the rush current IRUSH. For example, when the APT voltage Vcc changes from 1 V to 5.5 V within 0.59 //s, the rush current IRUSH can be as high as 17 Amps (A), which can significantly reduce operating time of the battery 32.

[0030] To avoid amplitude clipping to the analog signal 38 at the power amplifier circuit 36, the PMIC 30 is configured to generate the APT voltage Vcc in accordance with an APT target voltage VTGT that corresponds to average power of the analog signal 38. As such, the APT voltage Vcc can swing from low to high, or vice versa, from time to time. When the conventional power management circuit 26 is provided in a legacy second generation (2G), third generation (3G), or even fourth generation (4G) wireless communication device, the APT voltage Vcc may change at a relatively slower rate. As such, the rush current IRUSH may have a lesser impact on the battery 32. However, in a fifth generation (5G) new radio (5G-NR) wireless communication device, the APT voltage Vcc may need to change very frequently (e.g., between each of the OFDM symbols 20(1 )-20(N) in Figure 1 ) and rapidly (e.g., within the CP duration of 0.59 ps). As a result, the rush current I USH can have a tremendous impact on battery life. As such, it is desirable to reduce the rush current IRUSH concurrent to supporting fast and frequent switching of the APT voltage Vcc.

[0031] In this regard, Figure 3 is a schematic diagram of an exemplary power management circuit 40 configured according to an embodiment of the present disclosure to support fast voltage switching in a power management apparatus 42 with reduced rush current. Herein, voltage switching refers to a voltage change (increase or decrease) from one voltage level to a different voltage level. [0032] The power management circuit 40 includes a voltage output 44 that outputs an APT voltage Vcc to a power amplifier circuit 46 for amplifying an analog signal 48. The power management circuit 40 also includes a voltage amplifier 50 (denoted as “VA”). The voltage amplifier 50 is typically activated to generate an ET voltage VAMP in accordance with an ET target voltage VTGT-ET and based on a supply voltage VSUP.

[0033] The power management circuit 40 also includes an offset capacitor COFF that is coupled between an output 52 of the voltage amplifier 50 and the voltage output 44. The power management circuit 40 also includes a switch circuit 54, which includes a bypass switch SBYP coupled between the output 52 of the voltage amplifier 50 and the GND. When the bypass switch SBYP is opened, the offset capacitor COFF will raise the ET voltage VAMP by an offset voltage VOFF to generate the APT voltage Vcc at the voltage output 44 (Vcc = VAMP + VOFF). In contrast, when the bypass switch SBYP is closed, the offset capacitor COFF will be charged by a low-frequency current IDC to thereby maintain the APT voltage Vcc at a desired voltage level. Further, when the bypass switch SBYP is closed, the offset capacitor COFF also helps to reduce the impedance seen by the power amplifier circuit 46. In this regard, when the bypass switch SBYP is closed, the offset capacitor COFF is functionally equivalent to the offset capacitor COFF in the conventional power management circuit 26 of Figure 2. Accordingly, the low- frequency current IDC drawn by the offset capacitor COFF can be equated with the rush current IRUSH in Figure 2.

[0034] As discussed in detail below, the power management circuit 40 can be configured to opportunistically activate and deactivate the voltage amplifier 50 at appropriate times to help enable fast switching of the APT voltage Vcc while concurrently reducing the rush current IDC drawn by the offset capacitor COFF. AS a result, the power management circuit 40 is able to adapt the APT voltage Vcc frequently and rapidly to support such applications as dynamic power control. Furthermore, by utilizing the voltage amplifier 50 to support fast switching of the APT voltage Vcc, it is also possible to reduce the rush current IDC to help prolong battery life.

[0035] In embodiments disclosed herein, the power management circuit 40 is configured to adapt the APT voltage Vcc in between a pair of consecutive OFDM symbols SN-I and SN, which can be any pair of consecutive OFDM symbols among the OFDM symbols 20(1 )-20(N) in Figure 1. The OFDM symbol SN-I is referred to as a preceding one of the pair of consecutive OFDM symbols SN-I and SN, and the OFDM symbol SN is referred to as a succeeding one of the pair of consecutive OFDM symbols SN-I and SN. Understandably from Figure 1 , each of the OFDM symbols SN-I and SN includes a CP duration as configured according to Table 1 .

[0036] In this regard, the power management circuit 40 is configured according to embodiments of the present disclosure to increase or decrease the APT voltage Vcc within the CP duration in each of the OFDM symbols SN-I and SN. However, it should be appreciated that the power management circuit 40 can also support fast switching of the APT voltage Vcc in other usage scenarios, such as adapting the APT voltage Vcc within an inter-frame spacing (IFS) in between two consecutive Wi-Fi frames.

[0037] The power management circuit 40 includes a switcher circuit 56. In a non-limiting example, the switcher circuit 56 includes a multi-level charge pump (MCP) 58 and a power inductor 60. The MCP 58 is configured to generate a low- frequency voltage VDC based on a battery voltage VBAT and in accordance with an APT target voltage VTGT-APT. Depending on the APT target voltage VTGT-APT, the MCP 58 may alternate the low-frequency voltage VDC between different levels (e.g., 0V, VBAT, or 2*VBAT) based on an appropriate duty cycle. The power inductor 60, which is coupled between the MCP 58 and the voltage output 44, is configured to induce the low-frequency current IDC for charging the offset capacitor COFF.

[0038] The power management circuit also includes a control circuit 62, which can be a field-programmable gate array (FPGA), as an example. The control circuit 62 is configured to receive a target voltage VTGT, for example from a transceiver circuit (not shown). The target voltage VTGT provides an early indication of the APT voltage Vcc in any of the OFDM symbols SN-I and SN. For example, the target voltage VTGT received during OFDM symbol SN-I may provide an indication of the APT voltage Vcc in the OFDM symbol SN. AS such, the control circuit 62 can determine, based on the target voltage VTGT, that the APT voltage Vcc will change from one voltage level to another in the OFDM symbol SN prior to a start of the OFDM symbol SN. Accordingly, the control circuit 62 can generate the ET target voltage VTGT-ET and the APT target voltage VTGT-APT based on the target voltage VTGT prior to the start of the OFDM symbol SN to cause the power management circuit 40 to adapt the APT voltage Vcc within a defined temporal limit (e.g., the CP duration) from the start of the OFDM symbol SN.

[0039] In one embodiment, the control circuit 62 determines (e.g., during OFDM symbol SN-I ) that the APT voltage Vcc is set to increase in the OFDM symbol SN. In this regard, Figure 4 is a timing diagram providing an exemplary illustration of the power management circuit 40 of Figure 3 configured to increase the APT voltage Vcc from a present voltage level VLp in OFDM symbol SN-I (also referred to as “a present OFDM symbol” or “present time interval”) to a future voltage level VLF in OFDM symbol SN (also referred to as “an upcoming OFDM symbol” or “upcoming time interval”). Common elements between Figures 3 and 4 are shown therein with common element numbers and will not be re-described herein.

[0040] With reference to Figure 4, the control circuit 62 receives the target voltage VTGT during the OFDM symbol SN-I and prior to a start time Ti of the OFDM symbol SN. The target voltage VTGT indicates that the APT voltage Vcc is set to increase from the present voltage level VLp (e.g., 1 V) in the OFDM symbol SN-I to the future voltage level VLF (e.g., 5.5 V) in the OFDM symbol SN.

Accordingly, the control circuit 62 generates the ET target voltage VTGT-ET and the APT target voltage VTGT-APT that are similar or identical to the target voltage VTGT. Notably, during the OFDM symbol SN-I , the bypass switch SBYP is closed and the offset capacitor COFF is charged to maintain the APT voltage Vcc at the present voltage level VLp.

[0041] Prior to the start time Ti of the OFDM symbol SN (e.g., at time T2), the control circuit 62 activates the voltage amplifier 50 to generate the ET voltage VAMT and source the high-frequency current IAMP based on the ET target voltage VTGT-ET. In a non-limiting example, the time T2 can be so determined to account for ramping up and settling time of the voltage amplifier 50. In addition, the time T2 can be further determined to ensure that the voltage amplifier 50 can ramp up the ET voltage VAMP to a level substantially equal (VLF - VOFF) within the CP duration of the OFDM symbol SN.

[0042] Concurrent to generating the ET voltage VAMP to quickly raise the APT voltage Vcc to the level of (VLF - VOFF), the high-frequency current IAMP will charge up a load capacitor CL to help maintain the APT voltage Vcc at the level of (VLF - VOFF). The load capacitor CL, which may be provided inside or outside the power amplifier circuit 46, has a smaller capacitance (e.g., 500 pF) compared to the offset capacitor COFF. AS a result, according to equation (Eq. 1 ), it is possible to charge up the load capacitor CL quickly with a reduced amount of rush current.

[0043] At the start time Ti of the OFDM symbol SN, the control circuit 62 opens the bypass switch SBYP such that the offset capacitor COFF can be charged by the low-frequency current IDC to raise the offset voltage VOFF from the present voltage level VLp to the future voltage level VLF. Given that the APT voltage Vcc has already been raised by the voltage amplifier 50 and maintained by the load capacitor CL, it is thus possible to charge the offset capacitor COFF at a slower rate to help further reduce demand for the low-frequency current IDC (a.k.a., rush current). As the offset voltage VOFF gradually increases, the voltage amplifier 50 can gradually reduce the ET voltage VAMP such that a sum of the ET voltage VAMP and the offset voltage VOFF would equal the future voltage level VLF.

[0044] At time T3, the offset voltage VOFF is raised to the future voltage value VLF. In this regard, the ET voltage VAMP is no longer needed. Accordingly, the control circuit 62 can close the bypass switch SBYP and deactivate the voltage amplifier 50. In one embodiment, the control circuit 62 may close the bypass switch SBYP and deactivate the voltage amplifier 50 concurrently at time T3. Alternatively, the control circuit 62 may deactivate the voltage amplifier 50 with a timing delay TDLY from closing the bypass switch SBYP.

[0045] Figure 5 is a timing diagram providing an exemplary illustration of the power management circuit 40 of Figure 3 configured to decrease the APT voltage Vcc from a present voltage level VLp in OFDM symbol SN-I (also referred to as “a present OFDM symbol”) to a future voltage level VLF in OFDM symbol SN (also referred to as “an upcoming OFDM symbol”). Common elements between Figures 3 and 5 are shown therein with common element numbers and will not be re-described herein.

[0046] With reference to Figure 5, the control circuit 62 receives the target voltage VTGT during the OFDM symbol SN-I and prior to a start time T1 of the OFDM symbol SN. The target voltage VTGT indicates that the APT voltage Vcc is set to decrease from the present voltage level VLp (e.g., 5.5 V) in the OFDM symbol SN-I to the future voltage level VLF (e.g., 1 V) in the OFDM symbol SN. Accordingly, the control circuit 62 generates the ET target voltage VTGT-ET and the APT target voltage VTGT-APT that are similar or identical to the target voltage VTGT. Notably, during the OFDM symbol SN-I , the bypass switch SBYP is closed and the offset capacitor COFF is charged to maintain the APT voltage Vcc at the present voltage level VLp.

[0047] Prior to the start time Ti of the OFDM symbol SN (e.g., at time T2), the control circuit 62 opens the bypass switch SBYP to discharge the offset capacitor COFF to reduce the offset voltage VOFF from the present voltage level VLp to the future voltage level VLF. The time T2 may be so determined to ensure that the offset voltage VOFF can be reduced to the future voltage level VLF within the CP duration of the OFDM symbol SN.

[0048] Notably, the power management circuit 40 still needs to maintain the APT voltage Vcc at the present voltage level VLp during the OFDM symbol SN-I while the offset capacitor COFF is discharged to reduce the offset voltage VOFF. In this regard, the control circuit 62 is further configured to activate the voltage amplifier 50 to help maintain the APT voltage Vcc at the present voltage level VLp before discharging the offset capacitor COFF. In addition, the voltage amplifier 50 also serves as a current sink to absorb discharge current associated with discharging the offset capacitor COFF. The control circuit 62 may activate the voltage amplifier 50 with a timing advance TADV before opening the bypass switch SBYP to start discharging the offset capacitor COFF. The timing advance TADV may be so determined to ensure that the voltage amplifier 50 can be ramped up and settled to maintain the APT voltage Vcc at the present voltage level VLp by the time T2.

[0049] At time T3, the offset voltage VOFF is reduced to the future voltage value VLF. In this regard, the ET voltage VAMP is no longer needed. Accordingly, the control circuit 62 can close the bypass switch SBYP and deactivate the voltage amplifier 50. In one embodiment, the control circuit 62 may close the bypass switch SBYP and deactivate the voltage amplifier 50 concurrently at time T3. Alternatively, the control circuit 62 may deactivate the voltage amplifier 50 with a timing delay TDLY from closing the bypass switch SBYP. [0050] With reference back to Figure 3, the control circuit 62 may activate/deactivate the voltage amplifier 50 and open/close the bypass switch SBYP based on a control signal 64. The power management circuit 40 also includes a supply voltage circuit 66 configured to generate the supply voltage VSUP for the voltage amplifier 50 based on a supply target voltage VTGT-SUP. The control circuit 62 may further generate the supply target voltage VTGT-SUP based on the target voltage VTGT.

[0051] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

Claims What is claimed is:

1 . A power management circuit comprising: a voltage output that outputs an average power tracking (APT) voltage to a power amplifier circuit for amplifying an analog signal; a voltage amplifier coupled to the voltage output and configured to generate an envelope tracking (ET) voltage based on an ET target voltage and a supply voltage; and a control circuit configured to: receive a target voltage indicating that the APT voltage with change from a present voltage level in a present time interval to a future voltage level in an upcoming time interval; and activate the voltage amplifier prior to a start of the upcoming time interval to thereby cause the APT voltage to change to the target voltage within a defined temporal limit from the start of the upcoming time interval.

2. The power management circuit of claim 1 , wherein: the present time interval corresponds to a preceding one of a pair of consecutive orthogonal frequency division multiplexing (OFDM) symbols; the upcoming time interval corresponds to a succeeding one of the pair of consecutive OFDM symbols; and the defined temporal limit corresponds to a cyclic prefix (CP) in each of the pair of consecutive OFDM symbols.

3. The power management circuit of claim 1 , wherein the control circuit is further configured to generate the ET target voltage based on the target voltage.

4. The power management circuit of claim 1 , further comprising: a switcher circuit coupled to the voltage output and configured to generate a low-frequency current based on an APT target voltage; an offset capacitor coupled between an output of the voltage amplifier and the voltage output and configured to raise the ET voltage by an offset voltage to generate the APT voltage at the voltage output; and a bypass switch coupled between the output of the voltage amplifier and a ground.

5. The power management circuit of claim 4, wherein the control circuit is further configured to: receive the target voltage indicating that the APT voltage will increase from the present voltage level to the future voltage level; and activate the voltage amplifier prior to the start of the upcoming time interval to thereby raise the APT voltage from the present voltage level to the future voltage level within the defined temporal limit.

6. The power management circuit of claim 5, wherein the control circuit is further configured to: generate the APT target voltage based on the target voltage; and control the switcher circuit to generate the low-frequency current based on the APT target voltage.

7. The power management circuit of claim 6, wherein the control circuit is further configured to open the bypass switch after activating the voltage amplifier to thereby charge the offset capacitor from the present voltage level to the future voltage level based on the low-frequency current.

8. The power management circuit of claim 7, wherein the control circuit is further configured to close the bypass switch in response to the offset voltage being charged up to the future voltage level. 18

9. The power management circuit of claim 8, wherein the control circuit is further configured to deactivate the voltage amplifier after closing the bypass switch.

10. The power management circuit of claim 8, wherein the control circuit is further configured to deactivate the voltage amplifier and close the bypass switch concurrently.

1 1 . The power management circuit of claim 4, wherein the control circuit is further configured to: receive the target voltage indicating that the APT voltage will decrease from the present voltage level to the future voltage level; and activate the voltage amplifier prior to the start of the upcoming time interval to thereby maintain the APT voltage at the present voltage level.

12. The power management circuit of claim 1 1 , wherein the control is further configured to open the bypass switch after activating the voltage amplifier and prior to the start of the upcoming time interval to thereby discharge the offset capacitor from the present voltage level to the future voltage level within the defined temporal limit.

13. The power management circuit of claim 12, wherein the control circuit is further configured to close the bypass switch in response to the offset capacitor being discharged to the future voltage level.

14. The power management circuit of claim 13, wherein the control circuit is further configured to deactivate the voltage amplifier after closing the bypass switch. 19

15. The power management circuit of claim 13, wherein the control circuit is further configured to deactivate the voltage amplifier and close the bypass switch concurrently.

16. The power management circuit of claim 1 , further comprising a supply voltage circuit configured to generate the supply voltage based on a supply target voltage.

17. The power management circuit of claim 16, wherein the control circuit is further configured to generate the supply target voltage based on the target voltage.

18. A power management apparatus comprising: a power amplifier circuit configured to amplify an analog signal based on an average power tracking (APT) voltage; and a power management circuit comprising: a voltage output that outputs the APT voltage to the power amplifier circuit; a voltage amplifier coupled to the voltage output and configured to generate an envelope tracking (ET) voltage based on an ET target voltage and a supply voltage; and a control circuit configured to: receive a target voltage indicating that the APT voltage will change from a present voltage level in a present time interval to a future voltage level in an upcoming time interval; and activate the voltage amplifier prior to a start of the upcoming time interval to thereby cause the APT voltage to change to the target voltage within a defined temporal limit from the start of the upcoming time interval. 20

19. The power management apparatus of claim 18, wherein the power management circuit further comprises: a switcher circuit coupled to the voltage output and configured to generate a low-frequency current based on an APT target voltage; an offset capacitor coupled between an output of the voltage amplifier and the voltage output and configured to raise the ET voltage by an offset voltage to generate the APT voltage at the voltage output; and a bypass switch coupled between the output of the voltage amplifier and a ground.

20. The power management apparatus of claim 19, wherein the power amplifier circuit comprises a load capacitor having a smaller capacitance than the offset capacitor.