HK40112918A - Fast-switching power management integrated circuit - Google Patents

Description

Fast switching power management integrated circuit

Related applications

This application claims the benefit of U.S. Provisional Patent Application No. 63/352,301, filed June 15, 2022, the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

The technology disclosed herein generally relates to power management integrated circuits (PMICs).

Background Technology

Fifth-generation (5G) New Radio (NR) (5G-NR) is widely considered to be the next generation of wireless communication technology, surpassing current third-generation (3G) and fourth-generation (4G) technologies. In this regard, wireless communication devices capable of supporting 5G-NR technology are expected to achieve higher data rates, improved coverage, enhanced signal transmission efficiency, and reduced latency across a wide range of radio frequency (RF) bands, including low-frequency (below 1 GHz), mid-frequency (1 GHz to 6 GHz), and high-frequency (above 24 GHz) bands.

Downlink and uplink transmissions in 5G-NR systems are widely based on Orthogonal Frequency Division Multiplexing (OFDM). In this regard, Figure 1 is a schematic diagram of an exemplary OFDM time-frequency grid 10, illustrating at least one resource block (RB) 12 for physical resource allocation in a 5G-NR system. The OFDM time-frequency grid 10 includes a frequency axis 14 representing the frequency domain and a time axis 16 representing the time domain. Along the frequency axis 14, there are multiple subcarriers 18(1)-18(M). The subcarriers 18(1)-18(M) are orthogonally separated by a subcarrier spacing (SCS) (e.g., 15 kHz). Along the time axis 16, there are multiple OFDM symbols 20(1)-20(N). The OFDM symbols 20(1)-20(N) can be modulated into data symbols to carry data payloads and/or reference symbols to carry reference signals such as demodulation reference signals (DMRS), sounding reference signals (SRS), etc. Each of the OFDM symbols 20(1)-20(N) is separated by a cyclic prefix (CP) (not shown), which is configured to act as a guard band to help overcome inter-symbol interference (ISI) between OFDM symbols 20(1)-20(N). In the OFDM time-frequency grid 10, each intersection of the subcarriers 18(1)-18M) and OFDM symbols 20(1)-20(N) defines a resource element (RE) 22.

In a 5G-NR communication system, an RF signal can be modulated into multiple subcarriers in the frequency domain (along the frequency axis 14) of subcarriers 18(1)-18(N) and multiple OFDM symbols in the time domain (along the time axis 16) of OFDM symbols 20(1)-20(N). The following table (Table 1) summarizes the OFDM configurations supported by the 5G-NR communication system.

Table 1

In 5G-NR systems, RF signals are typically modulated with a high modulation bandwidth exceeding 200MHz. In this regard, according to Table 1, the SCS will be 120kHz, and the transition settling time (e.g., amplitude change of the PF signal) between two consecutive OFDM symbols in OFDM symbols 20(1)-20(N) needs to be a CP duration of less than or equal to 0.59μs.

In addition, wireless communication devices may need to support Internet of Things (IoT) applications such as keyless entry, remote garage door opening, contactless payments, and mobile boarding passes. Undoubtedly, the wireless communication devices must also always ensure 911/E911 service is accessible in emergencies. Therefore, it is crucial that the wireless communication devices remain operational when needed.

It is worth noting that wireless communication devices rely on battery cells (e.g., Li-ion batteries) to power their operation and services. Despite recent advancements in battery technology, wireless communication devices may occasionally be in a low-power state. In this regard, it is desirable to extend battery life while enabling rapid voltage changes between OFDM symbols 20(1) and 20(N).

Summary of the Invention

Embodiments of this disclosure relate to a fast-switching power management integrated circuit (PMIC). The PMIC is configured to provide an average power tracking (APT) voltage to a power amplifier circuit for amplifying radio frequency (RF) signals modulated over multiple time intervals. Herein, the PMIC is configured to increase or decrease the APT voltage from a current voltage level in the current time interval to a future voltage level in the upcoming time interval with very short switching intervals (e.g., <20 nanoseconds). As the APT voltage transitions from the current voltage level to the future voltage level, the PMIC activates the voltage amplifier in a timely manner to help ensure proper operation of the power amplifier circuit (e.g., maintaining the APT voltage at the current level and reducing fluctuations in the APT voltage). Therefore, the PMIC can switch the APT voltage frequently and rapidly as the inrush current decreases.

In one aspect, a power amplifier circuit (PMIC) is provided. The PMIC includes a voltage output that outputs an analog power supply (APT) voltage to a power amplifier circuit for amplifying an RF signal modulated in a plurality of modulation units, each comprising a plurality of time intervals. The PMIC also includes an offset circuit coupled to the voltage output and configured to change the APT voltage from a current voltage level in a current time interval to a future voltage level in an upcoming time interval during a transition interval, the transition interval falling within one of the current time interval and the upcoming time interval. The PMIC also includes a voltage amplifier coupled to an input of the offset circuit. The voltage amplifier is activated at the start of the transition interval and deactivated at the end of the transition interval to generate a modulation voltage at the input of the offset circuit based on an amplifier target voltage determined to make the modulation voltage higher than or equal to the headroom voltage at the end of the transition interval.

In another aspect, a wireless communication circuit is provided. The wireless communication circuit includes a power control interface (PMIC). The PMIC includes a voltage output that outputs an analog power supply (APT) voltage for amplifying an RF signal modulated in a plurality of modulation units, each comprising a plurality of time intervals. The PMIC also includes an offset circuit. The offset circuit is coupled to the voltage output and configured to change the APT voltage from a current voltage level in the current time interval to a future voltage level in an upcoming time interval during a transition interval, the transition interval falling within one of the current time interval and the upcoming time interval. The PMIC also includes a voltage amplifier. The voltage amplifier is coupled to an input of the offset circuit. The voltage amplifier is activated at the beginning of the transition interval and deactivated at the end of the transition interval to generate a modulation voltage at the input of the offset circuit based on an amplifier target voltage determined to make the modulation voltage higher than or equal to the headroom voltage at the end of the transition interval.

After reading the following detailed description of preferred embodiments in relation to the accompanying drawings, those skilled in the art will understand the scope of this disclosure and appreciate its additional aspects.

Attached Figure Description

The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

Figure 1 is a schematic diagram illustrating an exemplary orthogonal frequency division multiplexing (OFDM) time-frequency grid for at least one resource block (RB) used for physical resource allocation;

Figure 2 is a schematic diagram of an exemplary power management integrated circuit (PMIC) configured to support fast average power point tracking (APT) voltage switching according to an embodiment of the present disclosure;

Figure 3 is a timing diagram illustrating an exemplary illustration of the PMIC of Figure 2 configured according to an embodiment of the present disclosure to increase the APT voltage from the current voltage level to a future voltage level;

Figure 4 is a timing diagram illustrating an exemplary illustration of the PMIC of Figure 2 configured according to an embodiment of the present disclosure to reduce the APT voltage from the current voltage level to a future voltage level.

Figure 5 is a timing diagram illustrating an exemplary illustration of the PMIC of Figure 2 configured according to another embodiment of the present disclosure to reduce the APT voltage from the current voltage level to a future voltage level;

Figures 6A and 6B are block diagrams providing exemplary illustrations of some power profiles that can be used by the PMIC of Figure 2 to achieve fast APT voltage switching; and

Figure 7 is a schematic diagram of an exemplary user component that can provide the PMIC of Figure 2.

Detailed Implementation

The embodiments described below illustrate the information necessary to enable those skilled in the art to practice the embodiments and demonstrate the best mode of practice. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will appreciate the application of these concepts, which are not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

It will be understood that while terms such as "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish different elements. For example, a first element may be referred to as a second element without departing from the scope of this disclosure, and similarly, a second element may be referred to as a first element. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It should be understood that when an element, such as a layer, region, or substrate, is referred to as "on another element" or "extending" to another element, it may be directly on or directly extended to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly on another element" or "directly extending to another element," no intermediate elements are present. Similarly, it should be understood that when an element, such as a layer, region, or substrate, is referred to as "above another element" or "extending above another element," it may be directly above or directly extended above the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly above another element" or "extending directly above another element," no intermediate elements are present. It will also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements are present.

For example, relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the figures. It should be understood that these terms, and those discussed above, are intended to include different orientations of the device other than those depicted in the figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms. It should also be understood that, when used herein, the terms “comprises,” “comprising,” “includes,” and/or “including” specify the presence of the said feature, integer, step, operation, element, and/or component, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that the terms used herein shall be interpreted in a meaning consistent with that in the context of this specification and relevant precedents, and shall not be construed in an idealized or overly formal sense unless expressly defined herein.

Embodiments of this disclosure relate to a fast-switching power management integrated circuit (PMIC). The PMIC is configured to provide an average power tracking (APT) voltage to a power amplifier circuit for amplifying radio frequency (RF) signals modulated over multiple time intervals. Herein, the PMIC is configured to increase or decrease the APT voltage from a current voltage level in the current time interval to a future voltage level in the upcoming time interval with very short switching intervals (e.g., <20 nanoseconds). As the APT voltage transitions from the current voltage level to the future voltage level, the PMIC activates the voltage amplifier in a timely manner to help ensure proper operation of the power amplifier circuit (e.g., maintaining the APT voltage at the current level and reducing fluctuations in the APT voltage). Therefore, the PMIC can switch the APT voltage frequently and rapidly as the inrush current decreases.

In this regard, Figure 2 is a schematic diagram of an exemplary PMIC 24 disposed in wireless communication circuit 25 and configured to support fast APT voltage switching according to embodiments of the present disclosure. PMIC 24 includes a voltage output 26 that outputs the APT voltage _VCC to a power amplifier circuit 28 in wireless communication circuit 25. Power amplifier circuit 28 is configured to amplify RF signal 30 based on the APT voltage _VCC. The RF signal 30, which may be generated by transceiver circuit 31 in wireless communication circuit 25, is modulated by a plurality of modulation units, each modulation unit being further divided into a plurality of time intervals. In the context of this disclosure, a modulation unit is equivalent to a time division duplex (TDD) time slot or a micro-time slot, and the time interval within each modulation unit is equivalent to an orthogonal frequency division multiplexing (OFDM) symbol, such as OFDM symbols 20(1)-20(N) in Figure 1. In this regard, each of the time intervals can be modulated to carry a data payload (referred to herein as a “data symbol”) and a reference signal (referred to herein as a “reference symbol”), such as a demodulated reference signal (DMRS), a probe reference signal (SRS), etc.

Given that the power amplifier circuit 28 needs to amplify the data symbols and reference symbols to different power levels, the PMIC 24 may need to adjust (increase or decrease) the APT voltage _VCC based on each symbol. Furthermore, as previously described in Figure 1, the PMIC 24 must perform the APT voltage _VCC within the corresponding cyclic prefix (CP) of each of the OFDM symbols 20(1)-20(N).

PMIC 24 includes a voltage amplifier 32 (denoted as "VA") and an offset circuit 34. The voltage amplifier 32 is coupled to an input 36 of the offset circuit 34, and the offset circuit 34 is coupled to a voltage output 26. In the context of this disclosure, it is assumed that the power amplifier circuit 28 has a much higher bandwidth than the offset circuit 34. As described in detail below, the offset circuit 34 is configured to change (increase or _decrease ) the APT voltage _VCC from the current voltage level (denoted as " _{VCC( N-1} )") to a future voltage level (denoted as " _VCC(N) ") between a pair of adjacent time intervals (denoted as "SN-1" and "SN" in Figures 3-5). For distinction, the time intervals _SN-1 and _SN are also referred to as the "current time interval" and the "upcoming time interval," respectively.

More specifically, offset circuit 34 causes the APT voltage _VCC to change from the current voltage level VCC _(N-1 ) in the current time interval SN _-1 to the future voltage level VCC(N) in the upcoming time interval _SN during the transition interval _{(denoted as "TP" in Figures 3 to 5)} . Depending on whether the APT voltage _{VCC increases} or decreases from the current time interval _SN-1 to the upcoming time interval SN, the transition interval TP can be located in the current time interval SN _-1 or in the upcoming time interval _SN to ensure that the APT voltage _VCC can reach the future voltage level _VCC(N) through the CP of the upcoming time interval _SN .

As further shown in Figures 3 to 5, although the APT voltage _VCC transitions from the current voltage level _VCC(N-1) to the future voltage level VCC _(N) during the transition interval TP, the voltage amplifier 32 is activated at the beginning of the transition interval TP (denoted as " _T1 ") and deactivated at the end of the transition interval TP (denoted as " _T2 ") to ensure proper operation of the power amplifier circuit 28. According to an embodiment of this disclosure, the voltage amplifier 32 provides a modulation voltage _VAMP at input 36 of the offset circuit 34. In a non-limiting example, the voltage amplifier 32 is configured to generate the modulation voltage _VAMP based on the amplifier target voltage _VTTGT-AMP and one of a lower supply voltage _VSUPL and a higher supply voltage _VSUPH ( _VSUPH > _VSUPL ).

As illustrated in the detailed examples in Figures 3 to 5, the amplifier target voltage V _{_TGT-AMP} is determined in such a way that the voltage amplifier 32 can maintain the modulation voltage V _{_AMP} at or above the headroom voltage (represented as "V _{_NHEAD} " in Figures 3 to 5) at the end T_₂ of the transition interval TP, which is greater than 0V. Therefore, the voltage amplifier 32 can maintain the APT voltage V_{_CC} at the current voltage level V_{_CC(N-1)} and suppress fluctuations in the APT voltage V_{_CC} during the transition interval TP, thereby ensuring the proper operation of the power amplifier circuit 28 during the transition interval TP.

According to embodiments of this disclosure, PMIC 24 may include control circuitry 38, which may be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). In one aspect, control circuitry 38 may be configured to determine whether the transition interval TP should be within the current time interval _SN-1 or within the upcoming time interval SN based on the difference _ΔVCC ( _ΔVCC = _VCC(N-1) - _{VCC(N) )} between the current voltage level VCC( _N-1) and the future voltage level VCC( _N ). It is understood that the difference _ΔVCC will be positive when the current voltage level VCC _(N-1) is higher than the future voltage level VCC _(N ), or negative when the current voltage level VCC( _N-1) is lower than the future voltage level _{VCC (N)} . In a non-limiting example, control circuitry 38 may receive from transceiver circuitry 31 a modulated target voltage _VTGT indicating the future voltage level VCC _(N) in the upcoming time interval _SN . Therefore, control circuit 38 can (e.g., via control signal 40) control offset circuit 34 to transition from the current voltage level _VCC(N-1) to the future voltage level _VCC(N) during transition interval TP.

In another embodiment, control circuit 38 can also be configured to determine the amplifier target voltage _VTGT-AMP based on the determined differential _ΔVCC . In a non-limiting example, when the future voltage level VCC _(N) is higher than the current voltage level VCC _(N-1) , as shown in Figure 3, the amplifier target voltage _VTGT-AMP is equal to the sum of the future voltage level _VCC(N) and the marked voltage (denoted as " _VDIFF "), as shown in equation (Equation 1) below. In another non-limiting example, when the future voltage level _VCC(N) is lower than the current voltage level VCC _(N-1) , as shown in Figures 4 and 5, the amplifier target voltage _VTGT-AMP is equal to the sum of the current voltage level VCC _(N-1) and the marked voltage _VDIFF , as shown in equation (Equation 2) below.

V _{_TGT-AMP} = V _{_CC(N)} + V _{_DIFF} (Equation 1)

V _{_TGT-AMP} = V _{_CC(N-1)} + V _{_DIFF} (Equation 2)

In equations (Equations 1 and 2), the marker voltage _VDIFF can have different values depending on how the APT voltage _VCC changes from the current time interval SN _-1 to the upcoming time interval _SN . In this regard, by changing the amplifier target voltage _VTGT-AMP , and more specifically, by changing the marker voltage _VDIFF , the control circuit 38 can cause the voltage amplifier 32 to generate a modulation voltage _VAMP at an appropriate level during the transition interval TP to maintain the normal operation of the power amplifier circuit 28.

In another aspect, control circuit 38 may be further configured to activate voltage amplifier 32 at the beginning _T1 of transition interval TP and deactivate voltage amplifier 32 at the end _T2 of transition interval TP. In a non-limiting example, control circuit 38 may deactivate voltage amplifier 32 in response to receiving a lower supply voltage _VSUPL or activate it in response to receiving a higher supply voltage _VSUPH . By controlling offset circuit 34 to change APT voltage _VCC and activating/deactivating voltage amplifier 32 in a timely manner to ensure proper operation of power amplifier circuit 28 during transition interval TP, PMIC 24 can effectively switch APT voltage _VCC under increasingly stringent switching time requirements (e.g., <20 ns).

PMIC 24 also includes a multi-stage charge pump (MCP) 42. MCP 42 can be a DC-to-DC buck-boost converter configured to generate a low-frequency voltage _VDC (e.g., DC voltage) based on the battery voltage _VBAT . Specifically, MCP 42 can operate in buck mode to generate a low-frequency voltage _VDC at 0× _VBAT or 1× _VBAT , or in boost mode to generate a low-frequency voltage _VDC at 2× _VBAT . MCP 42 can be configured to switch between buck and boost modes based on specific duty cycles (e.g., 20%@0× _VBAT , 30%@1× _VBAT , and 50%@2× _VBAT ). In this way, MCP 42 can be controlled to generate a low-frequency voltage _VDC at a desired level.

In an embodiment, control circuit 38 may be further configured to generate an offset target voltage _VTGT-OFF based on the modulation target voltage _VTGT . The offset target voltage _VTGT-OFF may indicate the future voltage level _VCC(N) of the APT voltage _VCC . Therefore, MCP 42 may determine and operate based on the corresponding duty cycle to generate a low-frequency voltage _VDC at the desired level indicated by the offset target voltage _VTGT-OFF .

PMIC 24 also includes a power inductor _LP . The power inductor _LP is coupled between MCP 42 and voltage output 26 and is configured to induce a low-frequency current _IDC (e.g., DC current) based on a low-frequency voltage _VDC . It is understood that the induced low-frequency current _IDC is a function of the low-frequency voltage _VDC and the inductance of the power inductor _LP . Therefore, control circuitry 38 can further change the low-frequency current _IDC based on an offset target voltage _VTGT-OFF . In an embodiment, MCP 42 can receive feedback from the APT voltage _VCC .

In this document, the offset circuit 34 includes an offset capacitor C _OFF and a bypass switch S _BYP . The offset capacitor C _OFF is coupled between the input 36 and the voltage output 26, and the bypass switch S _BYP is coupled between the input 36 and ground (GND).

In one operating scenario, the APT voltage _VCC is set to increase from the current voltage level VCC _(N-1) in the current time interval SN _-1 to the future voltage level VCC( _{N ) in the upcoming time interval SN} ( _VCC(N-1) < _VCC(N) ). In this regard, control circuit 38 sets the offset target voltage _VTGT-OFF to the future voltage level _VCC(N) of the APT voltage _VCC , so that a low-frequency current _ICD is generated as desired, thereby charging the offset capacitor _COFF to the future voltage level _VCC(N) .

Control circuit 38 disconnects bypass switch S _BYP and activates voltage amplifier 32 at the start of transition interval TP to generate amplifier target voltage V _{_TGT-AMP} at a level higher than the future voltage level V _{_CC(N)} , allowing current I _{_TRAN} to flow from MCP 42 through offset capacitor C _{_OFF} and converge in voltage amplifier 32. In a non-limiting example, PMIC 24 may include auxiliary circuit 44 that can provide additional current to help maintain modulation voltage V_{_AMP} in the presence of current I _{_TRAN}. As a result, current I _{_TRAN} will gradually charge offset capacitor C_{_OFF} to the future voltage level V _{_CC(N)} during transition interval TP. When offset capacitor C _{_OFF} is charged to the future voltage level V _{_CC(N)} at the end of transition interval TP, control circuit 38 deactivates voltage amplifier 32 and closes bypass switch S _BYP . Thereafter, offset capacitor C _{_OFF} and MCP 42 will maintain APT voltage V_{_CC} at the future voltage level V_{_CC(N)} for the remainder of the upcoming time interval _SN .

The above operating scenario can be graphically illustrated in Figure 3. Figure 3 is a timing diagram providing an exemplary illustration of how the PMIC 24 of Figure 2 operates to increase the APT voltage _VCC under the above operating scenario. The components in Figure 2 are mentioned in Figure 3 and will not be described again herein.

As shown in the figure, the transition interval TP falls entirely within the upcoming time interval _SN , where the start _T1 of the transition interval TP aligns with the boundary _T0 between the current time interval SN _-1 and the upcoming time interval _SN (also known as the start time of CP in the upcoming time interval _SN ), and the end _T2 of the transition interval TP occurs after time _T3 (also known as the end time of CP in the upcoming time interval _SN ). It is understood that CP is typically much shorter than the transition interval TP. In this paper, the modulation target voltage _VTGT indicates that the APT voltage _VCC will increase from the current voltage level _VCC(N-1) (e.g., 2.3V) in the current time interval _SN-1 to the future voltage level _VCC(N) (e.g., 2.9V) in the upcoming time interval _SN . Therefore, the control circuit 38 determines that the offset target voltage _VTGT-OFF is equal to the future voltage level VCC _(N) .

Regarding the amplifier target voltage _VTGT-AMP , control circuit 38 is configured to set the marker voltage _VDIFF in equation (Equation 1) to be equal to the net voltage _VNHEAD ( _VTGT-AMP = VCC _(N) + _VNHEAD ). At time _T1 , control circuit 38 disconnects the bypass switch S _BYP and activates voltage amplifier 32 (e.g., by coupling the higher supply voltage _VSUPH to voltage amplifier 32). Therefore, voltage amplifier 32 will generate a modulation voltage _VAMP at input 36 according to the amplifier target voltage _VTGT-AMP . In a non-limiting example, with the assistance of auxiliary circuit 44, voltage amplifier 32 can rapidly drive the modulation voltage _VAMP from GND level to a differential _ΔVCC ( _ΔVCC < 0) at time _T3 to help stabilize the APT voltage _VCC during the transition interval TP. Thereafter, voltage amplifier 32 gradually decreases the modulation voltage _VAMP to the net voltage _VNHEAD at time _T2 .

Starting at time _T1 , the offset capacitor _COFF gradually charges to reach the future voltage level VCC _(N) at time _T2 . Therefore, at time _T2 , the control circuit 38 closes the bypass switch S _BYP and deactivates the voltage amplifier 32 to return the modulation voltage _VAMP to the GND level. The APT voltage _VCC, which is equal to the sum of the modulation voltage _VAMP and the offset voltage _VOFF, will stabilize at the future voltage level VCC _(N) at time _T3 . It is worth noting that since the voltage amplifier 32 maintains the modulation voltage _VAMP at or above the net voltage _VNHEAD when the bypass switch S _BYP is switched, the APT voltage _VCC will not drop below the net voltage _VNHEAD , thus ensuring the normal operation of the power amplifier circuit 28.

Returning to Figure 2, in another operating scenario, the APT voltage _VCC is set to decrease from the current voltage level VCC _(N-1) in the current time interval SN _-1 to the future voltage level VCC( _{N )} in the upcoming time interval SN ( _VCC(N-1) > _VCC(N) ). In this regard, control circuit 38 sets the offset target voltage _VTGT-OFF to the future voltage level VCC _(N) of the APT voltage _VCC , so that a low-frequency current _ICD is generated as desired, thereby causing the offset capacitor _COFF to discharge to the future voltage level VCC _(N) .

Control circuit 38 disconnects bypass switch S _BYP and activates voltage amplifier 32 at the start of transition interval TP to generate amplifier target voltage V _{_TGT-AMP} at the current voltage level V _{_CC(N-1)} , allowing current I _{_TRAN} to flow from voltage amplifier 32 through offset capacitor C _{_OFF} and back to MCP 42 and/or power amplifier circuit 28. In a non-limiting example, auxiliary circuit 44 can provide additional current to help maintain modulation voltage V_{_AMP} in the presence of current I _{_TRAN}. As a result, offset capacitor C_{_OFF} will be gradually discharged to future voltage level V _{_CC(N)} during transition interval TP. When offset capacitor C _{_OFF} discharges to future voltage level V _{_CC(N)} at the end of transition interval TP, control circuit 38 deactivates voltage amplifier 32 and closes bypass switch S _BYP . Thereafter, offset capacitor C_{_OFF} and MCP 42 will maintain APT voltage V_{_CC} at future voltage level V _{_CC(N)} for the remainder of the upcoming time interval _SN .

The above operating scenario can be illustrated graphically in Figures 4 and 5. Figure 4 is a timing diagram providing an exemplary illustration of how the PMIC 24 of Figure 2 can operate to reduce the APT voltage _VCC under one possible operating scenario. More specifically, Figure 4 shows the case where the headroom voltage _VNHEAD (e.g., 0.4V) is lower than the difference _ΔVCC (e.g., 0.6V) between the current voltage level _VCC(N-1) and the future voltage level _VCC(N) ( _VNHEAD < _ΔVCC ). The components in Figure 2 are mentioned in Figure 4 and will not be described further herein.

As shown in the figure, the transition interval TP falls entirely within the current time interval SN _-1 , where the start _T1 of the transition interval TP begins before the boundary _T0 between the current time interval SN _-1 and the upcoming time interval _SN , and the end _T2 of the transition interval TP is aligned with the boundary _T0 (also known as the start time of CP in the upcoming time interval _SN ). It is understood that CP is typically much shorter than the transition interval TP. In this paper, the modulation target voltage _VTGT indicates that the APT voltage _VCC will decrease from the current voltage level _{VCC(N-1) (} e.g., 2.9V) in the current time interval SN-1 to the future voltage level _VCC(N) (e.g., 2.3V) in the upcoming time interval _SN . Therefore, the control circuit 38 determines that the offset target voltage _VTGT-OFF is equal to the future voltage level _VCC(N) .

Regarding the amplifier target voltage _VTGT-AMP , control circuit 38 is configured to set the marker voltage _VDIFF in equation (Equation 2) to 0V ( _VTGT-AMP = _VCC(N-1) + 0). At time _T1 , control circuit 38 disconnects the bypass switch S _BYP and activates voltage amplifier 32 (e.g., by coupling the higher supply voltage _VSUPH to voltage amplifier 32). Therefore, voltage amplifier 32 will generate a modulation voltage _VAMP at input 36 according to the amplifier target voltage _VTGT-AMP . In a non-limiting example, with the assistance of auxiliary circuit 44, voltage amplifier 32 can immediately drive the modulation voltage _VAMP from GND level to the headroom voltage _VNHEAD at time _T1 . Thereafter, voltage amplifier 32 will continue to drive the modulation voltage _VAMP to the voltage differential _ΔVCC at time _T2 .

Starting at time _T1 , the offset capacitor _COFF gradually discharges to reach the future voltage level VCC _(N) at time _T2 . Therefore, at time _T2 , control circuit 38 closes the bypass switch S _BYP and deactivates voltage amplifier 32, causing the modulation voltage _VAMP to return to GND level at time _T3 . The APT voltage _VCC , equal to the sum of the modulation voltage _VAMP and the offset voltage _VOFF, will stabilize at the future voltage level VCC _(N) at time _T3 . It is noteworthy that because voltage amplifier 32 maintains the modulation voltage _VAMP at or above the net voltage _VNHEAD when the bypass switch S _BYP is switched, the APT voltage _VCC will not drop below the net voltage _VNHEAD , thus ensuring the normal operation of power amplifier circuit 28.

Figure 5 is a timing diagram providing an exemplary illustration of how the PMIC 24 of Figure 2 can operate to reduce the APT voltage _VCC under another possible operating scenario described above. More specifically, Figure 5 shows the case where the headroom voltage _VNHEAD (e.g., 0.4V) is higher than or equal to the difference _ΔVCC (e.g., 0.1V) between the current voltage level VCC( _N-1) and the future voltage level VCC _(N ) ( _VNHEAD ≥ _ΔVCC ). The components in Figure 2 are mentioned in Figure 5 and will not be described further herein.

As shown in the figure, the transition interval TP falls entirely within the current time interval SN _-1 , where the start _T1 of the transition interval TP begins before the boundary _T0 between the current time interval SN _-1 and the upcoming time interval _SN , and the end _T2 of the transition interval TP aligns with the boundary _T0 (also known as the start time of CP in the upcoming time interval _SN ). It is understood that CP is typically much shorter than the transition interval TP. In this paper, the modulation target voltage _VTGT indicates that the APT voltage _VCC will decrease from the current voltage level VCC(N _{-1 ) (e.g., 2.9V) in the current time interval SN-1} to the future voltage level _VCC(N) (e.g., 2.8V) in the upcoming time interval _SN . Therefore, the control circuit 38 determines that the offset target voltage _VTGT-OFF is equal to the future voltage level _VCC(N) .

Regarding the amplifier target voltage _VTGT-AMP , control circuit 38 is configured to set the marker voltage _VDIFF in equation (Equation 2) to be equal to the net voltage _VNHEAD minus the difference _ΔVCC between the current voltage level _VCC(N-1) and the future voltage level VCC _(N) ( _VTGT-AMP = VCC _(N-1) + _VNHEAD - _ΔVCC ). At time _T1 , control circuit 38 disconnects the bypass switch S _BYP and activates voltage amplifier 32 (e.g., by coupling the higher supply voltage _VSUPH to voltage amplifier 32). Therefore, voltage amplifier 32 will generate a modulation voltage _VAMP at input 36 according to the amplifier target voltage _VTGT-AMP . In a non-limiting example, voltage amplifier 32, with the assistance of auxiliary circuit 44, can immediately drive the modulation voltage _VAMP from the GND level to the differential _ΔVCC at time _T1 . Thereafter, voltage amplifier 32 will continue to drive the modulation voltage _VAMP to the net voltage _VNHEAD at time _T2 .

Starting at time _T1 , the offset capacitor _COFF gradually discharges to reach the future voltage level VCC _(N) at time _T2 . Therefore, at time _T2 , control circuit 38 closes the bypass switch S _BYP and deactivates voltage amplifier 32, causing the modulation voltage _VAMP to return to GND level at time _T3 . The APT voltage _VCC , equal to the sum of the modulation voltage _VAMP and the offset voltage _VOFF, will stabilize at the future voltage level VCC _(N) at time _T3 . It is noteworthy that because voltage amplifier 32 maintains the modulation voltage _VAMP at or above the net voltage _VNHEAD when the bypass switch S _BYP is switched, the APT voltage _VCC will not drop below the net voltage _VNHEAD , thus ensuring the normal operation of power amplifier circuit 28.

Referring back to Figure 2, in the example described above, control circuitry 38 is configured to receive the modulated target voltage _VTGT in each time interval (i.e., each OFDM symbol). In other words, transceiver circuitry 31 must transmit the future voltage level _VCC(N) during the current time interval SN _-1 or even before in the upcoming time interval _SN . As previously described in Figure 1, in a time division duplex (TDD) system, multiple time intervals (also known as OFDM symbols) can be included in modulation units (also known as TDD time slots or mini-time slots). Thus, control circuitry 38 can receive the modulated target voltage _VTGT in each modulation unit (also known as a TDD time slot or mini-time slot).

In this regard, PMIC 24 can be pre-configured to include multiple power profiles 46(1)-46(N). In a non-limiting example, the power profiles 46(1)-46(N) can be organized into a profile lookup table (LUT) 48 and stored in memory circuitry 50. The power profiles 46(1)-46(N) can be stored in memory circuitry 50 by transceiver circuitry 31 via, for example, an RF front-end (RFFE) interface (not shown).

Figures 6A and 6B are block diagrams providing exemplary illustrations of power profiles 46(1)-46(N), which can be used by PMIC 24 of Figure 2 to achieve fast switching of the APT voltage _VCC . In this document, each of the power profiles 46(1)-46(N) corresponds to a TDD time slot.

Figure 6A shows an exemplary power profile 46A in power profiles 46(1)-46(N). As shown, power profile 46A can be determined to indicate the future voltage levels of one or more data symbols and one or more SRS symbols.

Figure 6B shows an exemplary power profile 46B in power profiles 46(1)-46(N). As shown, power profile 46B can be determined to indicate the future voltage levels of one or more data symbols and one or more DMRS symbols.

Referring back to Figure 2, in this embodiment, transceiver circuitry 31 may transmit profile instruction 52 to indicate a selected power profile among power profiles 46(1)-46(N) to be used for an upcoming modulation unit (e.g., TDD slot) during or before the current modulation unit (e.g., TDD slot). Therefore, control circuitry 38 may retrieve the selected power profile from profile LUT 48 based on the received profile instruction 52.

The PMIC 24 in Figure 2 can be incorporated into a user component to enable fast voltage switching. Figure 7 is a schematic diagram of an exemplary user component 100 that can provide the PMIC of Figure 2.

In this document, user element 100 can be any type of user element, such as a mobile terminal, smartwatch, tablet computer, computer, navigation device, access point, and similar wireless communication devices supporting wireless communication, such as cellular, wireless local area network (WLAN), Bluetooth, and near field communication. User element 100 will typically include a control system 102, a baseband processor 104, a transmitting circuit system 106, a receiving circuit system 108, an antenna switching circuit system 110, multiple antennas 112, and a user interface circuit system 114. In a non-limiting example, for instance, the control system 102 may be a field-programmable gate array (FPGA). In this case, the control system 102 may include at least a microprocessor, embedded memory circuitry, and a communication bus interface. The receiving circuit system 108 receives radio frequency signals from one or more base stations via antennas 112 and through the antenna switching circuit system 110. Low-noise amplifiers and filters cooperate to amplify and cancel broadband interference from the received signals for processing. Then, a down-conversion and digitization circuit (not shown) down-converts the filtered received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter (ADC).

The baseband processor 104 processes the digitized received signal to extract the information or data bits transmitted in the received signal. This processing typically includes demodulation, decoding, and error correction operations, which will be discussed in more detail below. The baseband processor 104 is typically implemented in one or more digital signal processors (DSPs) and application-specific integrated circuits (ASICs).

For transmission, baseband processor 104 receives digitized data representing voice, data, or control information from control system 102, and encodes the digitized data for transmission. The encoded data is output to transmission circuitry 106, where a digital-to-analog converter (DAC) converts the digitally encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal at the desired transmission frequency or multiple frequencies. A power amplifier amplifies the modulated carrier signal to a level suitable for transmission and delivers the modulated carrier signal to antenna 112 via antenna switching circuitry 110. Multiple antennas 112 and replicated transmit circuitry 106 and receive circuitry 108 can provide spatial diversity. Those skilled in the art will understand the modulation and processing details.

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of this disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the claims below.

Claims (20)

1. A power management integrated circuit (PMIC) (24), comprising: Voltage output (26) outputs an average power tracking (APT) voltage ( _VCC ) to a power amplifier circuit (28) for amplifying a radio frequency (RF) signal (30) modulated in a plurality of modulation units, each of which includes a plurality of time intervals (SN _-1 , _SN ). An offset circuit (34), coupled to the voltage output (26), and configured to change the APT voltage ( _VCC ) during a transition interval (TP) from the current voltage level (VCC(N _-1 )) in the current time interval ( _SN-1 ) of the plurality of time intervals to the future voltage level ( _VCC(N) ) in the upcoming time interval ( _SN ) of the plurality of time intervals, the transition interval falling within one of the current time interval (SN _-1 ) and the upcoming time interval ( _SN ); and A voltage amplifier (32) coupled to the input (36) of the offset circuit (34) is activated at the beginning of the transition interval (TP) and deactivated at the end of the transition interval (TP) to generate the modulation voltage ( _VAMP ) at the input (36) of the offset circuit (34) based on an amplifier target voltage ( _VTTGT-AMP ) determined to make the modulation voltage (VAMP) higher than or equal to the headroom voltage ( _VHEAD ) at the end of the transition interval ( _TP ). 2. The PMIC of claim 1 further includes a control circuit, the control circuit being configured to: The start and end of the transition interval are determined based on the current voltage level and the future voltage level of the APT voltage; The amplifier target voltage is determined to be equal to the sum of the future voltage level and the marked voltage; The voltage amplifier is activated at the beginning of the transition interval; and The voltage amplifier is deactivated at the end of the transition interval. 3. The PMIC according to claim 2, wherein the control circuit is further configured to: Determine that the future voltage level of the APT voltage is higher than the current voltage level of the APT voltage; The start of the transition interval is determined at the boundary between the current time interval and the upcoming time interval; The end of the transition interval is determined to be later than the boundary between the current time interval and the upcoming time interval; Determine that the marked voltage is equal to the headroom voltage; and The offset circuit increases the APT voltage from the current voltage level to the future voltage level before the transition interval ends. 4. The PMIC according to claim 2, wherein the control circuit is further configured to: It is determined that the future voltage level of the APT voltage is lower than the current voltage level of the APT voltage, and the headroom voltage is lower than the difference between the current voltage level and the future voltage level; The start of the transition interval is determined to be earlier than the boundary between the current time interval and the upcoming time interval; The end of the transition interval is determined at the boundary between the current time interval and the upcoming time interval; Determine that the marked voltage is equal to zero; and The offset circuit reduces the APT voltage from the current voltage level to the future voltage level before the transition interval ends. 5. The PMIC according to claim 2, wherein the control circuit is further configured to: The future voltage level of the APT voltage is determined to be lower than the current voltage level of the APT voltage, and the headroom voltage is greater than or equal to the difference between the current voltage level and the future voltage level; The start of the transition interval is determined to be earlier than the boundary between the current time interval and the upcoming time interval; The end of the transition interval is determined at the boundary between the current time interval and the upcoming time interval; The marked voltage is determined to be equal to the headroom voltage minus the difference between the current voltage level and the future voltage level; and The offset circuit reduces the APT voltage from the current voltage level to the future voltage level before the transition interval ends. 6. The PMIC of claim 2, wherein the control circuitry is further configured to receive, during the current time interval, an indication of the future voltage level of the APT voltage in the upcoming time interval. 7. The PMIC of claim 2, wherein the control circuitry is further configured to receive a profile indication during the current modulation unit of the plurality of modulation units, the profile indication indicating a selected power profile of an upcoming modulation unit of the plurality of modulation units, the selected power profile including a plurality of future voltage levels, each of the plurality of future voltage levels corresponding to a corresponding time interval of the plurality of time intervals in the upcoming modulation unit of the plurality of modulation units. 8. The PMIC of claim 7 further includes a memory circuit configured to store a profile lookup table (LUT) (48) including a plurality of predetermined power profiles (46(1)-46(N)), wherein the control circuit is further configured to retrieve a selected power profile from the profile LUT based on a received instruction. 9. The PMIC according to claim 1, wherein: Each of the plurality of modulation units corresponds to a time-division duplex (TDD) time slot; and The plurality of time intervals in each of the plurality of modulation units correspond to Orthogonal Frequency Division Multiplexing (OFDM) symbols. 10. A wireless communication circuit (25) comprising a power management integrated circuit (PMIC) (24), the power management integrated circuit comprising: Voltage output (26) outputs an average power tracking APT voltage ( _VCC ) for amplifying a radio frequency (RF) signal (30) modulated in a plurality of modulation units, each of which includes a plurality of time intervals (SN _-1 , _SN ). An offset circuit (34), coupled to the voltage output (26), and configured to change the APT voltage ( _VCC ) during a transition interval (TP) from the current voltage level (VCC(N _-1 )) in the current time interval ( _SN-1 ) of the plurality of time intervals to the future voltage level ( _VCC(N) ) in the upcoming time interval ( _SN ) of the plurality of time intervals, the transition interval falling within one of the current time interval (SN _-1 ) and the upcoming time interval ( _SN ); and A voltage amplifier (32) coupled to the input (36) of the offset circuit (34) is activated at the beginning of the transition interval (TP) and deactivated at the end of the transition interval (TP) to generate the modulation voltage ( _VAMP ) at the input (36) of the offset circuit (34) based on an amplifier target voltage ( _VTTGT-AMP ) determined to make the modulation voltage (VAMP) higher than or equal to the headroom voltage ( _VHEAD ) at the end of the transition interval ( _TP ). 11. The wireless communication circuit of claim 10, wherein the PMIC further comprises a control circuit, the control circuit being configured to: The start and end of the transition interval are determined based on the current voltage level and the future voltage level of the APT voltage; The amplifier target voltage is determined to be equal to the sum of the future voltage level and the marked voltage; The voltage amplifier is activated at the beginning of the transition interval; and The voltage amplifier is deactivated at the end of the transition interval. 12. The wireless communication circuit according to claim 11, wherein the control circuit is further configured to: Determine that the future voltage level of the APT voltage is higher than the current voltage level of the APT voltage; The start of the transition interval is determined at the boundary between the current time interval and the upcoming time interval; The end of the transition interval is determined to be later than the boundary between the current time interval and the upcoming time interval; Determine that the marked voltage is equal to the headroom voltage; and The offset circuit increases the APT voltage from the current voltage level to the future voltage level before the transition interval ends. 13. The wireless communication circuit according to claim 11, wherein the control circuit is further configured to: It is determined that the future voltage level of the APT voltage is lower than the current voltage level of the APT voltage, and the headroom voltage is lower than the difference between the current voltage level and the future voltage level; The start of the transition interval is determined to be earlier than the boundary between the current time interval and the upcoming time interval; The end of the transition interval is determined at the boundary between the current time interval and the upcoming time interval; Determine that the marked voltage is equal to zero; and The offset circuit reduces the APT voltage from the current voltage level to the future voltage level before the transition interval ends. 14. The wireless communication circuit according to claim 11, wherein the control circuit is further configured to: The future voltage level of the APT voltage is determined to be lower than the current voltage level of the APT voltage, and the headroom voltage is greater than or equal to the difference between the current voltage level and the future voltage level; The start of the transition interval is determined to be earlier than the boundary between the current time interval and the upcoming time interval; The end of the transition interval is determined at the boundary between the current time interval and the upcoming time interval; The marked voltage is determined to be equal to the headroom voltage minus the difference between the current voltage level and the future voltage level; and The offset circuit reduces the APT voltage from the current voltage level to the future voltage level before the transition interval ends. 15. The wireless communication circuit of claim 11, wherein the control circuit is further configured to receive, during the current time interval, an indication of the future voltage level of the APT voltage in the upcoming time interval. 16. The wireless communication circuit of claim 11, wherein the control circuit is further configured to receive a profile indication during the current modulation unit of the plurality of modulation units, the profile indication indicating a selected power profile of an upcoming modulation unit of the plurality of modulation units, the selected power profile including a plurality of future voltage levels, each of the plurality of future voltage levels corresponding to a corresponding time interval of the plurality of time intervals in the upcoming modulation unit of the plurality of modulation units. 17. The wireless communication circuit of claim 16, wherein the PMIC further comprises a memory circuit configured to store a profile lookup table (LUT) (48) comprising a plurality of predetermined power profiles (46(1)-46(N)), wherein the control circuit is further configured to retrieve a selected power profile from the profile LUT based on a received instruction. 18. The wireless communication circuit according to claim 10, wherein: Each of the plurality of modulation units corresponds to a time-division duplex (TDD) time slot; and The plurality of time intervals in each of the plurality of modulation units correspond to Orthogonal Frequency Division Multiplexing (OFDM) symbols. 19. The wireless communication circuit of claim 10, further comprising a transceiver circuit (31), the transceiver circuit being configured to: The RF signal is generated and modulated in the plurality of modulation units, each of the plurality of modulation units including the plurality of time intervals; and The PMIC is provided with a modulated target voltage to indicate the future voltage level in the upcoming time interval among the plurality of time intervals. 20. The wireless communication circuit of claim 10 further includes a power amplifier circuit (28) configured to amplify the RF signal based on the APT voltage in each of the plurality of time intervals.