WO2023013101A1 - Oscillation circuit and pll circuit - Google Patents

Oscillation circuit and pll circuit Download PDF

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Publication number
WO2023013101A1
WO2023013101A1 PCT/JP2022/003574 JP2022003574W WO2023013101A1 WO 2023013101 A1 WO2023013101 A1 WO 2023013101A1 JP 2022003574 W JP2022003574 W JP 2022003574W WO 2023013101 A1 WO2023013101 A1 WO 2023013101A1
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Prior art keywords
circuit
oscillator
voltage
generation circuit
oscillation frequency
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PCT/JP2022/003574
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French (fr)
Japanese (ja)
Inventor
義暁 森
徹哉 藤原
諒 井上
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ソニーセミコンダクタソリューションズ株式会社
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Priority to JP2023539603A priority Critical patent/JPWO2023013101A1/ja
Publication of WO2023013101A1 publication Critical patent/WO2023013101A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/354—Astable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

Definitions

  • This technology relates to PLL (Phase Locked Loop) circuits. More specifically, the present invention relates to a technique for stabilizing the oscillation frequency of a PLL circuit and its oscillation circuit.
  • PLL Phase Locked Loop
  • a PLL circuit is used to generate an oscillation signal such as a system clock within a chip.
  • This PLL circuit requires a Voltage Controlled Oscillator (VCO) or a Digitally Controlled Oscillator (DCO) as the oscillator core for generating an oscillation signal according to the phase difference information with respect to the reference clock.
  • VCO Voltage Controlled Oscillator
  • DCO Digitally Controlled Oscillator
  • the output oscillation frequency is controlled by controlling the oscillator current flowing through these oscillator cores.
  • the PLL cannot respond to a fluctuation component at a frequency higher than the band of the PLL circuit, which causes phase shift and jitter in the PLL circuit.
  • the reference voltage and the power supply voltage are compared using a comparator, and correction is performed by digitally controlling the mirror ratio of the current mirror.
  • digital correction causes quantization noise, which makes it difficult to correct for fluctuations in high bands. .
  • This technology was created in view of such circumstances, and aims to suppress fluctuations in the output oscillation frequency of a PLL circuit.
  • a first aspect of the technology is to provide an oscillator that oscillates at a predetermined oscillation frequency, and an oscillator connected to at least one of a power supply terminal and a ground terminal of the oscillator.
  • a correction current generation circuit that supplies a correction current corresponding to the above-mentioned connection node, and a bias generation circuit that supplies a bias voltage for the correction current generation circuit to generate the correction current to the correction current generation circuit.
  • an oscillator circuit and a PLL circuit This produces an effect of suppressing fluctuations in the output oscillation frequency of the PLL circuit by generating a correction current corresponding to fluctuations in the power supply voltage based on the bias voltage.
  • the oscillation frequency control circuit is composed of one of a PMOS transistor and an NMOS transistor, and a voltage control circuit in which a voltage for controlling the oscillation frequency is supplied to the gate terminal as the input voltage.
  • the correction current generation circuit may be composed of the other of the PMOS transistor and the NMOS transistor, and the bias voltage may be supplied to the gate terminal of the PMOS transistor and the NMOS transistor.
  • the bias generation circuit may generate the bias voltage for the gate terminal of the correction current generation circuit by a current mirror circuit.
  • the bias generation circuit may include a low-pass filter connected to the gate terminal of the correction current generation circuit.
  • the oscillator may be a ring oscillator in which a plurality of stages of inverters are connected in a ring, and the bias generation circuit may include one stage of inverters as a replica circuit.
  • the bias generation circuit includes a drain conductance detection circuit that detects the drain conductance of the oscillation frequency control circuit, a transconductance detection circuit that detects the transconductance of the correction current generation circuit, and the A calibration circuit may be provided for performing calibration so that the drain conductance of the oscillation frequency control circuit and the transconductance of the correction current generation circuit are equal. This brings about the effect of supplying the bias voltage for generating the correction current with high accuracy.
  • the input voltage may be an analog value or a digital value.
  • the first aspect may further include a digital-to-analog converter that converts the input voltage from a digital signal to an analog signal and supplies the analog signal to the oscillation frequency control circuit.
  • the input voltage is a digital value
  • the oscillation frequency control circuit is composed of one of a PMOS transistor and an NMOS transistor, and the oscillation frequency is applied to the gate terminal as the input voltage.
  • a plurality of sets of circuits in which a voltage-controlled current source supplied with a voltage for control and a first switch are connected in series are connected in parallel, the first switches being controlled by corresponding bit values of the input voltage;
  • the correction current generating circuit is a circuit in which a second switch and a PMOS transistor and an NMOS transistor connected in parallel are connected in parallel, and the bias voltage is supplied to the gate terminal of the PMOS transistor and the NMOS transistor.
  • a plurality of sets may be connected in parallel, and the second switches may be controlled by corresponding bit values of the input voltage.
  • FIG. 3 is a diagram showing a circuit configuration example of the VCO 13 according to specific examples of the current source 120 and the correction current generation circuit 130 according to the first embodiment of the present technology;
  • FIG. 3 is a diagram showing a circuit configuration example of the VCO 13 according to a specific example of the bias generation circuit 140 according to the first embodiment of the present technology;
  • FIG. 7 is a diagram showing a circuit configuration example of a VCO 13 according to a specific example of a bias generation circuit 140 according to a second embodiment of the present technology
  • FIG. 11 is a diagram showing a circuit configuration example of a VCO 13 according to a specific example of a bias generation circuit 140 according to a third embodiment of the present technology
  • FIG. 7 is a diagram showing a circuit configuration example of a VCO 13 according to a specific example of a bias generation circuit 140 according to a second embodiment of the present technology
  • FIG. 11 is a diagram showing a circuit configuration example of a VCO 13 according to a specific example of a bias generation circuit 140 according to a third embodiment of the present technology
  • FIG. 7 is a diagram showing a circuit configuration example of a VCO 13 according to a specific example of
  • FIG. 11 is a diagram showing a circuit configuration example of a VCO 13 according to a specific example of a current source 120 and a correction current generation circuit 130 according to a fourth embodiment of the present technology; It is a figure showing an example of circuit composition of VCO13 in a 5th embodiment of this art. It is a figure which shows the structural example of the digital PLL circuit in 6th Embodiment of this technique. It is a figure which shows the structural example of the basic circuit of DCO23 in 6th Embodiment of this technique. It is a figure showing the 1st example of circuit composition of DCO23 in a 6th embodiment of this art.
  • FIG. 13 is a diagram illustrating a specific example of a first circuit configuration example of a DCO 23 according to a sixth embodiment of the present technology; It is a figure showing the 2nd example of circuit composition of DCO23 in a 6th embodiment of this art.
  • FIG. 16 is a diagram showing a specific example of a second circuit configuration example of the DCO 23 according to the sixth embodiment of the present technology;
  • FIG. 1 is a diagram illustrating a configuration example of an analog PLL circuit according to a first embodiment of the present technology.
  • This analog PLL circuit includes a phase comparator 11, an analog filter 12, a VCO 13, and a frequency divider .
  • the frequency divider 14 performs multiplication setting as a PLL circuit, and divides the frequency of the output signal.
  • the phase comparator 11 compares the phases of the input signal and the output signal divided by the frequency divider 14 and outputs a phase difference voltage corresponding to the phase difference.
  • the analog filter 12 is a low-pass filter that passes the low-frequency range of the phase difference voltage output from the phase comparator 11 and supplies it to the VCO 13 as an analog value input voltage.
  • the VCO 13 is a voltage controlled oscillator that generates a signal with a frequency according to the input voltage from the low-pass filter and outputs an output signal.
  • FIG. 2 is a diagram showing a configuration example of a basic circuit of the VCO 13 according to the embodiment of the present technology.
  • the VCO 13 has an oscillator 110 that oscillates at a predetermined oscillation frequency.
  • the VCO 13 also includes a current source 120 as indicated by a and b in FIG.
  • This current source 120 is a voltage controlled current source (VCCS: Voltage Controlled Current Source) that supplies a current corresponding to an input voltage. That is, the analog input voltage supplied from the analog filter 12 is converted by the current source 120 into a current flowing through the oscillator 110 .
  • the oscillation frequency of oscillator 110 is controlled by this converted current value.
  • This current source 120 may be connected to either the power supply side or ground side of the oscillator 110 .
  • a is an example in which the current source 120 is connected to the ground side of the oscillator 110 .
  • b in the figure is an example in which the current source 120 is connected to the power supply side of the oscillator 110 . That is, a and b in the figure are examples in which the polarities are different from each other.
  • the VCO 13 may include a regulator 150 as shown in c and d in the figure.
  • This regulator 150 is a voltage source that supplies a constant voltage to the oscillator 110 according to the input voltage.
  • the voltage width of the oscillator 110 is controlled to be between the output voltage of the regulator 150 and the power supply voltage.
  • the voltage width of the oscillator 110 is controlled to be between the output voltage of the regulator 150 and the ground potential. In this manner, oscillator 110 operates at an oscillation frequency such that the oscillation amplitude is the voltage width described above. It should be noted that c and d in FIG.
  • FIG. 3 is a diagram showing a circuit configuration example of the oscillator 110 according to the first embodiment of the present technology.
  • An example of the circuit configuration of this oscillator 110 is a ring oscillator in which three stages of inverters each including a PMOS transistor 111 and an NMOS transistor 112 are provided and connected in a ring.
  • the PMOS transistor 111 is connected to the power supply side
  • the NMOS transistor 112 is connected to the ground side.
  • the oscillation frequency can be controlled by using the change in the delay time per stage when the flowing current or amplitude (operating voltage width) is changed.
  • FIG. 4 is a diagram showing a circuit configuration example of the VCO 13 according to the first embodiment of the present technology.
  • the VCO 13 in this first embodiment comprises an oscillator 110 , a current source 120 , a correction current generation circuit 130 and a bias generation circuit 140 .
  • the basic circuit consisting of oscillator 110 and current source 120 is described above.
  • the correction current generation circuit 130 is connected to a connection node between the oscillator 110 and the current source 120, and supplies a correction current to the connection node according to fluctuations in the power supply voltage at the power supply terminal of the oscillator 110. . That is, the correction current generating circuit 130 monitors the power supply voltage fluctuation and generates a correction current using the analog characteristics of the charge injection device in order to correct the fluctuation of the current flowing through the oscillator 110 .
  • the bias generation circuit 140 supplies the correction current generation circuit 130 with a bias voltage for the correction current generation circuit 130 to generate the correction current.
  • FIG. 5 is a diagram showing a circuit configuration example of the VCO 13 according to specific examples of the current source 120 and the correction current generation circuit 130 according to the first embodiment of the present technology.
  • This example shows an example in which an NMOS transistor 121 is provided as the current source 120 and a PMOS transistor 131 is provided as the correction current generation circuit 130 .
  • the NMOS transistor 121 has a source connected to the ground terminal, a drain connected to the oscillator 110 , and a gate connected to the output of the analog filter 12 .
  • the PMOS transistor 131 has a source connected to the power supply terminal, a drain connected to the drain of the NMOS transistor 121 , and a gate connected to the bias generation circuit 140 .
  • the fluctuation of the drain current when the voltage between the gate and the source fluctuates is used as the correction current.
  • the gate potential of the PMOS transistor 131 is fixed, and when the power supply voltage fluctuates, the gate-source voltage of the PMOS transistor 131 is modulated, and a correction current is generated according to the characteristics of the PMOS transistor 131 .
  • the correction current generation circuit 130 is configured by an analog circuit and analog correction is performed using the analog characteristics of the PMOS transistor 131, so that quantization noise does not occur.
  • the correction current can be generated by following even the power supply voltage fluctuation having a high frequency component.
  • the current supplied by the NMOS transistor 121 fluctuates due to the conversion gain gds due to the change in the voltage between the drain and the source of the NMOS transistor 121 .
  • the correction current is generated by the conversion gain gm according to the fluctuation of the voltage between the gate and the source.
  • the transconductance gm is approximately several ten to one hundred times larger than the drain conductance gds. Therefore, the DC current required by the PMOS transistor 131 to generate the AC correction current is about several tenths to one hundredth of the DC current flowing through the NMOS transistor 121, so the problem does not arise. does not occur. Therefore, the noise generated in the correction current generating circuit 130 is sufficiently small, and the pull-in operation of the phase (frequency) of the PLL is not hindered.
  • the bias generation circuit 140 has a role of generating a bias for causing the correction current generated by the PMOS transistor 131 to follow the PVT variation of the current to be corrected; It has the role of fixing the gate potential of the PMOS transistor 131 .
  • FIG. 6 is a diagram showing a circuit configuration example of the VCO 13 according to a specific example of the bias generation circuit 140 according to the first embodiment of the present technology.
  • the bias generation circuit 140 includes a PMOS transistor 141, an NMOS transistor 142, a resistor 148, and a capacitor 149.
  • the drain of the PMOS transistor 141 is connected to the drain of the NMOS transistor 142, the source of the PMOS transistor 141 is connected to the power supply terminal, and the source of the NMOS transistor 142 is connected to the ground terminal.
  • the gate and drain of the PMOS transistor 141 are short-circuited, and the PMOS transistor 141 and the PMOS transistor 131 form a current mirror circuit.
  • the gate of the NMOS transistor 142 is connected to the gate of the NMOS transistor 121 .
  • the NMOS transistor 142 like the NMOS transistor 121, operates as a current source that generates a current corresponding to the gate voltage.
  • a current corresponding to the size ratio of the NMOS transistor 121 and the NMOS transistor 142 is reflected in the PMOS transistor 131 and the PMOS transistor 141 and flows from the PMOS transistor 131 to the NMOS transistor 121 . Therefore, the bias voltage to the gate of the PMOS transistor 131 can be generated so that the correction current generated by the PMOS transistor 131 follows the variation of the current flowing through the NMOS transistor 121 .
  • the PMOS transistor 131 can follow the characteristic variation of the NMOS transistor 121 . That is, the correction current can follow the PVT variation of the current to be corrected.
  • resistor 148 and capacitor 149 form a low-pass filter by an RC filter.
  • capacitor 149 is connected to ground. As a result, this low-pass filter can fix the gate potential of the PMOS transistor 131 above the filter band.
  • the capacitor 149 may have a relatively small capacity, and the band can be formed by the resistor 148.
  • the capacitor 149 can be approximately 1 PF and the resistor 148 can be approximately 1 M ⁇ .
  • the circuit configuration in the first embodiment is a very simple configuration, it is possible to reduce the area by suppressing the addition of elements.
  • FIG. 7 is a diagram illustrating an example of fluctuation characteristics of an output frequency according to an embodiment of the present technology
  • the horizontal axis indicates the fluctuation frequency (Hz) of the power supply voltage
  • the vertical axis indicates the normalized value (1/V) of the frequency fluctuation with respect to the power supply voltage fluctuation.
  • a smaller value on the vertical axis means better performance.
  • a solid line is an example of the characteristics of the circuit of the first embodiment.
  • a dotted line is an example of characteristics when the correction current generation circuit 130 and the bias generation circuit 140 are not provided.
  • the correction band is assumed to be about 100 kHz to 10 MHz, with a performance improvement of about one-tenth at 1 MHz and a performance improvement of about one-fifth at 10 MHz. That is, in the first embodiment, since the correction current is actively supplied, it is possible to realize higher power supply voltage fluctuation resistance (PSRR: Power Supply Rejection Ratio) compared to passive elements.
  • PSRR Power Supply Rejection Ratio
  • the PMOS transistor 131 as the correction current generation circuit 130 for correcting the current of the NMOS transistor 121 of the current source 120, fluctuations in the power supply voltage Correction can be actively performed depending on Further, by determining the bias voltage of the PMOS transistor 131 using the current mirror configuration in the bias generation circuit 140, the correction current can follow the PVT variation of the current of the NMOS transistor 121.
  • FIG. Furthermore, by providing a low-pass filter consisting of resistor 148 and capacitor 149, the gate potential of PMOS transistor 131 can be fixed above the filter band.
  • Second Embodiment> In the first embodiment described above, the current of the PMOS transistor 131 is reflected by the current mirror circuit, but in the second embodiment, the current of the PMOS transistor 131 is reflected using a replica circuit. Since the overall configuration of the analog PLL circuit is the same as that of the first embodiment, detailed description thereof will be omitted.
  • FIG. 8 is a diagram showing a circuit configuration example of the VCO 13 according to a specific example of the bias generation circuit 140 according to the second embodiment of the present technology.
  • a bias generation circuit 140 in the second embodiment includes a PMOS transistor 146 and an NMOS transistor 147 instead of the PMOS transistor 141 in the first embodiment.
  • PMOS transistor 146 and NMOS transistor 147 form an inverter. That is, assuming a ring oscillator as the oscillator 110 as described above, one stage of inverter in the ring oscillator is provided as a replica circuit of the oscillator 110 . Thereby, the bias voltage can be generated so as to reflect the current of the PMOS transistor 131 without using a current mirror circuit.
  • the correction current can follow the PVT variation of the current of the NMOS transistor 121. can be done.
  • the bias generating circuit 140 has a function of performing calibration so that the drain conductance of the NMOS transistor 121 and the transconductance of the PMOS transistor 131 are equal. Since the overall configuration of the analog PLL circuit is the same as that of the first embodiment, detailed description thereof will be omitted.
  • FIG. 9 is a diagram showing a circuit configuration example of the VCO 13 according to a specific example of the bias generation circuit 140 according to the third embodiment of the present technology.
  • the bias generation circuit 140 comprises a gdsn detection circuit 210 and a gmp detection/calibration circuit 230.
  • the gdsn detection circuit 210 is a circuit that detects the drain conductance gdsn of the NMOS transistor 121 .
  • the gmp detection/calibration circuit 230 is a circuit that detects the transconductance gmp of the PMOS transistor 131 and performs calibration so that the drain conductance gdsn and the transconductance gmp become equal.
  • the gdsn sensing circuit 210 comprises NMOS transistors 211, 213, 217, 218, 221 and 222; PMOS transistors 212, 215, 216 and 219;
  • the input voltage from the analog filter 12 is supplied to the gates of the NMOS transistors 211 and 213 .
  • NMOS transistors 217 and 218, 221 and 222, PMOS transistors 212 and 219, 215 and 215 respectively form a current mirror circuit.
  • the gmp detection/calibration circuit 230 comprises NMOS transistors 231 , 233 , 235 , 238 , 241 and 242 , PMOS transistors 232 and 236 , resistors 234 and 243 and operational amplifier 249 .
  • the input voltage from the analog filter 12 is supplied to the gates of the NMOS transistors 233 and 235 (terminal C).
  • Each of NMOS transistors 241 and 242 and PMOS transistors 232 and 131 form a current mirror circuit.
  • the output of operational amplifier 249 is connected to the gates of NMOS transistors 231 and 238 .
  • a terminal A of the operational amplifier 249 is connected to the drain of the NMOS transistor 222
  • a terminal B of the operational amplifier 249 is connected to the drain of the NMOS transistor 242 .
  • the gdsn detection circuit 210 converts the drain-source voltage-current conversion gain (drain conductance gdsn) of the NMOS transistor into the voltage of the terminal A in the following manner. That is, the gdsn current of the NMOS transistor is generated by creating a potential difference using resistor 214 . A current comparator is then used to extract the differential current gdsnIR. A voltage of the terminal A is generated by the resistor 223 from this differential current gdsnIR.
  • the gmp detection/calibration circuit 230 converts the gate-source voltage-current conversion gain (transconductance gmp) of the PMOS transistor into the voltage of the terminal B in a similar manner.
  • the operational amplifier 249 performs calibration so that the voltage of the terminal A and the voltage of the terminal B are equal, and adjusts the capability of the PMOS transistor 131 .
  • the ability of the PMOS transistor 131 is adjusted by detecting the drain conductance gdsn and the transconductance gmp and performing calibration so that both become equal. be able to.
  • FIG. 10 is a diagram showing a circuit configuration example of the VCO 13 according to the fourth embodiment of the present technology.
  • the correction current generation circuit 130 is connected to the connection node between the current source 120 connected to the power supply terminal of the oscillator 110, and the power supply voltage at the power supply terminal of the oscillator 110 fluctuates. A corresponding correction current is supplied to the connection node.
  • the bias generation circuit 140 supplies the correction current generation circuit 130 with a bias voltage for the correction current generation circuit 130 to generate a correction current.
  • FIG. 11 is a diagram showing a circuit configuration example of the VCO 13 according to specific examples of the current source 120 and the correction current generation circuit 130 according to the fourth embodiment of the present technology.
  • circuit configuration example of the fourth embodiment is only reversed in polarity from the circuit configuration example of the above-described first embodiment, and the basic operation is the same, so detailed description is omitted. do.
  • the present technology can be applied to a basic circuit in which the current source 120 is connected to the power supply terminal of the oscillator 110.
  • the current source 120 is connected only to either the ground terminal or the power supply terminal of the oscillator 110, but in the fifth embodiment, the ground terminal of the oscillator 110 or the power supply is connected. Assume that a current source 120 is connected to each side of the terminal. Such a circuit configuration can be employed when trying to generate a waveform close to a sine wave by supplying current from both the power supply side and the ground side of the oscillator 110 so as not to be clipped by the power supply potential or the ground potential. .
  • FIG. 12 is a diagram showing a circuit configuration example of the VCO 13 according to the fifth embodiment of the present technology.
  • the correction current generation circuit 130-1 is connected to the connection node between the current source 120-1 connected to the ground terminal of the oscillator 110, and responds to fluctuations in the power supply voltage.
  • a correction current is supplied to the current source 120-1.
  • the correction current generating circuit 130-2 is connected to the connection node between the current source 120-2 connected to the power supply terminal of the oscillator 110, and generates a correction current according to the fluctuation of the power supply voltage. supply for 2.
  • the present technology can also be applied to a circuit configuration that supplies current from both the power supply side and the ground side of the oscillator 110 .
  • FIG. 13 is a diagram illustrating a configuration example of a digital PLL circuit according to the sixth embodiment of the present technology
  • This digital PLL circuit includes a counter +TDC 21, a digital filter 22, a DCO 23, and a frequency divider 24.
  • the frequency divider 24 performs multiplication setting as a PLL circuit, and divides the frequency of the output signal.
  • the counter +TDC 21 compares the phases of the input signal and the output signal divided by the frequency divider 24 and outputs a phase difference digital signal corresponding to the phase difference. In this counter+TDC 21, the counter measures the integer part of how many times the output frequency becomes the reference input frequency, and the TDC (Time to Digital Converter) measures the decimal part.
  • the digital filter 22 is a low-pass filter that passes the low frequency band of the phase difference digital signal output by the counter +TDC 21 and supplies it to the DCO 23 as an input digital signal.
  • the DCO 23 is a digitally controlled oscillator that generates a signal with a frequency corresponding to the input digital signal from the low-pass filter and outputs an output signal.
  • FIG. 14 is a diagram showing a configuration example of a basic circuit of the DCO 23 according to the sixth embodiment of the present technology.
  • the DCO 23 includes an oscillator 110 that oscillates at a predetermined oscillation frequency.
  • the DCO 23 also includes a DAC 160 as indicated by a and b in FIG.
  • This DAC (Digital Analog Converter) 160 converts the digital value from the digital filter 22 into an analog value and supplies it to the oscillator 110 .
  • the oscillation frequency of oscillator 110 is controlled by this converted analog value.
  • This DAC 160 may be connected to either the power supply side or the ground side of the oscillator 110 .
  • a is an example in which the DAC 160 is connected to the ground side of the oscillator 110 .
  • b in the figure is an example in which the DAC 160 is connected to the power supply side of the oscillator 110 . That is, a and b in the figure are examples in which the polarities are different from each other.
  • FIG. 15 is a diagram showing a first circuit configuration example of the DCO 23 according to the sixth embodiment of the present technology.
  • the first circuit configuration example of the DCO 23 is based on the circuit configuration example (FIG. 6) of the current mirror circuit in the above-described first embodiment, and the DAC 160 is provided in the input section. That is, the digital value from the digital filter 22 is converted into an analog value by the DAC 160, and the internal configuration is configured by an analog circuit as in the first embodiment.
  • FIG. 16 is a diagram showing a specific example of the first circuit configuration example of the DCO 23 according to the sixth embodiment of the present technology.
  • the DAC 160 comprises a current source 161 and multiple NMOS transistors 162 .
  • a switch 163 is provided between the NMOS transistor 162 and the current source 161 respectively.
  • the control input terminals of the plurality of switches 163 are supplied with corresponding bits of the digital value from the digital filter 22 .
  • the reference current from the current source 161 flows through the NMOS transistors 162 whose number corresponds to the supplied digital value, and the corresponding voltage is applied to the gates of the NMOS transistors 142 and 121 .
  • FIG. 17 is a diagram showing a second circuit configuration example of the DCO 23 according to the sixth embodiment of the present technology.
  • a plurality of NMOS transistors 122 are connected as the current source 120 to the ground side of the oscillator 110 .
  • a switch 123 is provided between the NMOS transistor 122 and the oscillator 110 respectively.
  • a plurality of PMOS transistors 132 are connected to both ends of the oscillator 110 as a correction current generation circuit 130 .
  • a switch 133 is provided between each PMOS transistor 132 and the connection node.
  • the control input terminals of the plurality of switches 123 and 133 are supplied with corresponding bits of the digital value from the digital filter 22 . As a result, current flows through the number of PMOS transistors 132 and NMOS transistors 122 corresponding to the supplied digital value.
  • the reference bias voltage is supplied from the reference bias generation circuit 170 to the gates of the NMOS transistors 142 and 121 .
  • FIG. 18 is a diagram showing a specific example of a second circuit configuration example of the DCO 23 according to the sixth embodiment of the present technology.
  • the reference bias generation circuit 170 includes a current source 171 and an NMOS transistor 172.
  • a reference current supplied from the current source 171 flows through the NMOS transistor 172 .
  • the same voltage as the gate potential of NMOS transistor 172 is applied to the gates of NMOS transistors 142 and 122 .
  • the present technology can also have the following configuration. (1) an oscillator that oscillates at a predetermined oscillation frequency; an oscillation frequency control circuit connected to at least one of a power supply terminal and a ground terminal of the oscillator and controlling the oscillation frequency of the oscillator according to an input voltage; a correction current generation circuit connected to a connection node between the oscillator and the oscillation frequency control circuit to supply a correction current to the connection node according to fluctuations in the power supply voltage at the power supply terminal; and a bias generation circuit that supplies a bias voltage for the correction current generation circuit to generate the correction current to the correction current generation circuit.
  • the oscillation frequency control circuit is a voltage controlled current source comprising one of a PMOS transistor and an NMOS transistor and having a gate terminal supplied with a voltage for controlling the oscillation frequency as the input voltage;
  • the bias generation circuit generates the bias voltage for the gate terminal of the correction current generation circuit by a current mirror circuit.
  • the bias generation circuit includes a low-pass filter connected to the gate terminal of the correction current generation circuit.
  • the oscillator is a ring oscillator in which a plurality of stages of inverters are connected in a ring;
  • the bias generation circuit a drain conductance detection circuit for detecting the drain conductance of the oscillation frequency control circuit; a transconductance detection circuit that detects the transconductance of the correction current generation circuit;
  • the oscillator circuit according to any one of (2) to (5) above, further comprising a calibration circuit that performs calibration so that the drain conductance of the oscillation frequency control circuit and the transconductance of the correction current generation circuit are equal.
  • the input voltage is a digital value
  • the oscillation frequency control circuit comprises one of a PMOS transistor and an NMOS transistor, and includes a voltage controlled current source whose gate terminal is supplied with a voltage for controlling the oscillation frequency as the input voltage, and a first switch.
  • the correction current generation circuit is a circuit in which a second switch and a PMOS transistor and an NMOS transistor, which are connected in parallel to each other, are connected in series, and the bias voltage is supplied to the gate terminal of the transistor.
  • the oscillator circuit according to any one of (1) to (6), (8) or (9), wherein a plurality of sets are connected in parallel, and the second switches are controlled by corresponding bit values of the input voltage.
  • the oscillation circuit is an oscillator that oscillates at a predetermined oscillation frequency; an oscillation frequency control circuit connected to at least one of a power supply terminal and a ground terminal of the oscillator and controlling the oscillation frequency of the oscillator according to an input voltage; a correction current generation circuit connected to a connection node between the oscillator and the oscillation frequency control circuit to supply a correction current to the connection node according to fluctuations in the power supply voltage at the power supply terminal;
  • a PLL circuit comprising a bias generation circuit that supplies a bias voltage for the correction current generation circuit to generate the correction current to the correction current generation circuit.
  • phase comparator 11 phase comparator 12 analog filter 13 VCO (Voltage Controlled Oscillator) 14 Frequency divider 21 Counter + TDC (Time to Digital Converter) 22 Digital Filter 23 DCO (Digitally Controlled Oscillator) 24 frequency divider 110 oscillator 111 PMOS transistor 112 NMOS transistor 120 current source 121, 122 NMOS transistor 123 switch 130 correction current generation circuit 131, 132 PMOS transistor 133 switch 140 bias generation circuit 141, 146 PMOS transistors 142, 147 NMOS transistor 148 resistor 149 Capacitor 150 Regulator 160 DAC (Digital Analog Converter) 161 current source 162 NMOS transistor 163 switch 170 reference bias generation circuit 171 current source 172 NMOS transistor 210 gdsn detection circuit 211, 213, 217, 218, 221, 222 NMOS transistor 212, 215, 216, 219 PMOS transistor 214, 223 resistor 230 gmp detection/calibration circuit 231, 233, 235, 238, 241, 24

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The present invention addresses the problem of suppressing fluctuation of an output oscillation frequency in a PLL circuit.　According to the present invention, an oscillator oscillates at a predetermined oscillation frequency. An oscillation frequency control circuit is connected to at least one of a power source terminal and a grounding terminal of the oscillator, and controls the oscillation frequency of the oscillator according to an input voltage. A compensation current generation circuit is connected to a connection node between the oscillator and the oscillation frequency control circuit, and provides the connection node with a compensation current according to a fluctuation of a power source voltage at the power source terminal. A bias generation circuit provides the compensation current generation circuit with a bias voltage for enabling the compensation current generation circuit to generate the compensation current.

Description

発振回路およびＰＬＬ回路Oscillator circuit and PLL circuit
　本技術は、ＰＬＬ（Phase Locked Loop：位相同期ループ）回路に関する。詳しくは、ＰＬＬ回路の発振周波数を安定化させる技術およびその発振回路に関する。 This technology relates to PLL (Phase Locked Loop) circuits. More specifically, the present invention relates to a technique for stabilizing the oscillation frequency of a PLL circuit and its oscillation circuit.
　ＰＬＬ回路は、システムクロック等の発振信号をチップ内で生成するために用いられる。このＰＬＬ回路では、基準クロックとの位相差情報に応じた発振信号を生成するための発振器コアとして、電圧制御発振器（ＶＣＯ：Voltage Controlled Oscillator）やデジタル制御発振器（ＤＣＯ：Digitally Controlled Oscillator）が必要となる。これら発振器コアに流れる発振器電流が制御されることによって、出力発振周波数が制御される。これら発振器コアでは、例えば電源電圧変動の様な外乱によって、流れる電流が変動すると、それに応じて出力発振周波数が変動する。このような出力発振周波数変動の内、ＰＬＬ回路の帯域より高い周波数で変動する成分に対してはＰＬＬが応答することができず、ＰＬＬ回路における位相ズレやジッタの発生原因となる。 A PLL circuit is used to generate an oscillation signal such as a system clock within a chip. This PLL circuit requires a Voltage Controlled Oscillator (VCO) or a Digitally Controlled Oscillator (DCO) as the oscillator core for generating an oscillation signal according to the phase difference information with respect to the reference clock. Become. The output oscillation frequency is controlled by controlling the oscillator current flowing through these oscillator cores. In these oscillator cores, when the flowing current fluctuates due to disturbance such as power supply voltage fluctuation, the output oscillation frequency accordingly fluctuates. Of such fluctuations in the output oscillation frequency, the PLL cannot respond to a fluctuation component at a frequency higher than the band of the PLL circuit, which causes phase shift and jitter in the PLL circuit.
　このような発振器電流の変動を抑制する手法の一例として、容量素子を付加することが考えられるが、その場合、大きな容量面積が必要となるとともに、受動素子の面積が支配的になるとプロセス進化によるシュリンクの恩恵が小さくなるという問題がある。これに対し、電源電圧の変動をモニターして、変動に応じて補正信号を加える技術が提案されている（例えば、特許文献１参照。）。 As an example of a technique for suppressing such fluctuations in the oscillator current, it is possible to add a capacitive element. There is a problem that the benefits of shrinking are reduced. In response to this, a technique has been proposed in which a change in power supply voltage is monitored and a correction signal is added in accordance with the change (see, for example, Patent Document 1).
特開２００２－１７１１６５号公報Japanese Patent Application Laid-Open No. 2002-171165
　上述の従来技術では、基準電圧と電源電圧とを比較器を用いて比較し、カレントミラーのミラー比をデジタル的に制御することによって補正を行っている。しかしながら、この従来技術では、安定した基準電圧の生成を別途必要とすることに加えて、デジタル補正であるため量子化ノイズが生じてしまい、高帯域の変動に対する補正が困難であるという問題がある。 In the conventional technology described above, the reference voltage and the power supply voltage are compared using a comparator, and correction is performed by digitally controlling the mirror ratio of the current mirror. However, in this prior art, in addition to the need to generate a stable reference voltage separately, digital correction causes quantization noise, which makes it difficult to correct for fluctuations in high bands. .
　本技術はこのような状況に鑑みて生み出されたものであり、ＰＬＬ回路における出力発振周波数の変動を抑止することを目的とする。 This technology was created in view of such circumstances, and aims to suppress fluctuations in the output oscillation frequency of a PLL circuit.
　本技術は、上述の問題点を解消するためになされたものであり、その第１の側面は、所定の発振周波数により発振動作を行う発振器と、上記発振器の電源端子および接地端子の少なくとも一方に接続し、入力電圧に応じて上記発振器の上記発振周波数を制御する発振周波数制御回路と、上記発振器と上記発振周波数制御回路との間の接続ノードに接続して、上記電源端子における電源電圧の変動に応じた補正電流を上記接続ノードに対して供給する補正電流生成回路と、上記補正電流生成回路が上記補正電流を生成するためのバイアス電圧を上記補正電流生成回路に対して供給するバイアス生成回路とを具備する発振回路およびＰＬＬ回路である。これにより、バイアス電圧に基づいて電源電圧の変動に応じた補正電流を生成して、ＰＬＬ回路における出力発振周波数の変動を抑止するという作用をもたらす。 The present technology has been made to solve the above-described problems, and a first aspect of the technology is to provide an oscillator that oscillates at a predetermined oscillation frequency, and an oscillator connected to at least one of a power supply terminal and a ground terminal of the oscillator. a connection node between an oscillation frequency control circuit for controlling the oscillation frequency of the oscillator according to an input voltage; and a connection node between the oscillator and the oscillation frequency control circuit. a correction current generation circuit that supplies a correction current corresponding to the above-mentioned connection node, and a bias generation circuit that supplies a bias voltage for the correction current generation circuit to generate the correction current to the correction current generation circuit. and an oscillator circuit and a PLL circuit. This produces an effect of suppressing fluctuations in the output oscillation frequency of the PLL circuit by generating a correction current corresponding to fluctuations in the power supply voltage based on the bias voltage.
　また、この第１の側面において、上記発振周波数制御回路は、ＰＭＯＳトランジスタおよびＮＭＯＳトランジスタの一方からなり、そのゲート端子には上記入力電圧として上記発振周波数を制御するための電圧が供給される電圧制御電流源であって、上記補正電流生成回路は、ＰＭＯＳトランジスタおよびＮＭＯＳトランジスタの上記一方とは異なる他方からなり、そのゲート端子には上記バイアス電圧が供給されるようにしてもよい。これにより、互いに極性が異なるＰＭＯＳトランジスタおよびＮＭＯＳトランジスタを用いて、電源変動による影響を抑止するという作用をもたらす。 In the first aspect, the oscillation frequency control circuit is composed of one of a PMOS transistor and an NMOS transistor, and a voltage control circuit in which a voltage for controlling the oscillation frequency is supplied to the gate terminal as the input voltage. In the current source, the correction current generation circuit may be composed of the other of the PMOS transistor and the NMOS transistor, and the bias voltage may be supplied to the gate terminal of the PMOS transistor and the NMOS transistor. As a result, a PMOS transistor and an NMOS transistor having polarities different from each other are used to suppress the influence of power supply fluctuations.
　また、この第１の側面において、上記バイアス生成回路は、カレントミラー回路により上記補正電流生成回路の上記ゲート端子に対する上記バイアス電圧を生成するようにしてもよい。 Further, in this first aspect, the bias generation circuit may generate the bias voltage for the gate terminal of the correction current generation circuit by a current mirror circuit.
　また、この第１の側面において、上記バイアス生成回路は、上記補正電流生成回路の上記ゲート端子に接続するローパスフィルタを備えてもよい。 Further, in this first aspect, the bias generation circuit may include a low-pass filter connected to the gate terminal of the correction current generation circuit.
　また、この第１の側面において、上記発振器は、複数段のインバータを環状に接続したリングオシレータであり、上記バイアス生成回路は、１段分の上記インバータをレプリカ回路として備えてもよい。 Further, in the first aspect, the oscillator may be a ring oscillator in which a plurality of stages of inverters are connected in a ring, and the bias generation circuit may include one stage of inverters as a replica circuit.
　また、この第１の側面において、上記バイアス生成回路は、上記発振周波数制御回路のドレインコンダクタンスを検知するドレインコンダクタンス検知回路と、上記補正電流生成回路のトランスコンダクタンスを検知するトランスコンダクタンス検知回路と、上記発振周波数制御回路のドレインコンダクタンスと上記補正電流生成回路のトランスコンダクタンスとが等しくなるようにキャリブレーションを行うキャリブレーション回路とを備えてもよい。これにより、補正電流を生成するためのバイアス電圧を高い精度で供給するという作用をもたらす。 In the first aspect, the bias generation circuit includes a drain conductance detection circuit that detects the drain conductance of the oscillation frequency control circuit, a transconductance detection circuit that detects the transconductance of the correction current generation circuit, and the A calibration circuit may be provided for performing calibration so that the drain conductance of the oscillation frequency control circuit and the transconductance of the correction current generation circuit are equal. This brings about the effect of supplying the bias voltage for generating the correction current with high accuracy.
　また、この第１の側面において、上記入力電圧は、アナログ値またはデジタル値としてもよい。後者の場合において、この第１の側面において、上記入力電圧をデジタル信号からアナログ信号に変換して上記発振周波数制御回路に供給するデジタルアナログ変換器をさらに具備してもよい。 Also, in this first aspect, the input voltage may be an analog value or a digital value. In the latter case, the first aspect may further include a digital-to-analog converter that converts the input voltage from a digital signal to an analog signal and supplies the analog signal to the oscillation frequency control circuit.
　また、この第１の側面において、上記入力電圧は、デジタル値であって、上記発振周波数制御回路は、ＰＭＯＳトランジスタおよびＮＭＯＳトランジスタの一方からなってそのゲート端子には上記入力電圧として上記発振周波数を制御するための電圧が供給される電圧制御電流源と第１のスイッチとを直列接続した回路を複数組並列接続し、上記第１のスイッチは上記入力電圧の対応するビット値によってそれぞれ制御され、上記補正電流生成回路は、ＰＭＯＳトランジスタおよびＮＭＯＳトランジスタの上記一方とは異なる他方の並列接続からなってそのゲート端子には上記バイアス電圧が供給されるトランジスタと第２のスイッチとを直列接続した回路を複数組並列接続し、上記第２のスイッチは上記入力電圧の対応するビット値によってそれぞれ制御されるようにしてもよい。 In the first aspect, the input voltage is a digital value, and the oscillation frequency control circuit is composed of one of a PMOS transistor and an NMOS transistor, and the oscillation frequency is applied to the gate terminal as the input voltage. a plurality of sets of circuits in which a voltage-controlled current source supplied with a voltage for control and a first switch are connected in series are connected in parallel, the first switches being controlled by corresponding bit values of the input voltage; The correction current generating circuit is a circuit in which a second switch and a PMOS transistor and an NMOS transistor connected in parallel are connected in parallel, and the bias voltage is supplied to the gate terminal of the PMOS transistor and the NMOS transistor. A plurality of sets may be connected in parallel, and the second switches may be controlled by corresponding bit values of the input voltage.
本技術の第１の実施の形態におけるアナログＰＬＬ回路の構成例を示す図である。It is a figure showing an example of composition of an analog PLL circuit in a 1st embodiment of this art. 本技術の実施の形態におけるＶＣＯ１３の基本回路の構成例を示す図である。It is a figure showing an example of composition of a basic circuit of VCO13 in an embodiment of this art. 本技術の第１の実施の形態における発振器１１０の回路構成例を示す図である。It is a figure showing an example of circuit composition of oscillator 110 in a 1st embodiment of this art. 本技術の第１の実施の形態におけるＶＣＯ１３の回路構成例を示す図である。It is a figure showing an example of circuit composition of VCO13 in a 1st embodiment of this art. 本技術の第１の実施の形態における電流源１２０および補正電流生成回路１３０の具体例によるＶＣＯ１３の回路構成例を示す図である。3 is a diagram showing a circuit configuration example of the VCO 13 according to specific examples of the current source 120 and the correction current generation circuit 130 according to the first embodiment of the present technology; FIG. 本技術の第１の実施の形態におけるバイアス生成回路１４０の具体例によるＶＣＯ１３の回路構成例を示す図である。3 is a diagram showing a circuit configuration example of the VCO 13 according to a specific example of the bias generation circuit 140 according to the first embodiment of the present technology; FIG. 本技術の実施の形態における出力周波数の変動特性の一例を示す図である。It is a figure which shows an example of the fluctuation characteristic of the output frequency in embodiment of this technique. 本技術の第２の実施の形態におけるバイアス生成回路１４０の具体例によるＶＣＯ１３の回路構成例を示す図である。FIG. 7 is a diagram showing a circuit configuration example of a VCO 13 according to a specific example of a bias generation circuit 140 according to a second embodiment of the present technology; 本技術の第３の実施の形態におけるバイアス生成回路１４０の具体例によるＶＣＯ１３の回路構成例を示す図である。FIG. 11 is a diagram showing a circuit configuration example of a VCO 13 according to a specific example of a bias generation circuit 140 according to a third embodiment of the present technology; 本技術の第４の実施の形態におけるＶＣＯ１３の回路構成例を示す図である。It is a figure showing an example of circuit composition of VCO13 in a 4th embodiment of this art. 本技術の第４の実施の形態における電流源１２０および補正電流生成回路１３０の具体例によるＶＣＯ１３の回路構成例を示す図である。FIG. 11 is a diagram showing a circuit configuration example of a VCO 13 according to a specific example of a current source 120 and a correction current generation circuit 130 according to a fourth embodiment of the present technology; 本技術の第５の実施の形態におけるＶＣＯ１３の回路構成例を示す図である。It is a figure showing an example of circuit composition of VCO13 in a 5th embodiment of this art. 本技術の第６の実施の形態におけるデジタルＰＬＬ回路の構成例を示す図である。It is a figure which shows the structural example of the digital PLL circuit in 6th Embodiment of this technique. 本技術の第６の実施の形態におけるＤＣＯ２３の基本回路の構成例を示す図である。It is a figure which shows the structural example of the basic circuit of DCO23 in 6th Embodiment of this technique. 本技術の第６の実施の形態におけるＤＣＯ２３の第１の回路構成例を示す図である。It is a figure showing the 1st example of circuit composition of DCO23 in a 6th embodiment of this art. 本技術の第６の実施の形態におけるＤＣＯ２３の第１の回路構成例の具体例を示す図である。FIG. 13 is a diagram illustrating a specific example of a first circuit configuration example of a DCO 23 according to a sixth embodiment of the present technology; 本技術の第６の実施の形態におけるＤＣＯ２３の第２の回路構成例を示す図である。It is a figure showing the 2nd example of circuit composition of DCO23 in a 6th embodiment of this art. 本技術の第６の実施の形態におけるＤＣＯ２３の第２の回路構成例の具体例を示す図である。FIG. 16 is a diagram showing a specific example of a second circuit configuration example of the DCO 23 according to the sixth embodiment of the present technology;
　以下、本技術を実施するための形態（以下、実施の形態と称する）について説明する。説明は以下の順序により行う。
　１．第１の実施の形態（カレントミラー回路を利用した例）
　２．第２の実施の形態（レプリカ回路を利用した例）
　３．第３の実施の形態（キャリブレーション回路の導入例）
　４．第４の実施の形態（極性を反転した例）
　５．第５の実施の形態（電源側と接地側の両方に補正電流生成回路を接続した例）
　６．第６の実施の形態（デジタルＰＬＬ回路への適用例） Hereinafter, a form for carrying out the present technology (hereinafter referred to as an embodiment) will be described. Explanation will be given in the following order.
1. First Embodiment (Example Using a Current Mirror Circuit)
2. Second Embodiment (Example Using a Replica Circuit)
3. Third Embodiment (Example of Introduction of Calibration Circuit)
4. Fourth embodiment (example in which polarity is reversed)
5. Fifth embodiment (example in which a correction current generation circuit is connected to both the power supply side and the ground side)
6. Sixth Embodiment (Example of Application to Digital PLL Circuit)
　＜１．第１の実施の形態＞
　［アナログＰＬＬ回路］
　図１は、本技術の第１の実施の形態におけるアナログＰＬＬ回路の構成例を示す図である。 <1. First Embodiment>
[Analog PLL circuit]
FIG. 1 is a diagram illustrating a configuration example of an analog PLL circuit according to a first embodiment of the present technology.
　このアナログＰＬＬ回路は、位相比較器１１と、アナログフィルタ１２と、ＶＣＯ１３と、分周器１４とを備える。分周器１４は、ＰＬＬ回路としての逓倍設定を行うものであり、出力信号を分周する。位相比較器１１は、入力信号と分周器１４によって分周された出力信号との位相を比較して、位相差に応じた位相差電圧を出力するものである。アナログフィルタ１２は、位相比較器１１によって出力された位相差電圧の低周波域を通過させて、ＶＣＯ１３に対してアナログ値の入力電圧として供給するローパスフィルタである。ＶＣＯ１３は、ローパスフィルタからの入力電圧に応じた周波数の信号を生成して出力信号を出力する電圧制御発振器である。 This analog PLL circuit includes a phase comparator 11, an analog filter 12, a VCO 13, and a frequency divider . The frequency divider 14 performs multiplication setting as a PLL circuit, and divides the frequency of the output signal. The phase comparator 11 compares the phases of the input signal and the output signal divided by the frequency divider 14 and outputs a phase difference voltage corresponding to the phase difference. The analog filter 12 is a low-pass filter that passes the low-frequency range of the phase difference voltage output from the phase comparator 11 and supplies it to the VCO 13 as an analog value input voltage. The VCO 13 is a voltage controlled oscillator that generates a signal with a frequency according to the input voltage from the low-pass filter and outputs an output signal.
　［ＶＣＯ］
　図２は、本技術の実施の形態におけるＶＣＯ１３の基本回路の構成例を示す図である。 [VCO]
FIG. 2 is a diagram showing a configuration example of a basic circuit of the VCO 13 according to the embodiment of the present technology.
　ＶＣＯ１３は、所定の発振周波数により発振動作を行う発振器１１０を備える。また、ＶＣＯ１３は、同図におけるａおよびｂに示すように電流源１２０を備える。この電流源１２０は、入力電圧に応じた電流を供給する電圧制御電流源（ＶＣＣＳ：Voltage Controlled Current Source）である。すなわち、アナログフィルタ１２から供給されるアナログ値の入力電圧が電流源１２０によって発振器１１０に流れる電流に変換される。この変換された電流値によって発振器１１０の発振周波数が制御される。 The VCO 13 has an oscillator 110 that oscillates at a predetermined oscillation frequency. The VCO 13 also includes a current source 120 as indicated by a and b in FIG. This current source 120 is a voltage controlled current source (VCCS: Voltage Controlled Current Source) that supplies a current corresponding to an input voltage. That is, the analog input voltage supplied from the analog filter 12 is converted by the current source 120 into a current flowing through the oscillator 110 . The oscillation frequency of oscillator 110 is controlled by this converted current value.
　この電流源１２０は、発振器１１０の電源側および接地側の何れに接続してもよい。同図におけるａは、発振器１１０の接地側に電流源１２０を接続した例である。同図におけるｂは、発振器１１０の電源側に電流源１２０を接続した例である。すなわち、同図におけるａおよびｂは、互いに極性が異なる例である。 This current source 120 may be connected to either the power supply side or ground side of the oscillator 110 . In the figure, a is an example in which the current source 120 is connected to the ground side of the oscillator 110 . b in the figure is an example in which the current source 120 is connected to the power supply side of the oscillator 110 . That is, a and b in the figure are examples in which the polarities are different from each other.
　また、ＶＣＯ１３は、同図におけるｃおよびｄに示すようにレギュレータ１５０を備えてもよい。このレギュレータ１５０は、入力電圧に応じた一定の電圧を発振器１１０に供給する電圧源である。これにより、同図におけるｃの例では、レギュレータ１５０の出力電圧から電源電圧の間になるよう発振器１１０の電圧幅が制御される。一方、同図におけるｄの例では、レギュレータ１５０の出力電圧から接地電位の間になるよう発振器１１０の電圧幅が制御される。このようにして、発振器１１０は、発振振幅が上述の電圧幅となるような発振周波数で動作する。なお、同図におけるｃおよびｄは、互いに極性が異なる例である。 Also, the VCO 13 may include a regulator 150 as shown in c and d in the figure. This regulator 150 is a voltage source that supplies a constant voltage to the oscillator 110 according to the input voltage. As a result, in the example of c in the figure, the voltage width of the oscillator 110 is controlled to be between the output voltage of the regulator 150 and the power supply voltage. On the other hand, in the example of d in the figure, the voltage width of the oscillator 110 is controlled to be between the output voltage of the regulator 150 and the ground potential. In this manner, oscillator 110 operates at an oscillation frequency such that the oscillation amplitude is the voltage width described above. It should be noted that c and d in FIG.
　図３は、本技術の第１の実施の形態における発振器１１０の回路構成例を示す図である。 FIG. 3 is a diagram showing a circuit configuration example of the oscillator 110 according to the first embodiment of the present technology.
　この発振器１１０の回路構成例は、ＰＭＯＳトランジスタ１１１およびＮＭＯＳトランジスタ１１２からなるインバータを３段分設けて、環状に接続したリングオシレータである。ＰＭＯＳトランジスタ１１１は電源側に接続され、ＮＭＯＳトランジスタ１１２は接地側に接続される。 An example of the circuit configuration of this oscillator 110 is a ring oscillator in which three stages of inverters each including a PMOS transistor 111 and an NMOS transistor 112 are provided and connected in a ring. The PMOS transistor 111 is connected to the power supply side, and the NMOS transistor 112 is connected to the ground side.
　このようなリングオシレータでは、流れる電流や振幅（動作電圧幅）を変化させた際の、一段当たりの遅延時間の変化を利用することによって、発振周波数を制御することができる。 With such a ring oscillator, the oscillation frequency can be controlled by using the change in the delay time per stage when the flowing current or amplitude (operating voltage width) is changed.
　図４は、本技術の第１の実施の形態におけるＶＣＯ１３の回路構成例を示す図である。 FIG. 4 is a diagram showing a circuit configuration example of the VCO 13 according to the first embodiment of the present technology.
　この第１の実施の形態におけるＶＣＯ１３は、発振器１１０と、電流源１２０と、補正電流生成回路１３０と、バイアス生成回路１４０とを備える。発振器１１０および電流源１２０からなる基本回路は、上述の通りである。 The VCO 13 in this first embodiment comprises an oscillator 110 , a current source 120 , a correction current generation circuit 130 and a bias generation circuit 140 . The basic circuit consisting of oscillator 110 and current source 120 is described above.
　補正電流生成回路１３０は、発振器１１０と電流源１２０との間の接続ノードに接続して、発振器１１０の電源端子における電源電圧の変動に応じた補正電流を接続ノードに対して供給するものである。すなわち、この補正電流生成回路１３０は、電源電圧変動をモニターして、発振器１１０に流れる電流の変動を補正するために、電荷注入素子のアナログ特性を用いて補正電流を生成する。 The correction current generation circuit 130 is connected to a connection node between the oscillator 110 and the current source 120, and supplies a correction current to the connection node according to fluctuations in the power supply voltage at the power supply terminal of the oscillator 110. . That is, the correction current generating circuit 130 monitors the power supply voltage fluctuation and generates a correction current using the analog characteristics of the charge injection device in order to correct the fluctuation of the current flowing through the oscillator 110 .
　バイアス生成回路１４０は、補正電流生成回路１３０が補正電流を生成するためのバイアス電圧を、補正電流生成回路１３０に対して供給するものである。 The bias generation circuit 140 supplies the correction current generation circuit 130 with a bias voltage for the correction current generation circuit 130 to generate the correction current.
　図５は、本技術の第１の実施の形態における電流源１２０および補正電流生成回路１３０の具体例によるＶＣＯ１３の回路構成例を示す図である。 FIG. 5 is a diagram showing a circuit configuration example of the VCO 13 according to specific examples of the current source 120 and the correction current generation circuit 130 according to the first embodiment of the present technology.
　この例では、電流源１２０としてＮＭＯＳトランジスタ１２１を設け、補正電流生成回路１３０としてＰＭＯＳトランジスタ１３１を設けた例を示している。ＮＭＯＳトランジスタ１２１は、ソースが接地端子に接続し、ドレインが発振器１１０に接続し、ゲートがアナログフィルタ１２の出力に接続する。ＰＭＯＳトランジスタ１３１は、ソースが電源端子に接続し、ドレインがＮＭＯＳトランジスタ１２１のドレインに接続し、ゲートがバイアス生成回路１４０に接続する。 This example shows an example in which an NMOS transistor 121 is provided as the current source 120 and a PMOS transistor 131 is provided as the correction current generation circuit 130 . The NMOS transistor 121 has a source connected to the ground terminal, a drain connected to the oscillator 110 , and a gate connected to the output of the analog filter 12 . The PMOS transistor 131 has a source connected to the power supply terminal, a drain connected to the drain of the NMOS transistor 121 , and a gate connected to the bias generation circuit 140 .
　この例では、トランジスタの電圧電流変換能力を利用して、ゲート・ソース間電圧が変動した際の、ドレイン電流の変動を補正電流として用いる。この構成ではＰＭＯＳトランジスタ１３１のゲート電位が固定されており、電源電圧が変動したときにＰＭＯＳトランジスタ１３１のゲート・ソース間電圧が変調され、ＰＭＯＳトランジスタ１３１の特性に応じて補正電流が生成される。 In this example, using the voltage-to-current conversion capability of the transistor, the fluctuation of the drain current when the voltage between the gate and the source fluctuates is used as the correction current. In this configuration, the gate potential of the PMOS transistor 131 is fixed, and when the power supply voltage fluctuates, the gate-source voltage of the PMOS transistor 131 is modulated, and a correction current is generated according to the characteristics of the PMOS transistor 131 .
　このように、この実施の形態では、補正電流生成回路１３０をアナログ回路により構成し、ＰＭＯＳトランジスタ１３１のアナログ特性を利用したアナログ補正を行うため、量子化ノイズが発生しない。また、電源電圧変動を補正電流に直接変換するため、高い周波数成分をもつ電源電圧変動まで追従して、補正電流を生成することができる。 As described above, in this embodiment, the correction current generation circuit 130 is configured by an analog circuit and analog correction is performed using the analog characteristics of the PMOS transistor 131, so that quantization noise does not occur. In addition, since the power supply voltage fluctuation is directly converted into the correction current, the correction current can be generated by following even the power supply voltage fluctuation having a high frequency component.
　電源電圧変動が存在した場合、ＮＭＯＳトランジスタ１２１は、ドレイン・ソース間電圧が変化することにより、ＮＭＯＳトランジスタ１２１が供給している電流（被補正電流）が、変換ゲインｇdsにより変動する。一方、ＰＭＯＳトランジスタ１３１では、ゲート・ソース間電圧の変動によって、変換ゲインｇmにより補正電流を生成する。ここで、一般に飽和領域で動作するトランジスタにおいては、トランスコンダクタンスｇmはドレインコンダクタンスｇdsのおよそ数十倍から百倍程度大きい。そのため、交流の補正電流を生成するためにＰＭＯＳトランジスタ１３１が必要とする直流電流は、ＮＭＯＳトランジスタ１２１に流れる直流電流の数十分の一から百分の一程度の直流電流であるため、問題は生じない。そのため、補正電流生成回路１３０で発生するノイズが十分小さいことに加えて、ＰＬＬの位相（周波数）の引き込み動作を阻害しない。 When the power supply voltage fluctuates, the current supplied by the NMOS transistor 121 (current to be corrected) fluctuates due to the conversion gain gds due to the change in the voltage between the drain and the source of the NMOS transistor 121 . On the other hand, in the PMOS transistor 131, the correction current is generated by the conversion gain gm according to the fluctuation of the voltage between the gate and the source. Here, in a transistor that generally operates in the saturation region, the transconductance gm is approximately several ten to one hundred times larger than the drain conductance gds. Therefore, the DC current required by the PMOS transistor 131 to generate the AC correction current is about several tenths to one hundredth of the DC current flowing through the NMOS transistor 121, so the problem does not arise. does not occur. Therefore, the noise generated in the correction current generating circuit 130 is sufficiently small, and the pull-in operation of the phase (frequency) of the PLL is not hindered.
　ここで、バイアス生成回路１４０は、本技術における補正効果を最適化するために、ＰＭＯＳトランジスタ１３１が生成する補正電流を被補正電流のＰＶＴばらつきに対して追従させるためのバイアスを生成する役割と、ＰＭＯＳトランジスタ１３１のゲート電位を固定させる役割を備える。 Here, in order to optimize the correction effect in the present technology, the bias generation circuit 140 has a role of generating a bias for causing the correction current generated by the PMOS transistor 131 to follow the PVT variation of the current to be corrected; It has the role of fixing the gate potential of the PMOS transistor 131 .
　図６は、本技術の第１の実施の形態におけるバイアス生成回路１４０の具体例によるＶＣＯ１３の回路構成例を示す図である。 FIG. 6 is a diagram showing a circuit configuration example of the VCO 13 according to a specific example of the bias generation circuit 140 according to the first embodiment of the present technology.
　この例では、バイアス生成回路１４０は、ＰＭＯＳトランジスタ１４１と、ＮＭＯＳトランジスタ１４２と、抵抗１４８と、キャパシタ１４９とを備える。 In this example, the bias generation circuit 140 includes a PMOS transistor 141, an NMOS transistor 142, a resistor 148, and a capacitor 149.
　ＰＭＯＳトランジスタ１４１のドレインはＮＭＯＳトランジスタ１４２のドレインと接続され、ＰＭＯＳトランジスタ１４１のソースは電源端子と接続され、ＮＭＯＳトランジスタ１４２のソースは接地端子と接続される。また、ＰＭＯＳトランジスタ１４１のゲート・ドレイン間は短絡されており、ＰＭＯＳトランジスタ１４１およびＰＭＯＳトランジスタ１３１はカレントミラー回路を構成する。また、ＮＭＯＳトランジスタ１４２のゲートはＮＭＯＳトランジスタ１２１のゲートに接続される。 The drain of the PMOS transistor 141 is connected to the drain of the NMOS transistor 142, the source of the PMOS transistor 141 is connected to the power supply terminal, and the source of the NMOS transistor 142 is connected to the ground terminal. The gate and drain of the PMOS transistor 141 are short-circuited, and the PMOS transistor 141 and the PMOS transistor 131 form a current mirror circuit. Also, the gate of the NMOS transistor 142 is connected to the gate of the NMOS transistor 121 .
　ＮＭＯＳトランジスタ１４２はＮＭＯＳトランジスタ１２１と同様に、ゲート電圧に応じた電流を生じる電流源として動作する。ＮＭＯＳトランジスタ１２１とＮＭＯＳトランジスタ１４２のサイズ比に応じた電流が、ＰＭＯＳトランジスタ１３１とＰＭＯＳトランジスタ１４１に反映されて、ＰＭＯＳトランジスタ１３１からＮＭＯＳトランジスタ１２１に流れ込む。したがって、ＮＭＯＳトランジスタ１２１に流れる電流の変動に対して、ＰＭＯＳトランジスタ１３１が生成する補正電流を追従させるように、ＰＭＯＳトランジスタ１３１のゲートへのバイアス電圧を生成することができる。 The NMOS transistor 142, like the NMOS transistor 121, operates as a current source that generates a current corresponding to the gate voltage. A current corresponding to the size ratio of the NMOS transistor 121 and the NMOS transistor 142 is reflected in the PMOS transistor 131 and the PMOS transistor 141 and flows from the PMOS transistor 131 to the NMOS transistor 121 . Therefore, the bias voltage to the gate of the PMOS transistor 131 can be generated so that the correction current generated by the PMOS transistor 131 follows the variation of the current flowing through the NMOS transistor 121 .
　このように、被補正電流のカレントミラー構成を用いてＰＭＯＳトランジスタ１３１のバイアス電圧を決定することにより、ＮＭＯＳトランジスタ１２１の特性変動にＰＭＯＳトランジスタ１３１を追従させることができる。すなわち、被補正電流のＰＶＴばらつきに対して、補正電流を追従させることができる。 Thus, by determining the bias voltage of the PMOS transistor 131 using the current mirror configuration of the current to be corrected, the PMOS transistor 131 can follow the characteristic variation of the NMOS transistor 121 . That is, the correction current can follow the PVT variation of the current to be corrected.
　また、抵抗１４８およびキャパシタ１４９は、ＲＣフィルタによるローパスフィルタを形成する。このローパスフィルタにおいて、キャパシタ１４９は接地端子に接続する。これにより、このローパスフィルタはフィルタ帯域以上でＰＭＯＳトランジスタ１３１のゲート電位を固定することができる。 Also, resistor 148 and capacitor 149 form a low-pass filter by an RC filter. In this low pass filter, capacitor 149 is connected to ground. As a result, this low-pass filter can fix the gate potential of the PMOS transistor 131 above the filter band.
　ここで、キャパシタ１４９は比較的小さい容量でよく、抵抗１４８によって帯域を形成することができる。例えば、１００ＫＨｚ前後において、キャパシタ１４９を１ＰＦ程度、抵抗１４８を１ＭΩ程度とすることができる。 Here, the capacitor 149 may have a relatively small capacity, and the band can be formed by the resistor 148. For example, at around 100 KHz, the capacitor 149 can be approximately 1 PF and the resistor 148 can be approximately 1 MΩ.
　このように、第１の実施の形態における回路構成は、非常に単純な構成であるため、素子の追加を抑えて、面積を小さくすることができる。 Thus, since the circuit configuration in the first embodiment is a very simple configuration, it is possible to reduce the area by suppressing the addition of elements.
　［特性］
　図７は、本技術の実施の形態における出力周波数の変動特性の一例を示す図である。 [Characteristic]
FIG. 7 is a diagram illustrating an example of fluctuation characteristics of an output frequency according to an embodiment of the present technology;
　ここでは、横軸に電源電圧の変動周波数（Ｈｚ）を示し、縦軸に電源電圧変動に対する周波数変動の規格化された値（１／Ｖ）を示している。縦軸の値が小さいほど性能が良好であることを意味する。実線は、この第１の実施の形態の回路による特性例である。点線は、補正電流生成回路１３０およびバイアス生成回路１４０を設けない場合の特性例である。 Here, the horizontal axis indicates the fluctuation frequency (Hz) of the power supply voltage, and the vertical axis indicates the normalized value (1/V) of the frequency fluctuation with respect to the power supply voltage fluctuation. A smaller value on the vertical axis means better performance. A solid line is an example of the characteristics of the circuit of the first embodiment. A dotted line is an example of characteristics when the correction current generation circuit 130 and the bias generation circuit 140 are not provided.
　補正帯域としては１００ＫＨｚから１０ＭＨｚ程度を想定しており、１ＭＨｚで十分の一程度の性能改善が見られ、１０ＭＨｚで五分の一程度の性能改善が見られる。すなわち、この第１の実施の形態では、補正電流を能動的に供給しているため、受動素子と比べて高い電源電圧変動耐性（ＰＳＲＲ：Power Supply Rejection Ratio）を実現することができる。 The correction band is assumed to be about 100 kHz to 10 MHz, with a performance improvement of about one-tenth at 1 MHz and a performance improvement of about one-fifth at 10 MHz. That is, in the first embodiment, since the correction current is actively supplied, it is possible to realize higher power supply voltage fluctuation resistance (PSRR: Power Supply Rejection Ratio) compared to passive elements.
　このように、本技術の第１の実施の形態によれば、電流源１２０のＮＭＯＳトランジスタ１２１の電流を補正するための補正電流生成回路１３０として、ＰＭＯＳトランジスタ１３１を設けることにより、電源電圧の変動に応じて能動的に補正を行うことができる。また、バイアス生成回路１４０においてカレントミラー構成を用いてＰＭＯＳトランジスタ１３１のバイアス電圧を決定することにより、ＮＭＯＳトランジスタ１２１の電流のＰＶＴばらつきに対して、補正電流を追従させることができる。さらに、抵抗１４８およびキャパシタ１４９によるローパスフィルタを設けることにより、フィルタ帯域以上でＰＭＯＳトランジスタ１３１のゲート電位を固定することができる。 As described above, according to the first embodiment of the present technology, by providing the PMOS transistor 131 as the correction current generation circuit 130 for correcting the current of the NMOS transistor 121 of the current source 120, fluctuations in the power supply voltage Correction can be actively performed depending on Further, by determining the bias voltage of the PMOS transistor 131 using the current mirror configuration in the bias generation circuit 140, the correction current can follow the PVT variation of the current of the NMOS transistor 121. FIG. Furthermore, by providing a low-pass filter consisting of resistor 148 and capacitor 149, the gate potential of PMOS transistor 131 can be fixed above the filter band.
　＜２．第２の実施の形態＞
　上述の第１の実施の形態ではカレントミラー回路によってＰＭＯＳトランジスタ１３１の電流を反映させていたが、この第２の実施の形態ではレプリカ回路を利用してＰＭＯＳトランジスタ１３１の電流を反映させる。なお、アナログＰＬＬ回路としての全体構成は上述の第１の実施の形態と同様であるため、詳細な説明は省略する。 <2. Second Embodiment>
In the first embodiment described above, the current of the PMOS transistor 131 is reflected by the current mirror circuit, but in the second embodiment, the current of the PMOS transistor 131 is reflected using a replica circuit. Since the overall configuration of the analog PLL circuit is the same as that of the first embodiment, detailed description thereof will be omitted.
　［ＶＣＯ］
　図８は、本技術の第２の実施の形態におけるバイアス生成回路１４０の具体例によるＶＣＯ１３の回路構成例を示す図である。 [VCO]
FIG. 8 is a diagram showing a circuit configuration example of the VCO 13 according to a specific example of the bias generation circuit 140 according to the second embodiment of the present technology.
　この第２の実施の形態におけるバイアス生成回路１４０は、上述の第１の実施の形態におけるＰＭＯＳトランジスタ１４１に代えて、ＰＭＯＳトランジスタ１４６およびＮＭＯＳトランジスタ１４７を備える。ＰＭＯＳトランジスタ１４６およびＮＭＯＳトランジスタ１４７は、インバータを構成する。すなわち、上述のように発振器１１０としてリングオシレータを想定して、そのリングオシレータにおける１段分のインバータを発振器１１０のレプリカ回路として設ける。これにより、カレントミラー回路を用いることなく、ＰＭＯＳトランジスタ１３１の電流を反映させるようにバイアス電圧を生成することができる。 A bias generation circuit 140 in the second embodiment includes a PMOS transistor 146 and an NMOS transistor 147 instead of the PMOS transistor 141 in the first embodiment. PMOS transistor 146 and NMOS transistor 147 form an inverter. That is, assuming a ring oscillator as the oscillator 110 as described above, one stage of inverter in the ring oscillator is provided as a replica circuit of the oscillator 110 . Thereby, the bias voltage can be generated so as to reflect the current of the PMOS transistor 131 without using a current mirror circuit.
　このように、本技術の第２の実施の形態によれば、発振器１１０のレプリカ回路をバイアス生成回路１４０に設けることにより、ＮＭＯＳトランジスタ１２１の電流のＰＶＴばらつきに対して、補正電流を追従させることができる。 Thus, according to the second embodiment of the present technology, by providing the replica circuit of the oscillator 110 in the bias generation circuit 140, the correction current can follow the PVT variation of the current of the NMOS transistor 121. can be done.
　＜３．第３の実施の形態＞
　この第３の実施の形態では、バイアス生成回路１４０において、ＮＭＯＳトランジスタ１２１のドレインコンダクタンスとＰＭＯＳトランジスタ１３１のトランスコンダクタンスとが等しくなるようにキャリブレーションを行う機能を備える。なお、アナログＰＬＬ回路としての全体構成は上述の第１の実施の形態と同様であるため、詳細な説明は省略する。 <3. Third Embodiment>
In the third embodiment, the bias generating circuit 140 has a function of performing calibration so that the drain conductance of the NMOS transistor 121 and the transconductance of the PMOS transistor 131 are equal. Since the overall configuration of the analog PLL circuit is the same as that of the first embodiment, detailed description thereof will be omitted.
　［ＶＣＯ］
　図９は、本技術の第３の実施の形態におけるバイアス生成回路１４０の具体例によるＶＣＯ１３の回路構成例を示す図である。 [VCO]
FIG. 9 is a diagram showing a circuit configuration example of the VCO 13 according to a specific example of the bias generation circuit 140 according to the third embodiment of the present technology.
　この第３の実施の形態では、バイアス生成回路１４０は、ｇdsn検知回路２１０と、ｇmp検知／キャリブレーション回路２３０とを備える。ｇdsn検知回路２１０は、ＮＭＯＳトランジスタ１２１のドレインコンダクタンスｇdsnを検知する回路である。ｇmp検知／キャリブレーション回路２３０は、ＰＭＯＳトランジスタ１３１のトランスコンダクタンスｇmpを検知して、ドレインコンダクタンスｇdsnとトランスコンダクタンスｇmpとが等しくなるようにキャリブレーションを行う回路である。 In this third embodiment, the bias generation circuit 140 comprises a gdsn detection circuit 210 and a gmp detection/calibration circuit 230. The gdsn detection circuit 210 is a circuit that detects the drain conductance gdsn of the NMOS transistor 121 . The gmp detection/calibration circuit 230 is a circuit that detects the transconductance gmp of the PMOS transistor 131 and performs calibration so that the drain conductance gdsn and the transconductance gmp become equal.
　ｇdsn検知回路２１０は、ＮＭＯＳトランジスタ２１１、２１３、２１７、２１８、２２１および２２２と、ＰＭＯＳトランジスタ２１２、２１５、２１６、２１９と、抵抗２１４および２２３とを備える。ＮＭＯＳトランジスタ２１１および２１３のゲートには、アナログフィルタ１２からの入力電圧が供給される。ＮＭＯＳトランジスタ２１７および２１８、２２１および２２２、ＰＭＯＳトランジスタ２１２および２１９、２１５および２１５のそれぞれは、カレントミラー回路を形成する。 The gdsn sensing circuit 210 comprises NMOS transistors 211, 213, 217, 218, 221 and 222; PMOS transistors 212, 215, 216 and 219; The input voltage from the analog filter 12 is supplied to the gates of the NMOS transistors 211 and 213 . NMOS transistors 217 and 218, 221 and 222, PMOS transistors 212 and 219, 215 and 215 respectively form a current mirror circuit.
　ｇmp検知／キャリブレーション回路２３０は、ＮＭＯＳトランジスタ２３１、２３３、２３５、２３８、２４１および２４２と、ＰＭＯＳトランジスタ２３２および２３６と、抵抗２３４および２４３と、オペアンプ２４９とを備える。ＮＭＯＳトランジスタ２３３および２３５のゲートには、アナログフィルタ１２からの入力電圧が供給される（端子Ｃ）。ＮＭＯＳトランジスタ２４１および２４２、ＰＭＯＳトランジスタ２３２および１３１のそれぞれは、カレントミラー回路を形成する。ＮＭＯＳトランジスタ２３１および２３８のゲートにはオペアンプ２４９の出力が接続される。オペアンプ２４９の端子ＡにはＮＭＯＳトランジスタ２２２のドレインが接続され、オペアンプ２４９の端子ＢにはＮＭＯＳトランジスタ２４２のドレインが接続される。 The gmp detection/calibration circuit 230 comprises NMOS transistors 231 , 233 , 235 , 238 , 241 and 242 , PMOS transistors 232 and 236 , resistors 234 and 243 and operational amplifier 249 . The input voltage from the analog filter 12 is supplied to the gates of the NMOS transistors 233 and 235 (terminal C). Each of NMOS transistors 241 and 242 and PMOS transistors 232 and 131 form a current mirror circuit. The output of operational amplifier 249 is connected to the gates of NMOS transistors 231 and 238 . A terminal A of the operational amplifier 249 is connected to the drain of the NMOS transistor 222 , and a terminal B of the operational amplifier 249 is connected to the drain of the NMOS transistor 242 .
　まず、ｇdsn検知回路２１０は、ＮＭＯＳトランジスタのドレイン・ソース間電圧電流変換ゲイン（ドレインコンダクタンスｇdsn）を以下の要領で端子Ａの電圧に変換する。すなわち、抵抗２１４を用いて電位差を作ることによりＮＭＯＳトランジスタのｇdsn電流を生成する。そして、カレントコンパレータを用いて、差分電流ｇdsnＩＲを抽出する。この差分電流ｇdsnＩＲから抵抗２２３によって端子Ａの電圧を生成する。 First, the gdsn detection circuit 210 converts the drain-source voltage-current conversion gain (drain conductance gdsn) of the NMOS transistor into the voltage of the terminal A in the following manner. That is, the gdsn current of the NMOS transistor is generated by creating a potential difference using resistor 214 . A current comparator is then used to extract the differential current gdsnIR. A voltage of the terminal A is generated by the resistor 223 from this differential current gdsnIR.
　一方、ｇmp検知／キャリブレーション回路２３０は、同様の要領でＰＭＯＳトランジスタのゲート・ソース間電圧電流変換ゲイン（トランスコンダクタンスｇmp）を端子Ｂの電圧に変換する。 On the other hand, the gmp detection/calibration circuit 230 converts the gate-source voltage-current conversion gain (transconductance gmp) of the PMOS transistor into the voltage of the terminal B in a similar manner.
　そして、オペアンプ２４９は、端子Ａの電圧と端子Ｂの電圧とが等しくなるようにキャリブレーションを行って、ＰＭＯＳトランジスタ１３１の能力を調整する。 Then, the operational amplifier 249 performs calibration so that the voltage of the terminal A and the voltage of the terminal B are equal, and adjusts the capability of the PMOS transistor 131 .
　このように、本技術の第３の実施の形態によれば、ドレインコンダクタンスｇdsnおよびトランスコンダクタンスｇmpを検知して、両者が等しくなるようにキャリブレーションを行うことにより、ＰＭＯＳトランジスタ１３１の能力を調整することができる。 Thus, according to the third embodiment of the present technology, the ability of the PMOS transistor 131 is adjusted by detecting the drain conductance gdsn and the transconductance gmp and performing calibration so that both become equal. be able to.
　＜４．第４の実施の形態＞
　上述の第１乃至３の実施の形態では発振器１１０の接地端子に電流源１２０を接続していたが、この第４の実施の形態では発振器１１０の電源端子に電流源１２０を接続する。すなわち、この第４の実施の形態は、上述の第１乃至３の実施の形態と比べて極性が反転している。 <4. Fourth Embodiment>
While the current source 120 is connected to the ground terminal of the oscillator 110 in the first to third embodiments described above, the current source 120 is connected to the power supply terminal of the oscillator 110 in the fourth embodiment. That is, in this fourth embodiment, the polarities are reversed compared to the above-described first to third embodiments.
　［ＶＣＯ］
　図１０は、本技術の第４の実施の形態におけるＶＣＯ１３の回路構成例を示す図である。 [VCO]
FIG. 10 is a diagram showing a circuit configuration example of the VCO 13 according to the fourth embodiment of the present technology.
　この第４の実施の形態では、補正電流生成回路１３０は、発振器１１０の電源端子に接続された電流源１２０との間の接続ノードに接続して、発振器１１０の電源端子における電源電圧の変動に応じた補正電流を接続ノードに対して供給する。バイアス生成回路１４０は、補正電流生成回路１３０が補正電流を生成するためのバイアス電圧を、補正電流生成回路１３０に対して供給する。 In this fourth embodiment, the correction current generation circuit 130 is connected to the connection node between the current source 120 connected to the power supply terminal of the oscillator 110, and the power supply voltage at the power supply terminal of the oscillator 110 fluctuates. A corresponding correction current is supplied to the connection node. The bias generation circuit 140 supplies the correction current generation circuit 130 with a bias voltage for the correction current generation circuit 130 to generate a correction current.
　図１１は、本技術の第４の実施の形態における電流源１２０および補正電流生成回路１３０の具体例によるＶＣＯ１３の回路構成例を示す図である。 FIG. 11 is a diagram showing a circuit configuration example of the VCO 13 according to specific examples of the current source 120 and the correction current generation circuit 130 according to the fourth embodiment of the present technology.
　この第４の実施の形態の回路構成例は、上述の第１の実施の形態の回路構成例と極性が反転しているだけであり、基本的な動作は変わらないため、詳細な説明は省略する。 The circuit configuration example of the fourth embodiment is only reversed in polarity from the circuit configuration example of the above-described first embodiment, and the basic operation is the same, so detailed description is omitted. do.
　このように、本技術の第４の実施の形態によれば、発振器１１０の電源端子に電流源１２０を接続した基本回路に対しても本技術を適用することができる。 Thus, according to the fourth embodiment of the present technology, the present technology can be applied to a basic circuit in which the current source 120 is connected to the power supply terminal of the oscillator 110.
　＜５．第５の実施の形態＞
　上述の第１乃至４の実施の形態では発振器１１０の接地端子または電源端子の何れか一方のみに電流源１２０を接続していたが、この第５の実施の形態では発振器１１０の接地端子または電源端子の両側に電流源１２０を接続することを想定する。このような回路構成は、発振器１１０の電源側および接地側の両側から電流を供給して、電源電位や接地電位によってクリップされないように、サイン波に近い波形を生成しようとする場合に採用され得る。 <5. Fifth Embodiment>
In the first to fourth embodiments described above, the current source 120 is connected only to either the ground terminal or the power supply terminal of the oscillator 110, but in the fifth embodiment, the ground terminal of the oscillator 110 or the power supply is connected. Assume that a current source 120 is connected to each side of the terminal. Such a circuit configuration can be employed when trying to generate a waveform close to a sine wave by supplying current from both the power supply side and the ground side of the oscillator 110 so as not to be clipped by the power supply potential or the ground potential. .
　［ＶＣＯ］
　図１２は、本技術の第５の実施の形態におけるＶＣＯ１３の回路構成例を示す図である。 [VCO]
FIG. 12 is a diagram showing a circuit configuration example of the VCO 13 according to the fifth embodiment of the present technology.
　この第５の実施の形態では、補正電流生成回路１３０－１は、発振器１１０の接地端子に接続された電流源１２０－１との間の接続ノードに接続して、電源電圧の変動に応じた補正電流を電流源１２０－１に対して供給する。また、補正電流生成回路１３０－２は、発振器１１０の電源端子に接続された電流源１２０－２との間の接続ノードに接続して、電源電圧の変動に応じた補正電流を電流源１２０－２に対して供給する。 In this fifth embodiment, the correction current generation circuit 130-1 is connected to the connection node between the current source 120-1 connected to the ground terminal of the oscillator 110, and responds to fluctuations in the power supply voltage. A correction current is supplied to the current source 120-1. Further, the correction current generating circuit 130-2 is connected to the connection node between the current source 120-2 connected to the power supply terminal of the oscillator 110, and generates a correction current according to the fluctuation of the power supply voltage. supply for 2.
　このように、本技術の第５の実施の形態によれば、発振器１１０の電源側および接地側の両側から電流を供給する回路構成に対しても本技術を適用することができる。 Thus, according to the fifth embodiment of the present technology, the present technology can also be applied to a circuit configuration that supplies current from both the power supply side and the ground side of the oscillator 110 .
　＜６．第６の実施の形態＞
　上述の第１乃至５の実施の形態ではアナログＰＬＬ回路を想定したが、この第６の実施の形態ではデジタルＰＬＬ回路を想定する。 <6. Sixth Embodiment>
While analog PLL circuits are assumed in the above-described first to fifth embodiments, digital PLL circuits are assumed in this sixth embodiment.
　［デジタルＰＬＬ回路］
　図１３は、本技術の第６の実施の形態におけるデジタルＰＬＬ回路の構成例を示す図である。 [Digital PLL circuit]
FIG. 13 is a diagram illustrating a configuration example of a digital PLL circuit according to the sixth embodiment of the present technology;
　このデジタルＰＬＬ回路は、カウンタ＋ＴＤＣ２１と、デジタルフィルタ２２と、ＤＣＯ２３と、分周器２４とを備える。分周器２４は、ＰＬＬ回路としての逓倍設定を行うものであり、出力信号を分周する。カウンタ＋ＴＤＣ２１は、入力信号と分周器２４によって分周された出力信号との位相を比較して、位相差に応じた位相差デジタル信号を出力するものである。このカウンタ＋ＴＤＣ２１において、カウンタは基準入力周波数の何倍の出力周波数になるかの整数部分を計測し、ＴＤＣ（Time to Digital Converter）は小数部分を計測する。デジタルフィルタ２２は、カウンタ＋ＴＤＣ２１によって出力された位相差デジタル信号の低周波域を通過させて、ＤＣＯ２３に対して入力デジタル信号として供給するローパスフィルタである。ＤＣＯ２３は、ローパスフィルタからの入力デジタル信号に応じた周波数の信号を生成して出力信号を出力するデジタル制御発振器である。 This digital PLL circuit includes a counter +TDC 21, a digital filter 22, a DCO 23, and a frequency divider 24. The frequency divider 24 performs multiplication setting as a PLL circuit, and divides the frequency of the output signal. The counter +TDC 21 compares the phases of the input signal and the output signal divided by the frequency divider 24 and outputs a phase difference digital signal corresponding to the phase difference. In this counter+TDC 21, the counter measures the integer part of how many times the output frequency becomes the reference input frequency, and the TDC (Time to Digital Converter) measures the decimal part. The digital filter 22 is a low-pass filter that passes the low frequency band of the phase difference digital signal output by the counter +TDC 21 and supplies it to the DCO 23 as an input digital signal. The DCO 23 is a digitally controlled oscillator that generates a signal with a frequency corresponding to the input digital signal from the low-pass filter and outputs an output signal.
　［ＤＣＯ］
　図１４は、本技術の第６の実施の形態におけるＤＣＯ２３の基本回路の構成例を示す図である。 [DCO]
FIG. 14 is a diagram showing a configuration example of a basic circuit of the DCO 23 according to the sixth embodiment of the present technology.
　ＤＣＯ２３は、所定の発振周波数により発振動作を行う発振器１１０を備える。また、ＤＣＯ２３は、同図におけるａおよびｂに示すようにＤＡＣ１６０を備える。このＤＡＣ（Digital Analog Converter）１６０は、デジタルフィルタ２２からのデジタル値をアナログ値に変換して、発振器１１０に供給するものである。この変換されたアナログ値によって発振器１１０の発振周波数が制御される。 The DCO 23 includes an oscillator 110 that oscillates at a predetermined oscillation frequency. The DCO 23 also includes a DAC 160 as indicated by a and b in FIG. This DAC (Digital Analog Converter) 160 converts the digital value from the digital filter 22 into an analog value and supplies it to the oscillator 110 . The oscillation frequency of oscillator 110 is controlled by this converted analog value.
　このＤＡＣ１６０は、発振器１１０の電源側および接地側の何れに接続してもよい。同図におけるａは、発振器１１０の接地側にＤＡＣ１６０を接続した例である。同図におけるｂは、発振器１１０の電源側にＤＡＣ１６０を接続した例である。すなわち、同図におけるａおよびｂは、互いに極性が異なる例である。 This DAC 160 may be connected to either the power supply side or the ground side of the oscillator 110 . In the figure, a is an example in which the DAC 160 is connected to the ground side of the oscillator 110 . b in the figure is an example in which the DAC 160 is connected to the power supply side of the oscillator 110 . That is, a and b in the figure are examples in which the polarities are different from each other.
　図１５は、本技術の第６の実施の形態におけるＤＣＯ２３の第１の回路構成例を示す図である。 FIG. 15 is a diagram showing a first circuit configuration example of the DCO 23 according to the sixth embodiment of the present technology.
　このＤＣＯ２３の第１の回路構成例は、上述の第１の実施の形態におけるカレントミラー回路による回路構成例（図６）を基本として、入力部にＤＡＣ１６０を設けたものである。すなわち、デジタルフィルタ２２からのデジタル値をＤＡＣ１６０によってアナログ値に変換しており、内部構成は上述の第１の実施の形態と同様にアナログ回路により構成される。 The first circuit configuration example of the DCO 23 is based on the circuit configuration example (FIG. 6) of the current mirror circuit in the above-described first embodiment, and the DAC 160 is provided in the input section. That is, the digital value from the digital filter 22 is converted into an analog value by the DAC 160, and the internal configuration is configured by an analog circuit as in the first embodiment.
　図１６は、本技術の第６の実施の形態におけるＤＣＯ２３の第１の回路構成例の具体例を示す図である。 FIG. 16 is a diagram showing a specific example of the first circuit configuration example of the DCO 23 according to the sixth embodiment of the present technology.
　この具体例では、ＤＡＣ１６０は、電流源１６１と、複数のＮＭＯＳトランジスタ１６２を備える。ＮＭＯＳトランジスタ１６２と電流源１６１との間にはそれぞれスイッチ１６３が設けられる。複数のスイッチ１６３の制御入力端子にはデジタルフィルタ２２からのデジタル値の対応するビットが供給される。これにより、供給されるデジタル値に応じた数のＮＭＯＳトランジスタ１６２に、電流源１６１からの基準電流が流れ、これに応じた電圧がＮＭＯＳトランジスタ１４２および１２１のゲートに印可される。 In this specific example, the DAC 160 comprises a current source 161 and multiple NMOS transistors 162 . A switch 163 is provided between the NMOS transistor 162 and the current source 161 respectively. The control input terminals of the plurality of switches 163 are supplied with corresponding bits of the digital value from the digital filter 22 . As a result, the reference current from the current source 161 flows through the NMOS transistors 162 whose number corresponds to the supplied digital value, and the corresponding voltage is applied to the gates of the NMOS transistors 142 and 121 .
　図１７は、本技術の第６の実施の形態におけるＤＣＯ２３の第２の回路構成例を示す図である。 FIG. 17 is a diagram showing a second circuit configuration example of the DCO 23 according to the sixth embodiment of the present technology.
　このＤＣＯ２３の第２の回路構成例は、発振器１１０の接地側に電流源１２０として複数のＮＭＯＳトランジスタ１２２が接続される。ＮＭＯＳトランジスタ１２２と発振器１１０との間にはそれぞれスイッチ１２３が設けられる。 In this second circuit configuration example of the DCO 23 , a plurality of NMOS transistors 122 are connected as the current source 120 to the ground side of the oscillator 110 . A switch 123 is provided between the NMOS transistor 122 and the oscillator 110 respectively.
　また、発振器１１０の両端には補正電流生成回路１３０として複数のＰＭＯＳトランジスタ１３２が接続される。ＰＭＯＳトランジスタ１３２と接続ノードとの間にはそれぞれスイッチ１３３が設けられる。 A plurality of PMOS transistors 132 are connected to both ends of the oscillator 110 as a correction current generation circuit 130 . A switch 133 is provided between each PMOS transistor 132 and the connection node.
　複数のスイッチ１２３および１３３の制御入力端子にはデジタルフィルタ２２からのデジタル値の対応するビットが供給される。これにより、供給されるデジタル値に応じた数のＰＭＯＳトランジスタ１３２およびＮＭＯＳトランジスタ１２２に電流が流れる。 The control input terminals of the plurality of switches 123 and 133 are supplied with corresponding bits of the digital value from the digital filter 22 . As a result, current flows through the number of PMOS transistors 132 and NMOS transistors 122 corresponding to the supplied digital value.
　この例では、ＮＭＯＳトランジスタ１４２および１２１のゲートには、基準バイアス生成回路１７０から基準バイアス電圧が供給される。 In this example, the reference bias voltage is supplied from the reference bias generation circuit 170 to the gates of the NMOS transistors 142 and 121 .
　図１８は、本技術の第６の実施の形態におけるＤＣＯ２３の第２の回路構成例の具体例を示す図である。 FIG. 18 is a diagram showing a specific example of a second circuit configuration example of the DCO 23 according to the sixth embodiment of the present technology.
　この具体例では、基準バイアス生成回路１７０は、電流源１７１およびＮＭＯＳトランジスタ１７２を備える。ＮＭＯＳトランジスタ１７２には、電流源１７１から供給された基準電流が流れる。これにより、ＮＭＯＳトランジスタ１７２のゲート電位と同じ電圧がＮＭＯＳトランジスタ１４２および１２２のゲートに印可される。 In this specific example, the reference bias generation circuit 170 includes a current source 171 and an NMOS transistor 172. A reference current supplied from the current source 171 flows through the NMOS transistor 172 . Thereby, the same voltage as the gate potential of NMOS transistor 172 is applied to the gates of NMOS transistors 142 and 122 .
　このように、本技術の第６の実施の形態によれば、デジタルＰＬＬ回路においても、電源電圧の変動に応じて能動的に補正を行うことができる。 In this way, according to the sixth embodiment of the present technology, even in the digital PLL circuit, it is possible to actively perform correction in accordance with fluctuations in the power supply voltage.
　なお、上述の実施の形態は本技術を具現化するための一例を示したものであり、実施の形態における事項と、特許請求の範囲における発明特定事項とはそれぞれ対応関係を有する。同様に、特許請求の範囲における発明特定事項と、これと同一名称を付した本技術の実施の形態における事項とはそれぞれ対応関係を有する。ただし、本技術は実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において実施の形態に種々の変形を施すことにより具現化することができる。 It should be noted that the above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the matters specifying the invention in the scope of claims have corresponding relationships. Similarly, the matters specifying the invention in the scope of claims and the matters in the embodiments of the present technology with the same names have corresponding relationships. However, the present technology is not limited to the embodiments, and can be embodied by various modifications to the embodiments without departing from the scope of the present technology.
　なお、本明細書に記載された効果はあくまで例示であって、限定されるものではなく、また、他の効果があってもよい。 It should be noted that the effects described in this specification are only examples and are not limited, and other effects may also occur.
　なお、本技術は以下のような構成もとることができる。
（１）所定の発振周波数により発振動作を行う発振器と、
　前記発振器の電源端子および接地端子の少なくとも一方に接続し、入力電圧に応じて前記発振器の前記発振周波数を制御する発振周波数制御回路と、
　前記発振器と前記発振周波数制御回路との間の接続ノードに接続して、前記電源端子における電源電圧の変動に応じた補正電流を前記接続ノードに対して供給する補正電流生成回路と、
　前記補正電流生成回路が前記補正電流を生成するためのバイアス電圧を前記補正電流生成回路に対して供給するバイアス生成回路と
を具備する発振回路。
（２）前記発振周波数制御回路は、ＰＭＯＳトランジスタおよびＮＭＯＳトランジスタの一方からなり、そのゲート端子には前記入力電圧として前記発振周波数を制御するための電圧が供給される電圧制御電流源であり、
　前記補正電流生成回路は、ＰＭＯＳトランジスタおよびＮＭＯＳトランジスタの前記一方とは異なる他方からなり、そのゲート端子には前記バイアス電圧が供給される
前記（１）に記載の発振回路。
（３）前記バイアス生成回路は、カレントミラー回路により前記補正電流生成回路の前記ゲート端子に対する前記バイアス電圧を生成する
前記（２）に記載の発振回路。
（４）前記バイアス生成回路は、前記補正電流生成回路の前記ゲート端子に接続するローパスフィルタを備える
前記（２）に記載の発振回路。
（５）前記発振器は、複数段のインバータを環状に接続したリングオシレータであり、
　前記バイアス生成回路は、１段分の前記インバータをレプリカ回路として備える
前記（２）または（４）に記載の発振回路。
（６）前記バイアス生成回路は、
　前記発振周波数制御回路のドレインコンダクタンスを検知するドレインコンダクタンス検知回路と、
　前記補正電流生成回路のトランスコンダクタンスを検知するトランスコンダクタンス検知回路と、
　前記発振周波数制御回路のドレインコンダクタンスと前記補正電流生成回路のトランスコンダクタンスとが等しくなるようにキャリブレーションを行うキャリブレーション回路とを備える
前記（２）から（５）のいずれかに記載の発振回路。
（７）前記入力電圧は、アナログ値である
前記（１）から（６）のいずれかに記載の発振回路。
（８）前記入力電圧は、デジタル値である
前記（１）から（６）のいずれかに記載の発振回路。
（９）前記入力電圧をデジタル信号からアナログ信号に変換して前記発振周波数制御回路に供給するデジタルアナログ変換器をさらに具備する
前記（８）に記載の発振回路。
（１０）前記入力電圧は、デジタル値であって、
　前記発振周波数制御回路は、ＰＭＯＳトランジスタおよびＮＭＯＳトランジスタの一方からなってそのゲート端子には前記入力電圧として前記発振周波数を制御するための電圧が供給される電圧制御電流源と第１のスイッチとを直列接続した回路を複数組並列接続し、前記第１のスイッチは前記入力電圧の対応するビット値によってそれぞれ制御され、
　前記補正電流生成回路は、ＰＭＯＳトランジスタおよびＮＭＯＳトランジスタの前記一方とは異なる他方の並列接続からなってそのゲート端子には前記バイアス電圧が供給されるトランジスタと第２のスイッチとを直列接続した回路を複数組並列接続し、前記第２のスイッチは前記入力電圧の対応するビット値によってそれぞれ制御される
前記（１）から（６）、（８）または（９）のいずれかに記載の発振回路。
（１１）入力信号と出力信号の位相差に応じた位相差電圧を出力する位相比較器と、
　前記位相差電圧の低周波域を通過させて入力電圧として供給するローパスフィルタと、
　前記入力電圧に応じた周波数の信号を生成して前記出力信号を出力する発振回路とを具備し、
　前記発振回路は、
　所定の発振周波数により発振動作を行う発振器と、
　前記発振器の電源端子および接地端子の少なくとも一方に接続し、入力電圧に応じて前記発振器の前記発振周波数を制御する発振周波数制御回路と、
　前記発振器と前記発振周波数制御回路との間の接続ノードに接続して、前記電源端子における電源電圧の変動に応じた補正電流を前記接続ノードに対して供給する補正電流生成回路と、
　前記補正電流生成回路が前記補正電流を生成するためのバイアス電圧を前記補正電流生成回路に対して供給するバイアス生成回路とを備える
ＰＬＬ回路。 Note that the present technology can also have the following configuration.
(1) an oscillator that oscillates at a predetermined oscillation frequency;
an oscillation frequency control circuit connected to at least one of a power supply terminal and a ground terminal of the oscillator and controlling the oscillation frequency of the oscillator according to an input voltage;
a correction current generation circuit connected to a connection node between the oscillator and the oscillation frequency control circuit to supply a correction current to the connection node according to fluctuations in the power supply voltage at the power supply terminal;
and a bias generation circuit that supplies a bias voltage for the correction current generation circuit to generate the correction current to the correction current generation circuit.
(2) the oscillation frequency control circuit is a voltage controlled current source comprising one of a PMOS transistor and an NMOS transistor and having a gate terminal supplied with a voltage for controlling the oscillation frequency as the input voltage;
The oscillator circuit according to (1), wherein the correction current generating circuit is composed of the other of a PMOS transistor and an NMOS transistor, and the gate terminal thereof is supplied with the bias voltage.
(3) The oscillator circuit according to (2), wherein the bias generation circuit generates the bias voltage for the gate terminal of the correction current generation circuit by a current mirror circuit.
(4) The oscillator circuit according to (2), wherein the bias generation circuit includes a low-pass filter connected to the gate terminal of the correction current generation circuit.
(5) the oscillator is a ring oscillator in which a plurality of stages of inverters are connected in a ring;
The oscillator circuit according to (2) or (4), wherein the bias generation circuit includes one stage of the inverter as a replica circuit.
(6) the bias generation circuit,
a drain conductance detection circuit for detecting the drain conductance of the oscillation frequency control circuit;
a transconductance detection circuit that detects the transconductance of the correction current generation circuit;
The oscillator circuit according to any one of (2) to (5) above, further comprising a calibration circuit that performs calibration so that the drain conductance of the oscillation frequency control circuit and the transconductance of the correction current generation circuit are equal.
(7) The oscillator circuit according to any one of (1) to (6), wherein the input voltage is an analog value.
(8) The oscillator circuit according to any one of (1) to (6), wherein the input voltage is a digital value.
(9) The oscillator circuit according to (8), further comprising a digital-analog converter that converts the input voltage from a digital signal to an analog signal and supplies the analog signal to the oscillation frequency control circuit.
(10) The input voltage is a digital value,
The oscillation frequency control circuit comprises one of a PMOS transistor and an NMOS transistor, and includes a voltage controlled current source whose gate terminal is supplied with a voltage for controlling the oscillation frequency as the input voltage, and a first switch. a plurality of sets of series-connected circuits connected in parallel, the first switches each being controlled by a corresponding bit value of the input voltage;
The correction current generation circuit is a circuit in which a second switch and a PMOS transistor and an NMOS transistor, which are connected in parallel to each other, are connected in series, and the bias voltage is supplied to the gate terminal of the transistor. The oscillator circuit according to any one of (1) to (6), (8) or (9), wherein a plurality of sets are connected in parallel, and the second switches are controlled by corresponding bit values of the input voltage.
(11) a phase comparator that outputs a phase difference voltage corresponding to the phase difference between the input signal and the output signal;
a low-pass filter that passes a low-frequency region of the phase difference voltage and supplies it as an input voltage;
an oscillation circuit that generates a signal having a frequency corresponding to the input voltage and outputs the output signal;
The oscillation circuit is
an oscillator that oscillates at a predetermined oscillation frequency;
an oscillation frequency control circuit connected to at least one of a power supply terminal and a ground terminal of the oscillator and controlling the oscillation frequency of the oscillator according to an input voltage;
a correction current generation circuit connected to a connection node between the oscillator and the oscillation frequency control circuit to supply a correction current to the connection node according to fluctuations in the power supply voltage at the power supply terminal;
A PLL circuit comprising a bias generation circuit that supplies a bias voltage for the correction current generation circuit to generate the correction current to the correction current generation circuit.
　１１　位相比較器
　１２　アナログフィルタ
　１３　ＶＣＯ（Voltage Controlled Oscillator）
　１４　分周器
　２１　カウンタ＋ＴＤＣ（Time to Digital Converter）
　２２　デジタルフィルタ
　２３　ＤＣＯ（Digitally Controlled Oscillator）
　２４　分周器
　１１０　発振器
　１１１　ＰＭＯＳトランジスタ
　１１２　ＮＭＯＳトランジスタ
　１２０　電流源
　１２１、１２２　ＮＭＯＳトランジスタ
　１２３　スイッチ
　１３０　補正電流生成回路
　１３１、１３２　ＰＭＯＳトランジスタ
　１３３　スイッチ
　１４０　バイアス生成回路
　１４１、１４６　ＰＭＯＳトランジスタ
　１４２、１４７　ＮＭＯＳトランジスタ
　１４８　抵抗
　１４９　キャパシタ
　１５０　レギュレータ
　１６０　ＤＡＣ（Digital Analog Converter）
　１６１　電流源
　１６２　ＮＭＯＳトランジスタ
　１６３　スイッチ
　１７０　基準バイアス生成回路
　１７１　電流源
　１７２　ＮＭＯＳトランジスタ
　２１０　ｇdsn検知回路
　２１１、２１３、２１７、２１８、２２１、２２２　ＮＭＯＳトランジスタ
　２１２、２１５、２１６、２１９　ＰＭＯＳトランジスタ
　２１４、２２３　抵抗
　２３０　ｇmp検知／キャリブレーション回路
　２３１、２３３、２３５、２３８、２４１、２４２　ＮＭＯＳトランジスタ
　２３２、２３６　ＰＭＯＳトランジスタ
　２３４、２４３　抵抗
　２４９　オペアンプ 11 phase comparator 12 analog filter 13 VCO (Voltage Controlled Oscillator)
14 Frequency divider 21 Counter + TDC (Time to Digital Converter)
22 Digital Filter 23 DCO (Digitally Controlled Oscillator)
24 frequency divider 110 oscillator 111 PMOS transistor 112 NMOS transistor 120 current source 121, 122 NMOS transistor 123 switch 130 correction current generation circuit 131, 132 PMOS transistor 133 switch 140 bias generation circuit 141, 146 PMOS transistors 142, 147 NMOS transistor 148 resistor 149 Capacitor 150 Regulator 160 DAC (Digital Analog Converter)
161 current source 162 NMOS transistor 163 switch 170 reference bias generation circuit 171 current source 172 NMOS transistor 210 gdsn detection circuit 211, 213, 217, 218, 221, 222 NMOS transistor 212, 215, 216, 219 PMOS transistor 214, 223 resistor 230 gmp detection/ calibration circuit 231, 233, 235, 238, 241, 242 NMOS transistors 232, 236 PMOS transistors 234, 243 resistor 249 operational amplifier

Claims (11)

  1. 　所定の発振周波数により発振動作を行う発振器と、
    　前記発振器の電源端子および接地端子の少なくとも一方に接続し、入力電圧に応じて前記発振器の前記発振周波数を制御する発振周波数制御回路と、
    　前記発振器と前記発振周波数制御回路との間の接続ノードに接続して、前記電源端子における電源電圧の変動に応じた補正電流を前記接続ノードに対して供給する補正電流生成回路と、
    　前記補正電流生成回路が前記補正電流を生成するためのバイアス電圧を前記補正電流生成回路に対して供給するバイアス生成回路と
    を具備する発振回路。     an oscillator that oscillates at a predetermined oscillation frequency;
    an oscillation frequency control circuit connected to at least one of a power supply terminal and a ground terminal of the oscillator and controlling the oscillation frequency of the oscillator according to an input voltage;
    a correction current generation circuit connected to a connection node between the oscillator and the oscillation frequency control circuit to supply a correction current to the connection node according to fluctuations in the power supply voltage at the power supply terminal;
    and a bias generation circuit that supplies a bias voltage for the correction current generation circuit to generate the correction current to the correction current generation circuit.
  2. 　前記発振周波数制御回路は、ＰＭＯＳトランジスタおよびＮＭＯＳトランジスタの一方からなり、そのゲート端子には前記入力電圧として前記発振周波数を制御するための電圧が供給される電圧制御電流源であり、
    　前記補正電流生成回路は、ＰＭＯＳトランジスタおよびＮＭＯＳトランジスタの前記一方とは異なる他方からなり、そのゲート端子には前記バイアス電圧が供給される
    請求項１記載の発振回路。     The oscillation frequency control circuit is a voltage controlled current source which is composed of one of a PMOS transistor and an NMOS transistor, and whose gate terminal is supplied with a voltage for controlling the oscillation frequency as the input voltage,
    2. The oscillator circuit according to claim 1, wherein said correction current generation circuit comprises the other of a PMOS transistor and an NMOS transistor, the gate terminal of which is supplied with said bias voltage.
  3. 　前記バイアス生成回路は、カレントミラー回路により前記補正電流生成回路の前記ゲート端子に対する前記バイアス電圧を生成する
    請求項２記載の発振回路。     3. The oscillator circuit according to claim 2, wherein said bias generation circuit generates said bias voltage for said gate terminal of said correction current generation circuit by means of a current mirror circuit.
  4. 　前記バイアス生成回路は、前記補正電流生成回路の前記ゲート端子に接続するローパスフィルタを備える
    請求項２記載の発振回路。     3. The oscillator circuit according to claim 2, wherein said bias generation circuit comprises a low-pass filter connected to said gate terminal of said correction current generation circuit.
  5. 　前記発振器は、複数段のインバータを環状に接続したリングオシレータであり、
    　前記バイアス生成回路は、１段分の前記インバータをレプリカ回路として備える
    請求項２記載の発振回路。     The oscillator is a ring oscillator in which multiple stages of inverters are connected in a ring,
    3. The oscillation circuit according to claim 2, wherein said bias generation circuit comprises one stage of said inverter as a replica circuit.
  6. 　前記バイアス生成回路は、
    　前記発振周波数制御回路のドレインコンダクタンスを検知するドレインコンダクタンス検知回路と、
    　前記補正電流生成回路のトランスコンダクタンスを検知するトランスコンダクタンス検知回路と、
    　前記発振周波数制御回路のドレインコンダクタンスと前記補正電流生成回路のトランスコンダクタンスとが等しくなるようにキャリブレーションを行うキャリブレーション回路とを備える
    請求項２記載の発振回路。     The bias generation circuit is
    a drain conductance detection circuit for detecting the drain conductance of the oscillation frequency control circuit;
    a transconductance detection circuit that detects the transconductance of the correction current generation circuit;
    3. The oscillation circuit according to claim 2, further comprising a calibration circuit for performing calibration so that the drain conductance of the oscillation frequency control circuit and the transconductance of the correction current generation circuit are equal.
  7. 　前記入力電圧は、アナログ値である
    請求項１記載の発振回路。     2. The oscillator circuit according to claim 1, wherein said input voltage is an analog value.
  8. 　前記入力電圧は、デジタル値である
    請求項１記載の発振回路。     2. The oscillator circuit according to claim 1, wherein said input voltage is a digital value.
  9. 　前記入力電圧をデジタル信号からアナログ信号に変換して前記発振周波数制御回路に供給するデジタルアナログ変換器をさらに具備する
    請求項８記載の発振回路。     9. The oscillator circuit according to claim 8, further comprising a digital-to-analog converter that converts the input voltage from a digital signal to an analog signal and supplies the converted signal to the oscillation frequency control circuit.
  10. 　前記入力電圧は、デジタル値であって、
    　前記発振周波数制御回路は、ＰＭＯＳトランジスタおよびＮＭＯＳトランジスタの一方からなってそのゲート端子には前記入力電圧として前記発振周波数を制御するための電圧が供給される電圧制御電流源と第１のスイッチとを直列接続した回路を複数組並列接続し、前記第１のスイッチは前記入力電圧の対応するビット値によってそれぞれ制御され、
    　前記補正電流生成回路は、ＰＭＯＳトランジスタおよびＮＭＯＳトランジスタの前記一方とは異なる他方の並列接続からなってそのゲート端子には前記バイアス電圧が供給されるトランジスタと第２のスイッチとを直列接続した回路を複数組並列接続し、前記第２のスイッチは前記入力電圧の対応するビット値によってそれぞれ制御される
    請求項１記載の発振回路。     The input voltage is a digital value,
    The oscillation frequency control circuit comprises one of a PMOS transistor and an NMOS transistor, and includes a voltage controlled current source whose gate terminal is supplied with a voltage for controlling the oscillation frequency as the input voltage, and a first switch. a plurality of sets of series-connected circuits connected in parallel, the first switches each being controlled by a corresponding bit value of the input voltage;
    The correction current generation circuit is a circuit in which a second switch and a PMOS transistor and an NMOS transistor, which are connected in parallel to each other, are connected in series, and the bias voltage is supplied to the gate terminal of the transistor. 2. The oscillator circuit according to claim 1, wherein a plurality of sets are connected in parallel, and said second switches are each controlled by a corresponding bit value of said input voltage.
  11. 　入力信号と出力信号の位相差に応じた位相差電圧を出力する位相比較器と、
    　前記位相差電圧の低周波域を通過させて入力電圧として供給するローパスフィルタと、
    　前記入力電圧に応じた周波数の信号を生成して前記出力信号を出力する発振回路とを具備し、
    　前記発振回路は、
    　所定の発振周波数により発振動作を行う発振器と、
    　前記発振器の電源端子および接地端子の少なくとも一方に接続し、入力電圧に応じて前記発振器の前記発振周波数を制御する発振周波数制御回路と、
    　前記発振器と前記発振周波数制御回路との間の接続ノードに接続して、前記電源端子における電源電圧の変動に応じた補正電流を前記接続ノードに対して供給する補正電流生成回路と、
    　前記補正電流生成回路が前記補正電流を生成するためのバイアス電圧を前記補正電流生成回路に対して供給するバイアス生成回路とを備える
    ＰＬＬ回路。     a phase comparator that outputs a phase difference voltage corresponding to the phase difference between the input signal and the output signal;
    a low-pass filter that passes a low-frequency region of the phase difference voltage and supplies it as an input voltage;
    an oscillation circuit that generates a signal having a frequency corresponding to the input voltage and outputs the output signal;
    The oscillation circuit is
    an oscillator that oscillates at a predetermined oscillation frequency;
    an oscillation frequency control circuit connected to at least one of a power supply terminal and a ground terminal of the oscillator and controlling the oscillation frequency of the oscillator according to an input voltage;
    a correction current generation circuit connected to a connection node between the oscillator and the oscillation frequency control circuit to supply a correction current to the connection node according to fluctuations in the power supply voltage at the power supply terminal;
    A PLL circuit comprising a bias generation circuit that supplies a bias voltage for the correction current generation circuit to generate the correction current to the correction current generation circuit.
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JPH1098356A (en) * 1996-07-15 1998-04-14 Mitsubishi Electric Corp Voltage controlled oscillator
WO2017195614A1 (en) * 2016-05-11 2017-11-16 ソニー株式会社 Oscillation circuit, oscillation method, and pll circuit
WO2020105182A1 (en) * 2018-11-22 2020-05-28 株式会社ソシオネクスト Voltage-controlled oscillator and pll circuit in which same is used

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1098356A (en) * 1996-07-15 1998-04-14 Mitsubishi Electric Corp Voltage controlled oscillator
WO2017195614A1 (en) * 2016-05-11 2017-11-16 ソニー株式会社 Oscillation circuit, oscillation method, and pll circuit
WO2020105182A1 (en) * 2018-11-22 2020-05-28 株式会社ソシオネクスト Voltage-controlled oscillator and pll circuit in which same is used

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