WO2023010879A1 - Memory management method and apparatus, and computer device - Google Patents

Abstract

The present application relates to a memory management method and apparatus, and a computer device. The method comprises: receiving a buffer allocation instruction from an application, wherein the buffer allocation instruction is used to request the allocation of a buffer for the application in a memory; allocating a buffer for the application in a cache of the memory; and returning the address of the buffer in the memory. In the memory management method and apparatus, and the computer device provided in the present application, the memory space can be effectively saved.

Description

Memory management method, device and computer equipment

This application claims the priority of the Chinese patent application with the application number 202110892745.3 and the application name "memory management method, device and computer equipment" submitted to the China Patent Office on August 4, 2021, the entire contents of which are incorporated in this application by reference middle.

technical field

The present application relates to the field of data storage, in particular to a memory management method, device and computer equipment.

Background technique

In recent years, with the enhancement of processor computing power and the increase of data scale, longer data access time has gradually become the main factor restricting the speed of application operation.

When an application is running, it needs to read the data in the memory into the memory first, then use the data in the memory to perform calculations, write the calculation results into the memory, and finally store them in the memory for long-term storage. Usually, the system generally divides a storage space in the memory as a cache area (Cache), so as to speed up the speed of reading and writing data between the memory and the application. When an application writes data, it is not written directly to the memory, but is first written to the cache. Since the reading and writing speed of the cache area is very fast, the application can complete data writing quickly, and then the application can release resources for performing other tasks. The data temporarily stored in the cache area can be slowly written into the memory when the system is idle. When the application reads data, if there is data required by the application in the cache, it can be directly and quickly read in. Because the read and write speed of the memory is slower than the speed of the processor executing the application. In order to reduce the impact of a large number of sudden read and write operations on the processor in a short period of time, the system can divide a storage space in the memory as a buffer (Buffer) to temporarily store the data that the application needs to use. FIG. 1 shows a schematic structural diagram of a storage system in the related art. As shown in FIG. 1 , a storage system includes a memory and a storage, and the memory is divided into a cache area and a buffer. The system can first store the data that the application needs to use in the buffer, and when the amount of data in the buffer reaches a certain amount, the application reads the data in the buffer for calculation. When the amount of data in the buffer does not reach a certain amount, the application can perform other tasks. In the related technology, by optimizing the data interaction mode between the application and the cache area, the data interaction process between the application and the memory is optimized, and the reading and writing speed of the upper layer application is improved.

Referring to Figure 1, in related technologies, in terms of storage space, buffers and buffers occupy more memory space, resulting in a larger memory overhead; at the same time, the same data in the application buffer and memory cache One copy is copied in each area, resulting in a waste of memory resources. At the same time, the data reading and writing between the application and the cache area is divided into data reading and writing between the buffer area and the data reading and writing between the application and the buffer area, which increases the data interaction between the application and the memory. Latency consumes more processor computing resources. Therefore, how to provide an efficient memory management method that reduces waste of memory resources and read/write delays has become an urgent problem to be solved.

Contents of the invention

In view of this, a memory management method, device and computer equipment are proposed, which can save memory space.

In a first aspect, an embodiment of the present application provides a memory management method, the method comprising: receiving a buffer allocation instruction from an application, where the buffer allocation instruction is used to request to allocate a buffer in the memory for the application , after the data stored in the buffer reaches a certain amount, the application obtains the data in the buffer at one time; allocates a buffer for the application in the buffer area of the memory; returns the buffer The address of the region in said memory.

In the embodiment of the present application, by allocating the buffer in the buffer as the buffer of the application, the buffer of the buffer is reused, so that the buffer of the application no longer occupies additional memory space, reducing the occupation of memory resources. Memory resources are saved.

According to the first aspect, in the first possible implementation of the memory management method, the buffer allocation instruction includes the size of the buffer, and in the buffer area of the memory, the Allocating a buffer for the application includes: allocating a buffer of the size for the application in the buffer area of the memory, where the size is smaller than the size of the buffer area.

In this way, by indicating the size of the memory space in the buffer allocation instruction, the buffer can be allocated for the application on demand, which not only meets the requirements of the application, but also reduces the occupation of storage resources in the buffer area.

According to the first aspect, or the first possible implementation of the first aspect, in a second possible implementation of the memory management method, the method further includes: receiving a memory release instruction from the application, The memory release instruction is used to request to release the buffer of the application, and the memory release instruction includes the address of the buffer in the memory; release the buffer.

In this way, by releasing the buffer allocated for the application, the application will not occupy the memory resource all the time, and the dynamic allocation of the buffer is realized, thereby saving the memory resource to a large extent.

According to the first aspect, or any possible implementation of the above first aspect, in a third possible implementation of the memory management method, the method further includes: receiving data read from the application instruction, the data read instruction is used to request to transmit the data to be read to the application; when the data to be read is outside the cache area, read the data to be read from the memory to the in the buffer; and transfer the data in the buffer to the application.

In this way, the buffer located in the buffer area can directly interact with the memory for data, eliminating the need to copy data between the buffer area and the buffer area, achieving the effects of reducing read and write delays and saving processor computing resources.

According to the third possible implementation of the first aspect, in the fourth possible implementation of the memory management method, transmitting the data in the buffer to the application specifically includes: When the amount of data stored in the storage space buffer allocated by the application is greater than a first preset threshold, the data in the buffer is transferred to the application; or, all the data to be read required by the application has been read When fetching into the buffer, transfer the data in the buffer to the application; or, when the processor executing the application is in an idle state, transfer the data in the buffer to the application .

In this way, sending the data to the application when the amount of data stored in the buffer is large can reduce the time and resources consumed by the processor executing the application waiting for more data.

According to the first aspect, or any possible implementation of the above first aspect, in a fifth possible implementation of the memory management method, the method further includes: receiving data written from the application instruction, the data writing instruction is used to request to store the data to be written in the application; store the data to be written in the buffer; and remove the data to be written from the buffer stored in memory.

In this way, the buffer located in the buffer area can directly interact with the memory for data, eliminating the need to copy data between the buffer area and the buffer area, achieving the effects of reducing read and write delays and saving processor computing resources.

According to the fifth possible implementation of the first aspect, in the sixth possible implementation of the memory management method, when the amount of data stored in the buffer is greater than a second preset threshold, the storing the data to be written from the buffer into the memory; or, when all the data to be written required by the application has been stored in the buffer, storing the data to be written from the buffer to the memory or, when receiving a write completion instruction, store the data to be written from the buffer into the memory; or, when receiving a write pause instruction, store the data to be written from the buffer to in memory.

In this way, when the amount of data stored in the buffer is large, the data is transferred to the area in the buffer area other than the buffer area, thereby reducing the number of times of data copying and saving processor computing resources.

In a second aspect, an embodiment of the present application provides a memory management device, the device comprising: a first receiving module, configured to receive a buffer allocation instruction from an application, and the buffer allocation instruction is used to request for the The application allocates a buffer in the memory; the allocation module is used to allocate the buffer for the application in the buffer area of the memory; the return module is used to return the address of the buffer in the memory.

According to the second aspect, in the first possible implementation manner of the memory management device, the buffer allocation instruction includes the size of the buffer, and the allocation module is further configured to: In the buffer area, a buffer of the size is allocated to the application, and the size is smaller than the size of the buffer area.

According to the second aspect, or the first possible implementation manner of the second aspect, in the second possible implementation manner of the memory management device, the device further includes: a second receiving module, configured to receive the The memory release instruction of the application, the memory release instruction is used to request to release the buffer of the application, and the memory release instruction includes the address of the buffer in the memory; the release module is used to release the buffer buffer.

According to the second aspect, or any possible implementation of the above second aspect, in a third possible implementation of the memory management device, the device further includes: a third receiving module, configured to receive the The data reading instruction of the application, the data reading instruction is used to request to transmit the data to be read to the application; the reading module is used to, when the data to be read is located outside the cache area, reading the data to be read from the memory into the buffer; a transmission module, configured to transmit the data in the buffer to the application.

According to the third possible implementation of the second aspect, in the fourth possible implementation of the memory management device, the transmission module is further configured to: the amount of data stored in the buffer allocated for the application When it is greater than the first preset threshold, the data in the buffer is transferred to the application; or, when all the data to be read required by the application has been read into the buffer, the buffer is transferred to The data in the area is transferred to the application; or, when the processor executing the application is in an idle state, the data in the buffer is transferred to the application. .

According to the second aspect, or any possible implementation of the above second aspect, in a fifth possible implementation of the memory management device, the device further includes: a fourth receiving module, configured to receive the The data writing instruction of the application, the data writing instruction is used to request to store the data to be written in the application; the writing module is used to store the data to be written in the buffer; A module, configured to store the data to be written from the buffer into a memory.

According to a fifth possible implementation of the second aspect, in a sixth possible implementation of the memory management device, the storage module is further configured to: the amount of data stored in the buffer is greater than the second preset threshold, store the data to be written from the buffer into the memory; or, when all the data to be written required by the application has been stored in the buffer, store the data to be written from the The buffer is stored in the memory; or, when the write completion instruction is received, the data to be written is stored from the buffer to the memory; or, when the write suspend instruction is received, the data to be written is stored from the The buffer is stored in memory.

In a third aspect, the present application provides a data access method, which is executed by a storage system, the storage system includes a memory, a memory, and a memory manager, the memory includes a cache area and a buffer, and the buffer is located in the cache area, the method includes: receiving a data read instruction, the data read instruction is used to request to transmit the data to be read to the application; when the data to be read is located outside the buffer area, the The data to be read is read from the memory into the buffer; and the data in the buffer is sent to the application.

In a fourth aspect, an embodiment of the present application provides a computer device, the computer device includes a memory, a memory, and a memory manager, where the memory manager can implement the above-mentioned first aspect or multiple possible implementations of the first aspect One or more of the memory management methods.

In the fifth aspect, the embodiments of the present application provide a computer program product, including computer readable code, or a non-volatile computer readable storage medium bearing computer readable code, when the computer readable code is stored in an electronic When running in the device, the processor in the electronic device executes the memory management method of the first aspect or one or more of the multiple possible implementation manners of the first aspect.

In a sixth aspect, the embodiments of the present application provide a computer storage medium on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the method described in any one of claims 1 to 7 is implemented.

These and other aspects of the present application will be made more apparent in the following description of the embodiment(s).

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the application and, together with the specification, serve to explain the principles of the application.

FIG. 1 shows a schematic structural diagram of a storage system in the related art;

FIG. 2 shows a schematic structural diagram of a storage system in an embodiment of the present application;

FIG. 3 shows a schematic flow chart of the memory management method provided by the present application;

Fig. 4 shows the allocation diagram of the buffer zone in the embodiment of the present application;

FIG. 5 shows a schematic flow diagram of a memory management method provided by an embodiment of the present application;

FIG. 6 shows a schematic diagram of the process of reading data by an application in the embodiment of the present application;

FIG. 7 shows a schematic flowchart of a memory management method provided by an embodiment of the present application;

FIG. 8a shows a schematic diagram of interface redirection in an embodiment of the present application;

FIG. 8b shows a related technology and an interface implementation diagram in the embodiment of the present application;

FIG. 9 shows a schematic diagram of data interaction in the embodiment of the present application in a big data scenario;

FIG. 10 shows a schematic structural diagram of a memory management device provided by an embodiment of the present application;

FIG. 11 shows a schematic structural diagram of a computer device provided by an embodiment of the present application.

Detailed ways

Various exemplary embodiments, features, and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numbers in the figures indicate functionally identical or similar elements. While various aspects of the embodiments are shown in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as superior or better than other embodiments.

In addition, in order to better illustrate the present application, numerous specific details are given in the following specific implementation manners. It will be understood by those skilled in the art that the present application may be practiced without certain of the specific details. In some instances, methods, means, components and circuits well known to those skilled in the art have not been described in detail in order to highlight the gist of the present application.

FIG. 2 shows a schematic structural diagram of a storage system in an embodiment of the present application. As shown in FIG. 2 , the storage system 20 includes a memory manager 21 , a memory 22 and a storage 23 . Wherein, the memory 22 may be used for temporarily storing data, and the memory 23 may be used for persistently storing data. By way of example, memory 22 may be used to store pre-stored, intermediate, and outcome data during sample collection, modeling, and prediction. Memory 22 may include read-only memory and random-access memory, and may be either volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Among them, the non-volatile memory can be read-only memory (read-only memory, ROM), programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (erasable PROM, EPROM), electronic Erasable programmable read-only memory (electrically EPROM, EEPROM) or flash memory. The volatile memory can be random access memory (RAM), which acts as external cache memory. By way of illustration and not limitation, many forms of RAM are available such as static random access memory (static RAM, SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM), Double data rate synchronous dynamic random access memory (double data date SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous connection dynamic random access memory (synchlink DRAM, SLDRAM) and direct Memory bus random access memory (direct rambus RAM, DR RAM). The memory 23 can be a magnetic disk, a hard disk, an optical disk, and the like. The reading and writing speed of the memory 23 is relatively slow, and the reading and writing speed of the memory 22 is relatively fast. The memory manager 21 is used to manage the storage space of the memory. In the embodiment of the present application, the memory manager 21 has opened up a piece of storage space in the memory 22 as a cache area, and has opened up a piece of storage space in the cache area as an application 10 buffers. Specifically, the memory manager 21 may reserve an inherent storage space in the memory 22 as a cache area, and dynamically allocate a piece of storage space in the cache area as a buffer when the application 10 is running. Understandably, the size of the buffer is smaller than the size of the cache. Referring to FIG. 2 , it can be seen that in the embodiment of the present application, the buffer and the cache area reuse a part of the storage space of the memory 22 , which reduces the occupation of memory space and saves memory resources.

FIG. 3 shows a schematic flowchart of the memory management method provided by the present application. The method may be executed by the memory manager 21 in the storage system 20 shown in FIG. 2 . As shown in Figure 3, the method may include:

Step S401 , the memory manager 21 receives a buffer allocation instruction from the application 10 .

Wherein, the buffer allocation instruction is used to request the application 10 to allocate storage space in the memory. The application 10 may submit a buffer allocation instruction when starting to run. After receiving the buffer allocation instruction, the memory manager 21 can allocate a storage space in the memory 22 for the application 10, and the storage space can be used as a buffer (buffer for short) of the application 10. The application 10 may store data that needs to be interacted with (including data to be written and data to be read) in the buffer, so as to balance the speed between the processor executing the application 10 and the memory 22 .

In a possible implementation, the buffer allocation instruction may include the size (or capacity) of the storage space allocated for the application 10, that is, the size of the buffer, and the buffer allocation instruction is used to request for the application 10 Allocate storage of that size in the space.

Step S402 , the memory manager 21 allocates storage space for the application 10 in the buffer area of the memory 22 as a buffer of the application 10 .

In the embodiment of the present application, in response to the buffer allocation instruction, the memory manager 21 may allocate storage space for the application 10 in the buffer area of the memory 22 as a buffer of the application 10 . When the buffer allocation instruction includes the size of the storage space allocated for the application, the memory manager 21 may allocate a storage space of the size indicated by the buffer allocation instruction for the application 10 in the cache area of the memory 22 . FIG. 4 shows a schematic diagram of buffer allocation in the embodiment of the present application. As shown in FIG. 4 , the memory manager 21 allocates storage space in the cache area as the buffer of the application 10 in response to the buffer allocation instruction.

It can be understood that, in the cache area except the buffer zone, data read from the memory 23 and data to be written into the memory 23 can still be stored. In addition, areas other than the buffer area in the cache area have their own elimination mechanism. For example, when the amount of cached data exceeds the maximum capacity of this area, data that has not been used for a long time or has a long storage time will be deleted from this area. long data etc. The embodiment of this application does not limit the elimination mechanism.

Step S403 , the memory manager 21 returns the address of the buffer of the application in the memory 22 to the application 10 .

After the memory manager 21 returns the address of the buffer in the memory 22 to the application 10, the application 10 can read data from this address when it needs to read data, and can write data to this address when it needs to write data. In an example, the memory manager 21 may return a pointer corresponding to the buffer, and the pointer points to the first address of the storage space occupied by the buffer in the memory 22 .

In the embodiment of this application, by allocating storage space in the cache area as the application buffer, the storage space occupied by the cache area in the memory is reused, so that the application buffer no longer occupies additional memory space, reducing the need for memory Occupation of resources saves memory resources.

Application buffers are allocated dynamically. When the application finishes running, the memory manager 21 can reclaim the buffer allocated for the application 10 to further save memory resources. In a possible implementation manner, the memory management method provided by the embodiment of the present application further includes: receiving a memory release instruction from an application, and releasing the storage space occupied by the buffer in the memory.

Wherein, the memory release instruction may be used to request to release the buffer of the application, and the memory release instruction may include the address of the buffer in the memory. At the end of the running of the application, the application 10 may submit a memory release instruction. After receiving the memory release instruction, the memory manager 21 may release the application buffer according to the address indicated in the memory release instruction, thereby saving memory resources.

It should be noted that after releasing the storage space occupied by the buffer in the cache area, you can choose to clear the data stored in the storage space to store other data, or you can choose to keep the data stored in the storage space for the application to use next time Or use in other applications, which is not limited in this embodiment of the present application.

After a buffer is allocated for an application, the application's buffer exists in the buffer until the storage space occupied by the buffer in memory is released. During the running of the application, the data enters the buffer sequentially according to the application requirements. When the amount of data in the buffer reaches the size of the buffer, or approaches the size of the buffer (for example, reaching 90%, 95%, or 99% of the size of the buffer, etc.), the new data entering the buffer will overwrite the previous For the data entering the buffer, the overwriting position can be determined by the elimination mechanism of the buffer. In an example, the data in the buffer may be overwritten in descending order of the duration stored in the buffer.

The following describes the data reading process in the data interaction process in the embodiment of the present application. FIG. 5 shows a schematic flowchart of a memory management method provided by an embodiment of the present application, and the method may be executed by the memory manager 21 in the storage system 20 shown in FIG. 2 . As shown in Figure 5, the memory management method includes:

Step S601 , the memory manager 21 receives a data read instruction from the application 10 .

In step S601 , the data to be read represents data that the application 10 needs to obtain from the storage system 20 . When the application 10 needs to read data, it can submit a data reading instruction. The data read instruction is used to request to transmit the data to be read to the application. When the memory manager 21 receives the data read instruction, it may first determine whether the data to be read is located in the buffer area of the application, in an area other than the buffer area in the buffer area, or outside the buffer area. Subsequent processing is then performed according to the location of the data to be read.

In step S602, when the data to be read is located in the buffer, the memory manager 21 directly executes step S605.

In step S603, when the data to be read is located in the buffer area other than the buffer area of the application, the memory manager 21 reads the data to be read from the buffer area into the buffer area of the application, and then executes step S605.

In step S604, when the data to be read is outside the buffer area, the memory manager 21 reads the data to be read from the memory 23 into the application buffer, and then executes step S605.

Step S605 , if the first preset condition is satisfied, the memory manager 21 transmits the data in the buffer of the application to the application 10 .

In step S605, the first preset condition is used to determine whether to transmit the data in the buffer to the application. The first preset condition can be preset as required. The principle of setting the first preset condition is to save time and resources.

In an example, satisfying the first preset condition includes: the amount of data stored in the buffer is greater than a first preset threshold. Wherein, the first preset threshold can be set as required. For example, the first preset threshold may be 1024 bytes, 100M, and so on. The amount of data stored in the buffer is greater than the first preset threshold, indicating that there is more data in the buffer. The amount of data stored in the buffer is less than or equal to the first preset threshold indicates that there is less data in the buffer. Considering that the speed of the memory is lower than the speed of the processor executing the application, when there is less data in the buffer, if the data in the buffer is transmitted to the application, the processor immediately starts processing these data-related tasks, and the processor It may consume more time and resources due to waiting for more data. In order to save resources and time, when there is less data in the buffer, the data in the buffer will not be sent to the application temporarily, and the processor can handle other tasks. App transfer.

In yet another example, satisfying the first preset condition may include: all data to be read required by the application has been read into the buffer. At this time, the processor does not need to wait for more data, which means that the processor will not consume more time and resources for waiting for more data when it immediately starts processing these data-related services. Therefore, when all the data to be read required by the application has been read into the buffer, the storage system can transmit the data in the buffer of the application to the application.

In another example, satisfying the first preset condition may include: the processor executing the application is in an idle state. The processor executing the application is idle, indicating that the processor has no other tasks to process. At this point, the processor starts processing tasks related to the data to be read without affecting other tasks. Therefore, when the processor executing the application is in an idle state, the storage system can transfer the data in the buffer of the application to the application.

FIG. 6 shows a schematic diagram of a process of reading data by an application in an embodiment of the present application. FIG. 6 shows the process of reading data by the application in the above three cases.

As shown in FIG. 6, in the first case (corresponding to step S602), the data to be read is located in the buffer. The memory manager 21 may directly transmit the data to be read from the buffer to the application when the first preset condition is satisfied. In this case, there is no need to copy data from the memory 23, which reduces read and write delays and saves processor computing resources.

As shown in FIG. 6 , in the second case (corresponding to step S603 ), the data to be read is located in an area of the buffer area other than the buffer area. At this point, the cache has already prefetched the data to be read. Therefore, the memory manager 21 can read the data to be read from an area other than the buffer area in the buffer area into the buffer area, and then can read the data to be read under the condition that the first preset condition is satisfied. The data is sent to the application 10 . In this case, although it is necessary to copy data from an area other than the buffer area in the buffer area to the buffer area, the data copying time will not exceed the data copying time from mutually independent buffer areas to the buffer area in the related art.

As shown in FIG. 6 , in the third case (corresponding to step S604 ), the data to be read is located outside the buffer area (that is, located in the memory 23 ). At this time, the memory manager 21 may directly read the data to be read from the memory 23 into the buffer of the application, and then transmit the data to be read to the application 10 when the first preset condition is satisfied. In this case, since the buffer is located in the buffer, the data to be read can be directly copied from the memory 23 to the buffer without going through the process of copying from the buffer to the buffer, reducing the time for reading and writing. Delay and save processor computing resources.

In a possible implementation manner, the data reading instruction in step S601 may include the location in the memory of the file where the data to be read is located, the address of the buffer in the memory, and the length of the data to be read. The memory manager 21 can determine the part of the data to be read that is located in the buffer zone, the buffer zone, and the buffer zone according to the location of the file where the data to be read is located in the memory 23, the address of the buffer zone in the memory 22, and the length of the data to be read. The part of the region other than the buffer zone, and the part that resides in memory. Afterwards, the memory manager 21 may perform processing respectively according to the condition of each part of the data to be read.

During the process of copying the data in the memory to the buffer area (including the buffer area and areas other than the buffer area), the pointer to read the data will move along with the progress of copying. The memory manager 21 knows whether the data to be read has been copied from the memory 23 , and to which location in the memory 22 it has been specifically copied. Therefore, according to the location of the file where the data to be read is located in the memory, the address of the buffer in the memory, and the length of the data to be read, it is possible to determine the part of the data to be read that is located in the buffer area, the portion located in the cache area except the buffer The portion of the area outside the zone, and the portion located in memory.

In the three cases involved in the embodiment of the present application, the buffer is located inside the buffer area, which realizes the multiplexing of the storage space in the memory, saves memory resources, and reduces the number of times of data copying or improves the efficiency of data copying, thereby reducing The read and write delay is reduced and the processor computing resources are saved.

The data writing process in the data interaction process in the embodiment of the present application will be described below. FIG. 7 shows a schematic flowchart of a memory management method provided by an embodiment of the present application, and the method may be executed by the memory manager 21 in the storage system 20 shown in FIG. 2 . As shown in Figure 7, the memory management method includes:

In step S801 , the memory manager 21 receives a data writing instruction from the application 10 .

Step S802 , the memory manager 21 stores the data to be written into the buffer of the application 10 .

Step S803 , if the second preset condition is satisfied, the memory manager 21 stores the data to be written from the buffer of the application 10 into the memory 23 .

In step S801, the data to be written represents data that the application needs to write into the memory for persistent storage. When the application 10 needs to write data, it may submit a data writing instruction. The data writing instruction is used to request the data to be written in the storage application. When the memory manager 21 receives the data write instruction, it may store the data to be written indicated by the data write instruction in the buffer of the application 10 .

In a possible implementation manner, the data writing instruction in step S801 may include the address of the buffer in the memory and the length of the data to be written. Based on this, in step S802, in the case of satisfying the second preset condition, the memory manager 21 can determine the target memory address according to the address of the buffer in the memory 22 and the length of the data to be written; The data to be written is copied from the memory address of the buffer to the target memory address; finally, the data in the target memory address is stored in the memory 23 .

In step S803, the second preset condition is used to determine whether to transfer the data in the buffer to the memory. The second preset condition can be set as required. The setting principle of the second preset condition is that the data in the buffer will not be overwritten before being transferred to the memory.

In an example, satisfying the second preset condition includes: the amount of data stored in the buffer is greater than a second preset threshold. Wherein, the second preset threshold can be set as required. For example, the second preset threshold may be 1024 bytes, 100M, and so on. If the amount of data stored in the buffer is greater than the second preset threshold, it indicates that more data to be written has been stored in the buffer, and at this time, the data in the buffer can be transferred to the memory. The amount of data stored in the buffer is less than or equal to the second preset threshold, indicating that the data to be written in the buffer is relatively small. At this time, if the data in the buffer is transferred to the memory, it may occur that multiple transfers are required to transfer all the data. All the data to be written is stored in the memory, and the data is replicated many times, resulting in increased data writing delay and waste of processor computing resources.

In yet another example, satisfying the second preset condition may include: all data to be written that the application needs to write has been stored in the buffer. The data to be written that the application needs to write has been stored in the buffer, and at this time, the application will not send more data to its buffer. Therefore, the storage system can immediately transfer the data in the buffer to the memory without waiting for more data.

In another example, satisfying the second preset condition may include: receiving a write completion instruction from an application, or receiving a write suspend instruction from an application. When an application write is complete or a write is paused, it indicates that the application will not send any more data into its buffer. Therefore, the storage system can immediately transfer the data in the buffer to the memory without waiting for more data.

Considering that the application needs to complete the writing of data as soon as possible to perform other tasks, the time required for data copying inside the memory is much shorter than copying the data in the memory to the storage. Therefore, in the embodiment of the present application, the data in the buffer can be copied to an area other than the buffer in the buffer to implement fast writing of the application. After that, slowly store the data in the cache area into the memory.

In the process of storing the target memory address to the memory, the storage system can obtain the location of the file where the data to be written is located in the memory, the address of the buffer in the memory, and the offset of the data to be written in the file as a synchronization information, and then writes the data at the target memory address into the memory based on the synchronization information. As the data to be written is written, the offset of the data to be written in the file will change, and the location of the subsequent data to be written in the memory will also change synchronously.

In the embodiment of the present application, the data interaction process is simplified, and the application no longer indirectly performs data interaction with the buffer area through the buffer area, but directly performs data interaction with the buffer area, which saves time and resources.

Considering that in the embodiment of the present application, the processing performed by the memory manager after receiving a buffer allocation instruction, a memory release instruction, a data read instruction, and a data write instruction is completely different from that in the related art. And changes in the application programming interface (Application Programming Interface, API) will affect the upper application. Therefore, in this embodiment of the application, the buffer allocation instruction, memory release instruction, data read instruction, and data write instruction submitted by the application may not be changed, that is, the interface called by the application shall not be changed, but these After the interface is intercepted, the interface called by the application is redirected to the interface provided in the embodiment of the present application, so that the storage system executes the method provided in the embodiment of the present application. In this way, it not only ensures that the calls of upper-layer applications do not change, but also saves memory resources, processor computing resources, and reduces read and write delays in a simple and efficient manner.

The following four specific examples introduce the process of memory allocation, memory release, data reading and data writing:

In related technologies, an application may submit a buffer allocation command, a memory release command, a data read command, and a data write command by calling a malloc interface, a free interface, a read interface, and a write interface respectively. After the memory manager intercepts the above-mentioned interface, it is redirected to the application direct cache access (adca) interface provided by the embodiment of the present application, namely the adca_malloc interface, adca_free interface, adca_read interface and adca_write interface.

In the embodiment of the present application, the memory manager intercepts the malloc interface and redirects it to an adca_malloc interface, and intercepts the free interface and redirects it to an adca_free interface. And by calling the adca_malloc interface to allocate storage space for the application in the buffer area of the memory as the application buffer (ie steps S401 to S403), and by calling the adca_free interface to release the storage space occupied by the buffer in the memory. By calling the adca_malloc interface and adca_free interface, the application can directly allocate and release storage space from the buffer area, and perform buffer allocation and release without opening up additional space in the memory, which saves the occupation of memory resources.

In the embodiment of the present application, the memory manager intercepts the read interface and redirects it to the adca_read interface, and intercepts the write interface and redirects it to the adca_write interface. Data reading is implemented by calling the adca_read interface (ie steps S601 to S605), and data writing is implemented by calling the adca_write interface (ie steps S801 to S803). Since the buffer is located in the buffer, the application can directly obtain the data in the buffer in the buffer, without copying the data from the buffer to the buffer, and then obtaining the data from the buffer, saving the time consumed by data copying and processor resources.

Fig. 8a shows a schematic diagram of interface redirection in the embodiment of the present application. As shown in Figure 8a, for the application, the original interface is still called, that is, the malloc interface is called to allocate a buffer, the free interface is called to release the buffer, the read interface is called to read data, and the write interface is called to write data. But when the call enters the storage system provided by the embodiment of the present application, the call will be redirected to the adca_malloc interface, adca_free interface, adca_read interface and adca_write interface provided by the embodiment of the present application respectively. It can be seen that the upper-layer calls do not change, but the allocation and release of the storage space corresponding to the buffer is handled by the buffer in the storage system, and the data to be written and read by the application are also stored in the buffer in the buffer.

Fig. 8b shows a related technology and an interface implementation diagram in the embodiment of the present application. As shown in Figure 8b, the application can still call the malloc interface, free interface, read interface and write interface to perform corresponding operations, and the storage system will actively intercept the original interface, obtain the information required by the adca interface provided by the embodiment of the present application, and Execute the corresponding program.

When the application starts running, the application submits a buffer allocation instruction to the memory manager, and the memory manager allocates a buffer for the application. Comparing the standard interface and the adca interface shown in Figure 8b, the parameters required by both the malloc interface and the adca_malloc interface are the stored data type (such as: int4) and the total length of the data (such as: 1024), the former is stored in the memory by the operating system Open up storage space, which is opened up by the storage system in the cache area. Referring to step S401, it can be known that the buffer allocation instruction submitted by the application includes the buffer size. The buffer size here corresponds to the parameter "total data length".

Further, the application calls the fd.open interface to open the file. As shown in FIG. 8b, the parameters of the fd.open interface are information such as file path and file name. Based on the file path and file name, it can be determined which file the data to be read is read from, and which file the data to be written is to be written into, and information such as the file path and file name needs to be used in the adca_read interface as a file handle. After that, the application can open the file to read or write data. Comparing the standard interface shown in Figure 8b with the adca interface, the parameters required by both the read interface and the adca_read interface are file handle (fd), buffer pointer (*buf) and the number of bytes read (eg: 1024). Referring to step S601, it can be seen that the data reading instruction submitted by the application includes the location of the file in the memory, the address of the buffer in the memory, and the length of the data to be read. Here, the location of the file in the memory corresponds to the parameter "file handle", the address of the buffer in memory corresponds to the parameter "buffer pointer", and the length of the data to be read corresponds to the parameter "number of bytes read".

Comparing the standard interface and the adca interface shown in Figure 8b, the parameters of write include: file handle (fd), buffer pointer (*buf) and the number of bytes written (such as: 1024), and the actual adca_write interface execution It is a memcpy (memory copy) interface, its parameters are source memory address (*src), target memory address (*dst) and the number of bytes to be copied (eg: 1024), the function of the interface is from the source memory address The starting position begins to copy multiple bytes to the target memory address, that is, to copy multiple bytes from the source memory address to the target memory address. Referring to step S801, it can be known that the data writing instruction submitted by the application includes the address of the buffer in the memory and the length of the data to be written. Here, the address of the buffer in the memory corresponds to the parameter "source memory address", and the storage system can determine the parameter "target memory address" according to the address of the buffer in the memory and the length of the data to be written. The length corresponds to the parameter "number of bytes to copy".

sync.data shown in Figure 8b is used to transfer synchronization information. When the application performs read and write operations, it will automatically save the real-time read and write positions in the operating system, and the adca interface will intercept this information, and transfer this information to the buffer through the sync.data interface (fd is the file handle, *buf is buffer pointer, offset is the internal offset of the file), that is, which position of the file the file is read and written to at this time, so as to realize orderly reading and writing.

The memory management method provided by the embodiment of the present application can be better applied to scenarios where applications need to interact frequently with the storage system; and scenarios that are sensitive to memory usage and require less memory usage; and scenarios that are sensitive to delay and require reading and writing Short scenes. In the embodiment of the present application, a detection plug-in may be introduced, and the detection plug-in detects whether the application is a storage-intensive application. If it is detected that an application is a storage-intensive application, the memory management method provided by the embodiment of the present application can be used for memory management, and the interface called by the application can be intercepted and redirected, so as to save memory space, reduce read and write delays, and The effect of saving processor computing resources.

The following introduces the application of the memory management method provided by this application in big data scenarios:

In big data scenarios, data is frequently read and written. In order to improve the data interaction rate, many storage systems in big data scenarios use the design of large memory pools as back-end storage. In addition, since streaming computing is very common in big data scenarios, data often requires Multiple buffers to ensure uninterrupted computation of the pipeline. The memory management method provided by the embodiment of the present application can be better applied to this scenario.

FIG. 9 shows a schematic diagram of data interaction in the embodiment of the present application in a big data scenario. As shown in Figure 9, the front end is a data analysis application program built by Spark (that is, the Spark application), and the back end is a big data storage system using a memory pool. Wherein, the big data storage system includes a memory, a memory pool, and a memory manager, and the memory pool includes multiple memories. The memory manager allocates storage space in multiple memories as the cache area of the memory, and allocates storage space in each cache area as the buffer of the Spark application. Among them, the cache area of the memory and the buffer area of the Spark application have memory multiplexing. When the Spark application reads data, the data to be read in the memory is directly copied to the buffer in the cache area, and then can be copied from the buffer to the Spark application. The multiple buffers in Figure 9 can ensure sufficient data available for the Spark application, thereby supporting uninterrupted calculation of the pipeline. In a storage system in a big data scenario, the memory manager is used to execute the memory management methods shown in FIG. 3 , FIG. 5 and FIG. 7 . The storage system can include only one memory manager, which is used to manage all the buffers in the memory pool; the storage system can also include multiple memory managers, and each memory corresponds to a memory manager, which is used to manage the buffers in this memory .

In the embodiment of this application: the allocation of the buffer no longer occupies additional memory storage space, but reuses the storage space occupied by the buffer area in the memory; the same data does not need to be copied again in the buffer allocated for the application copies are stored. Taking FIG. 9 as an example, if there are 6 memories in the memory pool as an example, the storage space of 6 buffers can be saved in the memory pool. It can be seen that in a big data scenario with a lot of memory, the embodiment of the present application can save a lot of memory resources. At the same time, the buffer located in the buffer area can directly obtain data from the memory without duplication of data, which saves time for data duplication. When the amount of data is large or the data is read and written frequently, the read and write delay will be greatly reduced.

FIG. 10 shows a schematic structural diagram of a memory management device provided by an embodiment of the present application. The device may be a memory manager 21 as shown in FIG. 4 . As shown in Figure 10, the device 90 may include:

The first receiving module 91 is configured to receive a buffer allocation instruction from an application, and the buffer allocation instruction is used to request to allocate a buffer in memory for the application. Specifically, step S401 as shown in FIG. 3 and other implicit steps can be implemented.

The allocation module 92 is configured to allocate a buffer for the application in the buffer area of the memory; specifically, step S402 as shown in FIG. 3 and other implicit steps can be implemented.

The return module 93 is used to return the address of the buffer in the memory, specifically step S403 as shown in Figure 3 and other implicit steps can be implemented.

In a possible implementation manner, the buffer allocation instruction includes the size of the buffer, and the allocation module is further configured to: allocate a buffer of the size to the application in the cache area of the memory. a buffer, the size of which is less than the size of the cache.

In a possible implementation manner, the device further includes: a second receiving module, configured to receive a memory release instruction from the application, where the memory release instruction is used to request to release a buffer of the application, and the The memory release instruction includes the address of the buffer in the memory; the release module is used to release the buffer.

In a possible implementation manner, the device further includes: a third receiving module, configured to receive a data reading instruction from the application, and the data reading instruction is used to request to transmit the data to be read to the application. Data; a reading module, configured to read the data to be read from the buffer to the buffer when the data to be read is located in an area other than the buffer in the buffer area; when the data to be read is located outside the buffer area, the data to be read is read from the memory into the buffer; the transmission module is used to transfer the data in the buffer sent to the app.

In a possible implementation manner, the transmitting module is further configured to transmit the data in the buffer to the The application; or, when all the data to be read required by the application has been read into the buffer, transfer the data in the buffer to the application; or, execute the processing of the application When the memory is in an idle state, transmit the data in the buffer to the application. .

In a possible implementation manner, the device further includes: a fourth receiving module, configured to receive a data write instruction from the application, where the data write instruction is used to request to store the data to be written by the application data; a writing module, configured to store the data to be written into the buffer; a storage module, configured to store the data to be written from the buffer into a memory.

In a possible implementation manner, the storage module is further configured to: when the amount of data stored in the buffer is greater than a second preset threshold, store the data to be written from the buffer to the memory or, when the data to be written required by the application has been stored in the buffer, store the data to be written from the buffer into the memory; or, when receiving the write completion command, store the The data to be written is stored in the memory from the buffer; or, when a write suspend instruction is received, the data to be written is stored in the memory from the buffer.

In the embodiment of the present application, the allocation of the buffer does not occupy additional memory storage space, but reuses the storage space occupied by the buffer area in the memory, thereby saving memory resources. At the same time, the same data does not need to be copied in the buffer allocated for the application for storage. The buffer located in the buffer area can directly obtain the data from the memory without the need to copy the data, which can save the time for data copying , thereby reducing read and write delays and saving computing resources of the processor.

The embodiment of the present application also provides a computer device, and FIG. 11 shows a schematic structural diagram of the computer device provided in the embodiment of the present application. As shown in FIG. 11 , the computer device includes at least one processor 301 , memory 22 , bus 304 , input/output device 305 , memory manager 21 and storage 23 .

The processor 301 is the control center of the computer device, and may be one processing element, or may be a general term for multiple processing elements. Each of these processors can be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). A processor herein may refer to one or more devices, circuits, and/or processing cores for processing data (eg, computer program instructions). For example, the memory manager 21 is a CPU, may also be a specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits configured to implement the embodiments of the present disclosure, for example: one or more micro A processor (Digital Signal Processor, DSP), or, one or more Field Programmable Gate Arrays (Field Programmable Gate Array, FPGA).

Wherein, the processor 301 can execute various functions of the computer device by running or executing applications stored in the memory 22 and calling data stored in the memory 22 .

The memory manager 21 can be used to receive a buffer allocation instruction from an application, wherein the buffer allocation instruction is used to request the application to allocate a buffer in the memory; it can also be used to allocate a buffer to the application in the buffer area of the memory , and returns the address of the buffer in memory. The memory manager 21 can be an independent hardware or a software device, stored in the memory, and executed by the processor 301 .

Memory 22 may be used to store pre-stored, intermediate and result data during sample collection, modeling and prediction. Memory 22 may include read-only memory and random-access memory, and may be either volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Among them, the non-volatile memory can be read-only memory (read-only memory, ROM), programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically programmable Erases programmable read-only memory (electrically EPROM, EEPROM) or flash memory. The volatile memory can be random access memory (RAM), which acts as external cache memory. By way of illustration and not limitation, many forms of RAM are available such as static random access memory (static RAM, SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM), Double data rate synchronous dynamic random access memory (double data date SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous connection dynamic random access memory (synchlink DRAM, SLDRAM) and direct Memory bus random access memory (direct rambus RAM, DR RAM). The memory 22 can exist independently, and is connected to the processor 301 through the bus 304 . The memory 22 can also be integrated with the processor 301 . In the embodiment of the present disclosure, the memory 22 can also be used to store pre-stored data, intermediate data and result data stored in the process of sample collection, modeling and prediction.

The storage 23 may be a device for persistently storing data, such as a magnetic disk, a hard disk, and an optical disk. In the embodiment of the present application, the storage 23 may be used to store files accessed by applications.

The input and output device 305 is used for data transmission with other devices. In a specific implementation, as an example, the input and output device 305 may include a transmitter and a receiver. Among them, the transmitter is used to send data to other devices, and the receiver is used to receive data sent by other devices. The transmitter and receiver can exist independently or be integrated together. In this embodiment of the application, the input and output device 305 can perform buffer allocation instructions, memory release instructions, data read instructions and data write instructions, as well as data to be written and data to be read, between the processor executing the application. etc. transmission.

The bus 304 may be an Industry Standard Architecture (Industry Standard Architecture, ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (Extended Industry Standard Architecture, EISA) bus, etc. The bus can be divided into address bus, data bus, control bus and so on. For ease of representation, only one thick line is used in FIG. 11 , but it does not mean that there is only one bus or one type of bus.

The device structure shown in FIG. 11 does not constitute a limitation to the computer device, and may include more or less components than shown, or combine some components, or arrange different components.

An embodiment of the present application provides a computer-readable storage medium, on which computer program instructions are stored, and the above method is implemented when the computer program instructions are executed by a processor.

An embodiment of the present application provides a computer program product, including computer-readable codes, or a non-volatile computer-readable storage medium bearing computer-readable codes, when the computer-readable codes are stored in a processor of an electronic device When running in the electronic device, the processor in the electronic device executes the above method.

A computer readable storage medium may be a tangible device that can retain and store instructions for use by an instruction execution device. A computer readable storage medium may be, for example, but is not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (non-exhaustive list) of computer-readable storage media include: portable computer disk, hard disk, random access memory (Random Access Memory, RAM), read only memory (Read Only Memory, ROM), erasable Electrically Programmable Read-Only-Memory (EPROM or flash memory), Static Random-Access Memory (Static Random-Access Memory, SRAM), Portable Compression Disk Read-Only Memory (Compact Disc Read-Only Memory, CD -ROM), Digital Video Disc (DVD), memory sticks, floppy disks, mechanically encoded devices such as punched cards or raised structures in grooves with instructions stored thereon, and any suitable combination of the foregoing .

Computer readable program instructions or codes described herein may be downloaded from a computer readable storage medium to a respective computing/processing device, or downloaded to an external computer or external storage device over a network, such as the Internet, local area network, wide area network, and/or wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and/or edge servers. A network adapter card or a network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in each computing/processing device .

Computer program instructions for performing the operations of the present application may be assembly instructions, instruction set architecture (Instruction Set Architecture, ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or in one or more source or object code written in any combination of programming languages, including object-oriented programming languages—such as Smalltalk, C++, etc., and conventional procedural programming languages—such as the “C” language or similar programming languages. Computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server implement. In cases involving a remote computer, the remote computer can be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or it can be connected to an external computer such as use an Internet service provider to connect via the Internet). In some embodiments, electronic circuits, such as programmable logic circuits, field-programmable gate arrays (Field-Programmable Gate Array, FPGA) or programmable logic arrays (Programmable Logic Array, PLA), the electronic circuit can execute computer-readable program instructions, thereby realizing various aspects of the present application.

Aspects of the present application are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It should be understood that each block of the flowcharts and/or block diagrams, and combinations of blocks in the flowcharts and/or block diagrams, can be implemented by computer-readable program instructions.

These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine such that when executed by the processor of the computer or other programmable data processing apparatus , producing an apparatus for realizing the functions/actions specified in one or more blocks in the flowchart and/or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause computers, programmable data processing devices and/or other devices to work in a specific way, so that the computer-readable medium storing instructions includes An article of manufacture comprising instructions for implementing various aspects of the functions/acts specified in one or more blocks in flowcharts and/or block diagrams.

It is also possible to load computer-readable program instructions into a computer, other programmable data processing device, or other equipment, so that a series of operational steps are performed on the computer, other programmable data processing device, or other equipment to produce a computer-implemented process , so that instructions executed on computers, other programmable data processing devices, or other devices implement the functions/actions specified in one or more blocks in the flowcharts and/or block diagrams.

The flowchart and block diagrams in the figures show the architecture, functions and operations of possible implementations of apparatuses, systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in a flowchart or block diagram may represent a module, a portion of a program segment, or an instruction that includes one or more Executable instructions. In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks in succession may, in fact, be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved.

It should also be noted that each block in the block diagrams and/or flowcharts, and combinations of blocks in the block diagrams and/or flowcharts, can be implemented with hardware (such as circuits or ASIC (Application Specific Integrated Circuit, application-specific integrated circuit)), or can be implemented with a combination of hardware and software, such as firmware.

Although the present invention has been described in conjunction with various embodiments herein, in the process of implementing the claimed invention, those skilled in the art can understand and Other variations of the disclosed embodiments are implemented. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that these measures cannot be combined to advantage.

Having described various embodiments of the present application above, the foregoing description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and alterations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principle of each embodiment, practical application or improvement of technology in the market, or to enable other ordinary skilled in the art to understand each embodiment disclosed herein.

Claims (21)

1. A memory management method, characterized in that the method comprises:

   Receive a buffer allocation instruction, the buffer allocation instruction is used to allocate a buffer in the memory for the application, and after the data stored in the buffer reaches a certain amount, send the data in the buffer to the application;

   In the cache area of the memory, a buffer is allocated for the application.
2. The method according to claim 1, wherein the buffer allocation instruction includes the size of the buffer, and the buffer allocation for the application in the buffer area of the memory includes:

   In the buffer area of the memory, a buffer of the size is allocated for the application, and the size is smaller than the size of the buffer area.
3. The method according to claim 1 or 2, characterized in that the method further comprises:

   receiving a memory release instruction, the memory release instruction is used to request to release the buffer of the application, and the memory release instruction includes an address of the buffer in the memory;

   Frees said buffer.
4. The method according to any one of claims 1 to 3, further comprising:

   receiving a data read instruction, where the data read instruction is used to request to transmit data to be read to the application;

   When the data to be read is located outside the buffer area, read the data to be read from the memory into the buffer;

   The data in the buffer is transferred to the application.
5. The method according to claim 4, wherein the transferring the data in the buffer to the application specifically comprises:

   When the amount of data stored in the buffer allocated for the application is greater than a first preset threshold, transmitting the data in the buffer to the application; or,

   When all the data to be read required by the application has been read into the buffer, transfer the data in the buffer to the application; or,

   When the processor executing the application is in an idle state, transmit the data in the buffer to the application.
6. The method according to any one of claims 1 to 5, wherein the method further comprises:

   receiving a data write instruction, where the data write instruction is used to request to store the data to be written by the application;

   storing the data to be written into the buffer;

   storing the data to be written from the buffer into a memory.
7. The method according to claim 6, wherein the storing the data to be written from the buffer into the memory specifically comprises:

   When the amount of data stored in the buffer is greater than a second preset threshold, storing the data to be written from the buffer into the memory; or,

   When the data to be written required by the application has been stored in the buffer, storing the data to be written from the buffer to the memory; or,

   When receiving a write completion instruction, storing the data to be written from the buffer into the memory; or,

   When receiving the write suspend instruction, the data to be written is stored from the buffer into the memory.
8. A memory management device, characterized in that the device comprises:

   The first receiving module is configured to receive a buffer allocation instruction from an application, the buffer allocation instruction is used to request to allocate a buffer in memory for the application, and when the data stored in the buffer reaches a certain amount, The application acquires the data in the buffer once;

   The allocating module is configured to allocate a buffer for the application in the buffer area of the memory.
9. The device according to claim 8, wherein the buffer allocation instruction includes the size of the buffer, and the allocation module is also used for:

   In the buffer area of the memory, a buffer of the size is allocated for the application, and the size is smaller than the size of the buffer area.
10. The device according to claim 8 or 9, wherein the device further comprises:

    The second receiving module is configured to receive a memory release instruction from the application, the memory release instruction is used to request to release the buffer of the application, and the memory release instruction includes the memory release instruction of the buffer in the memory address;

    The release module is used to release the buffer.
11. The device according to any one of claims 8 to 10, wherein the device further comprises:

    The third receiving module is configured to receive a data reading instruction, and the data reading instruction is used to request to transmit the data to be read to the application;

    A reading module, configured to read the data to be read from the memory into the buffer when the data to be read is outside the buffer;

    A transmission module, configured to transmit the data in the buffer to the application.
12. The device according to claim 11, wherein the transmission module is further used for:

    When the amount of data stored in the buffer allocated for the application is greater than a first preset threshold, transmitting the data in the buffer to the application; or,

    When all the data to be read required by the application has been read into the buffer, transfer the data in the buffer to the application; or,

    When the processor executing the application is in an idle state, transmit the data in the buffer to the application.
13. The device according to any one of claims 8 to 12, wherein the device further comprises:

    The fourth receiving module is configured to receive a data writing instruction, and the data writing instruction is used to request to store the data to be written of the application;

    a writing module, configured to store the data to be written into the buffer;

    A storage module, configured to store the data to be written from the buffer into a memory.
14. The device according to claim 13, wherein the storage module is further used for:

    When the amount of data stored in the buffer is greater than a second preset threshold, storing the data to be written from the buffer into the memory; or,

    When the data to be written required by the application has been stored in the buffer, storing the data to be written from the buffer to the memory; or,

    When receiving a write completion instruction, storing the data to be written from the buffer into the memory; or,

    When receiving the write suspend instruction, the data to be written is stored from the buffer into the memory.
15. A data access method, characterized in that the method is executed by a storage system, the storage system includes a memory, a memory, and a memory manager, the memory includes a buffer area and a buffer, and the buffer is located in the buffer area , the method includes:

    receiving a data read instruction, where the data read instruction is used to request to transmit the data to be read to the application;

    When the data to be read is located outside the buffer area, read the data to be read from the memory into the buffer;

    The data in the buffer is transferred to the application.
16. The method according to claim 15, wherein the transferring the data in the buffer to the application includes:

    When the amount of data stored in the buffer allocated for the application is greater than a first preset threshold, transmitting the data in the buffer to the application; or,

    When all the data to be read required by the application has been read into the buffer, transfer the data in the buffer to the application; or,

    When the processor executing the application is in an idle state, transmit the data in the buffer to the application.
17. The method according to any one of claims 15 to 16, further comprising:

    receiving a data write instruction, where the data write instruction is used to request to store the data to be written by the application;

    storing the data to be written into the buffer;

    storing the data to be written from the buffer into a memory.
18. The method according to claim 17, wherein the storing the data to be written from the buffer into the memory specifically comprises:

    When the amount of data stored in the buffer is greater than a second preset threshold, storing the data to be written from the buffer into the memory; or,

    When the data to be written required by the application has been stored in the buffer, storing the data to be written from the buffer to the memory; or,

    When receiving a write completion instruction, storing the data to be written from the buffer into the memory; or,

    When receiving the write suspend instruction, the data to be written is stored from the buffer into the memory.
19. A computer device, characterized in that the computer device includes a memory, a memory, and a memory manager: the memory manager is configured to execute the method described in any one of claims 1 to 7 above.
20. A computer storage medium, on which computer program instructions are stored, wherein the computer program instructions implement the method according to any one of claims 1 to 7 when executed by a processor.
21. A computer program product, comprising computer readable codes, or a computer readable storage medium bearing computer readable codes, when the computer readable codes run in an electronic device, a processor in the electronic device executes the rights The method described in any one of 1 to 7 is required.

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