WO2023010788A1

WO2023010788A1 - Radar baseband module and radar system

Info

Publication number: WO2023010788A1
Application number: PCT/CN2021/142374
Authority: WO
Inventors: 吴佳蕊; 赵涤燹; 郭沫含
Original assignee: 网络通信与安全紫金山实验室
Priority date: 2021-08-02
Filing date: 2021-12-29
Publication date: 2023-02-09
Also published as: CN113341377B; CN113341377A

Abstract

A radar baseband module and a radar system. The radar baseband module comprises: a Fourier transform control sub-module, a Fourier transform calculation sub-module, a constant false alarm detection control sub-module, a constant false alarm calculation sub-module, a digital beam forming control sub-module, a digital beam forming calculation sub-module, a controller local area network (CAN) parsing sub-module, a memory read-write control sub-module, a first memory, a second memory, and a third memory. The radar baseband module and the radar system can be used to quickly measure the position, speed and angle of a surrounding object within a certain distance, and have a greater calculation speed but a lower power consumption and cost. In addition, a CAN protocol interface is directly configured, such that the radar baseband module and the radar system can be directly connected to an automobile main control system, thereby reducing the complexity of the system.

Description

Radar baseband module and radar system

Cross References to Related Applications

This application claims the priority of the Chinese patent application with the application number 202110878591.2 and the title of the invention "Radar Baseband Module and Radar System" filed on August 2, 2021, which is fully incorporated herein by reference.

technical field

The present application relates to the technical field of communication, in particular to a radar baseband module and a radar system.

Background technique

In order to help people judge the driving situation and at the same time escort autonomous driving, Advanced Driving Assistant System (ADAS) has been introduced into the public's field of vision. ADAS uses various sensors (millimeter wave radar, lidar, single/binocular camera and satellite navigation) installed on the car to sense the surrounding environment at any time during the driving process, collect data, and perform static and dynamic object detection. Identification, detection and tracking, combined with navigator map data, for systematic calculation and analysis, so that drivers can be aware of possible dangers in advance, effectively increasing the comfort and safety of car driving. Among them, the vehicle-mounted millimeter-wave radar is not easily affected by the shape and color of the target surface, nor is it hindered by the weather. It has the characteristics of strong environmental adaptability and stable detection performance, and is a research hotspot in automotive safety technology. The radar baseband module can analyze and process the analog data collected by the millimeter-wave radar to obtain target position and speed information.

The traditional vehicle radar system mainly uses digital signal processing (Digital Signal Process, DSP) or field programmable logic gate array (Field Programmable Gate Array, FPGA) for data analysis.

However, as general-purpose devices, FPGA and DSP basically cover various standard interfaces, but in actual automotive applications, these interfaces are rarely used, resulting in waste of resources, and for the same amount of data processing, DSP or FPGA It has the defects of high power consumption, slow speed and high complexity.

Contents of the invention

The present application provides a radar baseband module and a radar system, which are used to solve the technical problems of high power consumption, slow speed and high complexity of the radar baseband module in the prior art.

The application provides a radar baseband module, including: Fourier transform control submodule, Fourier transform calculation submodule, constant false alarm detection control submodule, constant false alarm calculation submodule, digital beamforming control submodule, digital Beamforming calculation submodule, controller area network CAN analysis submodule, memory read and write control submodule, first memory, second memory, third memory;

The first end of the Fourier transform control submodule is connected to the analog-to-digital converter, the second end is connected to the first end of the Fourier transform calculation submodule, and the third end is connected to the second end of the Fourier transform calculation submodule connection, the fourth terminal is connected to the first terminal of the constant false alarm detection control submodule, the fifth terminal is connected to the second terminal of the memory read-write control submodule, and the sixth terminal is connected to the first terminal of the memory read-write control submodule ;

The second terminal of the CFAR detection control submodule is connected to the first terminal of the CFAR calculation submodule, the third terminal is connected to the second terminal of the CFAR calculation submodule, and the fourth terminal is connected to the digital beamforming control submodule The first terminal is connected, and the fifth terminal is connected to the second terminal of the second memory;

The second terminal of the digital beamforming control submodule is connected to the first terminal of the digital beamforming calculation submodule, the third terminal is connected to the second terminal of the digital beamforming calculation submodule, and the fourth terminal is connected to the first terminal of the CAN analysis submodule. The terminals are connected, the fifth terminal is connected with the second terminal of the third memory, and the sixth terminal is connected with the first terminal of the second memory;

The second end of the CAN analysis sub-module is connected to the CAN bus, and the third end is connected to the first end of the third memory;

The third terminal of the memory read-write control submodule is respectively connected to the sixth terminal of the constant false alarm detection control submodule, the seventh terminal of the digital beamforming control submodule and the fourth terminal of the CAN analysis submodule, and the fourth terminal is connected to the fourth terminal of the CAN analysis submodule. The second end of a memory is connected, and the fifth end is connected with the first end of the first memory.

Optionally, m channels of ADC input data to the Fourier transform control sub-module at the same time, and window processing is performed on each data in a pipelined manner. When the data of each channel is accumulated to the required number of points, the Fourier transform The control sub-module saves the set of data. Since the sub-module used to calculate the Fourier transform can only calculate one set of data at a time, and in order to ensure that the sampling time of the four channels of data is the same, there are m sets of registers used to save the original sampled data. In chronological order, m groups of raw data are sequentially entered into the Fourier transform calculation sub-module for calculation, and the results are stored in m groups of registers again for storage. After all antenna data calculations are completed, the calculation results are stored in the first memory, and the Fourier transform The leaf transformation control submodule reads in the ADC data again. After the above process is repeated to the length required by the specified speed dimension data, the total amount of data has reached the demand for two-dimensional FFT calculation, and the Fourier transform of the speed dimension is started; where m is equal to the number of antennas;

The Fourier transform of the velocity dimension starts. First, a set of velocity dimension data of antenna 0 is read in, and the data is windowed in real time. After the required amount of data is met, the data is transferred to the Fourier calculation sub-module for calculation. After the Fourier transform result is obtained, the data is written back to the same position of the antenna 0 data in the first memory, and the data of the antenna 1 is read in while writing. Since the data written in antenna 0 has the same length as the read data read by antenna 1, and there is no read-write conflict in different address partitions in the first memory, in order to improve the system processing speed, the write operation and read operation are combined in the Fourier control submodule designed to be done simultaneously. After the data of antenna 1 is read out, FFT is performed on the data of antenna 1, and the result is written back into the first memory and the data of antenna 2 is read in at the same time. The same operation is performed on each group of antenna data in turn, and the antenna 0 data at the next position is read in again while writing back the data of the last group of antennas, and the next-dimensional Fourier transform is performed. Repeat the above operations until the Fourier transform of all velocity-dimensional data is completed.

Optionally, the radar baseband module only has one Fourier transform calculation sub-module, and the antenna data to be processed is multiple groups;

The Fourier transform control sub-module adopts the pipeline structure to realize the Fourier transform of multiple sets of antenna data.

Optionally, the Fourier transform calculation submodule adopts a parallel iterative structure;

The calculation of the 0th level and the 1st level is realized by an adder. After the calculation result of each subsequent level is completed, according to the extraction rule, the output of the calculation result of the upper level corresponds to the calculation input of the next level and is sent to the butterfly unit. in the calculation array.

Optionally, after all calculations of the single-dimensional fast Fourier transform FFT are completed, they are sequentially written into the first memory in the following order:

After the i-th FFT calculation is completed, the write addresses are i-1, i-1+speed dimension FFT size points, i-1+2*velocity dimension FFT size points, ... until the last FFT calculation of this time is written result;

Wherein, the value range of i is 1~n, and n is equal to the number of continuous frequency modulation waves.

Optionally, the configuration parameters of the FFT matrix specification are configured through the CAN bus.

Optionally, the Fourier transform control submodule adopts a 24-bit arithmetic unit, and each of the real part and the imaginary part of the data is 24 bits;

The first memory adopts the format of storing 16 bits of each real part and imaginary part, wherein the upper 13 bits represent the data content, and the lower 3 bits represent the data index.

Optionally, the CFAR detection control submodule adjusts the detection window function and the detection coefficient according to the register configuration, and the CFAR calculation submodule selects a one-dimensional window through the chip selection signal to calculate and synthesize a two-dimensional constant virtual alarm according to the window function setting. The alarm window is calculated, and finally by comparing the calculation result with the threshold value, it is judged whether the target exists.

Optionally, when there is a target in the unit to be detected, the CFAR detection control submodule writes the corresponding address into the second memory.

Optionally, the type of the detection window function and the detection coefficient are configured through the CAN bus.

Optionally, the digital beamforming control submodule reads in the data of multiple sets of antennas corresponding to the target point through the memory read and write control submodule, and sends each set of data to different digital beamforming calculations sequentially through the data selector (MUX) submodule. The digital beam forming calculation sub-module is used to determine the target angle by performing beam form on the peak data of multiple groups of antennas. Finally, the angle of the target is sequentially output through the data selector, and the result is written into the third memory.

Optionally, the storage read-write control sub-module avoids the read-write conflict of each sub-module accessing the memory through a preset priority order, and the preset priority order from high to low is: Fourier transform control sub-module, constant false alarm Detection control sub-module, digital beam forming control sub-module, CAN analysis sub-module.

Optionally, the calculation result of the system communicates with the outside through the CAN bus, and can analyze specific messages through the CAN bus, so that the external system can access the internal memory and sub-module configuration of the system.

The present application also provides a radar system, including the above-mentioned radar baseband module.

This application provides a radar baseband module and radar system, which can be used to quickly detect the position, speed and angle of surrounding objects within a certain distance, specifically faster calculation speed, lower power consumption and cost, and directly configure the CAN protocol The interface can be directly connected with the main control system of the car, reducing the complexity of the system.

Description of drawings

In order to more clearly illustrate the technical solutions in this application or the prior art, the accompanying drawings that need to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings in the following description are the present For some embodiments of the application, those skilled in the art can also obtain other drawings based on these drawings without creative work.

Fig. 1 is a schematic structural diagram of the radar baseband module provided by the present application;

Fig. 2 is the timing diagram of the Fourier transform provided by the present application;

Fig. 3 is one of the circuit structure diagrams of the Fourier transform control submodule provided by the present application;

Fig. 4 is the circuit structure diagram two of the Fourier transform control submodule provided by the present application;

Fig. 5 is the third circuit structure diagram of the Fourier transform control sub-module provided by the application;

Fig. 6 is a schematic diagram of the parallel iterative structure of the Fourier transform calculation sub-module provided by the present application;

Fig. 7 is a schematic diagram of the storage format of the Fourier transform result provided by the present application;

Fig. 8 is a schematic diagram of the window function provided by the present application;

Fig. 9 is the circuit structure diagram of the constant false alarm calculation submodule provided by the present application;

Fig. 10 is a circuit structure diagram of the beamforming sub-module provided by the present application;

Fig. 11 is a schematic diagram of the CAN frame structure used by the present application;

FIG. 12 is a schematic diagram of the corresponding relationship between the specific format and function of the data segment (DATA) in the CAN frame structure used in this application.

Detailed ways

In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings in this application. Obviously, the described embodiments are part of the embodiments of this application , but not all examples. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.

This application provides a radar baseband module (chip), which can replace the original DSP/FPGA solution with lower cost and lower power consumption.

The radar baseband module described in this application is applicable to a multi-antenna frequency modulated continuous wave (Frequency Modulated Continuous Wave, FMCW) radar. The front-end input of the chip is the chirp signal echo continuously sampled by the Analog-to-Digital Converter (ADC); the output of the chip is the angle, speed and distance of the target.

The algorithm adopted by the radar baseband module described in this application is: by performing two-dimensional Fourier transform on multiple groups of continuous linear frequency modulation signals, the distance information of the target is converted into a two-dimensional spectrum diagram; the constant false alarm algorithm identifies the spectrum diagram The peak value in the two-dimensional spectrogram determines the distance and speed information of the target through the position of the peak value in the two-dimensional spectrogram; the digital beamforming algorithm synthesizes the target data obtained by multiple antennas to determine the angle of the target.

Fig. 1 is a schematic structural diagram of the radar baseband module provided by the present application. As shown in Fig. 1, the radar baseband module provided by the present application includes: Fourier transform control submodule, Fourier transform calculation submodule, constant false alarm detection Control submodule, constant false alarm calculation submodule, digital beamforming control submodule, digital beamforming calculation submodule, controller area network CAN analysis submodule, memory read and write control submodule, first memory, second memory, second Three storage.

The first end of the Fourier transform control submodule is connected to the analog-to-digital converter, the second end is connected to the first end of the Fourier transform calculation submodule, and the third end is connected to the second end of the Fourier transform calculation submodule connection, the fourth terminal is connected to the first terminal of the constant false alarm detection control submodule, the fifth terminal is connected to the second terminal of the memory read-write control submodule, and the sixth terminal is connected to the first terminal of the memory read-write control submodule .

The second terminal of the CFAR detection control submodule is connected to the first terminal of the CFAR calculation submodule, the third terminal is connected to the second terminal of the CFAR calculation submodule, and the fourth terminal is connected to the digital beamforming control submodule The first end is connected to the first end, and the fifth end is connected to the second end of the second memory.

The second terminal of the digital beamforming control submodule is connected to the first terminal of the digital beamforming calculation submodule, the third terminal is connected to the second terminal of the digital beamforming calculation submodule, and the fourth terminal is connected to the first terminal of the CAN analysis submodule. The terminals are connected, the fifth terminal is connected with the second terminal of the third memory, and the sixth terminal is connected with the first terminal of the second memory.

The second end of the CAN analysis sub-module is connected to the CAN bus, and the third end is connected to the first end of the third memory.

Among them, the Fourier transform control sub-module is used to receive and count the RF front-end radar data transmitted by the front-end ADC, control the combination of data arrays, and select the corresponding data to transfer to the Fourier transform calculation sub-module for calculation, through Fourier transform The calculation sub-module obtains the speed and distance of the target. The Fourier transform control submodule is also used to store and manage the results of the Fourier transform, that is, to store the results of the Fourier transform into the first memory (two-dimensional fast Fourier transform (Fast Fourier Transform, FFT) memory ).

The RF front-end radar data transmitted by the ADC is an intermediate frequency signal, which comes from the transformation of the FMCW echo signal reflected back from the target.

After the two-dimensional Fourier transform is completed, the Fourier transform control sub-module sends an enable signal to the CFAR detection control sub-module, and the constant false alarm detection control sub-module calculates the storage address of the data in the two-dimensional FFT memory according to the window function , and read out the corresponding data, the constant false alarm calculation submodule identifies the position of the data containing the target information in the two-dimensional FFT spectrogram, judges whether it is a peak value, if so, calculates the address of the peak value data in the first memory, and sends This address is stored in the second memory (CFAR memory).

The digital beamforming control submodule accesses the second memory to obtain the address of the peak data in the second memory, and the digital beamforming control submodule accesses the peak data of different antennas in the first memory according to the address, and beams the data Form the angle to get the target.

The memory read and write control sub-module controls the access of different modules to the memory to prevent read and write conflicts.

The storage read-write control sub-module avoids read-write conflicts when multiple modules access the two-dimensional FFT memory by means of preset priorities. The priority order from high to low is: Fourier transform control sub-module, constant false alarm detection Control sub-module, digital beam forming control sub-module, CAN analysis sub-module.

The controller area network (CAN) analysis sub-module realizes the communication between the chip and the external system, and outputs the target data (sensing information). The target data includes the target's speed, distance and angle.

Optionally, before data processing, the radar baseband module should be configured first, and the radar baseband module can send configuration-related information through the CAN bus. The configuration-related information includes the configuration parameters of the FFT matrix specification, the type of the detection window function and detection coefficient, etc. The register modifies the register by parsing the content of the data field of the CAN standard frame to realize the specification of the two-dimensional Fourier transform matrix of different regulations. For example, in this embodiment, the distance dimension FFT size is 256 points, the speed dimension FFT size is 128 points, and the number of antennas is 4.

The front-end ADC performs analog-to-digital conversion in real time and inputs data to the radar baseband module. The number of ADCs is consistent with the number of antennas.

When the data converted by the ADC is an echo signal containing target information, the ADC will output a valid indication signal while outputting the sampling signal, indicating that the sampling signal corresponds to the valid data interval of the FMCW echo.

When the sampling signal is a new period, the ADC will output a synchronous indication signal while outputting the sampling signal, indicating that the data after the sampling signal comes from a new set of FMCW echoes.

The radar baseband module (Fourier transform control sub-module) starts counting after receiving a valid signal, and when a preset amount (for example, 256 points) of data is accumulated, the Fourier transform control sub-module sends the data into the Fourier transform Lie transform calculation sub-module.

The Fourier transform calculation sub-module is used to perform one-dimensional FFT transformation. The Fourier transform control sub-module sends the single-dimensional FFT data to be calculated to the Fourier transform calculation sub-module through counting processing and calculation of data read and write addresses. So as to realize the two-dimensional FFT transformation.

The Fourier transform control sub-module is used to process the input signal of the previous stage, count and arrange the data that needs FFT transform according to the matrix specification and send it to the Fourier transform calculation sub-module, control the reading, writing and storage of the multi-antenna FFT transform results, and realize the calculation The storage address of the memory required by the two-dimensional FFT transformation.

Since there are 4 groups of antennas, there are four groups of two-dimensional FFT spectrograms to be calculated. Since the FFT calculation unit uses a large number of multipliers, considering the chip area and power consumption, the data of the 4 groups of antennas enters the Fourier transform calculation sub-module in turn.

Fig. 2 is the timing diagram of the Fourier transform provided by the present application. As shown in Fig. 2, the radar baseband module only has one Fourier transform calculation sub-module, and the antenna data to be processed are multiple groups;

In the embodiment of this application, the radar baseband module only has one Fourier transform calculation sub-module, and the antenna data to be processed is multiple groups, and the Fourier transform control sub-module adopts a pipeline structure to realize the Fourier transform of multiple groups of antenna data , thereby reducing the area of the chip and reducing the power consumption of the chip.

Taking 4 groups of antennas as an example, the implementation method is as follows: collect the data of 4 groups of antennas at the same time, first perform distance dimension FFT on the data of antenna 0, and wait for the data of other antennas; then, store the distance dimension FFT results of antenna 0, At the same time, perform distance-dimension FFT on the data of antenna 1, and wait for the data of antenna 2 and antenna 3; then perform velocity-dimension FFT on the data of antenna 0, store the distance-dimension FFT results of antenna 1, and simultaneously perform an FFT on the data of antenna 2 For distance dimension FFT, the data of antenna 3 is waiting, and so on.

Figure 3, Figure 4 and Figure 5 are the hardware implementation schemes of the Fourier transform control sub-module. Taking 4 groups of antennas as an example, four ADCs input data to the Fourier transform control sub-module at the same time, and each When the data of each channel is accumulated to 256 points, the Fourier transform control sub-module saves the group of data. Since the calculation sub-module used to calculate Fourier transform can only calculate one set of data at a time, and in order to ensure that the sampling time of the four channels of data is the same, the four groups of registers CH0_REG, CH1_REG, CH2_REG, and CH3_REG are used to save the original sampled data. In chronological order, the four sets of original data enter the Fourier transform calculation sub-module for calculation, and store the results again in CH0_REG, CH1_REG, CH2_REG, and CH3_REG. After the four sets of calculations are completed, the calculation results are stored in the first memory. , the Fourier transform control submodule reads in the ADC data again. After the above process is repeated 128 times, the total amount of data has reached the demand for two-dimensional FFT calculation, and the Fourier transform of the velocity dimension is started.

The Fourier transform of the velocity dimension starts. First, a set of velocity dimension data of antenna 0 is read in, and the data is windowed in real time. After accumulating 128 data, the data is transferred to the Fourier calculation sub-module for calculation. After the Fourier transform result is obtained, the data is written back to the same position of the antenna 0 data in the first memory, and the data of the antenna 1 is read in while writing. Since the data written in antenna 0 has the same length as the read data read by antenna 1, and there is no read-write conflict in different address partitions in the first memory, in order to improve the system processing speed, the write operation and read operation are combined in the Fourier control submodule designed to be done simultaneously. After the data of antenna 1 is read out, FFT is performed on the data of antenna 1, and the result is written back into the first memory and the data of antenna 2 is read in at the same time. The same operation is performed on the data of antenna 2 and antenna 3 in turn, and the data of antenna 0 at the next position is read again while the data of antenna 3 is written back, and the next-dimensional Fourier transform is performed. When the loop is operated 128 times as above, the Fourier transform of all velocity-dimensional data is completed.

As far as the specific circuit is concerned, the ADC input data is windowed using the Hamming window, and the window function is solidified in the circuit by hardware. rd_adc_cnt is used to count the data read from the ADC in each group of continuous frequency modulation signals. According to the count value of rd_adc_cnt, the corresponding window function is multiplied by the original data to realize the windowing algorithm. In order to reduce the chip area and power consumption, it is considered that in the design implementation, the original data is no longer needed after the Fourier transform calculation is completed, so the MUX can select channels according to the different states of the system, so that CH{n}_REG is used for storage The data after windowing can also be used to store the data after FFT. The data output by CH{n}_REG is output to the next stage through a decoder (Decoder, referred to as "DC"). If the output is windowed data, the data is input to ADDR_REV to rearrange the data, and finally Output to the Fourier transform calculation sub-module for calculation. If the output is the data completed by the FFT calculation, the data is output to the memory read/write control sub-module for storage. Since the directions of the two FFT calculations are inconsistent, skip-continuous storage is used in the storage of the first memory. For the data of the same group of continuous frequency modulation signals, one data is written in each 128-bit address in sequence, so as to ensure that the next module can follow Read data in increments of one. The implementation method is as shown in the figure. The address is divided into high 7bit and low 7bit. The high 7bit is incremented by 1 every time a data is written, and the low 7bit is incremented by 1 every time a group of continuous frequency modulation signal data is written.

After all the data in the distance dimension are processed, the data is sequentially read from the first memory in accordance with the order of the input data in the speed dimension, and the windowing function is implemented through the multiplier operation to realize windowing. After the row module (ADDR_REV) is sent to the Fourier transform calculation sub-module for FFT calculation. After receiving the calculation completion signal, the Fourier transform control sub-module saves the data in the register, and writes the data into the memory for the first time in sequence according to the address.

Figure 6 is a schematic diagram of the parallel iterative structure of the Fourier transform calculation sub-module provided by the present application. As shown in Figure 6, the Fourier transform calculation sub-module adopts a parallel iterative structure to realize one-dimensional FFT transformation, the 0th level and the 1st level The calculation of the first level is directly realized by the adder. After the calculation result of each level is completed, according to the extraction rule, the output of the calculation result of the upper level is corresponding to the calculation input of the next level, and is sent to the calculation array of the butterfly unit. After all calculations of the one-dimensional FFT are completed, the data is sequentially written into the second memory.

It should be noted that: in the embodiment of the present application, the writing sequence of the addresses is performed according to the preset sequence. For example, after the first 256-point FFT calculation is completed, the write addresses are 0, 0+speed dimension FFT size points, 0+2×velocity dimension FFT size points, ... until the last result of this FFT calculation is written; After the second 256-point FFT calculation is completed, the write addresses are 1, 1+speed dimension FFT size points, 1+2×velocity dimension FFT size points, ... until the last result of this FFT calculation is written, and follow By analogy, after the nth FFT calculation is completed, the write addresses are n-1, n-1+speed dimension FFT size points, n-1+2*speed dimension FFT size points; where n is equal to the number of continuous FM waves, That is, the velocity dimension FFT size points.

After receiving the effective start signal of the second group of continuous chirp signals, start to calculate the second 256-point FFT calculation, and repeat in turn.

When a total of 128 groups of 256 points of data have been received, the original data required for the two-dimensional FFT spectrum map of the radar baseband chip has been collected, and since the distance dimension FFT adopts a pipeline architecture, it is completed synchronously with the receipt collection.

Therefore, the distance-dimension FFT results are fetched from the first memory, and the velocity-dimension FFTs are calculated sequentially.

Due to the order setting of distance dimension FFT storage, only 128 points of data need to be taken out sequentially when calculating velocity dimension.

In the embodiment of the present application, the Fourier transform calculation sub-module adopts a parallel iterative structure, and addresses are written in the order described above, thereby increasing the calculation speed and reducing the area of the chip.

Due to the gain in FFT calculation, in order to improve the calculation speed and storage efficiency, Figure 7 is a schematic diagram of the storage format of the Fourier transform result provided by this application. As shown in Figure 7, the embodiment of this application uses 24-bit operations when performing FFT calculations The unit, that is, the real part and the imaginary part of the data are 24 bits each, and the real part and the imaginary part are stored in a format of 16 bits each. Among them, the high (MSB) 13 bits represent the data content, and the low (LSB) 3 bits represent the data index.

In the embodiment of the present application, a 24-bit arithmetic unit is used for FFT calculation, and a 16-bit storage format for real and imaginary parts is used for storage, thereby reducing memory area, chip area and power consumption.

After the FFT calculation is completed, an enabling signal is sent to the CFAR detection control sub-module.

The constant false alarm detection control sub-module is used to calculate the address and result storage of the data to be taken out according to the window function, and the constant false alarm detection calculation module is used to calculate whether the detection condition is met between the detection target and the window.

The type of detection window function and detection coefficient are configured through the CAN bus. The constant false alarm detection control submodule can adjust the detection window function and detection coefficient according to the register configuration. The register modifies the register by analyzing the content of the data field of the CAN standard frame. Realize the configuration of different window functions and detection coefficients.

In the embodiment of this application, the CAN parsing sub-module is integrated, so that the automotive system can be directly configured with a radar baseband module without an additional CPU.

FIG. 8 is a schematic diagram of a window function provided by the present application. As shown in FIG. 8 , the window function includes a unit to be detected, a protection unit and a window unit.

The constant false alarm detection calculation sub-module calculates the address of the data that needs to be taken out of the four groups of antennas in real time according to the selected window function and calculates the average value.

When the absolute value of the value of the unit to be detected is greater than the product of the mean value of the window unit multiplied by the detection coefficient, there is a target in the unit to be detected, otherwise there is no target.

When there is a target in the unit to be detected, the CFAR detection control submodule writes the address into the CFAR memory.

After all the detections are completed, the CFAR detection control submodule sends an enabling signal to the digital beamforming control submodule.

FIG. 9 is a schematic structural diagram of the CFAR calculation sub-module of the present application. For the designed CFAR detection, the calculation sub-module must be able to run the above six window function modes at the same time. According to the setting of the window function, the CFAR calculation sub-module selects a one-dimensional window through the chip selection signal for calculation and synthesizes a two-dimensional constant false alarm window for calculation, and finally judges whether the target exists by comparing the calculation result with the threshold value.

For example, the smallest window is 3*3, and correspondingly, three one-dimensional CFAR window calculation units are multiplexed to realize two-dimensional constant false alarm window calculation. The initial read address of the first one-dimensional constant false alarm window calculation unit takes the start address of the second row, and substitutes the input signal into the calculation; the initial read address of the second one-dimensional constant false alarm window calculation module takes the first row The starting address of , the input signal of the second one-dimensional false alarm window calculation module is the value of the detection unit. The value of the window calculated at this time contains a window with a row of zeros. When the newline starts, the third one-dimensional CFAR module is enabled, the initial read address is zero, and the input signal is substituted into the calculation.

For a 5*5 window, 5 one-dimensional CFAR modules are used for multiplexing. The initial reading address of the first one-dimensional CFAR module is the starting address of the third row of the matrix, and the input signal is substituted into the window for calculation; the initial reading address of the second one-dimensional CFAR module is the starting address of the second row of the matrix , and select different protection unit lengths corresponding to different modes; the initial read address of the third one-dimensional CFAR module is the starting address of the first row of the matrix, and its input signal is the detection unit. When the newline starts, the next two one-dimensional CFAR modules are enabled one by one, and the starting addresses are both zero. The digital beamforming calculation sub-module includes multiple calculation units, for example, a total of 8 calculation units are designed, and each calculation unit can independently complete the beamforming and obtain the target angle.

After receiving the enable signal sent by the CFAR detection control sub-module, in the first clock cycle, the digital beam-forming control sub-module takes out the data in the constant false alarm memory address 0, that is, the first peak data in the two-dimensional FFT memory address in .

In the second clock cycle, access the two-dimensional FFT memory according to the address, and read out the original value of the peak data corresponding to the four groups of antennas. The address of peak data in the two-dimensional FFT memory.

In the third clock cycle, the original value of the first peak data corresponding to the four groups of antennas is sent to the calculation unit 1 of the digital beamforming calculation sub-module, and at the same time, the two-dimensional FFT memory is accessed according to the data of the constant false alarm memory address 1, Read out the original value of the second peak data corresponding to the four groups of antennas.

In the fourth clock cycle, the original value of the second peak data corresponding to the four groups of antennas is sent to the calculation unit 2 of the digital beamforming calculation sub-module.

The usage sequence of calculation unit 3, calculation unit 4, ..., calculation unit 8 is consistent with the previous ones, and all of them calculate data in the form of pipeline.

In the embodiment of the present application, various window functions can be adapted to different scenarios (weather, humidity, etc.) in actual driving to ensure radar detection results in different scenarios.

The beamforming calculation unit sets different weights (-ω, 0, ω, 2ω) according to the 0 to 180 degrees corresponding to the four groups of antennas, where ω changes according to the transformation of the angle value. Assume that the peak data vectors corresponding to the four groups of antennas are

The beamforming calculation formula is

able to satisfy

The angle corresponding to ω0 of , indicates the direction of the target.

Optionally, in this embodiment of the present application, the peak data corresponding to the four groups of antennas are multiplied by the antenna weights using the CORDIC algorithm instead of the multiplier, which can further increase the calculation speed.

When the calculation unit completes a set of calculations, the value and calculation results of the initially read-in constant false alarm memory are written into the third memory (beamforming result memory), and the contents of this memory can also be related to the angle, distance, One-to-one correspondence with speed.

The specific circuit structure is shown in Figure 10. The digital beamforming control submodule reads the data of antenna 0, antenna 1, antenna 2, and antenna 3 corresponding to the target point through the memory read and write control submodule, and passes the data selector (MUX ) sequentially send each group of data to different digital beamforming calculation sub-modules.

For example, the digital beamforming calculation sub-module implements the multiplication of the peak data and the weights (-ω, 0, ω, 2ω) of four sets of antenna angles through the CORDIC algorithm, (ω is a variable value, and each angle has a corresponding ω value), and add the product results corresponding to the same angle, that is, the calculation formula for realizing beamforming is

Determine the maximum value of the sum of all products through the comparator, that is, find the maximum value that can satisfy

ω0, the angle corresponding to this ω0 is the target angle. Finally, the angle of the target is sequentially output through the data selector, and the result is written into the third memory.

After the digital beamforming calculation is completed, it communicates with the outside through the CAN bus.

First, the radar baseband module broadcasts a message, indicating that a target detection is completed.

After that, the radar baseband module starts to wait, and the timer starts counting at the same time. When the CAN analysis sub-module in the radar baseband module receives the transmission permission and the timer is not 0, the data result is transmitted according to the requirements of the transmission permission, and the next round of target detection is started; if the timer counts down to 0, it has not yet After receiving the transmission permission, the radar baseband module will also start the next round of target detection.

It should be noted that the above-mentioned broadcast message and transmission permission are transmitted through the CAN standard frame. The standard frame structure is shown in Figure 11. Only writing specific characters in the DATA field triggers the corresponding mechanism; among them, the DATA field The upper 4 bytes of the upper 4 bytes are fixed as control instructions, followed by specific data. The CAN analysis sub-module of the radar baseband module can access the Fourier transform memory, constant The false alarm memory and the digital beamforming memory realize the function of chip debugging, and the corresponding relationship between their specific formats and functions is shown in Figure 12. Among them, the 7th bit of Byte3 represents the data direction, the 6th to 4th bits represent specific data functions, such as configuring FFT parameters, CFAR parameters, DBF parameters or accessing RAM data, and the 3rd to 0th bits are based on the 6th to 0th bits. Different 4-bit values represent different meanings. For example, if CFAR parameters are configured, different values represent different corresponding registers; if RAM is accessed, it represents the number and method of accessing RAM (all/a piece of data/a certain data). The configuration of Byte2 and Byte1 has different meanings according to the meaning of Byte3. If the instruction of Byte3 is a configuration register, Byte2 and Byte1 represent the specific value of the register; if the instruction of Byte3 is to access RAM, then Byte2 and Byte1 represent the starting range of the access address . The configuration of Byte0 is a reserved bit for the configuration register function; for the function of accessing a piece of data, it represents the data length.

In addition, the first memory, the second memory, and the third memory in the embodiment of the present application may also be combined into one memory. The first memory, the second memory and the third memory are all random access memories (Random Access Memory, RAM).

Optionally, this embodiment of the present application further provides a radar system, including the radar baseband module described in any of the foregoing embodiments.

Specifically, the structure and working principle of the radar baseband module in the above-mentioned radar system provided by the embodiment of the present application can refer to the above-mentioned embodiment, and can achieve the same technical effect, and the same parts and beneficial effects will not be described in detail here. .

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, rather than limiting them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present application.

Claims

A radar baseband module, characterized in that it includes: Fourier transform control submodule, Fourier transform calculation submodule, constant false alarm detection control submodule, constant false alarm calculation submodule, digital beamforming control submodule, Digital beamforming calculation sub-module, controller area network CAN analysis sub-module, memory read and write control sub-module, first memory, second memory, third memory;

The first end of the Fourier transform control submodule is connected to the analog-to-digital converter, the second end is connected to the first end of the Fourier transform calculation submodule, and the third end is connected to the second end of the Fourier transform calculation submodule connection, the fourth terminal is connected to the first terminal of the constant false alarm detection control submodule, the fifth terminal is connected to the second terminal of the memory read-write control submodule, and the sixth terminal is connected to the first terminal of the memory read-write control submodule ;

The second terminal of the CFAR detection control submodule is connected to the first terminal of the CFAR calculation submodule, the third terminal is connected to the second terminal of the CFAR calculation submodule, and the fourth terminal is connected to the digital beamforming control submodule The first terminal is connected, and the fifth terminal is connected to the second terminal of the second memory;

The second terminal of the digital beamforming control submodule is connected to the first terminal of the digital beamforming calculation submodule, the third terminal is connected to the second terminal of the digital beamforming calculation submodule, and the fourth terminal is connected to the first terminal of the CAN analysis submodule. The terminals are connected, the fifth terminal is connected with the second terminal of the third memory, and the sixth terminal is connected with the first terminal of the second memory;

The second end of the CAN analysis sub-module is connected to the CAN bus, and the third end is connected to the first end of the third memory;

The third terminal of the memory read-write control submodule is respectively connected to the sixth terminal of the constant false alarm detection control submodule, the seventh terminal of the digital beamforming control submodule and the fourth terminal of the CAN analysis submodule, and the fourth terminal is connected to the fourth terminal of the CAN analysis submodule. The second end of a memory is connected, and the fifth end is connected with the first end of the first memory.
The radar baseband module according to claim 1, wherein the radar baseband module is only provided with a Fourier transform calculation submodule, and the antenna data to be processed are multiple groups;

The Fourier transform control sub-module adopts the pipeline structure to realize the Fourier transform of multiple sets of antenna data.
The radar baseband module according to claim 1, wherein the Fourier transform calculation submodule adopts a parallel iterative structure;

The calculation of the 0th level and the 1st level is realized by an adder. After the calculation result of each subsequent level is completed, according to the extraction rule, the output of the calculation result of the upper level corresponds to the calculation input of the next level and is sent to the butterfly unit. in the calculation array.
The radar baseband module according to claim 1, wherein, after all calculations of the single-dimensional fast Fourier transform (FFT) are completed, it is sequentially written into the first memory in the following order:

After the i-th FFT calculation is completed, the write addresses are i-1, i-1+speed dimension FFT size points, i-1+2*velocity dimension FFT size points, ... until the last FFT calculation of this time is written result;

Wherein, the value range of i is from 1 to n, and n is equal to the number of continuous frequency modulation waves.
The radar baseband module according to claim 3, wherein the configuration parameters of the FFT matrix specification are configured through the CAN bus.
The radar baseband module according to claim 1, wherein the Fourier transform control submodule adopts a 24-bit arithmetic unit, and each of the real part and the imaginary part of the data is 24 bits;

The first memory adopts the format of storing 16 bits of each real part and imaginary part, wherein the upper 13 bits represent the data content, and the lower 3 bits represent the data index.
The radar baseband module according to claim 1, wherein the constant false alarm detection control submodule adjusts the detection window function and the detection coefficient according to the register configuration, the constant false alarm calculation submodule is set according to the window function, and is selected by the chip selection signal Determine the one-dimensional window calculation and synthesize the two-dimensional constant false alarm window calculation, and finally judge whether the target exists by comparing the calculation result with the threshold value.
The radar baseband module according to claim 6, wherein when there is a target in the unit to be detected, the constant false alarm detection control submodule writes the corresponding address into the second memory.
The radar baseband module according to claim 6, wherein the type of the detection window function and the detection coefficient are configured through the CAN bus.
The radar baseband module according to claim 1, wherein the digital beamforming control submodule reads in the data of multiple groups of antennas corresponding to the target point through the memory read and write control submodule, and sequentially converts each group of data through the data selector Send to different digital beamforming calculation sub-modules;

The digital beamforming calculation sub-module is used to determine the target angle through the beam form of the peak data of multiple groups of antennas, and finally output the target angle sequentially through the data selector, and write the result into the third memory.
The radar baseband module according to claim 1, wherein the storage read-write control sub-module avoids the read-write conflict of each sub-module accessing the memory through a preset priority order, and the preset priority order is from high to low: Fourier transform control sub-module, constant false alarm detection control sub-module, digital beam forming control sub-module, CAN analysis sub-module.
A radar system, characterized by comprising the radar baseband module according to any one of claims 1 to 11.