WO2023010206A1

WO2023010206A1 - Time-domain comparator and phase frequency detector

Info

Publication number: WO2023010206A1
Application number: PCT/CA2022/051175
Authority: WO
Inventors: Mahin ESMAEILZADEH; Mohamad Sawan; Yves Audet
Original assignee: Polyvalor, Limited Partnership
Priority date: 2021-08-02
Filing date: 2022-08-02
Publication date: 2023-02-09

Abstract

A phase-frequency detector comprises first transistor branch generating a first intermediate signal based on an input frequency signal, another first transistor branch generating a second intermediate signal based on a reference frequency signal, a second transistor branch receiving the input frequency and first intermediate signals and producing a first result signal, another second transistor branch receiving the reference frequency and second intermediate signals and producing a second result signal, a third transistor branch receiving the first result signal from the second transistor branch and the second result signal from the other second transistor branch, another third transistor branch receiving the second result signal from the other transistor branch and the first result signal from the second transistor branch, a first voltage divider producing a third result signal based on the first result signal, and a second voltage divider producing a fourth result signal based on the second result signal.

Description

TIME-DOMAIN COMPARATOR AND PHASE FREQUENCY DETECTOR

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims the benefit of United States Provisional Patent Application No. 63/228,245 filed on August 2, 2021 , the contents of which are hereby incorporated by reference in their entirety.

TECHNICAL FIELD

[0002] The present disclosure relates generally to the field of signal processing, and more specifically to signal comparators.

BACKGROUND

[0003] The field of signal processing is wide-ranging, and techniques for signal processing can be performed both in the time domain and the frequency domain. One type of system used for time-domain signal processing is a time domain comparator (TDC). TDCs are a constituent block in a variety of electronic designs, and the precision of a TDC affects the performance of electronic systems in which the TDC is incorporated. In turn, the precision of a given TDC is dependent on the components of the TDC, which may include voltage-to-time converters and phase detectors.

[0004] As a result, improvements remain desirable.

SUMMARY

[0005] In accordance with one aspect, there is provided a phase-frequency detector, comprising a first sub-circuit and a second sub-circuit, each of the first and the second subcircuit comprising a first stage comprising interconnected first and second transistor branches and a second stage connecting to the first stage, the second stage comprising third, fourth, and fifth transistor branches. The first transistor branch of the first sub-circuit is configured for receiving an input frequency signal and for generating a first intermediate signal based on the input frequency signal, and the first transistor branch of the second sub-circuit is configured for receiving a reference frequency signal and for generating a second intermediate signal based on the reference frequency signal. The second transistor branch of the first sub-circuit is configured for receiving the input frequency signal and the first intermediate signal and for producing a first result signal, and the second transistor branch of the second sub-circuit is configured for receiving the reference frequency signal and the second intermediate signal and for producing a second result signal. The third transistor branch of the first sub-circuit is configured for receiving the first result signal from the second transistor branch of the first subcircuit and the second result signal from the second transistor branch of the second sub-circuit, and the third transistor branch of the second sub-circuit is configured for receiving the second result signal from the second transistor branch of the second sub-circuit and the first result signal from the second transistor branch of the first sub-circuit. The fourth and fifth transistor branches of the first sub-circuit form a first voltage divider configured for producing a third result signal based on the first result signal, and the fourth and fifth transistor branches of the second sub-circuit form a second voltage divider configured for producing a fourth result signal based on the second result signal, the third and fourth result signals indicative of at least one difference in at least one of frequency and phase between the input frequency signal and the reference frequency signal.

[0006] In some embodiments, the third transistor branch of each of the first and second sub-circuits comprises a first p-type metal-oxide-semiconductor (PMOS) transistor and a second PMOS transistor connected in series, the first PMOS transistor of the first sub-circuit and the second PMOS transistor of the second sub-circuit being gate-controlled by the second result signal, and the second PMOS transistor of the first sub-circuit and the first PMOS transistor of the second sub-circuit being gate-controlled by the first result signal.

[0007] In some embodiments, the fourth transistor branch of each of the first and second sub-circuits comprises a PMOS transistor and a first and a second n-type metal-oxide- semiconductor (NMOS) transistor connected in series, the PMOS transistor and the first and second NMOS transistors of the first sub-circuit being gate-controlled by the first result signal, and the PMOS transistor and the first and second NMOS transistors of the second sub-circuit being gate-controlled by the second result signal.

[0008] In some embodiments, the phase-frequency detector further comprises a first inverter configured to receive the first result signal and to output a first inverted signal based on the first result signal, and a second inverter configured to receive the second result signal and to output a second inverted signal based on the second result signal.

[0009] In some embodiments, the first transistor branch of each of the first and second subcircuits comprises a PMOS transistor and a first, a second, and a third NMOS transistor connected in series, the first NMOS transistor of the first sub-circuit and the second NMOS transistor of the second sub-circuit being gate-controlled by the second inverted signal, and the second NMOS transistor of the first sub-circuit and the first NMOS transistor of the second sub-circuit being gate-controlled by the first inverted signal.

[0010] In some embodiments, the fifth transistor branch of each of the first and second subcircuits comprises an NMOS transistor having its source connected to ground, the NMOS transistor of the first sub-circuit being gate-controlled by the second inverted signal and the NMOS transistor of the second sub-circuit being gate-controlled by the first inverted signal.

[0011] In some embodiments, the first transistor branch of each of the first and second subcircuits is configured for resetting the first stage when the input frequency signal and the reference frequency signal are at logical high and the first and second result signals are at logical low.

[0012] In some embodiments, the third transistor branch of each of the first and second sub-circuits is configured for maintaining the first result signal at logical high when the input frequency signal and the reference frequency signal are at logical high.

[0013] In some embodiments, when one of a phase and a frequency of the input frequency signal is leading that of the reference frequency signal, the fourth transistor branch of the first sub-circuit produces the third result signal based on the first result signal and generates a logical high output on a first output line, and the fourth transistor branch of the second subcircuit produces the fourth result signal based on the second result signal and generates a zero output on a second output line.

[0014] In some embodiments, when one of the phase and the frequency of the input frequency signal is lagging that of the reference frequency signal, the fourth transistor branch of the first sub-circuit produces the third result signal based on the first result signal and generates the zero output on the first output line, and the fourth transistor branch of the second sub-circuit produces the fourth result signal based on the second result signal and generates the logical high output on the second output line.

[0015] In some embodiments, the third result signal and the fourth result signal each comprises a plurality of pulses, and the first voltage divider is configured to reduce a width of erroneous ones of the plurality of pulses in the third result signal and the second voltage divider is configured to reduce the width of the erroneous ones of the plurality of pulses in the fourth result signal.

[0016] In accordance with another aspect, there is provided a time-domain comparator, comprising a phase-frequency detector, a first voltage-to-time converter and a second voltage- to-time converter, the first voltage-to-time converter coupled to an input for receiving an input signal therefrom, the first voltage-to-time converter configured to output the input frequency signal based on the input signal, and a voltage reference generator coupled to the second voltage-to-time converter for providing a reference signal to the second voltage-to-time converter, the second voltage-to-time converter configured to output the reference frequency signal based on the reference signal. The phase-frequency detector is coupled to the first and second voltage-to-time converters for receiving the input frequency signal and the reference frequency signal therefrom and for producing the third and fourth result signals indicative of the at least one difference in at least one of frequency and phase between the input frequency signal and the reference frequency signal.

[0017] In some embodiments, the first voltage-to-time converter is configured to output the input frequency signal having a first oscillation frequency indicative of the input signal, and the second voltage-to-time converter is configured to output the reference frequency signal having a second oscillation frequency indicative of the reference signal.

[0018] In some embodiments, the time-domain comparator further comprises a control unit configured to produce a control signal for selectively enabling and disabling an operation of the first and second voltage-to-time converters. [0019] In some embodiments, the control unit is configured to produce the control signal for disabling the operation of the first and second voltage-to-time converters subsequent to the third and fourth result signals being produced by the phase-frequency detector.

[0020] In some embodiments, each of the first voltage-to-time converter and the second voltage-to-time converter is a ring-oscillatory type voltage controlled oscillator.

[0021] In accordance with yet another aspect, there is provided a method of controlling a time-domain comparator. The method comprises providing an input signal to a first voltage- to-time converter and providing a reference signal to a second voltage-to-time converter, obtaining, at a phase-frequency detector, an input frequency signal from the first voltage-to- time converter and a reference frequency signal from the second voltage-to-time converter, the input frequency signal generated based on the input signal and the reference frequency signal generated based on the reference signal, comparing, at the phase-frequency detector, a magnitude of the input signal to a magnitude of the reference signal, and comparing the input frequency signal to the reference frequency signal, when the magnitude of the reference signal is greaterthan the magnitude of the input signal and the input frequency signal is greater than the reference frequency signal, setting, at the phase-frequency detector, a first output signal provided on a first output line to logical high and a second output signal provided on a second output line to logical low, when the magnitude of the reference signal is smaller than the magnitude of the input signal and the input frequency signal is smaller than the reference frequency signal, setting, at the phase-frequency detector, the first output signal to logical low and the second output signal to logical high, and outputting the first output signal.

[0022] In some embodiments, the method further comprises producing a control signal for selectively enabling and disabling an operation of the first and second voltage-to-time converters.

[0023] In some embodiments, the control signal is produced for disabling the operation of the first and second voltage-time-time converters subsequent to the first and second output signals being set. [0024] In some embodiments, producing the control signal comprises setting the control signal to logical high to deactivate discharging paths of the first and second voltage-to-time converters and cause outputs of the first and second voltage-to-time converters to remain at their previous states.

[0025] Many further features and combinations thereof concerning embodiments described herein will appear to those skilled in the art following a reading of the instant disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In the figures:

[0027] FIG. 1 is a block diagram of an example time-domain comparator.

[0028] FIG. 2 is a flowchart of an example method for controlling the time-domain comparator of FIG. 1 .

[0029] FIG. 3 is circuit diagram of an example phase-frequency detector.

[0030] FIG. 4 is a flowchart of an example method for controlling the phase-frequency detector of FIG. 3.

[0031] FIG. 5 illustrates example timing diagrams for the phase-frequency detector of FIG. 3.

[0032] FIG. 6 illustrates an example timing diagram for an example input signal to the phase-frequency detector of FIG. 3.

[0033] FIG. 7 illustrates example timing diagrams for the phase-frequency detector of FIG. 3 and a conventional phase-frequency detector.

[0034] FIG. 8 is an example transient simulation of the phase-frequency detector of FIG. 3.

[0035] FIG. 9 is a graphical representation of example transfer characteristics of the phasefrequency detector of FIG. 3. [0036] FIG. 10A is an example transient wave diagram of the time-domain comparator of

FIG. 1.

[0037] FIG. 10B is an example plot illustrating the performance of the time-domain comparator of FIG. 1 , when employing a dead-zone compensated phase-frequency detector as per FIG. 3 versus when employing a non-zero dead-zone phase-frequency detector.

[0038] FIG. 10C is an example plot illustrating the comparison time of the time-domain comparator of FIG. 1 versus input voltage difference.

[0039] FIG. 11 A is a schematic diagram of an example voltage-controlled oscillator used to implement the voltage-to-time converter (VTC) units of FIG. 1 .

[0040] FIG. 11 B is a graphical representation of an example oscillation frequency versus control voltage of the voltage-controlled oscillator of FIG. 1 1 A.

[0041] FIG. 12A is a schematic diagram of an alternative circuit design used to implement the VTC units of FIG. 1 .

[0042] FIG. 12B is a graphical representation of oscillation frequency versus control voltage for the example VTC circuit design of FIG. 12A.

[0043] FIG. 13 is a block diagram of an example computer for implementing part or all of the flowcharts of FIG. 2 and/or 4, and/or for implementing part or all of the time-domain comparator of FIG. 1 .

DETAILED DESCRIPTION

[0044] The present disclosure relates to time-domain comparators (TDCs) and their constituent blocks, including phase-frequency detectors (PFDs). At least some of the embodiments described herein provide a wide-band and high-precision TDC for comparing an input signal with a reference signal via their time-domain information and/or frequency domain information. At least some of the embodiments described herein provide a PFD which reduces or eliminates the presence of glitches, dead-zones, blind-zones, which offers linear performance over a full phase-range, and which has a wide frequency of operation. At least some of the embodiments described herein provide voltage-controlled oscillators (VCOs) to provide a voltage-to-time conversion based on an input signal. At least some of the embodiments described herein provide a control scheme, which in some instances reduces power consumption of the TDC during the comparison process.

[0045] PFDs have many use cases, including in the aforementioned TDCs, as well as in (but not limited to) phase lock loop (PLL), delay lock loop (DLL), or clock data recovery (CDR). PFDs can be used to measure differences in both frequency and phase substantially concomitantly, for instance unlike phase detectors, which detect a phase transition error. Certain conventional PFD designs have drawbacks, which may include high power consumption, significant area requirements on silicon dies, and may exhibit dead zones and/or blind zones in phase characteristics, which may cause jitter in the output of the PFD and may be added to random input-referred offset and noise of the comparator, and may limit the speed of operation thereof. The terms “dead zone” and “blind zone” are used to refer to regions of phase difference (between an input signal and a reference signal) for which a PFD is incapable of detecting or measuring the phase difference. The term “dead zone” is used to refer to undetectable phase differences centered around 0 phase error, and the term “blind zone” is used to refer to the time slot around +2TT for which phase differences are undetectable. The existence of dead zones and blind zones in the phase characteristics of a PFD may be due to an inability of the PFD to detect a rising edge on the input signal, or due to other issues.

[0046] In a TDC application, thermal and flicker noises can be presented as jitter at the VCO outputs and integrated over time. Because of these phase fluctuations, a dead zone in a PFD inhibits fast decision. Consequently, a dead zone is responsible for noise and comparator delay. A blind zone becomes more crucial for high-frequency operation. Both dead zones and blind zones thus have a significant effect on the resolution of the comparator. Also, different noise sources can contribute to the PFD, such as dead zones, finite reset time, and transistors. As will be discussed further below, in one embodiment, the proposed PFD circuit configuration minimizes the reset process time and hence the dead zone region, such that an improved phase noise performance can be achieved. In PLL applications, a dead zone introduces phase noise into a PLL system, and a blind zone aggravates cycle slips, lengthens the frequency acquisition process and reduces the range of phase-locking. [0047] With reference to FIG. 1 , a TDC 100 is illustrated. The TDC receives an input signal V_in via an input 102 and a reference signal V_ref via a voltage reference generator 1 10, and is governed by a clock 105 (indicated as CLK). The TDC 100 includes voltage-to-time conversion (VTC) units 120 and 122, a PFD unit 130, a control unit 140, and a determination unit 150. The TDC 100 produces a comparison output signal via an output 104. The input signal V_in and the reference signal V_ref are provided from the input 102 and the voltage reference generator 110, respectively, to the VTC units 120, 122 for transformation into time domain pulse signals. The output of the VTC units 120, 122 (termed frequency signals F_in and F_ref) are provided to the PFD unit 130, and have an oscillation frequency which is indicative of the input and reference signals (V_in and V_ref).

[0048] When the frequency signals F_in and F_ref are provided to the PFD unit 130, the PFD unit 130 can detect differences in phase and/or frequency between the two frequency signals F_in and F_ref . The structure of the PFD unit 130 is described in greater detail hereinbelow. In one example implementation, when the phase or the frequency of the input frequency signal F_in is leading (i.e., ahead of) that of the reference frequency signal F_ref , the PFD unit 130 will produce a logical high output on a first output line (indicated as UP line) whose average value is proportional to the phase difference of the frequency signals F_in and F_ref , and will produce a zero output on a second output line (indicated as DN line). Conversely, if the frequency signal F_in (i.e. the signal’s phase or frequency) is lagging the frequency signal F_ref , a logical high output is produced on the DN line, and a zero output is produced on the UP line. The control unit 140 serves to prevent or reduce power dissipation following a comparison procedure, i.e., when a result is provided at the output 104. In particular, the control unit 140 produces a control signal V_cntrl which serves to selectively enable or disable the operation of the VTC units 120, 122. In one embodiment, when V_cntrl is set to one (i.e., logic ‘1 ’), discharging paths of the outputs of the VTC units 120, 122 are deactivated, causing the outputs to remain at their previous state. It should however be understood that the operation of the control unit 140 may vary when other VTC designs are used.

[0049] With additional reference to FIG. 2, a method 200 for controlling the TDC 100 is illustrated in accordance with one embodiment. The method 200 starts at step 202, on the rising edge of the clock 105 (i.e., with the clock being at value ‘1 ’). At step 204, the input signal V_in and the reference signal V_ref are connected to, or otherwise provided to, the VTC units 120, 122, respectively. At decision step 206, the magnitude of the input signal V_in is compared to the magnitude of the reference signal V_ref. When the magnitude of the reference signal V_ref is greater than the magnitude of the input signal V_in, the method 200 moves to step 210. When the magnitude of the input signal V_in is greaterthan the magnitude of the reference signal V_ref, the method 200 moves to step 220.

[0050] At step 210, the frequency signal F_in is found to be greaterthan the frequency signal F_ref, since the frequency signals F_in and F_ref are based on the input signals V_in and V_ref (and on the design of the VTC units 120, 122). At step 212, an output signal indicative of the phase and/or frequency difference between the frequency signals F_in and F_ref is produced on the UP line of the PFD 130, and a zero output is produced on the DN line of the PFD 130. At decision step 214, a determination is made regarding whether the output signal on the UP line of the PFD 130 has reached logic ‘T. When the output signal on the UP line of the PFD 130 has not reached logic ‘T, the method 200 returns to step 212. When the output signal on the UP line of the PFD 130 has reached logic ‘T, the method 200 moves to step 216. At step 216, the control signal V_cntrl produced by the control unit 140 is set to 1 , in order to disable the VTC units 120, 122. At step 218, the output signals of the UP and DN lines are set to logic ‘1 ’ and ‘O’, respectively. The method 200 then moves to step 230.

[0051] At step 220, the frequency signal F_in is found to be less than the frequency signal F_ref, since the frequency signals F_in and F_ref are based on the input signals V_in and V_ref (and on the design of the VTC units 120, 122). At step 222, an output signal indicative of the phase and/or frequency difference between the frequency signals F_in and F_ref is produced on the DN line of the PFD 130, and a zero output is produced on the UP line of the PFD 130. At decision step 224, a determination is made regarding whether the output signal on the DN line of the PFD 130 has reached logic ‘T. When the output signal on the DN line of the PFD 130 has not reached logic ‘T, the method 200 returns to step 222. When the output signal on the DN line of the PFD 130 has reached logic ‘1 ’, the method 200 moves to step 226. At step 226, the control signal V_cntrl produced by the control unit 140 is set to 1 , in order to disable the VTC units 120, 122. At step 228, the output signals of the DN and UP lines are set to logic ‘1 ’ and ‘O’, respectively. The method 200 then moves to step 230.

[0052] At step 230, the output signal of the UP line is provided as the comparison output signal via the output 104. The comparison output signal may be provided to any other suitable device or system, for instance in embodiments in which the TDC 100 forms part of a broader signal processing device or system. At step 232, the method 200 ends.

[0053] With reference to FIG. 3, a circuit diagram of a PFD 300 (which forms at least part of the PFD unit 130) is illustrated. The PFD 300 is composed of two sub-circuits 310 and 320, in which the sub-circuit 310 is configured for receiving the input frequency signal F_in, and the sub-circuit 320 is configured for receiving the reference frequency signal F_ref . In addition, each of the sub-circuits 310, 320 is composed of two connected stages: sub-circuit 310 is composed of a first stage 312 and a second stage 314, and sub-circuit 320 is similarly composed of a first stage 322 and a second stage 324. For completeness, inverters 330 are also illustrated. In FIG. 3, NMOS (n-type metal-oxide-semiconductor field-effect transistor) transistors are labelled as M_NX, and PMOS (p-type metal-oxide-semiconductor field-effect transistor) transistors are labelled as M_PX, where X is an incrementing index value.

[0054] The first stage 312 of the sub-circuit 310 is composed of two interconnected transistor branches 312i, 3122. The first stage 312 obtains the frequency signal F_in and produces a result signal x_t (also referred to herein as a “first result signal”), which is in turn provided to the second stage 314 at node 316. Similarly, the first stage 322 of the sub-circuit 320 is composed of two interconnected transistor branches 322i, 3222. The first stage 322 obtains the frequency signal F_ref and produces a result signal x₂ (also referred to herein as a “second result signal”), which is in turn provided to the second stage 324 at node 326. In particular, the first transistor branch 312i of the first sub-circuit 310 is configured for receiving the input frequency signal F_in and for generating a first intermediate signal (at node ‘A’) based on the input frequency signal F_in, and the first transistor branch 322i of the second sub-circuit 320 is configured for receiving the reference frequency signal F_ref and for generating a second intermediate signal (at node ‘B’) based on the reference frequency signal F_ref . The second transistor branch 3122 of the first sub-circuit 310 is then configured for receiving the input frequency signal F_in and the first intermediate signal and for producing the first result signal x_{l t} and the second transistor branch 3222 of the second sub-circuit 320 is configured for receiving the reference frequency signal F_ref and the second intermediate signal and for producing the second result signal x₂.

[0055] The operation of the first stages 312, 322 is also dependent on inverted result signals x^, x^, which are produced by the inverters 330. In particular, a first one of the inverters 330 is configured to receive the first result signal

and to output a first inverted signal x^ based on the first result signal x_{l t} and a second one of the inverters 330 is configured to receive the second result signal ₂ and to output a second inverted signal x^ based on the second result signal x₂. The first transistor branch 312i, 3122 of each of the first and second sub-circuits 310, 320 comprises a PMOS transistor (MPI , Mp3) and a first NMOS transistor (MNI , MNS), a second NMOS transistor (MN2, MN ), and a third NMOS transistor (MN3, MNS) connected in series. The first NMOS transistor of the first sub-circuit 310 and the second NMOS transistor of the second sub-circuit 320 are gate-controlled by the second inverted signal

and the second NMOS transistor of the first sub-circuit 310 and the first NMOS transistor of the second sub-circuit 320 are gate-controlled by the first inverted signal rf. It should be noted that the first stages 312, 322, are reset through the transistors of branches 312i, 322i when the frequency signals F_in and F_ref are both at logical high (i.e. logic ‘1 ’), and when result signals and x₂ are both at logical low (i.e. logic ‘0’).

[0056] The second stage 314 of the sub-circuit 310 is composed of three interconnected transistor branches 314i, 3142, and 314s, and connects to the first stage 312 of the sub-circuit 310 at node 316. The transistor branch 314i is composed of two transistors and connects a logic high node (indicated as ‘VDD’) to the node 316. The inputs to the transistors of transistor branch 314i are the result signals x_{l t} x₂, and the transistor branch 314i serves to reduce or prevent leakage currents and charge losses at node x_± and keep it at high potential (i.e. logical high, or logic ‘1 ’) when both frequency signals F_in and F_ref are logic ‘T, which substantially accelerates the reset process. The transistor branch 3142 is composed of three transistors having the result signal x_± input at their respective gates, and connects the VDD node to ground. The transistor branch 314s is composed of a single transistor connected between node 318 and ground. [0057] The combination of transistors MP9-MNH-MNI2 (in transistor branch 3142) provides an inverter using a stacking technique, in which the width and height of signal ₃ at node 318 may be modulated. Due to the stacking effect, the sub-threshold leakage current flowing through the transistors of transistor branch 3142 decreases when more than one transistor in the stack is turned off. Together, the transistor branches 3142 and 314s act as a voltage divider to reduce the width of erroneous (i.e. undesired) pulses (also referred to herein as “glitches” or “spikes”) in signal ₃ produced at node 318, thereby diminishing the output produced by the second stage 314, which may in turn reduce the presence of glitches (i.e. erroneous spikes) produced by the PFD unit 130. The transistors in transistor branch 3142 are gate-controlled by the result signal x_t while the NMOS transistor (M_N15) in the fifth transistor branch 314s is gate-controlled by the second inverted signal x^.

[0058] The second stage 324 of the sub-circuit 320 is similarly composed of three interconnected transistor branches 324i, 3242, and 324s, and connects to the first stage 322 through transistor branch 3222 of the sub-circuit 320 at node 326. The transistor branch 324i is composed of two transistors and connects the VDD node to the node 326. The inputs to the transistors of transistor branch 324i are the result signals x , x₂, and the transistor branch 324i serves to reduce or prevent leakage currents and charge losses at node ₂ and keep it at high potential when both frequency signals F_in and F_ref are logic ‘T, which substantially accelerates the reset process. The transistor branch 3242 is composed of three transistors having the result signal x₂ input at their respective gates, and connects the VDD node to ground. The transistor branch 324s is composed of a single transistor connected between node 328 and ground. The combination of transistors MPIO-MNIS-MN- (in transistor branch 3242) provides an inverter using a stacking technique, in which the width and height of signal x₄ at node 328 may be modulated. Due to the stacking effect, the sub-threshold leakage current flowing through the transistors of transistor branch 3242 decreases when more than one transistor in the stack is turned off. Together, the transistor branches 3242 and 324s act as a voltage divider to reduce the width of erroneous (i.e. undesired) pulses (also referred to herein as “glitches” or “spikes”) in signal x₄ produced at node 328, thereby diminishing the output produced by the second stage 324, which may in turn reduce the presence of glitches produced by the PFD unit 130. The transistors in transistor branch 3242 are gate-controlled by the result signal %₂ while the NMOS transistor (M_N16) of the fifth transistor branch 324s is gate- controlled by the first inverted signal rf.

[0059] The third transistor branch 314i, 324i of each of the first and second sub-circuits 310, 320 comprises a first PMOS transistor (MP5, MP?) and a second PMOS transistor (MP6, MPS) connected in series, the first PMOS transistor of the first sub-circuit 310 and the second PMOS transistor of the second sub-circuit 320 being gate-controlled by the second result signal x₂, and the second PMOS transistor of the first sub-circuit 310 and the first PMOS transistor of the second sub-circuit 320 being gate-controlled by the first result signal x_±.

[0060] With additional reference to FIG. 4, a method 400 for controlling the PFD 300 is illustrated in accordance with one embodiment. The method starts at step 402. At step 404, a starting state for the PFD 300, with the output signals of the UP and DN lines set at logic ‘O’, is established. The method 400 then moves to one of branches 410 and 420, depending on decision steps 412 and 422. The method 400 moves to branch 410 when, at decision step 412, it is determined that the frequency signal F_in is equal to logic ‘1 ’, and frequency signal F_ref is equal to logic ‘O’. The method 400 moves to branch 420 when, at decision step 422, it is determined that the frequency signal F_ref is equal to logic ‘T, and frequency signal F_in is equal to logic ‘O’. If the values forthe frequency signals F_in and F_ref do not meet the conditions in decision steps 412 or 422, the method 400 returns to step 404.

[0061] In branch 410, the method 400 moves from decision step 412 to step 414 when the frequency signal F_in is equal to logic T and frequency signal F_ref is equal to logic ‘O’. At step 414, the output signal of the UP line is set at logic ‘T, and the output signal DN line is set at logic ‘O’. At decision step 416, a determination is made regarding whether the output signal of the UP line is set at logic ‘1 ’ when the frequency signal F_ref is equal to logic ‘T. When the output signal of the UP line and the frequency signal F_ref are not both equal to logic ‘1 ’, the method 400 returns to step 414. When the output signal of the UP line and the frequency signal F_ref are both equal to logic ‘T, the method 400 proceeds to step 418. At step 418, the output signal of the UP line is set at logic ‘O’, and the method 400 then returns to decision steps 412, 422. [0062] In branch 420, the method 400 moves from decision step 422 to step 424 when the frequency signal F_ref is equal to logic ‘1 and frequency signal F_in is equal to logic ‘O’. At step 424, the output signal of the DN line is set at logic ‘1 ’, and the output signal UP line is set at logic ‘O’. At decision step 426, a determination is made regarding whether the output signal of the DN line is set at logic ‘1 ’ when the frequency signal F_in is equal to logic ‘1 ’. When the output signal of the DN line and the frequency signal F_in are not both equal to logic ‘1 ’, the method 400 returns to step 424. When the output signal of the DN line and the frequency signal F_in are both equal to logic ‘1 ’, the method 400 proceeds to step 418. At step 418, the output signal of the DN line is set at logic ‘O’, and the method 400 then returns to decision steps 412, 422.

[0063] In this fashion, changes in the output signals on lines UP and DN occur on the basis of existing values of the output signals and on the frequency signals F_in and F_ref. The transitions in the output signals on lines UP and DN determines which generates a reciprocal pulse signal and which one remains at logic ‘O’. Depending on the frequency of the frequency signal F_in, transitions between the logic states for the output signals on lines UP and DN may occur at higher frequencies. When the frequency signal F_in has a higher frequency ora leading phase vis-a-vis the frequency signal F_ref, a pulse signal corresponding the phase and frequency of the frequency signal F_in will appear as the output signal on line UP, and a zero signal will appear on line DN. When the frequency signal F_in has a lower frequency ora lagging phase vis-a-vis the frequency signal F_ref, a pulse signal corresponding the phase and frequency of the frequency signal F_in will appear as the output signal on line DN, and a zero signal will appear on line UP.

[0064] With additional reference to FIG. 5, timing diagrams 510, 520, 530, and 540 illustrating the operation of the PFD 300 are presented. Timing diagram 510 illustrates the signals F_in, F_ref, UP, and DN in a situation where the voltage of the input signal V_ref is greater than the frequency of the reference signal V_in (and thus that the frequency signal F_in is greater than the frequency signal F_ref). Because the frequency of the input signal F_in is greater than the frequency of the reference signal F_ref, the output signal on line DN remains at logic ‘O’. Timing diagram 520 illustrates the signals F_in, F_ref, UP, and DN in a situation where the frequency signal F_in is less than the frequency signal F_ref. Because the frequency of the input signal F_in is less than the frequency of the reference signal F_ref, the output signal on line UP remains at logic ‘O’.

[0065] Timing diagram 530 illustrates the signals F_in, F_ref, UP, and DN in a situation where the frequencies of the input and reference signals F_in, F_ref are equivalent, but where the input signal F_in leads the reference signal F_ref in phase. The output signal on line DN remains at logic ‘O’, and the output signal on line UP rises when F_in is high but F_ref is low. Timing diagram 540 illustrates the signals F_in, F_ref, UP, and DN in a situation where the frequencies of the input and reference signals F_in, F_ref are equivalent, but where the input signal F_in lags the reference signal F_ref in phase. The output signal on line UP remains at logic ‘O’, and the output signal on line DN rises when F_ref is high but F_in is low.

[0066] With reference to FIG. 6 and additional reference to FIG. 3, there is illustrated an timing diagram 600 illustrating various signals of the PFD 300 in response to a given input signal V_in. The input and reference signals V_in, V_ref (not illustrated) are converted to timedomain pulse signals — in this case, the frequency signals F_in and F_ref — by the VTC units 120, 122 of the TDC 100. In this example, the input signal frequency signal F_in 610 is of a higher frequency and leads the frequency signal F_ref 620. Prior to time t_x, the frequency signal F_in 610 is at logic ‘O’, and thus signal 630 (at node ‘A’ in FIG. 3, between transistor branches 312i and 3122) is at logic ‘1 ’. At time t_x, frequency signal F_in 610 rises to logic ‘T, while the frequency signal F_ref 620 remains at logic ‘O’. This causes transistors MN4 and MN5 of transistor branch 3122 to turn on, which in turn causes result signal x_t 640 to fall to logic ‘O’. The change in result signal

640 causes the signal 670 on line UP to rise to logic ‘T. Because, in this example, the input signal F_in is of a higher frequency and leads the reference signal F_ref, the signal 680 on line DN remains at logic ‘0’ throughout.

[0067] At time t₂, the frequency signal F_ref 620 rises to logic ‘T. Priorto time t₂, signal 650 (at node ‘B’ in FIG. 3, between transistor branches 322i and 3222) is at logic ‘T. As a result, transistors MN9 and MNIO in transistor branch 3222 turn on, causing result signal x₂ 660 to fall to logic ‘O’. Since both result signals x_± 640 and x₂ 660 are at logic ‘0’ at the same time, this causes their inverse signals (j and x^) to be at logic ‘T. The inverse signals *7 and * being at logic ‘1 ’ at the same time causes signals 630 and 650 (at nodes ‘A’ and ‘B’, respectively) to be reset to logic ‘0’ through transistors MN-I , MN2, and through transistors MN6, MN , respectively. When signals 630 and 650 are at logic ‘O’, transistors MP2 (in transistor branch 3122) and Mp4 (in transistor branch 3222) turn on, causing result signals x_± 640 and x₂ 660 to switch to logic ‘1 ’, which in turn drives the output on line UP to logic ‘O’.

[0068] With reference to FIG. 7, timing diagrams 710 and 720 are presented to illustrate the operation of the PFD 300 vis-a-vis a conventional PFD. In timing diagram 710, input frequency signal 712 and reference frequency signal 714 are of the same frequency, but the input frequency signal 712 leads the reference frequency signal 714. The conventional PFD cannot, however, detect the small phase difference between the input and reference frequency signals 712 and 714 and mistakenly provides a zero signal in the output. In contrast, the response 718 of the PFD 300 shows changes in the output of the UP line, thus allowing forthe detection of the phase difference between the input and reference frequency signals 712 and 714. Indeed, the PFD 300 is able to detect even a small phase difference (i.e. very close to zero phase error) between the input and reference frequency signals 712 and 714 because the PFD 300 is a minimized dead zone structure.

[0069] In timing diagram 720, input and reference frequency signals 722 and 724 are also of the same frequency, but there is a delay before the reference frequency signal 724 is provided. Because the time delay (or the phase difference) between the input and reference frequency signals 722 and 724 is close to 2n phase error, conventional PFD cannot detect the changes in the reference frequency signal 724. In contrast, the response 728 of the PFD 300 shows changes in the output of the UP line, thus allowing for the detection of the phase difference between the input and reference frequency signals 722 and 724.

[0070] With reference to FIG. 8, a transient simulation 800 illustrates differences in the response of a traditional PFD and the PFD 300 on the basis of an input frequency signal 802 and a reference frequency signal 804, which is at a lower frequency than the input frequency signal 802. Signals 810 illustrate the response of a conventional PFD: one-shot pulses 812 may occur at the start of the operation of the conventional PFD, and glitches 814 may occur at the state-switching time of the conventional PFD. In contrast, the signals 820 illustrate the response of the PFD 300, which does not produce glitches and avoids one-shot pulses. These intruding spikes mean that the UP and DN output signals of the PFD are simultaneously at logical high for a short interval, causing leakage currents and increasing reference spurs in the system.

[0071] In particular, and with additional reference to FIG. 3, in this example the frequency of the input frequency signal F_in 802 is greater than the frequency of the reference frequency signal F_ref 804. The presence or absence of a dead zone is based on the speed of transition of the sub-circuit 310, and how quickly the output on line UP can transition to logic T when the input frequency signal F_in 802 switches to logic ‘1 ’. The presence or absence of a blind zone is based on the reset time and pre-setting time of the sub-circuit 310, and how quickly the output on line UP can transition to logic ‘0’ when the reference frequency signal F_ref 804 switches to logic ‘T. The transition speed of the sub-circuit 310 is a function of the characteristics of the transistors MPI , MN4, MN5, and Mpg, which may allow rapid transition of the output on line UP to logic T to reduce or eliminate the presence of dead zones. The presence of the transistor MNI5 may allow a rapid transition of the output on line UP to logic ‘0’ to reduce or eliminate the presence of blind zones. The foot transistor MN3 in the reset stack of transistor branch 312i help to reduce the blind zone, because it minimizes the reset time, specially when the phase difference is about 2TT.

[0072] When operating at very high frequency (e.g., on the order of GHz), small phase differences between signals 802, 804 may result in the delay between the rising edge of the input frequency signal F_in 802 and the rising edge of the of reference frequency signal F_ref 804 being difficult to detect by conventional PFDs. The PFD 300 may be configured such that switching the output on line UP to logic ‘1 ’ occurs quicker than switching the output to logic ‘O’. This functionality of the PFD 300 may be obtained via the use of the inverted result signals j , to control the outputs on lines UP and DN. For instance, the output on line UP is logic ‘1 ’ when the result signal x_t is set to logic ‘O’, and the output on line UP is logic ‘0’ when the result signal is set to logic ‘1 ’ or when the signal x₃ at node 318 is set to logic ‘O’. The result signal x- being pulled down to logic ‘0’ is based on Fin and signal at node A, and the signal x₃ being pulled down to logic ‘0’ is based on x^, which is slightly delayed relative to ₂. As a result, the result signal

will achieve logic ‘0’ before the signal x₃ at node 318 settles to logic ‘O’. In addition, the presence of additional NMOS transistors MNI2 and MNI4 in the second stages 314 and 324 increases the falling edge delay and decreases the rising edge delay for the signals %₃ and x₄ at nodes 318 and 328. Also, transistors MP5 and Mp? in the transistor branches 314i and 324i, driving through signal results of x₂ and x_lt significantly accelerates the reset process, which may enable the PFD 300 to operate at high GHz frequencies.

[0073] With reference to FIG. 9, chart 900 illustrates the transfer characteristics of a conventional PFD and of the PFD 300, illustrated at 902 and 904, respectively. The transfer characteristic 902 illustrates the range of operation of the conventional PFD as between [-it, 7r] radians, and demonstrates both a dead zone (centered at a phase error of 0) and blind zones (near the end of the range of operation). The transfer characteristic of the PFD 300 illustrates the range of operation of the PFD 300 as spanning the range [-2TT, 2TT], and demonstrates minimized dead zones or blind zones.

[0074] With reference to FIG. 10A, a transient wave diagram 1000 for the TDC 100 of FIG. 1 is presented. Signal 1010 represents the input signal V_in, signal 1020 represents the clock signal provided via clock 105, and signal 1030 represents the control signal V_cntrl produced by the control unit 140. Signals 1040 and 1050 represent the frequency signals F_in and F_ref, and signals 1060 and 1070 represent the outputs on lines UP and DN.

[0075] During a first part 1002 of the transient wave diagram 1000, the input signal V_in is greater than the reference signal V_ref . Thus, the frequency signal F_in produced by the VTC 120 is of a lower frequency than the frequency signal F_ref produced by the VTC 122. As a result, the output on line DN will transition to logic ‘T, while the output on line UP remains at logic ‘O’. During a second part 1004 of the transient wave diagram 1000, the input signal V_in is less than the reference signal V_ref . Thus, the frequency signal F_in produced by the VTC 120 is of a higher frequency than the frequency signal F_ref produced by the VTC 122. As a result, the output on line DN will transition to logic ‘O’, while the output on line UP transitions to logic ‘T. The length oftime forwhich the VTC units 120 and 122 are enabled and drawing power is illustrated by the portions of the signal 1030 at logic ‘O’, which may be illustrative of the reduction in power consumption provided by the use of the control unit 140. [0076] With reference to FIG. 10B, the operation principle of the proposed TDC (e.g. the TDC 100 of FIG. 1), when employing a dead zone compensated PFD and a non-zero deadzone PFD, is illustrated in the timing diagram 1080. LSB in this example represents the minimum detectable voltage difference of the TDC. Supposing the CLK signal times the operation, when the control signal V_cntrl is ’O’, the two VTC units as in 120, 122 are enabled and begin oscillation. If AVin (i.e. the voltage difference between V_in and V_ref) is large enough (e.g. more than 5 LSB), the frequency signal F_in rises faster than the frequency signal F_ref and the PFD yields the comparison results. Once the comparison output is acquired, the control signal V_cntrl converts to “disable" and prevents further oscillation of the VTC units 120, 122. When AVin is too small (e.g., about 1 LSB), the VTC units’ outputs frequencies are very close and show a small time difference. In such conditions, the conventional comparator with a non-zero dead-zone PFD cannot make a correct decision, since the slight period difference (or phase difference) between signals is within the dead-zone. Therefore, the VTC units 120, 122 remain activated and transmit pulses through PFD until the difference in pulse times exceeds the dead-zone. As a result, the drawing power and the length of time for which the VTC units 120, 122 are enabled and oscillating are significantly lower when the TDC 100 employs the dead-zone compensated PFD, compared to the conventional TDC with a large dead-zone PFD.

[0077] Fig. 10C illustrates a plot 1090 that presents the comparison time of the proposed TDC (e.g., TDC 100) versus input voltage difference, which also referred to herein as “comparator sensitivity” or “comparator resolution”. The comparator resolution is directly influenced by the comparator enable time and the dead-zone of PFD. As shown in Fig. 10C, in one embodiment, incrementing the comparison duration time may enhance the resolution, owing to suppression of the available dead-zone at the cost of a longer activation time of the comparator. Due to the minimal dead-zone and fast operation response of the employed PFD in the proposed TDC, the comparison time may be in range of a few hundred ns.

[0078] With reference to FIG. 11 A, an embodiment of the VTC units 120, 122 is illustrated as a ring-oscillator type voltage controlled oscillator (VCO) 1100. The ring-oscillator type VCO 1100 may be used for voltage-to-time conversion, frequency translation, and generating periodic signals fortiming in digital circuits. In some embodiments, the ring-oscillator type VCO 1100 may be provided with the capability to produce multi-phase outputs. As implemented within the TDC 100, the VTC units 120, 122 together form a pseudo-differential VCO composed of symmetric VCOs which produce the frequency signals F_in and F_ref, corresponding to voltage-domain input signals V_in and V_ref, respectively. Voltage-to-time conversion techniques may cause non-linearity issues, which may be undesirable in the TDC 100. One source of the non-linearity issues results from the relationship between the inverter current in the VTC units 120, 122 and the voltage used to control the PMOS transistors in the PFD 300. It should be understood that voltage may alternatively be used to control the NMOS transistors of the PFD 300, resulting in similar non-linearity issues. To reduce or minimize the impacts of the non-linearity of the VTC units 120, 122, the ring-oscillator type VCO 1100 implements a linearization method.

[0079] As illustrated in FIG. 11A, the ring-oscillator type VCO 1100 is composed of five delay stages (also referred to herein as “delay cells”) 1110. The input signal (y_in) is applied to a voltage controlled current source PMOS transistor (MPI) 1122, and the resulting current is mirrored to the five delay stages 1110 through a current mirror 1124, composed of transistors MN-I , MN2, and MP2. In addition, the ring-oscillator type VCO 1100 includes a buffer 1130 at the output, which may serve to sharpen the produced frequency signal. With additional reference to FIG. 11 B, a simulated output frequency of the ring-oscillator type VCO 1100 with linearization is illustrated at 1140, and without linearization at 1142.

[0080] It should however be understood that the VTC units 120, 122 may be implemented using any suitable circuit design other than VCO. For example, a voltage control delay line (VCDL) may be used. Fig. 12A illustrates an alternative circuit 1200 to be used for the VTC units 120, 122. The circuit 1200 comprises five delay stages 1210, where each stage 1210 comprises a current mirror 1212 connected to a transistor branch 1214. The circuit 1200 includes a buffer 1220 at its output, which may serve to sharpen the produced frequency signal (Foutput), similarly to buffer 1130 of FIG. 11A. With additional reference to FIG. 12B, a simulated output frequency of the circuit 1200 with linearization is illustrated at 1230, and without linearization at 1240.

[0081] With reference to FIG. 13, a schematic diagram of computing device 1300 is illustrated. As depicted, computing device 1300 includes a processing unit 1302, a memory 1304 which includes instructions 1306, and is configured for receiving inputs and producing outputs. The inputs and outputs may be obtained and/or provided by way of an input/output interface, which enables computing device 1300 to interconnect with one or more input devices, such as a keyboard, mouse, camera, touch screen and a microphone, or with one or more output devices such as a display screen and a speaker, or with one or more networked devices, as appropriate.

[0082] Each processor 1302 may be, for example, any type of general-purpose microprocessor or microcontroller, a digital signal processing (DSP) processor, an integrated circuit, a field programmable gate array (FPGA), a reconfigurable processor, a programmable read-only memory (PROM), or any combination thereof.

[0083] Memory 1304 may include a suitable combination of any type of computer memory that is located either internally or externally such as, for example, random-access memory (RAM), read-only memory (ROM), compact disc read-only memory (CDROM), electro-optical memory, magneto-optical memory, erasable programmable read-only memory (EPROM), and electrically-erasable programmable read-only memory (EEPROM), Ferroelectric RAM (FRAM) or the like.

[0084] The embodiments of the devices, systems and methods described herein may be implemented in a combination of both hardware and software. These embodiments may be implemented on programmable computers, each computer including at least one processor, a data storage system (including volatile memory or non-volatile memory or other data storage elements or a combination thereof), and at least one communication interface.

[0085] Program code is applied to input data to perform the functions described herein and to generate output information. The output information is applied to one or more output devices. In some embodiments, the communication interface may be a network communication interface. In embodiments in which elements may be combined, the communication interface may be a software communication interface, such as those for interprocess communication. In still other embodiments, there may be a combination of communication interfaces implemented as hardware, software, and combination thereof. [0086] The following discussion provides many example embodiments. Although each embodiment represents a single combination of inventive elements, other examples may include all possible combinations of the disclosed elements. Thus if one embodiment comprises elements A, B, and C, and a second embodiment comprises elements B and D, other remaining combinations of A, B, C, or D, may also be used.

[0087] The term “connected” or "coupled to" may include both direct coupling (in which two elements that are coupled to each other contact each other) and indirect coupling (in which at least one additional element is located between the two elements).

[0088] The embodiments described herein are implemented by physical computer hardware, including computing devices, servers, receivers, transmitters, processors, memory, displays, and networks. The embodiments described herein provide useful physical machines and particularly configured computer hardware arrangements. The embodiments described herein are directed to electronic machines and methods implemented by electronic machines adapted for processing and transforming electromagnetic signals which represent various types of information. The embodiments described herein pervasively and integrally relate to machines, and their uses; and the embodiments described herein have no meaning or practical applicability outside their use with computer hardware, machines, and various hardware components. Substituting the physical hardware particularly configured to implement various acts for non-physical hardware, using mental steps for example, may substantially affect the way the embodiments work. Such computer hardware limitations are clearly essential elements of the embodiments described herein, and they cannot be omitted or substituted for mental means without having a material effect on the operation and structure of the embodiments described herein. The computer hardware is essential to implement the various embodiments described herein and is not merely used to perform steps expeditiously and in an efficient manner.

[0089] Although the embodiments have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the scope as defined by the appended claims. [0090] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps

[0091] As can be understood, the examples described above and illustrated are intended to be exemplary only. The scope is indicated by the appended claims.

Claims

WHAT IS CLAIMED IS:

1 . A phase-frequency detector, comprising: a first sub-circuit and a second sub-circuit, each of the first and the second sub-circuit comprising a first stage comprising interconnected first and second transistor branches and a second stage connecting to the first stage, the second stage comprising third, fourth, and fifth transistor branches; the first transistor branch of the first sub-circuit configured for receiving an input frequency signal and for generating a first intermediate signal based on the input frequency signal, and the first transistor branch of the second sub-circuit configured for receiving a reference frequency signal and for generating a second intermediate signal based on the reference frequency signal; the second transistor branch of the first sub-circuit configured for receiving the input frequency signal and the first intermediate signal and for producing a first result signal, and the second transistor branch of the second sub-circuit configured for receiving the reference frequency signal and the second intermediate signal and for producing a second result signal; the third transistor branch of the first sub-circuit configured for receiving the first result signal from the second transistor branch of the first sub-circuit and the second result signal from the second transistor branch of the second sub-circuit, and the third transistor branch of the second sub-circuit configured for receiving the second result signal from the second transistor branch of the second sub-circuit and the first result signal from the second transistor branch of the first sub-circuit; and the fourth and fifth transistor branches of the first sub-circuit forming a first voltage divider configured for producing a third result signal based on the first result signal, and the fourth and fifth transistor branches of the second sub-circuit forming a second voltage divider configured for producing a fourth result signal based on the second result signal, the third and fourth result signals indicative of at least one difference in at least one of frequency and phase between the input frequency signal and the reference frequency signal.

2. The phase-frequency detector of claim 1 , wherein the third transistor branch of each of the first and second sub-circuits comprises a first p-type metal-oxide-semiconductor (PMOS) transistor and a second PMOS transistor connected in series, the first PMOS

25 transistor of the first sub-circuit and the second PMOS transistor of the second sub-circuit being gate-controlled by the second result signal, and the second PMOS transistor of the first sub-circuit and the first PMOS transistor of the second sub-circuit being gate-controlled by the first result signal.

3. The phase-frequency detector of claim 1 , wherein the fourth transistor branch of each of the first and second sub-circuits comprises a PMOS transistor and a first and a second n- type metal-oxide-semiconductor (NMOS) transistor connected in series, the PMOS transistor and the first and second NMOS transistors of the first sub-circuit being gate- controlled by the first result signal, and the PMOS transistor and the first and second NMOS transistors of the second sub-circuit being gate-controlled by the second result signal.

4. The phase-frequency detector of claim 1 , further comprising a first inverter configured to receive the first result signal and to output a first inverted signal based on the first result signal, and a second inverter configured to receive the second result signal and to output a second inverted signal based on the second result signal.

5. The phase-frequency detector of claim 4, wherein the first transistor branch of each of the first and second sub-circuits comprises a PMOS transistor and a first, a second, and a third NMOS transistor connected in series, the first NMOS transistor of the first sub-circuit and the second NMOS transistor of the second sub-circuit being gate-controlled by the second inverted signal, and the second NMOS transistor of the first sub-circuit and the first NMOS transistor of the second sub-circuit being gate-controlled by the first inverted signal.

6. The phase-frequency detector of claim 4, wherein the fifth transistor branch of each of the first and second sub-circuits comprises an NMOS transistor having its source connected to ground, the NMOS transistor of the first sub-circuit being gate-controlled by the second inverted signal and the NMOS transistor of the second sub-circuit being gate- controlled by the first inverted signal.

7. The phase-frequency detector of any one of claims 1 to 6, wherein the first transistor branch of each of the first and second sub-circuits is configured for resetting the first stage when the input frequency signal and the reference frequency signal are at logical high and the first and second result signals are at logical low.

8. The phase-frequency detector of claim 7, wherein the third transistor branch of each of the first and second sub-circuits is configured for maintaining the first result signal at logical high when the input frequency signal and the reference frequency signal are at logical high.

9. The phase-frequency detector of any one of claims 1 to 8, wherein, when one of a phase and a frequency of the input frequency signal is leading that of the reference frequency signal, the fourth transistor branch of the first sub-circuit produces the third result signal based on the first result signal and generates a logical high output on a first output line, and the fourth transistor branch of the second sub-circuit produces the fourth result signal based on the second result signal and generates a zero output on a second output line.

10. The phase-frequency detector of claim 9, wherein, when one of the phase and the frequency of the input frequency signal is lagging that of the reference frequency signal, the fourth transistor branch of the first sub-circuit produces the third result signal based on the first result signal and generates the zero output on the first output line, and the fourth transistor branch of the second sub-circuit produces the fourth result signal based on the second result signal and generates the logical high output on the second output line.

11 . The phase-frequency detector of any one of claims 1 to 10, wherein the third result signal and the fourth result signal each comprises a plurality of pulses, and further wherein the first voltage divider is configured to reduce a width of erroneous ones of the plurality of pulses in the third result signal and the second voltage divider is configured to reduce the width of the erroneous ones of the plurality of pulses in the fourth result signal.

12. A time-domain comparator, comprising: a phase-frequency detector according to any one of claims 1 to 11 ; a first voltage-to-time converter and a second voltage-to-time converter, the first voltage- to-time converter coupled to an input for receiving an input signal therefrom, the first voltage- to-time converter configured to output the input frequency signal based on the input signal; and a voltage reference generator coupled to the second voltage-to-time converter for providing a reference signal to the second voltage-to-time converter, the second voltage-to- time converter configured to output the reference frequency signal based on the reference signal; the phase-frequency detector coupled to the first and second voltage-to-time converters for receiving the input frequency signal and the reference frequency signal therefrom and for producing the third and fourth result signals indicative of the at least one difference in at least one of frequency and phase between the input frequency signal and the reference frequency signal.

13. The time-domain comparator of claim 12, wherein the first voltage-to-time converter is configured to output the input frequency signal having a first oscillation frequency indicative of the input signal, and the second voltage-to-time converter is configured to output the reference frequency signal having a second oscillation frequency indicative of the reference signal.

14. The time-domain comparator of claim 12 or 13, further comprising a control unit configured to produce a control signal for selectively enabling and disabling an operation of the first and second voltage-to-time converters.

15. The time-domain comparator of claim 14, wherein the control unit is configured to produce the control signal for disabling the operation of the first and second voltage-to-time converters subsequent to the third and fourth result signals being produced by the phasefrequency detector.

16. The time-domain comparator of any one of claims 12 to 15, wherein each of the first voltage-to-time converter and the second voltage-to-time converter is a ring-oscillatory type voltage controlled oscillator.

17. A method of controlling a time-domain comparator, the method comprising: providing an input signal to a first voltage-to-time converter and providing a reference signal to a second voltage-to-time converter; obtaining, at a phase-frequency detector, an input frequency signal from the first voltage-to-time converter and a reference frequency signal from the second voltage-to-time converter, the input frequency signal generated based on the input signal and the reference frequency signal generated based on the reference signal;

28 comparing, at the phase-frequency detector, a magnitude of the input signal to a magnitude of the reference signal, and comparing the input frequency signal to the reference frequency signal; when the magnitude of the reference signal is greaterthan the magnitude of the input signal and the input frequency signal is greater than the reference frequency signal, setting, at the phase-frequency detector, a first output signal provided on a first output line to logical high and a second output signal provided on a second output line to logical low; when the magnitude of the reference signal is smallerthan the magnitude of the input signal and the input frequency signal is smaller than the reference frequency signal, setting, at the phase-frequency detector, the first output signal to logical low and the second output signal to logical high; and outputting the first output signal.

18. The method of claim 17, further comprising producing a control signal for selectively enabling and disabling an operation of the first and second voltage-to-time converters.

19. The method of claim 18, wherein the control signal is produced for disabling the operation of the first and second voltage-time-time converters subsequent to the first and second output signals being set.

20. The method of claim 19, wherein producing the control signal comprises setting the control signal to logical high to deactivate discharging paths of the first and second voltage- to-time converters and cause outputs of the first and second voltage-to-time converters to remain at their previous states.

29