WO2022266760A1 - Printed photonic component based photonic device probing and testing - Google Patents

Abstract

On-wafer die level testing of photonic integrated circuits (PICs) is difficult due to the requirement to couple optical signals into and from optical waveguides within the PICs such that testing is typically performed at the discrete die level or upon a bar of PICs separated from the wafer. Accordingly it would be beneficial to provide circuit designers and production teams with an optical technique that enables on-wafer die level testing / screening through the use of printed photonic components which allow optical coupling to / from the PIC on-wafer to the external optical testing equipment. Further, the mechanical footprint of many PICs is driven by the optical waveguide structures these are large compared to, for example, the area of a CMOS compatible waveguide photodetector etc. Accordingly, the post-wafer formation of printed photonic components enables on-die re-routing to bypass defective elements of the PIC as well as on-wafer die testing.

Description

PRINTED PHOTONIC COMPONENT BASED PHOTONIC DEVICE PROBING

AND TESTING

CROSS-REFERENCE TO RELATED APPLICATIONS

[001] This patent claims the benefit of priority from U.S. Provisional Patent Application 63/213,889 filed June 23, 2021; and the benefit of priority from U.S. Provisional Patent Application 63/216,131 filed June 29, 2021.

FIELD OF THE INVENTION

[002] This invention is directed to photonic waveguide devices and more particularly to methods and systems of providing on wafer photonic testing.

BACKGROUND OF THE INVENTION

[003] Silicon Photonics is a promising technology for adding integrated optics functionality to integrated circuits by leveraging the economies of scale of the CMOS microelectronics industry. Some variants of Silicon Photonics may use other materials as the waveguide core such as silicon nitride (SixNy) and silicon oxynitride (SiOxNl-x) for example. Silicon Photonics in addition to leveraging CMOS based silicon fabrication processes also allows for the integration of control and driver CMOS electronics discretely or in conjunction with microelectromechanical systems (MEMS) elements to provide Micro-Opto-Electro- Mechanical-Systems (MOEMS).

[004] However, irrespective of whether they are passive photonic integrated circuits (PICs) such as dense wavelength division multiplexers or splitters for example; dynamic PICs such as switches or reconfigurable add-drop multiplexers (ROADMs) for example; or active PICs employing semiconductor elements in conjunction with the silicon photonic waveguides such as semiconductor optical amplifiers (SOAs), laser diodes (LDs), light emitting diodes (LEDs) and photodetectors for example these all share a common issue with respect to testing.

[005] Within CMOS microelectronics and other semiconductor electronic technologies a wafer contains multiple dies which are tested at the wafer level prior to being separated to individual die with those passing the initial wafer level testing progressing to packaging etc. This testing may be low frequency testing, high frequency testing or a combination of both employing a wafer probe station that employs electrical probes to make contact to electrical pads upon the die for power, applying signals and detecting signals. [006] However, with PICs the on-wafer die level testing of components has been difficult at best and has typically been performed at the die level after die separation or upon a bar of devices separated from the wafer. This being a result of the requirement , typically, to access a high quality end-facet of the optical waveguides in order to be able to couple light into and/or out of these optical waveguides. This increases costs through additional processing prior to die screening etc. even where automatic alignment systems are employed to bring the input and/or output coupling elements into alignment with the optical waveguides upon the PIC.

[007] Accordingly, it would be desirable to provide circuit designers and production teams with an optical technique to enable wafer level die testing / screening. Embodiments of the invention therefore address providing techniques to support such wafer level testing.

[008] Further, as the mechanical footprint of most PICs is driven by aspects of the design of the optical waveguide structures many PIC die are large compared to, for example, the area of a CMOS compatible waveguide photodetector etc. Accordingly, embodiments of the invention support on-die re-routing to bypass defective elements of the PIC in a manner similar to some electronic circuits that isolate / bypass fault elements.

[009] Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.

SUMMARY OF THE INVENTION

[0010] It is an object of the present invention to mitigate limitations in the prior art relating to photonic waveguide devices and more particularly to methods and systems of providing on wafer photonic testing.

[0011] In accordance with an embodiment of the invention there is provided [0012] Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Embodiments of the present invention will now be described, by way of example only, with reference to the attached Figures, wherein:

[0014] Figure 1 depicts an exemplary cross-section of a silicon nitride - silica optical photonic integrated circuit (PIC) formed upon a silicon substrate; [0015] Figure 2A depicts exemplary prior art techniques for testing a PIC;

[0016] Figure 2B depicts an exemplary method according to an embodiment of the invention employing printed photonic components (PPCs) according to an embodiment of the invention; [0017] Figure 3 depicts an exemplary manufacturing sequence for implementing PPCs for photonic interconnection;

[0018] Figure 4A depicts an exemplary embodiment of the invention exploiting PPCs for on- wafer photonic testing (OW-PHOTE) of a PIC prior to die separation and packaging;

[0019] Figure 4B depicts the exemplary embodiment of the invention depicted in Figure 4A with surface grating and optical fiber interfaces for the OW-PHOTE and final device configurations respectively.

[0020] Figure 5A depicts an exemplary embodiment of the invention exploiting PPCs for OW- PHOTE of a PIC prior to die separation and packaging;

[0021] Figure 5B depicts an exemplary embodiment of the invention exploiting PPCs for OW- PHOTE of a PIC prior to die separation and packaging;

[0022] Figure 6 depicts an exemplary embodiment of the invention exploiting PPCs for OW- PHOTE of a PIC prior to die separation and packaging;

[0023] Figure 7 depicts an exemplary embodiment of the invention exploiting PPCs for OW- PHOTE with multiple ports on a PIC prior to die separation and packaging;

[0024] Figure 8 depicts an exemplary embodiment of the invention exploiting PPCs for on- chip re-routing (OC-RER) of a PIC prior to die separation and packaging;

[0025] Figure 9 depicts an exemplary embodiment of the invention exploiting PPCs for OC- RER) of a PIC prior to die separation and packaging;

[0026] Figure 10 depicts an exemplary embodiment of the invention exploiting PPCs for OW- PHOTE of a PIC prior to die separation and packaging;

[0027] Figure 11 depicts an exemplary embodiment of the invention exploiting PPCs for OW- PHOTE of a PIC prior to die separation and packaging;

[0028] Figure 12 depicts an exemplary embodiment of the invention exploiting temporary element for OW-PHOTE of a PIC prior to die separation and packaging;

[0029] Figure 13 depicts an exemplary embodiment of the invention exploiting post-die processing to enable OW-PHOTE of a PIC prior to die separation and packaging;

[0030] Figure 14 depicts an exemplary embodiment of the invention exploiting a PPC turning mirror and post-die processing to enable OW-PHOTE of a PIC prior to die separation and packaging; and [0031] Figure 15 depicts an exemplary embodiment of the invention exploiting a PPC turning mirror and PPC interconnect processing to enable OW-PHOTE of a PIC prior to die separation and packaging.

DETAILED DESCRIPTION

[0032] The present invention is directed to photonic waveguide devices and more particularly to methods and systems of providing on wafer photonic testing.

[0033] The ensuing description provides representative embodiment(s) only, and is not intended to limit the scope, applicability or configuration of the disclosure. Rather, the ensuing description of the embodiment(s) will provide those skilled in the art with an enabling description for implementing an embodiment or embodiments of the invention. It would be understood by one of skill in the art that various changes can be made in the function and arrangement of elements without departing from the scope of the invention as set forth in the claims. Accordingly, an embodiment is an example or implementation of the inventions and not the sole implementation. Various appearances of “one embodiment,” “an embodiment” or “some embodiments” do not necessarily all refer to the same embodiments. Although various features of the invention may be described in the context of a single embodiment, the features may also be provided separately or in any suitable combination. Conversely, although the invention may be described herein in the context of separate embodiments for clarity, the invention can also be implemented in a single embodiment or any combination of embodiments.

[0034] Reference in the specification to “one embodiment,” “an embodiment,” “some embodiments” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least one embodiment, but not necessarily all embodiments, of the inventions. The phraseology and terminology employed herein is not to be construed as limiting but is for descriptive purpose only. It is to be understood that where the claims or specification refer to “a” or “an” element, such reference is not to be construed as there being only one of that element. It is to be understood that where the specification states that a component feature, structure, or characteristic “may,” “might,” “can” or “could” be included, that particular component, feature, structure, or characteristic is not required to be included.

[0035] Reference to terms such as “left,” “right,” “top,” “bottom,” “front” and “back” are intended for use in respect to the orientation of the particular feature, structure, or element within the figures depicting embodiments of the invention. It would be evident that such directional terminology with respect to the actual use of a device has no specific meaning as the device can be employed in a multiplicity of orientations by the user or users.

[0036] Reference to terms “including,” “comprising,” “consisting” and grammatical variants thereof do not preclude the addition of one or more components, features, steps, integers or groups thereof and that the terms are not to be construed as specifying components, features, steps or integers. Likewise, the phrase “consisting essentially of,” and grammatical variants thereof, when used herein is not to be construed as excluding additional components, steps, features integers or groups thereof but rather that the additional features, integers, steps, components or groups thereof do not materially alter the basic and novel characteristics of the claimed composition, device or method. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional elements.

[0037] A “two-dimensional” waveguide, also referred to as a 2D waveguide or a planar waveguide, as used herein may refer to, but is not limited to, an optical waveguide supporting propagation of optical signals within a predetermined wavelength range which does not guide the optical signals laterally relative to the propagation direction of the optical signals.

[0038] A “three-dimensional” waveguide, also referred to as a 3D waveguide, a channel waveguide, or simply waveguide as used herein may refer to, but is not limited to, an optical waveguide supporting propagation of optical signals within a predetermined wavelength range which guides the optical signals laterally relative to the propagation direction of the optical signals.

[0039] A “photonic integrated circuit” (PIC) as used herein may refer to, but is not limited to, an optical component formed upon a substrate providing an optical routing and processing functionality. A PIC may as outlined below be a passive PIC, a dynamic PIC or an active PIC or combine elements of two or more of these. The PIC is fabricated using processing techniques at a wafer level, e.g. CMOS manufacturing flows, MEMS processing flows, etc.

[0040] A “printed photonic component” (PPC) as used herein may refer to, but is not limited to a two-dimensional or three-dimensional photonic element which is formed to couple one or more optical elements, e.g. optical waveguides, laser diodes, photodetectors, semiconductor optical amplifiers, etc., to one or more other optical elements. A PPC may be formed using a direct-writing technique using, for example optical beam techniques (e.g. using a photopolymer), ion beam techniques or electron-beam (e-beam) (e.g. using an e-beam polymer or resist) techniques where the direct-writing technique may be established in dependence upon the materials employed in its formation and/or cost-speed processing aspects of the direct-write process within the overall manufacturing process flow. A PPC may be, for example, a photonic wirebond, micro-lens, micro-mirror, three-dimensional optical waveguide (also referred to as a channel waveguide or optical waveguide) and a two-dimensional optical waveguide (also referred to as a planar waveguide) although it would be evident that such PPCs may encompass other optical elements and optical functionality without departing from the scope of the invention.

[0041] A “photonic wirebond” (PWB) as used herein may refer to, but is not limited to, a three- dimensional optical waveguide (optical waveguide) which is formed to couple to one or more optical waveguides of a PIC after either full processing of the PIC or part-processing of the PIC wherein the PIC processing is completed post-application and/or removal of the photonic wirebond. A PWB may, for example, comprise a core formed from a predetermined material clad with air, a core formed from a predetermined material clad with another predetermined material, and a structured core formed from two or more materials clad with one or more other materials. A PWB may be formed using a direct-writing technique using, for example optical beam techniques (e.g. using a photopolymer), ion beam techniques or electron-beam (e-beam) (e.g. using an e-beam polymer or resist) techniques where the direct-writing technique may be established in dependence upon the materials employed in its formation and/or cost-speed processing aspects of the direct-write process within the overall manufacturing process flow. [0042] A “photopolymerizable polymer” (photopolymer) as used herein may refer to, but is not limited to, a polymer which changes its properties when exposed to light, often in the ultraviolet or visible region of the electromagnetic spectrum. These changes are often manifested structurally, for example hardening of the material occurs as a result of cross- linking when exposed to light. A photopolymer may, for example, comprises a mixture of monomers, oligomers, and photoinitiators that conform into a hardened polymeric material. A polymer bases for photopolymers may include, but not be limited to, an acrylic, polyvinyl alcohol (PVA), poly(vinyl cinnamate), polyisoprene, a polyamide, an epoxy, a polyimide, a styrenic block copolymer and nitrile rubber.

[0043] An e-beam polymer or resist as used herein may refer to, but is not limited to, a polymer or resist that undergoes cross-linking upon exposure to an electron beam. The polymer or resist may also undergo chain scission (making the polymer chains shorter) during cross-linking. Examples, of such e-beam polymers and resists may include poly(vinylidene fluoride- trifluoroethylene) copolymers, e-beam crosslinkable thermoplastics, e-beam crosslinkable elastomers, a poly(meth)acrylate (PMMA) or PMMAs, a copolymer of methyl methacrylate and methacrylic acid, one or more styrene acrylates, and novolac based resists. [0044] A passive PIC as used herein may refer to, but is not limited to, a PIC which contains no dynamic or active elements. Examples of passive PICs may include, for example, a dense wavelength division multiplexers such as an array waveguide grating (AWG), a combiner, and a splitter.

[0045] A dynamic PIC as used herein may refer to, but is not limited to, a PIC which contains elements that are tunable or controllable such as directional couplers, Mach-Zehnder interferometers (MZIs), etc. which can be electrically adjusted to provide modulation, switching, etc. Electrical adjustment may be through localized heating, for example with a Si0₂ — Si₃N₄ — Si0₂ waveguide structure, or current injection. Examples of dynamic PICs include, for example, optical switches and reconfigurable add-drop multiplexers (ROADMs). [0046] An active PIC as used herein may refer to, but is not limited to, a PIC which contains either monolithically integrated or hybridly integrated optoelectronic elements. Such optoelectronic elements including, for example, semiconductor optical amplifiers (SOAs), laser diodes (LDs), light emitting diodes (LEDs), superluminescent LEDS, photodetectors (PDs) and avalanche photodetectors (APDs).

[0047] Within the embodiments of the invention described below the optical waveguides exploit a silicon nitride core with silicon oxide upper and lower cladding, a Si0₂ — Si₃N₄ — Si0₂ waveguide structure. However, it would be evident that embodiments of the invention may also be employed in conjunction with other waveguide materials systems employing a CMOS compatible manufacturing process or semiconductor manufacturing processes upon silicon. These may include, but not be limited to:

• a silicon core and silicon nitride upper and lower claddings, a Si₃N₄ — Si — Si₃N₄ waveguide structure;

• a silicon core with silicon oxide upper and lower claddings, a SOI waveguide, e.g.

Si0₂ - Si - Si0₂;

• a doped silica core relative to undoped cladding, a Si0₂ — doped_Si0₂ — Si0₂, e.g. germanium doped (Ge) yielding Si0₂ — Ge: Si0₂ — Si0₂;

• a silicon core and silicon oxynitride upper and lower claddings, a SiO_xN_Y — Si —

SiO_xN_Y waveguide structure;

• silicon oxynitride core with silicon oxide upper and lower claddings, a Si0₂ —

SiO_xN_Y — Si0₂ waveguide structure;

• polymer-on-silicon; and

• doped silicon waveguides. [0048] Additionally, waveguide structures without upper claddings may be employed.

[0049] However, it would be evident to one skilled in the art that the embodiments of the invention may be employed in conjunction with PICs employing a wide variety of other material systems that may include, but not be limited to:

• ion exchanged glass;

• ion implanted glass;

• polymers;

• indium gallium arsenide phosphide ( InGaAsP );

• indium phosphide ( InP );

• gallium arsenide ( GaAs );

• those employing other III — V materials;

• those employing II — VI materials;

• silicon (Si);

• silicon germanium (SiGe); and

• ferroelectric materials such as lithium niobate ( LiNb0₃ ), lithium tantalate (LiTaO_i). [0050] Further, whilst the embodiments of the invention are described and depicted with respect to a waveguide employing a core embedded within a cladding, a so-called buried waveguide, it would be evident that other waveguide geometries such as rib waveguide, diffused waveguide, ridge or wire waveguide, strip-loaded waveguide, slot waveguide, and anti-resonant reflecting optical waveguide (ARROW waveguide), photonic crystal waveguide, suspended waveguide, alternating layer stack geometries, sub-wavelength grating (SWG) waveguides and augmented waveguides (e.g. Si — Si0₂ — Polymer). Further, whilst the embodiments of the invention are described and depicted with respect to a step-index waveguide it would be evident that other waveguide geometries such as graded index and hybrid index (combining inverse-step index and graded index) may be employed.

[0051] Whilst embodiments of the invention are described and considered from the perspective of being performed at the wafer level prior to die separation and packaging it would be evident to one of skill in the art that the embodiments of the invention may be applied post-partial die separation from wafer (e.g. into a bar form, column of die, part of wafer etc.) as well as post die separation, and post die packaging without departing from the scope of the invention. [0052] Referring to Figure 1 there is depicted an exemplary cross-section 100 of a silicon nitride - silica optical photonic integrated circuit (PIC) formed upon a silicon substrate. Accordingly there is depicted a substrate lOOC formed from Si 110 upon which is a lower cladding 100B formed from Si0₂(thermal ) 120 which was thermally grown atop the Si 110. Atop these are waveguide layer 100A which is depicted as comprising first to third Regions 100D to 100F respectively for different exemplary PIC elements. First Region 100D depicting a series of waveguides embedded within the upper cladding formed from Si0₂ ( deposited ) 130, being Si0₂ deposited by one or more processes such as plasma enhanced chemical vapour deposition (PECVD), sputtering, thermal evaporation and e-beam evaporation for example. Within first Region 100D is first waveguide 110G formed from 5/ 110 and second waveguide 100H formed from Si₃N₄ 195 (silicon nitride). Within a variant embodiment the second waveguide 100H may be formed from silicon oxynitride ( SiO_xN_Y . The optical waveguides within first Region 100D may be upon a single plane, upon multiple planes isolated from one another, multiple planes optical coupled to one another, etc.

[0053] Second Region 100B depicts an exemplary modulator structure wherein the waveguide section comprises doped silicon (p-doped Si 170 and n-doped Si 180) portions coupled to electrical pads upon the upper surface of the upper cladding for the application of the appropriate drive and/or control signals. These being formed from Metal 2 160 contacts to the p-doped 5/ 170 and n-doped 5/ 180 and Metal 1 150 vias through the upper cladding. Also depicted above the modulator is a heater formed from Metal 3 140 which is similarly coupled to an electrical pad via a via formed from Metal 1 150. Optionally, a 5/₃/n₄ core waveguide or Si core waveguide may be controlled through thermo-optic induced refractive index changes allowing low speed thermo-optically controlled switches, attenuators etc. to be formed. These would employ one or more heaters discretely.

[0054] Third region 100F depicts an exemplary embodiment of a photodetector wherein the waveguide section comprises a central Si 110 portion with n — doped Si 170 and p — doped Si 180 either side to apply biassing / withdraw photocurrent. Atop the core is a region formed from Ge 190 as the photoabsorber. The n — doped Si 170 and p — doped Si 180 being similarly connected to Metal 2 160 contacts and therein via vias of Metal 1 150 to electrode pads upon the surface.

[0055] Accordingly, first to third Regions 100D to 100F respectively may discretely form part of a PIC or form part of a PIC in various combinations. In order to test a passive PIC formed from a structure such as first Region 100D optical signals must be coupled into the waveguide(s) and the resulting outputs detected. However, as the waveguides are within the plane of the substrate then when considering on-wafer testing the ends of each waveguide must be accessed. With a dynamic PIC employing a region such as second Region 100E then not only must optical signals be coupled in plane but electrical signals applied / detected. Similarly, with a PIC employing a region such as third Region 100F then not only must optical signals be coupled in plane but electrical signals applied / detected.

[0056] Now referring to Figure 2A there are depicted exemplary prior art techniques fortesting a PIC. First image 200A depicts end-coupling which has been the dominant method used to date wherein a PIC die or a bar of PIC die is separated from the wafer and optical input(s) / optical output(s) aligned to the waveguides for a PIC die, the PIC die tested, and then another PIC die aligned. Using a bar of PIC die allows automated testing with reduced pick-place operations. The optical input / output may, as depicted in first image 200A, be a free-space coupling as from a lens, a microscope objective, graded refractive index (GRIN) lens. Alternatively, it may be the alignment of an optical fiber(s). As depicted therefore in first image 200A the optical waveguide 210 is upon the substrate 220 and the free-space optics 230 aligned to it.

[0057] Second image 200B depicts a surface grating coupling methodology wherein a waveguide 210 upon substrate couples to a surface diffraction grating (grating) 230 which couples the light out of plane to an optical element 240. Accordingly, light within the waveguide 210 is coupled out of plane by the grating 230 and captured by optical element 240 or light from the optical element 240 impinges on the grating 230 and is coupled to a guided mode which is then coupled to the waveguide 210. Whilst the grating 230 provides for coupling of light out of the plane of the wafer they exhibit issues which may impact their application to on-wafer photonic testing (ON-PHOTE). These limitations include coupling efficiency, wavelength sensitivity, polarization sensitivity, positional tolerances and footprint that limits their integration density. Whilst within the prior art techniques towards addressing coupling efficiency, wavelength sensitivity and polarization sensitivity have been presented these have increased fabrication complexities. Further, positional tolerances require microalignment systems for the optical elements 240. Further, these surface gratings are incompatible with automated self-aligned fiber packaging techniques that exploit end-coupling from optical fibers placed within U-grooves or V-grooves formed within the silicon substrate unless they are removed and the die post-test processed to add the U-grooves / V-grooves which is highly complex at the die or bar level rather than wafer level processing. However, as will become evident with respect to embodiments of the invention the grating 230 may be beneficial for ON-PHOTE and be bypassed in the final package product through the use of PPCs.

[0058] Accordingly, it would be beneficial to provide an alternate solution to ON-PHOTE. Referring to Figure 2B there is depicted an exemplary method according to an embodiment of the invention employing a printed photonic component (PPC) or PPCs, in this instance photonic wirebonds (PWBs). Accordingly, a PIC 250 is depicted, such as formed upon a wafer, wherein a PWB 260 is formed from a region of a waveguide 290 to another location on the PIC. As noted below with respect to embodiments of the invention the other location can be an end of another waveguide, another element of the PIC etc. The PWB 260 being formed through direct writing for example. As depicted the direct writing is with an optical beam 270 within a photopolymer 280 although it would be evident that other direct write technologies such as UV direct writing, visible direct writing, electron-beam (e-beam) direct writing and ion beam direct writing may be employed without departing from the scope of the invention.

[0059] Figure 3 depicts an exemplary manufacturing sequence for implementing PWBs for photonic interconnection according to an embodiment of the invention. Whilst the exemplary sequence depicted in Figure 3 relates to interconnecting multiple PIC die upon a common substrate the principles, as would be evident to one of skill in the art, may be applied to interconnect multiple locations within a single PIC die upon a wafer, between locations on one PIC die to another PIC die on the wafer, between locations on one PIC die to a test block on the wafer, etc. Accordingly, the gaps between Chip 1 310 and Chip 2 320 and between Chip 2 320 and Chip 3 330 may be etched regions of the wafer within embodiments of the invention. [0060] Accordingly, referring to Figure 3 there are depicted first to fifth Steps 300A to 300E respectively together with first to third Images 300F and 300H respectively. Accordingly, referring initially to first Step 300A then Chip 1 310, Chip 2 320 and Chip 3 330 are depicted upon Base 390. Base 390 may for example be a common silicon substrate upon which a PIC or PICs are formed or a carrier upon which the PICs are placed.

[0061] In second Step 300B a photosensitive resist is applied such that the regions between the facets of Chip 1 310, Chip 2 320 and Chip 3 330 are filled. The actual positions of waveguide facets and/or coupling structures within the resist are detected using, for example, three- dimensional (3D) machine vision techniques. For example, these may provide sub-micron accuracy or sub-100 nm accuracy. In third Step 300C the PWB is “designed” based upon the recorded positions between its start point and end point. The PWB is then written using optical direct writing within the embodiment depicted wherein exposure of the photosensitive resist results in cross-linking of the resist providing a hardened region, the PWB, within the liquid photosensitive resist.

[0062] In fourth Step 300D the unexposed photosensitive resist is removed through a development step. Next in fifth Step 300 the PWB structures are embedded within a low index cladding material. This being depicted as first Region 380 A between the first Chip 310 and second Chip 320, second Region 380B between the second Chip 820 and third Chip 830, and third Region 380C between the third Chip 830 and an optical fiber. Within embodiments of the invention described below the PWBS between third Chip 830 and the optical fiber would typically not be employed as the PWBs although within other embodiments of the invention these may be employed.

[0063] Referring to first to third Images 300F to 300H respectively these depict:

• PWBs between horizontal cavity surface-emitting laser (HCSEL) devices and a silicon-on-insulator (SOI) PIC;

• PWBs between two regions of a single SOI PIC or between a pair of SOI PICs;

• PWBS between a multi -core optical fiber (MCF) and a SOI PIC.

[0064] Within Figure 3 direct writing with an optical beam is depicted, for example a UV beam or visible beam, although it would be evident that other direct write technologies electron-beam (e-beam) direct writing and ion beam direct writing may be employed without departing from the scope of the invention. The technique employed may be determined in dependence upon the material or materials from which the PWBs are to be formed. The technique employed may be determined in dependence upon the logistics of the PWB process, such as with respect to processing time per PWB for example.

[0065] Within the following schematics one side of a PIC is depicted when describing embodiments of the invention. If the PIC were reflective then the optical signals coupled to the PIC via the interfaces would be reflected and transmitted back through the interfaces. However, if the PIC were transmissive then the optical signals coupled to the PIC via the interfaces would be transmitted and coupled through another set of interfaces on the other side of the PIC. For simplicity, therefore, only a single set of interfaces are depicted within the different embodiments of the invention.

[0066] Further, with respect to Figure 3 above and Figures 4 to 10 below the PPCs are described with respect to being PWBs. However, as evident from discussions below the PPCs between different die / different optical components may be different PPCs including, for example, micro-lenses, micro-mirrors, three-dimensional optical waveguides, two- dimensional optical waveguides, and gratings.

[0067] Now referring to Figure 4A there are depicted first and second Schematics 400A and 400B with respect to an exemplary embodiment of the invention exploiting a printed photonic component (PPC), in this instance a PWB, for on-wafer photonic testing (OW-PHOTE) of a PIC prior to die separation and packaging. Referring to first Schematic 400 A there are depicted a PIC 410, a photonic wirebond (PWB) Coupler 420, a Transition Coupler 430 and an Optical Interface 440. Accordingly, optical signals may be coupled to the Optical Interface 440 which propagate via Transition Coupler 430 and PWB Coupler 420 to the PIC 410 or optical signals may be coupled from the Optical Interface 440 having propagated via Transition Coupler 430 and PWB Coupler 420 from the PIC 410.

[0068] Now referring to Figure 4B there is depicted a plan view of an embodiment of the invention according to the design outlined in Figure 4A after this OW-PHOTE as depicted in second Schematic 400D a PWB is formed comprising a first Portion 450A coupled to the PWB Coupler 420 and a second Portion 450B which couples from the first Portion 450A to a second Optical Interface 460. Accordingly, optical signals are routed to / from the PIC via the second Optical Interface 460 rather than via the Transition Coupler 430 and Optical Interface 440. [0069] Accordingly, in first Schematic 400A there are depicted the PIC 410, the PWB Coupler 420, Transition Coupler 430 and Optical Interface 440 which is depicted as a surface grating coupler. Accordingly, the PIC 410 can be tested by coupling optical signals to / from it via the PWB Coupler 420, Transition Coupler 430 and Optical Interface 440 where, by virtue of using a surface grating coupler, the optical elements acquiring or providing optical signals are out of the plane of the PIC 410. Disposed adjacent to the Optical Interface 440 are second Optical Interface 460 which has a second PWB Coupler 470 coupled to it.

[0070] Subsequently, in second Schematic 400D the PWB 450 is provided which couples from the PWB Coupler 420 to the second PWB Coupler 470. Disposed in association with the second Optical Interface 460 is Optical Fiber 480 which projects past the Facet 490 of the separated die comprising the PIC 410. Accordingly, optical signals are coupled to or from the PIC 410 from the Optical Fiber 480 via the PWB 450, the PWB Coupler 420 and the second PWB Coupler 470. It would be evident that other geometry configurations would be possible without departing from the scope of the invention. For example, the Transition Coupler 430 may transition away from the line of the PWB Coupler 420 such that the Optical Interface 440 is offset relative to the axis of the PWB Coupler 420 such that the second PWB Coupler 470, second Optical Interface 460 and Optical Fiber 480 are axial with the first PWB Coupler 420. [0071] Within embodiments of the invention a PWB Coupler 420 and/or second PWB Coupler 470 may be, for example, an unmodified waveguide of the PIC or a modified waveguide of the PIC tailored to providing low loss coupling to the PWB. Optionally, that portion of a PWB which overlaps a waveguide of the device, e.g. the PWB Coupler 420, may vary in geometry to transition optical signals to/from the waveguide of the device from/to the PWB. Similarly, another portion of the PWB overlapping the second PWB Coupler 470 may vary in geometry to transition optical signals to/from the PWB Coupler 470 of the device from/to the PWB. [0072] Optionally, a PWB may not overlap a waveguide of the device, e.g. the PWB Coupler 420, may end with the PWB starting at the end of the PWB Coupler 420 and the start of second Optical Interface 460. As depicted in Figure 4A the second Optical Interface 460 may not be present during the OW-PHOTE stage of the PIC manufacturing and packaging process.

[0073] Optionally, within other embodiments of the invention such as Figure 4B the second Optical Interface 460 may be present but not populated such as depicted in Figure 4B where the second Optical Interface is a fiber interface element, e.g. a U-groove or V-groove for example, such that once the PWB has been formed and the PIC die separated the optical fiber is introduced into the second Optical Interface 460.

[0074] Optionally, within other embodiments of the invention such as Figure 4B the second Optical Interface 460 may be present and be populated. For example, second Optical Interface 460 may be another portion of the PIC, a waveguide transition to an active or passive optical component etc.

[0075] Now referring to Figure 4B there are depicted first and second Schematics 400C and 400D with respect to an exemplary embodiment of the invention exploiting PWBs for on-wafer photonic testing (OW-PHOTE) of a PIC prior to die separation and packaging. Referring to first Schematic 400C there are depicted a PIC 410, a first photonic wirebond (PWB) Coupler 420, a Transition Coupler 430, an Optical Interface 440, a second PWB coupler 470 and second Optical Interface 460. Accordingly, prior to placement / formation of the PWB optical signals may be coupled to the Optical Interface 440 which propagate via Transition Coupler 430 and PWB Coupler 420 to the PIC 410 or optical signals may be coupled from the Optical Interface 440 having propagated via Transition Coupler 430 and PWB Coupler 420 from the PIC 410. As depicted the Optical Interface 450 is a surface diffraction grating (SDG) allowing optical signals to be coupled out of the plane of the substrate upon which the PIC 410, the first photonic wirebond (PWB) Coupler 420, the Transition Coupler 430, the Optical Interface 440, the second PWB coupler 470 and second Optical Interface 460 are formed. As such the SDG allows optical elements to couple light into / out of the device of which the PIC forms part whilst integrated in wafer form either at the end of the manufacturing sequence or part way through it. However, it would be evident that Optical Interface 440 may be another optical element rather than an SDG such as a mirror reflecting out of plane, an optical waveguide, holographic grating, etc. [0076] Subsequently as depicted in second Schematic 400D the PWB 450 is formed between first PWB Coupler 420 and second PWB Coupler 470 such that optical signals are coupled to / from the second Optical Interface 460 from / to the PIC 401. As depicted the second Optical Interface 460 is a fiber interface into which an Optical Fiber 480 is disposed, i.e. second Optical Interface 460 is a U-groove or V-groove for example. Accordingly, also depicted is device facet 490.

[0077] Optionally, the second Optical Interface460 could be another portion of the device, another waveguide, a waveguide transition to external optics, a recess / opening within the substrate for placement of an active component such as laser diode (LD), light emitting diode (LED) or semiconductor optical amplifier (SOA) either directly or through an intermediate mounting or flip-chip assembled.

[0078] Accordingly, the PIC 410 can be subjected to OW-PHOTE, assessed for performance, separated, and packaged if the OW-PHOTE testing indicated acceptable performance.

[0079] Now referring to Figure 5A there are depicted first and second schematics 500A and 500B of an exemplary embodiment of the invention exploiting a printed photonic component (PPC), in this instance a PWB, for OW-PHOTE of a PIC prior to die separation and packaging. Referring to first Schematic 500A there are depicted a PIC 510, a photonic wirebond (PWB) Coupler 520, a Transition Coupler 530, a first Optical Interface 540 and a second Optical Interface 560. Accordingly, optical signals may be coupled to the first Optical Interface 540 which propagate via Transition Coupler 530 and PWB Coupler 520 to the PIC 510 or optical signals may be coupled from the Optical Interface 540 having propagated via Transition Coupler 530 and PWB Coupler 520 from the PIC 510. First Optical Interface 540 may, for example, be an SDG, a mirror reflecting out of plane, an optical waveguide or a holographic grating. In contrast to Figures 4A and 4B where optical coupling was in-line between PWB Coupler 420 and Transition Coupler 430 within the embodiment depicted in Figure 5 the coupling is evanescent between the PWB Coupler 520 and Transition Coupler 530. This evanescent coupling may be lateral coupling, vertical coupling or a combination thereof. [0080] Subsequently, as depicted in second Schematic 500B a PWB is provided comprising a first PWB Section 550A in association with the PWB Coupler 520 and a second PWB Section 550B which couples from the PWB Coupler 520 to the second Optical Interface 560. Accordingly, optical signals are coupled to or from the PIC 510 from the second Optical Interface 560 via the first and second PWB Sections 550 A and 550B and the PWB Coupler 520 and the second PWB Coupler 470. It would be evident that other geometry configurations would be possible without departing from the scope of the invention. For example, the Transition Coupler 530 may transition away from the line of the PWB Coupler 520 such that the first Optical Interface 540 is offset relative to the axis of the PWB Coupler 520 such that the second Optical Interface 560 is inline (axial) with the first PWB Coupler 520. Optionally, a second PWB Coupler may be disposed prior to the second Optical Interface 560.

[0081] Optionally, a PWB may not overlap a waveguide of the device, e.g. the PWB Coupler 420, may end with the PWB starting at the end of the PWB Coupler 420 and the start of second Optical Interface 460. As depicted in Figure 4A the second Optical Interface 460 may not be present during the OW-PHOTE stage of the PIC manufacturing and packaging process.

[0082] Now referring to Figure 5B there are depicted first and second schematics 500C and 500D of an exemplary embodiment of the invention exploiting a PPC, in this instance a PWB, for OW-PHOTE of a PIC prior to die separation and packaging. Referring to first Schematic 500C there are depicted a PIC 5010, a photonic wirebond (PWB) Coupler 5020, a Transition Coupler 5030, a first Optical Interface 5040, a second Transition Coupler 5070 and a second Optical Interface 5060. Prior to OW-PHOTE a first PWB 5050A is formed between the PWB Coupler 5020 and the Transition Coupler 5030 such that optical signals can be coupled to / from the first Optical Interface 5040 which propagate via Transition Coupler 5030, first PWB 5050A and PWB Coupler 5020 from / to the PIC 5010. First Optical Interface 5040 may, for example, be an SDG, a mirror reflecting out of plane, an optical waveguide or a holographic grating.

[0083] Subsequent to the OW-PHOTE first PWB 5050A is removed and second PWB 5050B formed between the PWB Coupler 5020 and the second Transition Coupler 5070 such that optical signals are now coupled to / from the PIC 5010 via the second Optical Interface 5060. Subsequently the die with PCI 5010 may be separated and the second Optical Interface 5060 employed for coupling signal to the die. For example, second Optical Interface 5060 may be a U-groove or V-groove populated with an optical fiber as depicted in Figure 4B or it may an optical transition to an external interface, e.g. an external free-space optical coupling assembly, a light source (e.g. LD or LED), or photodetector.

[0084] Now referring to Figure 6 there are depicted first and second schematics 600A and 600B of an exemplary embodiment of the invention exploiting a PPC, in this instance a PWB, for OW-PHOTE of a PIC prior to die separation and packaging. Referring to first Schematic 500A there are depicted a PIC 610, a photonic wirebond (PWB) Coupler 620, a Loop Back Structure 630, a first Optical Interface 640 and a second Optical Interface 670. Accordingly, optical signals may be coupled to the first Optical Interface 640 which propagate via Loop Back Structure 630 and PWB Coupler 620 to the PIC 610 or optical signals may be coupled from the first Optical Interface 640 having propagated via PWB Coupler 620 and Loop Back Structure 630 from the PIC 610. First Optical Interface 540 may, for example, be an SDG, a mirror reflecting out of plane, an optical waveguide, a holographic grating, or an integrated photodetector. Subsequently, after OW-PHOTE, the PWB comprising first and second Sections 650A and 650B is formed to couple the optical signals to/from second Optical Interface 670 rather than first Optical Interface 640. Whilst Loop Back Structure 630 is depicted as continuous with PWB Coupler 620 it would be evident that alternatively a gap may be disposed between there wherein the Loop Back Structure 630 and PWB Coupler 620 may be inline or as depicted with respect to Figure 5A off axis with respect to one another such that evanescent coupling is employed to provide the necessary coupling during OW-PHOTE. [0085] Now referring to Figure 7 there are depicted first and second schematics 700A and 700B of an exemplary embodiment of the invention exploiting PPCs, in this instance PWBs, for OW-PHOTE with multiple ports on a PIC prior to die separation and packaging. In essence, Figure 7 depicts the same scenario as Figure 4A but for an array of ports to the PIC 710 rather than a single interface. Accordingly, in first Schematic 700A a PIC 710 is depicted with an array of PWB Couplers 720(1) to 720(N) respectively which each couple a respective one of Transition Couplers 730(1) to 730(N) respectively and therein the set of first Optical Interfaces 740(1) to 740(N) allowing OW-PHOTE to be performed. Subsequently, an array of PWBs 750(1) to 750(N) are formed coupling each Transition Coupler of the Transition Couplers 730(1) to 730(N) respectively to a second Optical Interface of the set of second Optical Interfaces 760(1) to 760(N) respectively. Within the scenario depicted the set of second Optical Interfaces 760(1) to 760(N) respectively are not present during OW-PHOTE, e.g. they may be an array of optical fibers disposed relative to the separated die comprising the PIC 710 such that the array of PWBs 750(1) to 750(N) are formed during the packaging stage rather than post OW-PHOTE at the wafer level. Within other embodiments of the invention the set of second Optical Interfaces 760(1) to 760(N) respectively are present during OW-PHOTE as they are integrated into the substrate with the PIC 710. Other configurations would be evident to one of skill in the art.

[0086] Figure 8 depicts an exemplary embodiment of the invention exploiting a PPC, in this instance a PWB, for on-chip re-routing (OC-RER) of a PIC prior to die separation and packaging. Accordingly there are depicted first and second schematics 800A and 800B of an exemplary embodiment of the invention exploiting PWBs for OW-PHOTE / on-chip re-routing of a PIC prior to die separation and packaging. Referring to first Schematic 800A there are depicted a PIC 810, a first Transition Coupler 820, a second Transition Coupler 830, a first Optical Interface 840, a third Transition Coupler 850 and a second Optical Interface 860. Accordingly, initially optical signals may be coupled to / from the PIC 810 from / to the first Optical Interface 840 via the first and second Transition Couplers 820 and 830 respectively. Post OW-PHOTE it is determined that rather than second Optical Interface 840 that third Optical Interface 860 will be employed. According, the PWB comprising first PWB Transition 870A, PWB Section 870B and second PWB Transition 870C is formed such that optical signals now propagate to/from the second Optical Interface 860 from/to the PIC 810.

[0087] For example, first Optical Interface 840 may represent an optical interface, such as an SDG of a first design or a U-groove / V-groove of a first geometry for example. Second Optical Interface 860 may represent another optical interface, such as an SDG of a second design or a U-groove / V-groove of a second geometry for example. Accordingly, for example, manufacturing variations may be accommodated by providing alternate interfaces wherein the actual interface is either a target (default) one, e.g. second Transition Coupler 830 and second Optical Interface 840) or a variant one, e.g. third Transition Coupler 850 and second Optical Interface 860. Whilst two interface variants are depicted it would be evident that 3 or more may be provided with the appropriate PWB formed to connect between the first Transition Coupler820 and the selected Optical Interface post OW-PHOTE.

[0088] For example, consider Insert 800C a Fiber Probe 880 is depicted relative to a groove within the die during OW-PHOTE. This may indicate that third Transition Coupler 850 should be employed rather than second Transition Coupler 830 (i.e. it has a different design such that manufacturing results in it having enhanced performance). Optionally, the decision could be based solely upon a mechanical measurement, e.g. width or depth of the U-grooves/V-grooves forming first and second Optical Interfaces 840 and 860 respectively. Optionally the decision could be based upon a defect within the second Transition Coupler 830 / first Optical Interface 840 where the second Transition Coupler 830 / first Optical Interface 840 are the same as third Transition Coupler 850 / second Optical Interface 860.

[0089] Now referring to Figure 9 there are depicted first and second Schematics 900A and 900B for an extension of these concepts to exploiting PPCs, in this instance PWBs, for on-chip re-routing (OC-RER) of a PIC prior to die separation and packaging. Referring to first Schematic 900 A there is depicted a structure comprising:

• optical element 950;

• an upper path comprising first PIC 910A, first and second Waveguide Structures 920A and 930A respectively and first Optical Interface 940A; and • a lower path comprising second PIC 910B, third and fourth Waveguide Structures 920B and 930B respectively and second Optical Interface 940A.

[0090] During OW-PHOTE the upper path and lower path are both tested. Accordingly, in second Schematic 900B this OW-PHOTE stage defines the upper path as having improved performance relative to the lower path such that a PWB 960 is formed from the first Waveguide Structure 920A to the Optical Element 950. Alternatively, as depicted in third Schematic 900C the OW-PHOTE stage defines the lower path as having improved performance relative to the lower path such that a different PWB 970 is formed from the third Waveguide Structure 920B to the Optical Element 950. For example, Optical Element 950 may be an optical source such as an LED or LD monolithically integrated or hybridly integrated. Alternatively, Optical Element 950 may be a photodetector. In this manner multiple PICs may be implemented, for example 2, 3 or more where the selected PIC is coupled to the Optical Element 950 post OW- PHOTE. It would be evident that within other embodiments of the invention multiple Optical Elements 950 may be coupled to the selected PIC and that these may comprise either sources, photodetectors or sources and photodetectors for example. Optionally, first PIC 910A and second PIC 910B may parts of the same PIC where internal elements in the PIC may route to the first PIC 910A or second PIC 910B respectively. Accordingly, manufacturing tolerances and/or manufacturing defects may be addressed by dynamically optically re-routing within the device and/or PIC. Optionally, Optical Element 950 is an interface to another PIC and/or active semiconductor element, e.g. SOA, LED, LD, photodiode (PD), etc.

[0091] Figure 10 depicts an exemplary embodiment of the invention exploiting a PPC, in this instance a PWB, a PPC, in this instance a PWB, for OW-PHOTE of a PIC prior to die separation and packaging wherein a PWB is created to provide the desired optical routing for OW-PHOTE but is then removed for die separation / packaging. Accordingly, the scenario depicted in Figure 10 may be viewed as the reverse of that in Figures 4A to 9 wherein the PWB is formed post OW-PHOTE. Accordingly, referring to Figure 10 there are depicted first to third Schematics 1000 A to lOOOC respectively wherein within each there is depicted a Device Structure 1000D comprising a PIC 1010 coupled to an Optical Interface 1030 via a Waveguide 1020 together with a Transition Coupler 1040 and Test Optical Interface 1050 which are not optically connected to the Device Structure 1000D. Accordingly, first Schematic 1000A depicts a die comprising the Device Structure 1000D either part-way through manufacturing or after wafer manufacturing prior to die separation.

[0092] In second Schematic 1000B a PWB 1060 is implemented between a portion of the Waveguide 1020 and the Transition Coupler 1040 such that optical signals can be coupled to/from the PIC 1010 from/to the Test Optical Interface 1050. Subsequently, post OW-PHOTE the PWB 1060 is removed yielding the structure depicted in third Schematic lOOOC wherein the PIC 1010 is optically connected to the Optical Interface 1030 via the Waveguide 1020. [0093] Within embodiments of the invention the second Schematic 1000B may be prior to deposition of an upper cladding such that the core of Waveguide 1020 is accessible such that the PWB 1060 can couple light evanescently from the core of Waveguide 1020.

[0094] Within other embodiments of the invention the second Schematic 1000B may after deposition of an upper cladding such that the core of Waveguide 1020 is not accessible but the PWB 1060 can couple light evanescently from the core of Waveguide 1020.

[0095] Within other embodiments of the invention the second Schematic 1000B may after deposition of an upper cladding such that the core of Waveguide 1020 is not accessible generally but a region may be thinned either on side(s) and/or tip so that the PWB 1060 can couple light evanescently from the core of Waveguide 1020.

[0096] It would be evident that the length /overlap of the PWB 1060 and portion of the Waveguide 1020 may be established through factors including, but not limited to, desired coupling efficiency to PWB 1060, refractive index of the PWB 1060, refractive index of the Waveguide 1020, geometry of the Waveguide 1020, geometry of the PWB 1060 and thickness of any upper cladding 1020 on the Waveguide 1020.

[0097] Figure 11 depicts an exemplary embodiment of the invention exploiting a PPC for OW- PHOTE of a PIC prior to die separation and packaging wherein a PPC is created to provide the desired optical routing for OW-PHOTE but is then removed for die separation / packaging. Accordingly with each of first to third Schematics 1100A to 1100C there are depicted a PIC 1110, Waveguide 1120, Optical Interface 1130, Coupler Section 1140A, Interconnect 1140B and Test Optical Interface 1150. The Coupler Section 1140A being designed to have no or low optical coupling to the Waveguide 1120 within the final device.

[0098] First Schematic 1100 A depicts these elements part way through processing prior to upper cladding formation. Second Schematic 1100B depicts a PPC 1160 formed between the Coupler Section 1140A and Waveguide 1120 such that optical coupling occurs to/from the Coupler Section 1140A from/to Waveguide 1120. Second Schematic 1100B depicting the device at the OW-PHOTE stage. Once the OW-PHOTE is complete the PPC 1160 is removed and an Upper Cladding 1170 deposited over part of the structure, in the instance depicted over everything but the Optical Interface 1130 and Test Optical Interface 1150 although in other embodiments of the invention one or both of these may also be coated with the Upper Cladding 1170. As no or low optical coupling has been designed for the final structure between the Coupler Section 1140A and the Waveguide 1120 then the PIC 1010 is optically coupled to the Optical Interface 1130 without additional attenuation arising from optical power being coupled to the Coupler Section 1140A. Accordingly, the die can be subjected to OW-PHOTE testing prior to deposition of the Upper Cladding 1170. Optionally, the Upper Cladding 1170- may be adjusted in dependence upon measurements of the PIC 1110 and/or test structures implemented onto the wafer or within the same die as the PIC 1110.

[0099] Figure 12 depicts an exemplary embodiment of the invention exploiting a PPC for OW- PHOTE of a PIC prior to die separation and packaging wherein a PPC is created to provide the desired optical routing for OW-PHOTE but is then removed for die separation / packaging. Within first to third Schematics there are depicted a PIC 1210, Waveguide 1220, Optical Interface 1230, Coupler Section 1240 A, Interconnect 1240B and Test Optical Interface 1250. The Coupler Section 1240 A being designed to have no or low optical coupling to the Waveguide 1220 within the final device.

[00100] First Schematic 1200A depicts these elements after processing with Upper Cladding 1270. Whilst this is depicted as not covering the Optical Interface 1230 and Test Optical Interface 1250 within other embodiments of the invention the Upper Cladding 1270 may cover these as well. As depicted an Opening 1260 is formed within the Upper Cladding 1270 such that the region between Optical Waveguide 1220 and Coupler Section 1240A is air at this point. This Opening 1260 may extend to the core of the Optical Waveguide 1220 and Coupler Section 1240A or these may have thin sidewalls of the Upper Cladding 1270.

[00101] In second Schematic 1200B the Opening 1260 has been filled with PPC 1280, i.e. within the region between the Coupler Section 1120A and Waveguide 1220, such that optical coupling occurs to/from the Coupler Section 1240A from/to Waveguide 1220. Second Schematic 1200B depicting the device at the OW-PHOTE stage. Once the OW-PHOTE is complete the PPC 1280 is removed so that the Opening 1260 is either filled with air or another low refractive index material as depicted in third Schematic 1260. Accordingly, during OW- PHOTE optical signals are coupled to/from the Test Optical Interface 1250 from/to the PIC 1210 via the Coupler Section 1220A. Post OW-PHOTE then optical signals are coupled to/from Optical Interface 1230 from/to PIC 1210.

[00102] Now referring to Figure 13 there is depicted an exemplary embodiment of the invention exploiting post-die processing to enable OW-PHOTE of a PIC prior to die separation and packaging. Referring to first to third Schematics 1300A to 1300C respectively there are depicted PIC 1310, first Waveguide Core 1320, second Waveguide Core 1330 and Optical Interface 1340. Also depicted are Substrate 1360, Lower Cladding 1350A and Upper Cladding 1350B. As depicted in first Schematic 1300A part-way through wafer processing the first Waveguide Core 1320 comprises a facet within an opening of the Upper Cladding 1350B. Next in second Schematic 1300B a Test Optical Interface 1370 is positioned with respect to the opening in the Upper Cladding 1350B and facet of the first Waveguide Core 1320 such that optical signals can be coupled to/from the PIC 1310 from/to the Test Optical Interface 1370 via the first Waveguide Core 1320. The facet of the first Waveguide Core 1320A reflecting optical signals to/from the Test Optical Interface 1370 from/into the first Waveguide Core 1320 A.

[00103] Subsequent to OW-PHOTE (second Schematic 1300B) then the region between the facets of the first and second Waveguide cores 1320A and 1320B are filled with PPC 1380 and a Cladding Fill 1390 provided. Optionally, according to factors such as the design of the optical waveguides, material refractive indices, refractive index of the PPC 1380 and refractive index of the Cladding Fill 1390 then the material employed for the PPC 1380 and Cladding Fill 1390 may be same or it may be different materials. Accordingly, once provided then the optical signals to/from PIC 1310 are coupled from/to Optical Interface 1340 via the first and second Waveguide cores 1320 A and 1320B.

[00104] Optionally, the opening within the Upper Cladding 1350 and the facet of the first Waveguide Core 1320A may be formed in a single processing step so that the Upper Cladding 1350B is similarly angled.

[00105] Optionally, the facet on the first Waveguide Core 1320 may be inverted such that the optical signals are coupled down into the Fower Cladding 1350A and Substrate 1360 according to the optical properties of these materials. For example, PDs may be formed in the Substrate 1360 or vertical cavity light sources for OW-PHOTE or these optical signals are coupled to or provided by optical elements below the substrate.

[00106] Optionally, as depicted in fourth Schematic 1300D the facet is provided on the second Waveguide Core 1330 rather than the first Waveguide Core 1320. This may be beneficial through the processing to provide the facet. Accordingly, during OW-PHOTE the PIC 1310 is coupled to or from via the first Waveguide Core 1320 and the optical signals reflecting off the facet on the second Waveguide Core 1330.

[00107] Figure 14 depicts an exemplary embodiment of the invention exploiting a PPC, namely a turning mirror, with post-die processing to enable OW-PHOTE of a PIC prior to die separation and packaging. Referring to first to third Schematics 1400A to 1400C respectively there are depicted PIC 1410, first Waveguide Core 1420, second Waveguide Core 1430 and Optical Interface 1440. Also depicted are Substrate 1360, Fower Cladding 1350A and Upper Cladding 1350B. As depicted in first Schematic 1400 A part-way through wafer processing there is a gap between the first Waveguide Core 1420 and the second Waveguide Core 1430 within an opening within the Upper Cladding 1450B.

[00108] Next as depicted in second Schematic 1400B a PPC 1470 is formed comprising a turning structure such that optical signals can be coupled to / from Test Optical Interface 1480 from / to the PIC 1410 via the first Waveguide Core 1420. An exemplary CAD model and scanning electron microscope micrograph of a PPC 1470 are depicted in first and second images 1400D and 1400E respectively. The PPC 1470 provides for a right angle turning of the optical signal propagation from in the plane of the Substrate 1460 to substantially perpendicular to the Substrate 1460.

[00109] Post OW-PHOTE as depicted in third Schematic 1400C subsequent processing results in PPC Core 1490A and PPC Cladding 1490B being deposited. The PPC Core 1490A by virtue of its refractive index destroys the turning-mirror aspect of PPC 1470 such that PPC 1470, PPC Core 1490A and PPC Cladding 1490B result in an optical waveguide transitioning from a first waveguide, comprising first Waveguide Core 1420A and Upper Cladding 1450B, to a second waveguide, comprising second Waveguide Core 1430 and Upper Cladding 1450B, such that the PIC 1410 and Optical Interface 1440 are optical coupled.

[00110] Alternatively, as depicted in Figure 15 the subsequent processing after OW-PHOTE is the removal of the PPC(l) 1510, e.g. turning mirror structure, and the writing of a new PPC(2) 1530, e.g. a PWB, with PPC Cladding 1540. This being depicted in third Schematic 1500C where first and second Schematics 1500A and 1500B are equivalent to first and second Schematics 1400A and 1400B in Figure 14.

[00111] Within an alternate embodiment of the invention described with respect to Figure 15 then the PPC(l) 1510 may according to the materials which can be deposited and processed be a surface diffraction grating (SDG), a turning-mirror with micro-lens, etc.

[00112] Accordingly, within embodiments of the invention the methodology may be described as comprising first to fourth steps, these being design of the PIC, wafer test, calibration and PPC formation where in this sequence the PPC is fabricated post OW-PHOTE such as described and depicted with respect to Figures 4A, 4B, 5 A, 6, 7, and 13 where the PPC provides an optical routing to the optical interface employed in packaging the die.

[00113] Alternatively, the sequence may be design of the PIC, PPC formation, wafer test, calibration and PPC removal / re-routing where in this sequence the PPC is fabricated prior to OW-PHOTE such as described and depicted with respect to Figures 8, 9, 10, 11, and 12 where the PPC provides an optical routing to an interim optical interface for OW-PHOTE rather than the optical interface to be employed in packaging the die.

[00114] However, it is noted that some processes as described above include PWB steps both prior to and post OW-PHOTE such as those depicted with respect to Figures 14 and 15. [00115] Considering the PIC design step then the following features may be considered where the PPC employed is a PWB:

• The PIC may comprise at least one optical input consisting of at least one photonic wirebond (PWB) coupler and at least one transition coupler (e.g., a butt coupler, a gap less butt coupler, or an evanescent coupler);

• When the PWB coupler is not connected to a photonic wirebond (PWB), one end of the transition coupler couples light from or into the PWB coupler;

• Another end of the transition coupler is connected to an optical interface that can be optically probed by an optical fiber, optical prober or other optical interface at the wafer scale level prior to die and/or bar separation;

• When the PWB coupler is connected to a PWB, the light, partially or wholly, that otherwise couples to the transition coupler is coupled to the PWB.

[00116] Considering the step of wafer test then the PIC(s) on the wafer may be tested by coupling optical signals into / out of optical interfaces that are not those which will be ultimately employed in packaging the PIC(s). These OW-PHOTE optical interfaces may be temporarily connected by PPC(s) and/or bypassed / circumvented by the provisioning of PPC(s). It would be evident that the PIC design step may take a different sequence where the PPC is a photonic component other than a PWB.

[00117] Considering the calibration step then this may comprise the sub-steps of:

• Measuring optical responses of the transition coupler and the optical interface using another one or more sets of units with the same designs of the transition coupler and the optical interface without passing through the PIC; and

• Calculating the optical response of the PIC by subtracting the measured optical responses of the transition coupler and the optical interface from the measured result in the wafer test.

[00118] Within the descriptions above with respect to Figures 4A to 15 the primary consideration / goal has been the provisioning of optical interfaces for on-wafer photonic testing (OW-PHOTE) prior to the separation of the PICs upon the wafer into bar and/or die form. However, it would be evident that the methods and geometries described and depicted with respect to Figures 4A to 15 may also be performed on PICs at the bar level or on discrete PIC die without departing from the scope of the invention.

[00119] Within the descriptions above with respect to Figures 4A to 15 a coupler and transition coupler have been described being disposed between a PIC and an optical interface. It would be evident to one of skill in the art that within embodiments of the invention these may be physically short and/or have zero physical length without departing from the scope of the invention. Accordingly, the recitation of the presence of a coupler and/or a transition coupler within the description and claims should be viewed as including elements of zero physical length as well as elements having a physical length.

[00120] Specific details are given in the above description to provide a thorough understanding of the embodiments. However, it is understood that the embodiments may be practiced without these specific details. For example, circuits may be shown in block diagrams in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring the embodiments.

[00121] The foregoing disclosure of the exemplary embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many variations and modifications of the embodiments described herein will be apparent to one of ordinary skill in the art in light of the above disclosure. The scope of the invention is to be defined only by the claims appended hereto, and by their equivalents.

[00122] Further, in describing representative embodiments of the present invention, the specification may have presented the method and/or process of the present invention as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. As one of ordinary skill in the art would appreciate, other sequences of steps may be possible. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. In addition, the claims directed to the method and/or process of the present invention should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the present invention.

Claims

CLAIMS What is claimed is:

1. A method of testing a photonic integrated circuit (PIC) comprising the steps of: fabricating a die comprising the PIC, a photonic wirebond coupler (PWB coupler), a transition coupler and an optical interface to a predetermined stage; forming a photonic wirebond (PWB); and optically testing the PIC.

2. The method according to claim 1, wherein the PWB coupler is optically coupled to the transition coupler and therein the optical interface; the optical testing of the PIC is performed prior to forming the PWB by coupling optical signals at least one of to and from the PIC via the optical interface, the transition coupler and PWB coupler; and the PWB is formed from the PWB coupler to another optical interface wherein the PWB couples optical signals at least one of to and from the PWB coupler.

3. The method according to claim 1, wherein the PWB coupler is optically coupled to the transition coupler and therein the optical interface; the optical testing of the PIC is performed prior to forming the PWB by coupling optical signals at least one of to and from the PIC via the optical interface, the transition coupler and PWB coupler; the PWB is formed from the PWB coupler to another optical interface wherein the PWB couples optical signals at least one of to and from the PWB coupler; and the optical interface is at least one of a surface diffraction grating, a fiber interface and a reflector coupling optical signals to or from a plane of a substrate upon which the die is formed to another plane perpendicular to the substrate.

4. The method according to claim 1, wherein the PWB coupler optical is optically coupled to the transition coupler and therein the optical interface; the optical testing of the PIC is performed prior to forming the PWB by coupling optical signals at least one of to and from the PIC via the optical interface, the transition coupler and PWB coupler; the PWB is formed from the PWB coupler to another optical interface wherein the PWB couples optical signals at least one of to and from the PWB coupler; the optical interface is at least one of a surface diffraction grating, a fiber interface and a mirror coupling optical signals to or from a plane of a substrate upon which the die is formed to another plane perpendicular to the substrate; and the another optical interface is at least one of another surface diffraction grating, another fiber interface, an optical fiber, and optical element and a reflector coupling optical signals to or from a plane of a substrate upon which the die is formed to another plane perpendicular to the substrate.

5. The method according to claim 1, further comprising removing the PWB; and forming another PWB; wherein the die further comprises another transition coupler and another optical interface; the PWB optically couples the PWB coupler to the transition coupler and therein the optical interface; the another PWB optically couples the PWB coupler to the another transition coupler and therein the another optical interface; the optical testing of the PIC is performed after formation of the PWB; and the another PWB is formed after PIC testing and removal of the PWB.

6. The method according to claim 1, wherein the die further comprises another PIC, another PWB coupler, another transition coupler and another optical interface, and an optical element; the optical testing of the PIC also comprises the optical testing the another PIC; and forming the PWB comprises forming the PWB from the optical element to one of the PWB coupler and another PWB coupler in dependence upon the testing of the PIC and another PIC.

7. A method of testing a photonic integrated circuit (PIC) comprising the steps of: fabricating a die comprising the PIC, a waveguide, an optical interface, a transition coupler and another optical interface to a predetermined stage; forming a printed photonic component (PPC); and optically testing the PIC.

8. The method according to claim 7, wherein the PPC optical couples signals at least one of to and from the optical waveguide; the PPC optically couples to the transition coupler and another optical interface; the another optical interface is employed for optically testing the PIC; and the PPC is removed after testing such that optical signals propagate via the waveguide between the optical interface and the PIC.

8. The method according to claim 7, wherein the predetermined stage is prior to formation of an upper cladding layer to the die; the PPC optical couples signals between the optical waveguide and transition coupler by supporting evanescent coupling between the optical waveguide and transition coupler; evanescent coupling between the optical waveguide and transition coupler is suppressed without the PPC present; the another optical interface is employed for optically testing the PIC; the PPC is removed after testing such that optical signals propagate via the waveguide between the optical interface and the PIC; and the wafer processing comprising at least formation of the upper cladding is completed after removal of the PPC.

9. The method according to claim 7, wherein the predetermined stage is after formation of an upper cladding layer to the die; the PPC optical couples signals between the optical waveguide and transition coupler by supporting evanescent coupling between the optical waveguide and transition coupler; evanescent coupling between the optical waveguide and transition coupler is suppressed without the PPC present; the another optical interface is employed for optically testing the PIC; the PPC is removed after testing such that optical signals propagate via the waveguide between the optical interface and the PIC; and the PPC is formed within an opening in the upper cladding layer between the optical waveguide and transition coupler.

10. A method of testing a photonic integrated circuit (PIC) comprising the steps of: fabricating a die comprising the PIC, a waveguide, an optical interface and a transition coupler to a predetermined stage; forming a printed photonic component (PPC); and optically testing the PIC.

11. The method according to claim 7, wherein the waveguide comprises a reflector coupling optical signals to or from a plane of a substrate upon which the die is formed to another plane perpendicular to the substrate; optical testing of the PIC is performed prior to formation of the PPC; and the PPC is formed between an end of the waveguide comprising the reflector to an end of the transition coupler distal to the optical interface to suppress the reflector functionality.

12. The method according to claim 7, further comprising forming another PPC; wherein the PPC is disposed at an end of the waveguide distal to the PIC and comprises a reflector coupling optical signals to or from a plane of a substrate upon which the die is formed to another plane perpendicular to the substrate; optical testing of the PIC is performed after formation of the PPC but before formation of the another PPC; and the another PPC is formed between the PPC and an end of the transition coupler distal to the optical interface to suppress the reflector functionality.

13. The method according to claim 7, further comprising removing the PPC; and forming another PPC; wherein the PPC is disposed at an end of the waveguide distal to the PIC and comprises a reflector coupling optical signals to or from a plane of a substrate upon which the die is formed to another plane perpendicular to the substrate; optical testing of the PIC is performed after formation of the PPC; and the another PPC is formed after removal of the PPC between the end of the waveguide distal to the PIC and an end of the transition coupler distal to the optical interface.