WO2022265552A1

WO2022265552A1 - System, method, and apparatus for fine-grained control of input/output data placement in a memory subsystem

Info

Publication number: WO2022265552A1
Application number: PCT/SE2021/050803
Authority: WO
Inventors: Amir ROOZBEH; Alireza FARSHIN; Dejan Kostic; Gerald Q. MAGUIRE, Jr.; Chakri PADALA
Original assignee: Telefonaktiebolaget Lm Ericsson (Publ)
Priority date: 2021-06-14
Filing date: 2021-08-17
Publication date: 2022-12-22

Abstract

Methods and systems for fine-grained control of input/output data placement in a memory subsystem. A request to transfer a packet between a network interface and a memory subsystem of a processing unit is received. The memory subsystem and the processing unit are coupled through a communication bus and the memory subsystem includes a cache for the processing unit. A first portion of the packet that is to be transferred to the cache is determined based on a destination address of the packet. The first portion of the packet is transferred to the cache.

Description

SYSTEM, METHOD, AND APPARATUS FOR FINE-GRAINED CONTROL OF INPUT/OUTPUT DATA PLACEMENT IN A MEMORY SUBSYSTEM

TECHNICAL FIELD

[0001] Embodiments of the invention relate to the field of packet networking; and more specifically, to the fine-grained control of input/output placement in a memory subsystem.

BACKGROUND

[0002] A network device (ND) is an electronic device that communicatively interconnects other electronic devices on the network (e.g., other network devices, end-user devices). Some network devices are “multiple services network devices” that provide support for multiple networking functions (e.g., routing, bridging, switching, Layer 2 aggregation, session border control, Quality of Service, and/or subscriber management), and/or provide support for multiple application services (e.g., data, voice, and video).

[0003] A network device receives input data, processes the data, and outputs the data following its processing. For example, a network device may receive network packets, and output network packets following their processing. A network device includes one or more processing units on which code is executed for processing the input data. The processing units are coupled with a network interface. A network interface (NI) is an electronic device operative to establish network connections (to transmit and/or receive data using propagating signals) with other electronic devices. For example, a NI receives the data from other network devices, transfers the data to the processing unit(s) for processing, receives the processed data from the processing unit(s), and outputs the processed data towards other network devices.

[0004] An NI and the processing unit(s) are interconnected via a communication bus (e.g., Peripheral Component Interconnect Express (PCIe) bus). Different approaches exist for transferring data to a processing unit. In a first approach data can be stored in a main memory of the processing unit (e.g., using a Direct Memory Access (DMA) mechanism) before being retrieved by the processing unit for processing. In another approach data is directly sent to the processing unit. In one example, the data is sent to a cache of the processing unit through a direct cache access mechanism. Technologies such as Intel Data Direct I/O (DDIO) technology, or/and ARM Cache Stashing are examples of technologies that allow sending data to a last level cache (LLC) or other cache levels or other on chip storages of the processing unit. SUMMARY

[0005] The embodiments described herein present a solution for fine-grained control of input/output data placement in a memory subsystem. The solution integrates to network and electronic devices the ability to selectively transfer data or portions of data to a processing unit. The solution advantageously integrates the notion of prioritizing some data over other data for direct access to a processing unit. The solutions enable an efficient processing of the data, by directly sending the data to the processing unit, and/or sending portions of the data to the processing unit.

[0006] One general aspect includes a method in an electronic device for enabling selective transfer of data to a memory subsystem of a processing unit. The method includes receiving information from one or more applications, a network interface, the memory subsystem, and an operating system; determining, based on the information, one or more configuration parameters for data associated with a destination address in a main memory of the electronic device, where the data is intended to be transferred by the network interface to a location of the destination address in the main memory; and configuring the electronic device with the configuration parameters, where the configuring causes a portion of the data associated with the destination address to be transferred to a cache for the processing unit instead of the main memory.

[0007] One general aspect includes an electronic device. The electronic device includes a non- transitory machine -readable storage medium that provides instructions that, if executed by a processor, will cause the electronic device to perform operations may include, receiving information from one or more applications, a network interface, the memory subsystem, and an operating system; determining, based on the information, one or more configuration parameters for data associated with a destination address in a main memory of the electronic device, where the data is intended to be transferred by the network interface to a location of the destination address in the main memory; and configuring the electronic device with the configuration parameters, where the configuring causes a portion of the data associated with the destination address to be transferred to a cache for the processing unit instead of the main memory.

[0008] One general aspect includes a method including receiving a first request to transfer first data between a network interface and a memory subsystem of a processing unit that are coupled through a communication bus, where the memory subsystem includes a cache for the processing unit; determining, based on a first destination address of the first data, that a first portion of the first data is to be transferred to the cache; and transferring the first portion of the first data to the cache.

[0009] One general aspect includes an electronic device. The electronic device includes a non- transitory machine -readable storage medium that provides instructions that, if executed by a processor, will cause the electronic device to perform operations including: receiving a first request to transfer first data between a network interface and a memory subsystem of a processing unit that are coupled through a communication bus, where the memory subsystem includes a cache for the processing unit; determining, based on a first destination address of the first data, that a first portion of the first data is to be transferred to the cache; and transferring the first portion of the first data to the cache.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The invention may best be understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the invention. In the drawings:

[0011] Figure 1 A illustrates a block diagram of a system for fine-grained control of input/output placement in a memory subsystem, in accordance with some embodiments.

[0012] Figure IB illustrates a block diagram of an exemplary EO address table 182 that can be used to enable selective transfer of data to a memory subsystem, according to some embodiments.

[0013] Figure 1C illustrates an example implementation encoding scheme with 64-bit address field and 40 bits of physical memory, in accordance with some embodiments.

[0014] Figure 2 illustrates a flow diagram of exemplary operations that can be performed for configuring a network device for selectively transferring data to a cache of a processing unit, in accordance with some embodiments.

[0015] Figure 3 A illustrates a flow diagram of exemplary operations that can be performed for selectively transferring data to a cache of a processing unit, in accordance with some embodiments.

[0016] Figure 3B illustrates exemplary operations of a method that can be performed to determine how to transfer a portion of data to the memory subsystem, in accordance with some embodiments.

[0017] Figure 3C illustrates exemplary operations of another method that can be performed to determine how to transfer data or a portion of data to the memory subsystem, in accordance with some embodiments.

[0018] Figure 4A illustrates connectivity between network devices (NDs) within an exemplary network, as well as three exemplary implementations of the NDs, according to some embodiments of the invention.

[0019] Figure 4B illustrates an exemplary way to implement a special-purpose network device according to some embodiments of the invention. [0020] Figure 4C illustrates various exemplary ways in which virtual network elements (VNEs) may be coupled according to some embodiments of the invention.

[0021] Figure 4D illustrates a network with a single network element (NE) on each of the NDs, and within this straight forward approach contrasts a traditional distributed approach (commonly used by traditional routers) with a centralized approach for maintaining reachability and forwarding information (also called network control), according to some embodiments of the invention.

[0022] Figure 4E illustrates the simple case of where each of the NDs implements a single NE, but a centralized control plane has abstracted multiple of the NEs in different NDs into (to represent) a single NE in one of the virtual network(s), according to some embodiments of the invention.

[0023] Figure 4F illustrates a case where multiple VNEs are implemented on different NDs and are coupled to each other, and where a centralized control plane has abstracted these multiple VNEs such that they appear as a single VNE within one of the virtual networks, according to some embodiments of the invention.

[0024] Figure 5 illustrates a general-purpose control plane device with centralized control plane (CCP) software 550), according to some embodiments of the invention.

DETAILED DESCRIPTION

[0025] The following description describes methods and systems for efficient input/output transfer in network devices. In the following description, numerous specific details such as logic implementations, opcodes, means to specify operands, resource partitioning/sharing/duplication implementations, types and interrelationships of system components, and logic partitioning/integration choices are set forth in order to provide a more thorough understanding of the present invention. It will be appreciated, however, by one skilled in the art that the invention may be practiced without such specific details. In other instances, control structures, gate level circuits and full software instruction sequences have not been shown in detail in order not to obscure the invention. Those of ordinary skill in the art, with the included descriptions, will be able to implement appropriate functionality without undue experimentation.

[0026] References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0027] Bracketed text and blocks with dashed borders (e.g., large dashes, small dashes, dot- dash, and dots) may be used herein to illustrate optional operations that add additional features to embodiments of the invention. However, such notation should not be taken to mean that these are the only options or optional operations, and/or that blocks with solid borders are not optional in certain embodiments of the invention.

[0028] In the following description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. “Coupled” is used to indicate that two or more elements, which may or may not be in direct physical or electrical contact with each other, co-operate or interact with each other. “Connected” is used to indicate the establishment of communication between two or more elements that are coupled with each other.

[0029] While different approaches exist for transfer of data to/from a processing unit and a network interface of a network device, these approaches (e.g., direct cache access, or main memory access) have limited efficiency and several disadvantages. A cache is a limited resource that is used to store code/data and I/O. In approaches that rely on direct cache access, different applications running on the processing unit have different requirements, e.g., some need more cache for I/O and some more for code/data, making it hard to have a one-size-fits-all solution for dividing the cache between I/O and code/data. Therefore, current approaches use a limited portion of the cache for I/O, resulting in hiding the benefits of the direct-access approach or in making the portion of the cache that is reserved for direct-access a bottleneck. This problem is particularly significant in network devices of packet networks where the packet arrival rate can be faster than the packet processing rate. In this case, new incoming packets repeatedly evict previously loaded packets (i.e., not-yet-processed or already-processed packets) in the limited portion of the cache that is used for direct access. Consequently, the processing unit of the network device has to load not-yet-processed packets from the main memory rather than from the cache, and the processed packets needs to be loaded from the main memory, instead of being directly output from the processing unit thereby missing the benefits of direct cache access. Further, existing approaches do not allow to selectively send data directly to the processing unit or to explicitly bypass this direct transmission. In other words, when direct access to the processing unit (e.g., direct cache access or direct register access) is enabled, all data/packet(s) is sent to the processing unit through this process. Alternatively, when direct access is not enabled, all data is sent to the processing unit through the main memory. [0030] A NI is connected to a processing unit through a communication bus. Peripheral Component Interconnect express (PCIe) is an example of such communication buses. As the NI transmits packets to the processing unit, the packets are split into PCIe maximum transmission unit (MTU) sized frames and a PCIe header is added to each frame. The PCIe frames are sent over the PCIe bus to the processing unit. In some implementations, PCIe protocol headers can provide some hints as to where to place the packets in a cache of the processing unit. Cache placement can be enabled via three different fields in the PCIe protocol header. A first field is the TH field. When the TH bit is set in the header of the PCIe frame, that indicates that the TL (Transaction Layer) Processor Hint (TPH) is enabled. A second field is the R field, which is contained in the last two bits of the address field. The R bits indicate how the data access is likely to occur: where 00 indicates that the data access is bidirectional (i.e., accessed by both host and NI), 01 indicates that the data access is by the Requester (i.e., by the NI), 10 indicates that the data access is by the Target (Completer) (i.e., by the host), and 11 indicates that the data access is by the Target with priority (by host with high temporal locality (e.g., using the local cache as much as possible)). The third field, the Tag field, is a host’s specific identifier that enables a particular type of processing. For example, a value of 200 can indicate that the PCIe frame is to be written to cache, while value 201 can indicate that the PCIe frame is to be written to remote processing unit. By setting TH bit to 1, followed by setting the R bits in the address field to 01 and using a predefined value for the Tag field, the packets could be placed appropriately in the memory subsystem by the NI. However, this approach requires support from the network interface (e.g., to set the PCIe header bits) and does not provide enough flexibility as TAGs are defined in the firmware or Central Processing Unit (CPU) and either require a reboot to define new types or are not customizable at all. It also does not provide a way to distinguish between different cache lines if portions of a PCIe frame need to be processed differently (e.g., a portion stored in a cache and another in the main memory). Thus, using PCIe header fields does not allow for fine-grained I/O data placement into the memory subsystem of a processing unit.

[0031] Existing direct cache access mechanisms do not perform fine-grained I/O placement of data from the NI to the memory subsystem of the processing unit(s). Existing direct cache access mechanisms (e.g., DDIO and Cache Steering) simply inject all incoming data (e.g., PCIe frame) from the queues of the NI into one or more multiple cache lines of a cache. However, not all of data added to these cache lines is needed by the applications during processing. Existing direct cache access mechanisms are not able to selectively inject data into the cache (e.g., sending one specific packet or a portion of the packet (e.g., high priority packet or a header of a packet) to cache while loading other packets or another portion of the same packet (e.g., low-priority packets, or payload of a packet) to the main memory) or bypass it.

[0032] The embodiments described herein present efficient methods and systems of fine grained control of Input/Output data placement in a memory subsystem. The embodiments described herein allow to selectively load a packet (or a portion of the packet) to the cache of the processing device and optionally send the remaining portion or other packets into the main memory of a network device. The embodiments herein enable full control over the positioning of the Input/Output data in the system’s memory subsystem. Additionally, the embodiments herein enable dynamic and programmable control over Input/Output data, where the placement of I/O data can be configured at runtime based on different scenarios. The embodiments, allow to drop selected portion(s) of packets, thereby saving memory and cache bandwidth.

[0033] The embodiments described herein present several additional advantages with respect to existing direct cache access mechanisms. The embodiments herein present a generic solution that can be applied in both userspace and kernel-space packet processing. The proposed embodiments are application agnostic and do not require modification at the application level. The proposed embodiments are flexible and cloud friendly. For example, with the proposed embodiments, changing a configuration on how to handle a PCIe frame and packet can be done just by a minor adjustment in an I/O address table rather than changing the configuration in system's firmware and restarting the system (e.g., as is the case in TPH hint-based approaches). Based on the embodiments herein, a cloud/service provider can define which application (e.g., in a multi-tenant environment) can benefit from direct accessing its I/O data from the cache of the processing unit. The embodiments herein enable applications to make the most out of the limited cache space available for I/O transfer, thereby improving their service tail (especially tail latencies that are important to cloud providers) and enabling more predictable service offerings. [0034] While the embodiments herein will be described with respect to packets received at a network interface as an example of Input/Output data transfer with a processing unit, the embodiments are not so limited and they can be applied to any other types of data transfer (e.g., data originated from communication buses (e.g., other I/O devices such as PCIe SSDs), other processing units such as GPUs and FPGAs, etc.).

[0035] Figure 1 A illustrates a block diagram of a system 100 for efficient I/O transfer to a processing unit, in accordance with some embodiments. The system 100 includes a network device 102. The network device 102 includes a processing unit 160, a memory subsystem 164, a network interface (NI) 110, and an input output memory manager 180. The network device 102 is operative to be coupled with one or more other network devices through the NI 110. [0036] The network interface 110 and the NI driver 172 form an NI system. The NI driver 172 is operative to operate or control the NI. For example, the NI driver 172 provides an interface to NI 110, enabling operating systems, networking libraries, packet processing framework, and the applications 178A-N to access the NI. NI driver 172 communicates with NI 110 through a bus or a communications subsystem to which NI 110 connects. When a calling program invokes a routine in the driver, the driver issues commands to the NI. The network interface 110 is operative to establish network connections (to transmit and/or receive data using propagating signals) for the network device 102 with other electronic devices (e.g., with ND 102B). For example, the NI (or the NI in combination with the processor unit executing code) may perform any formatting, coding, or translating to allow the network device to send and receive data whether over a wired and/or a wireless connection.

[0037] The NI 110 includes an input/output (I/O) controller 105 that is operative to send and receive data (e.g., packets) from an external electronic device. The I/O controller 105 may facilitate connecting the network device to other electronic devices, allowing them to communicate via wire through plugging in a cable to a physical port connected to the controller. In some embodiments, the I/O controller 105 is a Media Access Controller (MAC). In some embodiments, a physical NI may comprise radio circuitry capable of receiving data from other electronic devices over a wireless connection and/or sending data out to other devices via a wireless connection. This radio circuitry may include transmitted s), receiver(s), and/or transceiver(s) suitable for radiofrequency communication. The radio circuitry may convert digital data into a radio signal having the appropriate parameters (e.g., frequency, timing, channel, bandwidth, etc.). The radio signal may then be transmitted via antennas to the appropriate recipient(s).

[0038] The NI 110 includes an NI manager 130. The NI manager 130 is operative to perform multiple tasks that may include packet classification, packet filtering, and scheduling. For example, the NI manager 130 is operative to decide how a packet is distributed among available receive queues, RX queues Ql-QN. These queues are used to store packets/data that are to be processed by the processing unit 160. In some embodiments, receive side scaling (RSS) mechanism can be used to distribute/schedule data to the RX queues Ql-QN. RSS is a network driver technology that enables the distribution of received packets across multiple RX queues based on the hash of different fields of a packet. In some embodiments, NI 110 provides advanced flow-steering techniques that support advanced packet filtering. These advanced filtering techniques enable the NI to direct the received packets to different queues based on a rule. The NI 110 can further include NI memory 120. NI memory 120 is a non-transitory computer readable storage medium included in the NI that can act as a buffer for storing data. In some embodiments, data is stored in the NI memory 120 when other components of NI are busy and cannot perform the tasks associated with this data. The NI 110 also includes transmit queues, TX queues PI -PM. The TX queues PI -PM receive processed data/packets from the processing unit 160 to be output from the NI 110. The TX queues PI -PM can receive packets/data from the main memory 166 and/or from the cache 162.

[0039] The NI 110 further includes a memory communication manager 140. The memory communication manager is operative to transfer packets/data to and from the memory subsystem of a processing unit 160. The memory communication manager 140 transfers packets between the NI RX/TX queues and the memory subsystem 164 based on the descriptor(s) for the packets. A packet descriptor includes information that describes the packet. For example, the packet descriptor indicates where the packet can be (or is) stored (packet buffer address), the length of the packet, one or more fields from packet headers (e.g., Virtual Local Area Network ID), timestamp, Receive Side Scaling (RSS) Hash, flow director filter identifier, information regarding packet checksum, etc.).

[0040] Two mechanisms can be used for transferring data/packets from the NI 110 to the processing unit 160, 1) a first technique where data/packets are stored in main memory 166, 2) directly sending packets/data to the processing unit 160. The latter technique is sometimes referred to as direct cache access, (e.g., DDIO, or cache stashing). When an NI sends data/packets directly to the processing unit 160, the data/packets are directly stored in the cache of the processing unit 160, e.g., cache 162, or alternatively the data packets are directly sent to other on-chip memories, e.g., registers 165, or directly stacked high bandwidth memories, of the processing unit 160. Direct transmission of data/packets to the processing unit 160 is performed without transmission of the data/packets to the main memory 166. The data/packets are then processed by the processor(s) from the cache 162 or from the registers 165. Directly sending the packets/data to the processing unit 160 enables a faster processing of the data/packets than when the packets/data are sent to the main memory 166 for processing in the processing unit 160. When the data is stored in the main memory 166, the data is retrieved by the processing unit 160 and stored in the cache before being processed by the processor(s) or retrieved by the processing unit 160 and stored directly in registers 165 to be processed by the processor(s).

[0041] The processing unit 160 includes one or more processor(s) (not illustrated) that are coupled with non-transitory computer readable storage media, such as the memory subsystem 164. The memory subsystem 164 can include a cache 162 and/or a main memory 166. The cache 162 is part of the processing unit 160. During operation, the processor(s) execute code that is stored in non-transitory computer readable storage media to instantiate one or more sets of one or more applications 178A-N and/or NI driver 172. The application(s) 178A-N process data/packets received from the NI 110. The data can be received directly from the NI 110 (through the cache 162) or from the main memory 166. In some embodiments, the NI 110 is connected to the processing unit 160 and the memory subsystem 164 through a communication bus.

[0042] The network device 102 further includes an optional input/output (I/O) memory manager 180. The I/O memory manager 180 can sometimes be referred to as an input-output memory management unit (IOMMU). The I/O memory manager 180 connects I/O devices, such as the NI 110, to the memory subsystem 164. The I/O memory manager 180 translates device- visible addresses (also called device addresses or I/O addresses) to physical addresses of the memory subsystem. In some embodiments, the I/O memory manager 180 provides memory protection from faulty or malicious devices. For example, the I/O memory manager 180 can protect the memory subsystem 164 by ensuring that I/O devices such as the NI only have access to authorized locations in the main memory. The authorization can be enabled by providing virtual addresses to the I/O devices instead of physical addresses. In addition, the I/O memory manager 180 can overcome deficiencies in addressing schemes. For example, the I/O memory manager 180 enables 32-bit-only-capable I/O devices to communicate with a 64-bit memory subsystem. If a device only supports 32-bit address, but the actual physical address assigned is a 64-bit physical address, a virtual address of 32 bit is generated and given to the I/O device. The I/O memory manager 180 translates the virtual address of 32-bit into the 64-bit physical address when the I/O device, e.g., NI 110, starts the memory access operation. In some embodiments, the I/O address table 182 is stored in the main memory 166. In other embodiments, a portion or all of the I/O address table 182 is cached in the I/O memory manager 180 to enable faster lookups. The I/O address table 182 is described in further detail below with reference to Figure IB.

[0043] The network device 102 further includes a I/O data transfer agent 190. In some embodiments, the I/O data transfer agent 190 is an extension for the I/O memory manager 180. In other embodiments, the I/O data transfer agent 190 is independent of the I/O memory manager 180. The I/O data transfer agent 190 is operative to selectively transfer data received from the NI 110 to a component of the memory subsystem 164, e.g., to the cache 162 or the main memory 166. In some embodiments, the I/O memory manager 180 is operative to send a portion of a packet to the cache while sending the remaining portion of a packet to the main memory. In some embodiments, the I/O memory manager 180 is operative to perform the selective transfer of data based on the I/O address table 182. Alternatively, the I/O memory manager 180 is operative to perform the selective transfer of data based on one or more bits of a destination address of the packet (e.g., the NI address). In other embodiments, the I/O memory manager 180 is operative to perform the selective transfer of data based on one or more bits of a destination address of the packet (e.g., the NI address).

[0044] In some embodiments, the applications 178A-N are networking/packet processing applications, such as the network function virtualization (NFV) applications. Additionally or alternatively, one or more of the applications 178A-N can perform operations other than networking/packet processing. During initialization, the applications 178A-N and/or the NI driver 172 allocate buffers in the memory subsystem 164 to store the data that is transferred to and from the NI. The applications and/or NI driver 172 update a packet descriptor for packet that is to be transferred to/from the NI 110 with addresses for these buffers and transmits the descriptors to the NI. Before updating a packet descriptor with addresses for a buffer, the application/driver communicates with the I/O memory manager 180 to receive a NI address (virtual address) that maps to a physical address of the buffer. The NI address is inserted in the packet descriptor of the packet instead of the physical address. The mapping of the NI address to physical address becomes an I/O table entry in the I/O address table 182.

[0045] The network device 102 further includes a data transfer optimizer 132. The data transfer optimizer 132 is operative to receive information from one or multiple components of the network device 102 and determine based on the information, configuration parameters for enabling selective data transfer between the NI 110 and the processing unit through the memory subsystem. The components include the application 178A-N, the NI 110, the memory subsystem 164, and/or the operating system (not illustrated). The information can include identifiers of packet flows, the applications’ priorities/requirements (e.g., a priority level associated with each flow of packets), physical addresses of buffers in the memory subsystem 164 (e.g., addresses in main memory 166) for the flows, reservation of space in packet buffers for application use and/or other information regarding the memory hierarchy of the memory subsystem 164, NI configuration and NI queue assignment for different flows, etc. As it will be described in further detail below, the configuration parameters can be used to configure, the I/O data transfer agent 190, the I/O memory manager 180, and/or the NI 110 for enabling a selective transfer of data from the NI to the memory subsystem 164. For example, the configuration parameters cause portion(s) of a packet received in the NI to be placed in the cache, while the rest of the packet bypasses the cache (e.g., it will be sent directly to the main memory or other part(s) of the memory subsystem 164). While the data transfer optimizer 132 is illustrated as a separate component of the network device 102, one of ordinary skill in the art would understand that the embodiments should not be so limited, and that the data transfer optimizer can be implemented as part of another element in the network device 102. For instance, the data transfer optimizer 132 can be part of an initialization phase that is performed for allocating addresses in the memory subsystem to the applications 178A-N. The data transfer optimizer 132 enables applications to make the most out of the limited cache 162 available for data transfer, thereby improving the service tail (e.g., tail latencies) of the applications. Further, the data transfer optimizer 132 allows to dynamically adapt the I/O data transfers by updating the configuration parameters over time. The data transfer optimizer 132 can be beneficial in multi -tenant systems where different applications might be allocated/deallocated/migrated on/to the same system. While embodiments herein will be described with the example of transfer of data from the NI to the processing unit (e.g., transfer of packets received at the NI, which are to be processed by applications 178A-N of the processing unit), the mechanisms herein can be applied to any data to be loaded to memory locations that are to be accessed by both the NI 110 and the processing unit 160. This data, such as packet descriptors or queues, can benefit from being loaded in a memory unit that is closer to the processing unit 160 (such as the cache 162).

[0046] Figure IB illustrates a block diagram of an exemplary I/O address table 182 that can be used to enable selective transfer of data to a memory subsystem, according to some embodiments. The I/O table 182 is an enhanced I/O address table that includes additional information for an entry to enable selective transfer of data/packets from the NI 110 to the memory subsystem 164. The I/O address table 182 includes one or multiple entries. While Figure IB illustrates three entries in the I/O address table 182, this is intended to be exemplary only and any number of entries can be included. As it will be discussed below, an entry of the I/O address table 182 is accessed according to a virtual address and a port identifier.

[0047] An entry of the I/O address table 182 table includes an entry identifier (entry ID) 183 A, a port identifier (port ID) 183B, a virtual address 183C, a physical address 183D, one or more bitmask flags 183E, and additional fields 183F. The port ID 183B identifies a physical or virtual port of the communication bus (e.g., PCIe port). The virtual address 183C specifies the virtual address as either an address range or a starting address and an address mask so that any corresponding addresses can be translated into the physical addresses 183D. The physical address 183D indicates the corresponding real system’s memory address. The entry bitmask flags 183E. The flags can include an ENABLED field, which when set indicates the entry is valid. The READ and WRITE fields indicate whether the memory subsystem’s address (i.e., the physical address 183D) can be read from or written to.

[0048] The enhanced I/O address table 182 further includes additional bitmask flags,

C ACHED WRITE, PARTIAL C ACHING and SLICED C ACHE, P ARTIAL DROPPING to enable selective transfer of I/O data. When the CACHED WRITE field is set this indicates that the packet (that matches the entry in the table based on the port and virtual address) should be stored entirely in the cache 162. When the PARTIAL CACHING field is set, this indicates that partial caching is enabled. If partial caching is enabled, only a portion of the packet received at the I/O memory manager 180 is cached (i.e., sent to be stored in the cache 142). If partial caching is not enabled and CACHED WRITE is set, the whole packet is cached (i.e., sent to be stored in the cache 142). When a SLICED CACHE field is set, this indicates that the packet should be stored in a particular slice of the cache 162 when multiple different slices of cache exist. PARTIAL CACHE BITMASK field specifies the portions of the packet that need to be cached in the cache 162. The PARTIAL CACHE BITMASK field is used when the PARTIAL CACHING is enabled. SLICED CACHE BITMASK field indicates the cache segment(s) that should be used to cache the packet when the processing unit has Non-Uniform Caching Architecture (NUCA) system. When a PARTI AL DROPPING field is set, this indicates that one or more portions of an incoming packet are to be dropped. The DATA SZ field specifies the maximum size of the incoming packet. A DROP BITMASK field indicates the portions of the packet that can be dropped.

[0049] Figure 2 illustrates a flow diagram of exemplary operations that can be performed for configuring a network device for selectively transferring data to a cache of a processing unit, in accordance with some embodiments. At operation 202, the data transfer optimizer 132 receives information from one or multiple entities of the network device 102 such as the applications 178A-N, the NI 110, the memory subsystem 164, and/or the operating system (not illustrated). The information relates to data that is to be transferred from the NI to the applications for processing or from the applications to the NI for output transmission. The information can include one or more of an identifier of the data, a priority level for the data, a destination address of a buffer in the memory subsystem (e.g., a physical address in the main memory).

[0050] At operation 204, the data transfer optimizer 132 determines, based on the information, configuration parameters for the data that is associated with the destination address. In some embodiments, the data is to be transferred by the NI 110 to the processing unit of the electronic device 102. In some embodiments, the configuration parameters include an identifier of the data, the destination address, an indication of whether the data for that address is to be transferred to the cache 162, and optionally an indication of a portion of the data that is to be transferred to the cache 162. In some embodiments, the configuration parameters can include one or more values for the flags identified in fields 183E and 183F of Figure IB.

[0051] At operation 206, the data transfer optimizer 132 configures the network device 102 with the configuration parameters. In some embodiments, the data transfer optimizer 132 can configure the I/O address memory manager 180, the NI 110, and/or the I/O data transfer agent 190 based on the configuration parameters. [0052] In some embodiments, the data transfer optimizer 132 configures the I/O memory manager 180 and the I/O data transfer agent 190. The data transfer optimizer 132 configures the I/O memory manager 180 by updating the I/O address table 182. For example, the data transfer optimizer 132 can configure the I/O memory table to include and/or update one or more of the entries 1, 2, or 3. The data transfer optimizer 132 configures the fields 183E and 183F to enable selective transfer of data to the cache or to the main memory of the memory subsystem. Further, the data transfer optimizer 132 configures the I/O data transfer agent 190 to cause the I/O data transfer agent 190 to steer data towards the memory subsystem 164 (cache 162 or the main memory 166) according to the entries of the I/O address table 182.

[0053] In some embodiments, the data transfer optimizer 132 determines encodings for bits of the destination address of the data. In these embodiments, the destination address can be a physical address in the main memory when the I/O memory manager 180 is not present or is enabled in the electronic device 102. In other embodiments, the destination address can be a virtual address that is associated with a physical address in the main memory, when the I/O memory manager 180 is enabled. In some embodiments, unused upper bits of the destination address can be used for encoding information used for steering the packets. In some embodiments, one or more of the flags 183E-183F can be encoded in the bits of the destination address. For example, the data transfer optimizer 132 can determines a first flag SP can be encoded to indicate that bits of the destination address allow for selective transfer of data to the memory subsystem, a flag CW: CACHED WRITE can be encoded using 1 bit of the destination address, a PC: PARTIAL C ACHING flag can be encoded using 1 bit of the destination address, a PD: PARTI AL DROPPING flag can be encoded using lbit of the destination address, and a PS: PKT SIZE flag can be encoded using 3 bits of the destination address. Figure 1C illustrates an example implementation of an encoding scheme when the address field of the destination address is 64-bit and there are 40 bits of physical memory, in accordance with some embodiments. While the example of Figure 1C provides a particular size of address field and physical memory, this is intended to be exemplary only and other sizes and scenarios can be applicable. In this example, a subset of the fields described above with reference to Figure IB can be used. For example, bits 64-56 of a physical address of the packet can include the following encoded information: 1 bit for encoding the CACHED WRITE field, 1 bit for encoding the PARTIAL C ACHING field, lbit for encoding the PARTI AL DROPPING field, and 3 bits for encoding the packet size (PKT SIZE field). In addition, bits 55-40 can be used to encode a P ARTI AL C ACHED B ITM A SK and DROP BITMASK fields. In other embodiments, the data transfer optimizer 132 can determine an index and the SP flag to be encoded in the destination address. The index can be used by the EO data transfer agent 190 upon receipt of the data to retrieve an entry in a table (not illustrated) that includes the associated flags (e.g., the fields 183E and 183F or a subset thereof), which will be used to steer the data towards the appropriate component of the memory subsystem 164.

[0054] In some embodiments, the data transfer optimizer 132 is operative to determine the destination address for the data and update the bits of the destination address of the data to include the flags and/or index based on the information received from the multiple entities of the network device 102. In these embodiments, the destination address is added to a data descriptor with the encoded flags/index and sent to the NI 110 for the data. In these embodiments, the NI 110 receives the descriptor and is operative to send the data with the destination address already including the encoded flags and/or index for use by the I/O data transfer agent 190 for steering the data to the memory subsystem 164. In other embodiments, the data transfer optimizer 132 configures the NI 110 so that it identifies the data and then it updates the bits of the destination address to encode the flags. Thus, in these embodiments, the encoding of the flags and/or index in the bits of the destination address is performed by the NI 110 instead of the data transfer optimizer 132.

[0055] Once one or more components of the network device 102 are configured (e.g., by configuration of the NI 110, the I/O memory manager 180, and/or the I/O data transfer agent 190), the network device 102 is operative to selectively transfer data from the NI to the memory subsystem according to the embodiments described below. For example, the configuration of the components of the network device 102, causes portions of a packet received in the NI to be placed in the cache, while the rest of the packet is sent directly to the main memory or other part(s) of the memory subsystem 164.

[0056] Figure 3 A illustrates a flow diagram of exemplary operations that can be performed for selective transfer of I/O data to a memory subsystem, in accordance with some embodiments. As described above, data received at the NI 110 is added to a queue from the RX queues, e.g., Ql, for transfer to the memory subsystem 164 of the processing unit 160. The transfer of the data from the queues to the memory subsystem is performed by the memory communication manager according to the descriptor for the data (when an available descriptor exists at the NI). For example, the memory communication manager 140 issues a request to transfer data from an RX queue in which the packet is buffered towards a location in the memory subsystem (e.g., cache or main memory). The request includes a destination address that can be used to identify the location in the memory subsystem where the packet is intended to be written to. In some embodiments, the request includes data encapsulated in a packet of the communication bus (e.g., PCIe frame). The packet includes a destination address. The destination address can be a virtual address associated with a physical address in the memory subsystem 164 or a physical address in the memory subsystem 164. The packet is output on the communication bus (not illustrated). [0057] At operation 302, the I/O data transfer agent 190 receives the request for transferring the data. The request includes the data and is received through a port of the communication bus that is associated with a port identifier.

[0058] At operation 304, the I/O data transfer agent 190 determines, based on a destination address of the data how to transfer the data to the memory subsystem 164. In some embodiments, the determination of how to transfer the data is further performed based on the port identifier. The I/O data transfer agent 190 may determine whether to transfer a portion of the data (where the portion can be the entire data or strictly less than the entire data) to the cache 162, to the main memory 166, or to drop the data without transferring the data to the memory subsystem. In one embodiment, the I/O data transfer agent 190 can determine to transfer a portion of the data to the cache 162. Additionally or alternatively, the I/O data transfer agent 190 can determine to transfer a portion of the data to the main memory 166. In another embodiment, the I/O data transfer agent 190 can determine to drop the portion of the data. In a first embodiment, the determination of how to transfer the portion of the data is performed according to the I/O address table 182 as described with reference to Figure 3B. In a second embodiment, the determination of how to transfer the portion of the data is performed according to bits in the destination address of the packet as described with reference to Figure 3C.

[0059] When the I/O data transfer agent 190 determines that a portion of the data is to be transferred to the cache 162, the flow of operations moves to operation 306. When the I/O data transfer agent 190 determines that a portion of the data is to be transferred to the main memory 166, the flow of operations moves to operation 308. When the I/O data transfer agent 190 determines that a portion of the data is to be dropped without being transferred to the memory subsystem, the flow of operations moves to operation 310.

[0060] At operation 306, the I/O data transfer agent 190 transfers the portion of the data to the cache. The physical address determined for the data based on the destination address is used to identify the location in the cache in which the portion of the data is to be stored. The cache control logic can identify where in the cache the data should be loaded/stored based on the physical address. At operation 308, the I/O data transfer agent 190 transfers the portion of the data to the main memory. The portion sent to the main memory can be different from the portion that is sent to the cache. At operation 310, the I/O data transfer agent 190 drops the portion of the data. [0061] Figure 3B illustrates exemplary operations of a method that can be performed to determine how to transfer a packet or a portion of packet to the memory subsystem, in accordance with some embodiments.

[0062] At operation 322, the I/O data transfer agent 190 determines an entry of an I/O address table 182 based on the destination address of the packet and the port identifier. The I/O data transfer agent 190 determines whether an entry associated with the destination address of the packet and the port identifier exists in the I/O address table 182 stored locally (e.g., in the cache of the I/O memory manager 180). When the I/O address table 182 does not include an entry associated with the destination address and the port identifier, the I/O memory manager 180 traverses the page tables in the main memory to find the address entry. If a match is found in the main memory, the entry is retrieved and stored in the I/O address table 182. If there is no match, an exception is raised to the processing unit (e.g., CPU) and the transfer of data is blocked. [0063] At operation 324, the I/O data transfer agent 190 determines based on a first field of the entry of the I/O address table 182 that a portion of the packet is to be transferred to the cache. In some embodiments, the determination that a portion of the data is to be transferred to the cache 162 includes determining a physical address for the data and one or more flags that define if and which portion of the data is to be transferred to the cache. The I/O data transfer agent 190 determines a physical address that is associated with the destination address of the packet. The physical address indicates the location in the main memory 166 of memory subsystem 164 where the data is intended to be stored. Additionally, the I/O data transfer agent 190 determines whether the entire packet or a portion of the packet that is strictly less than the entire packet is to be stored at that location indicated by the physical address. In one embodiment, the I/O memory manager 180 determines that a portion of the packet is to be stored in cache when the CACHED WRITE field is set.

[0064] At operation 326, the I/O data transfer agent 190 identifies based on one or more fields of the entry which portion of the first packet is to be transferred to the cache. In some embodiments, a size of an entry in the I/O address table can be larger than a typical packet. For example, an entry of the I/O address table 182 can match several packets of data. In a non limiting example, a data packet can have a size of 2048 bytes and an entry in the table 182 can be of size 4096 bytes. In this example, a single entry in the table 182 can match two packets. In other example, the entry sizes in the table 182 can be 4 kB, 8kB, 16kB, 1 MB, 256 MB, etc. In some embodiments, portions of the same data received at the NI can be encapsulated in two separate packets of the communication bus (e.g., two PCIe frames) and will consequently arrive independently at the EO memory manager 180 for an entry lookup in the table 182. In these embodiments, the I/O memory manager 180 determines an offset of the packet from the beginning of the destination address of the corresponding table entry. The offset is sufficient to find the memory address for the packet based on the memory address in the table entry. When a PARTIAL CACHE BITMASK field is enabled (indicating that a portion of the packet that is strictly less than the entire packet is to be sent to the cache), the I/O memory manager 180 is further operative to determine the start and range of the packets. The DATA SZ field can be used for enabling the determination of the portion of the packet that is to be sent to the memory address. For example, based on the start of the memory address for the packet and an indication of the beginning of the packet segment, the I/O data transfer agent 190 returns the portion of the packet that needs to be written to the cache.

[0065] In one embodiment, the I/O data transfer agent 190 determines that a portion of the packet that includes the entire packet is to be stored in the main memory based on CACHED WRITE field or the PARTIAL CACHING field. For example, when a first packet arrives with destination address 0x6000, port ID Portl, and a length of 512 Bytes, the I/O memory manager 180 matches this packet with the entry 1 in the table 182. According to this entry, the address is ENABLED, and the physical address of memory is determined to be 0x220006000 (0x22004000 + (0x6000-0x4000)) for storing the data. In addition, the CACHED WRITE is set and PARTIAL CACHING is not set, the I/O data transfer agent 190 returns a bitmask of OxFF (e.g., when a cache line size is 64, the input size of 512 bytes represents cache-lines 0 through 7 bits of the bitmask, hence OxFF). This causes the entire packet to be loaded into the cache 162 corresponding to the physical address of 0x220006000 in the cache 162.

[0066] In one embodiment, the I/O data transfer agent 190 determines that a portion of the packet that is strictly less than the entire packet is to be stored in cache and remaining portions of the packets are to be stored in the main memory based on the PARTIAL CACHING field, the DATA SZ field, and PARTIAL CACHE BITMASK field. For example, when a second packet arrives from Port2, with destination address 0x8400 and packet size of 512 bytes, the second packet matches the second entry of the table 182. The physical address for storing the data in memory is determined to be 0x23000400. Since DATA SZ is 0x400 indicating that the packet size is expected to be 1024 bytes, this packet is determined to be a first segment of a larger data packet. Since PARTI AL CACHING is enabled, the

PARTIAL CACHED BITMASK is 0x3, the first 192 bytes of the packets will be sent to the cache 162, and the remaining portions of the packet (i.e., the remaining 320 bytes) are sent to the corresponding physical location in the main memory.

[0067] In another example, when a third packet arrives from Port2 with destination address 0x8600 and a packet size of 512 bytes, the third packet matches the second entry of the table 182. The physical address is determined to be 0x23000600. Since the start of the packet does not fall on DATA SZ (0x400) boundary, the I/O memory manager 182 determines that this packet includes a segment starting from the 8th cache line. Since PARTIAL CACHED BITMASK does not have any matching bits for this cache line, it results in all of this segment to be sent to the main memory. If there was a PARTIAL CACHED BITMASK that matched the packet would have been sent to SLICE 2 on CPU2 (as indicated in the entry 2).

[0068] In some embodiments, the I/O memory manager 180 is further operative to drop selected portion(s) of a packet. For example, an entry of the table 182 can be configured to transfer a first portion of the packet to the cache 162 and drop the rest of the packet. In this scenario, the PARTIAL DROPPING and DROP BITMASK fields can be used to indicate what parts of the packet need to be dropped. For example, the 3rd entry of the table 182Error! Reference source not found., shows the use of PARTI AL DROPPING field and DROP BITMASK field. When the PARTIAL DROPPING is set, it indicates that the portions of the packet identified with the DROP BITMASK can be dropped. When a packet with a length of 1024B arrives, PARTIAL C ACHING and PARTIAL CACHE BITMASK are processed and the first 4 cache lines (i.e., decided based on OxF value shown in third row of table 182) are written to the cache 162. If a packet of size larger than 256 bytes (assuming a cache line size of 64 bytes) is received, subsequent cache lines (4-15), i.e., bytes starting from 256-1024 of the packet, match the PACKET DROPPING & DROP BITMASK fields and are dropped by the I/O memory manager 180, saving both memory and cache bandwidths.

[0069] In some embodiments, flags of the communication bus header can be used to skip caching a packet or for caching a smaller portion of a packet than the one indicated in the entry in the table 182 for the packet. The NI 110 is operative to add PCIe TPH hints in the PCIe header for indicating that the packet cannot be cached or that only a small portion of the packet can be cached. For example, a TPH hint with TAG 200 might indicate that only a first portion (e.g., a first cache line) of the packet can be stored in cache and the rest of the packet is to be sent to the main memory. In another example, a TAG 201 might indicate that all of the packet is to be sent to the main memory even if the packet matches an entry in the I/O address table that indicates that a portion of the packet is to be sent to the cache.

[0070] Additionally or alternatively, in some embodiments, an entry of the table 182 can further include a DUPLICATE PKT field and a DUPLCATE PKT BASE field. The DUPLICATE PKT field indicates that the packet is to be duplicated to two different memory locations.

[0071] Figure 3C illustrates exemplary operations of another method that can be performed to determine how to transfer a packet or a portion of packet to the memory subsystem, in accordance with some embodiments. In some embodiments, the operations of Figure 3C can be performed when an I/O address table 182 is not implemented or not enabled in the network device 102. In some embodiments, the operations of Figure 3C can be performed in trusted environments, where security is not a concern. In these embodiments, unused upper bits of the memory address of a packet can be used to encode additional information that indicates whether a portion of a packet is to be cached or dropped. The I/O data transfer agent 190 is then operative to determine based on the encoded information how to route the packet to the memory subsystem 164.

[0072] At operation 332, the I/O data transfer agent 190 determines based on one or more bits in the destination address that a portion of the data is to be transferred to the cache. For example, the I/O data transfer agent 190 can determine that a bit of the destination address associated with the SP flag is set indicating that bits of the destination address allow for selective transfer of data to the memory subsystem (to cache or main memory). Alternatively, when this bit of the destination address associated with the SP flag is not set, this indicates the destination address does not allow for selective transfer of data to the memory subsystem (to cache or main memory).

[0073] At operation 334, the I/O data transfer agent 190 identifies based on one or more bits of the destination address which portion of the first packet is to be transferred to the cache. The I/O data transfer agent 190 identifies based on bits associated with the CW flag (CACHED WRITE), the bit associated with the PC flag (PARTIAL CACHING), the bit associated with the PD flag (PARTIAL DROPPING), and the bits associated with the PS flag (PKT SIZE) how to transfer the data to the memory subsystem 166. When the CW and PC flag bits are set, the I/O data transfer agent 190 determines that a portion of the data is to be sent to the cache 162. The PS flag allows the identification of which portion of the data is to be sent to the cache 162. In some embodiments, bits 64-56 of a physical address of the data can include the following encoded information: 1 bit for encoding the CACHED WRITE field, 1 bit for encoding the PARTIAL C ACHING field, lbit for encoding the PARTI AL DROPPING field, and 3 bits for encoding the packet size (PKT SIZE field). In addition, bits 55-40 can be used to encode a PARTIAL CACHED BITMASK and DROP BITMASK fields.

[0074] In other embodiments, the I/O data transfer agent 190 can determine an index and the SP flag from the destination address and look up based on the index and the SP flag, a table entry to obtain the associated flags (e.g., the fields 183E and 183F or a subset thereof), which will be used to steer the data towards the appropriate component of the memory subsystem 164. In this embodiment, the table contains an index and upon look up based on the index returns the BITMASK fields that indicates which portion of the packet is to be transferred to the cache 162. The index along with the SP flag as specified in Figure 1C are included in the unused bits of the physical address of the packet. Consequently, the addresses of the packets received from the NI 110 contain the index along with a value for the SP field.

Infrastructure:

[0075] An electronic device stores and transmits (internally and/or with other electronic devices over a network) code (which is composed of software instructions and which is sometimes referred to as computer program code or a computer program) and/or data using machine-readable media (also called computer-readable media), such as machine-readable storage media (e.g., magnetic disks, optical disks, solid state drives, read only memory (ROM), flash memory devices, phase change memory) and machine-readable transmission media (also called a carrier) (e.g., electrical, optical, radio, acoustical or other form of propagated signals - such as carrier waves, infrared signals). Thus, an electronic device (e.g., a computer) includes hardware and software, such as a set of one or more processors (e.g., wherein a processor is a microprocessor, controller, microcontroller, central processing unit, digital signal processor, application specific integrated circuit, field programmable gate array, other electronic circuitry, a combination of one or more of the preceding) coupled to one or more machine-readable storage media to store code for execution on the set of processors and/or to store data. For instance, an electronic device may include non-volatile memory containing the code since the non-volatile memory can persist code/data even when the electronic device is turned off (when power is removed), and while the electronic device is turned on that part of the code that is to be executed by the processor(s) of that electronic device is typically copied from the slower non volatile memory into volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)) of that electronic device. Typical electronic devices also include a set or one or more physical network interface(s) (NI(s)) to establish network connections (to transmit and/or receive code and/or data using propagating signals) with other electronic devices. For example, the set of physical NIs (or the set of physical NI(s) in combination with the set of processors executing code) may perform any formatting, coding, or translating to allow the electronic device to send and receive data whether over a wired and/or a wireless connection. In some embodiments, a physical NI may comprise radio circuitry capable of receiving data from other electronic devices over a wireless connection and/or sending data out to other devices via a wireless connection. This radio circuitry may include transmitted s), receiver(s), and/or transceiver(s) suitable for radiofrequency communication. The radio circuitry may convert digital data into a radio signal having the appropriate parameters (e.g., frequency, timing, channel, bandwidth, etc.). The radio signal may then be transmitted via antennas to the appropriate recipient(s). In some embodiments, the set of physical NI(s) may comprise network interface controller(s) (NICs), also known as a network interface card, network adapter, or local area network (LAN) adapter. The NIC(s) may facilitate in connecting the electronic device to other electronic devices allowing them to communicate via wire through plugging in a cable to a physical port connected to a NIC. One or more parts of an embodiment of the invention may be implemented using different combinations of software, firmware, and/or hardware.

[0076] Figure 4A illustrates connectivity between network devices (NDs) within an exemplary network, as well as three exemplary implementations of the NDs, according to some embodiments of the invention. Figure 4A shows NDs 400A-H, and their connectivity by way of lines between 400A-400B, 400B-400C, 400C-400D, 400D-400E, 400E-400F, 400F-400G, and 400A-400G, as well as between 400H and each of 400A, 400C, 400D, and 400G. These NDs are physical devices, and the connectivity between these NDs can be wireless or wired (often referred to as a link). An additional line extending from NDs 400A, 400E, and 400F illustrates that these NDs act as ingress and egress points for the network (and thus, these NDs are sometimes referred to as edge NDs; while the other NDs may be called core NDs).

[0077] Two of the exemplary ND implementations in Figure 4A are: 1) a special-purpose network device 402 that uses custom application-specific integrated-circuits (ASICs) and a special-purpose operating system (OS); and 2) a general purpose network device 404 that uses common off-the-shelf (COTS) processors and a standard OS.

[0078] The special-purpose network device 402 includes networking hardware 410 comprising a set of one or more processor(s) 412, forwarding resource(s) 414 (which typically include one or more ASICs and/or network processors), and physical network interfaces (NIs) 416 (through which network connections are made, such as those shown by the connectivity between NDs 400 A-H), as well as non-transitory machine readable storage media 418 having stored therein networking software 420. During operation, the networking software 420 may be executed by the networking hardware 410 to instantiate a set of one or more networking software instance(s) 422. Each of the networking software instance(s) 422, and that part of the networking hardware 410 that executes that network software instance (be it hardware dedicated to that networking software instance and/or time slices of hardware temporally shared by that networking software instance with others of the networking software instance(s) 422), form a separate virtual network element 430A-R. Each of the virtual network element(s) (VNEs) 430A-R includes a control communication and configuration module 432A-R (sometimes referred to as a local control module or control communication module) and forwarding table(s) 434A-R, such that a given virtual network element (e.g., 430 A) includes the control communication and configuration module (e.g., 432A), a set of one or more forwarding table(s) (e.g., 434A), and that portion of the networking hardware 410 that executes the virtual network element (e.g., 430A). [0079] The special-purpose network device 402 is often physically and/or logically considered to include: 1) a ND control plane 424 (sometimes referred to as a control plane) comprising the processor(s) 412 that execute the control communication and configuration module(s) 432A-R; and 2) a ND forwarding plane 426 (sometimes referred to as a forwarding plane, a data plane, or a media plane) comprising the forwarding resource(s) 414 that utilize the forwarding table(s) 434A-R and the physical NIs 416. By way of example, where the ND is a router (or is implementing routing functionality), the ND control plane 424 (the processor(s) 412 executing the control communication and configuration module(s) 432A-R) is typically responsible for participating in controlling how data (e.g., packets) is to be routed (e.g., the next hop for the data and the outgoing physical NI for that data) and storing that routing information in the forwarding table(s) 434A-R, and the ND forwarding plane 426 is responsible for receiving that data on the physical NIs 416 and forwarding that data out the appropriate ones of the physical NIs 416 based on the forwarding table(s) 434A-R.

[0080] Figure 4B illustrates an exemplary way to implement the special-purpose network device 402 according to some embodiments of the invention. Figure 4B shows a special-purpose network device including cards 438 (typically hot pluggable). While in some embodiments the cards 438 are of two types (one or more that operate as the ND forwarding plane 426 (sometimes called line cards), and one or more that operate to implement the ND control plane 424 (sometimes called control cards)), alternative embodiments may combine functionality onto a single card and/or include additional card types (e.g., one additional type of card is called a service card, resource card, or multi-application card). A service card can provide specialized processing (e.g., Layer 4 to Layer 7 services (e.g., firewall, Internet Protocol Security (IPsec), Secure Sockets Layer (SSL) / Transport Layer Security (TLS), Intrusion Detection System (IDS), peer-to-peer (P2P), Voice over IP (VoIP) Session Border Controller, Mobile Wireless Gateways (Gateway General Packet Radio Service (GPRS) Support Node (GGSN), Evolved Packet Core (EPC) Gateway)). By way of example, a service card may be used to terminate IPsec tunnels and execute the attendant authentication and encryption algorithms. These cards are coupled together through one or more interconnect mechanisms illustrated as backplane 436 (e.g., a first full mesh coupling the line cards and a second full mesh coupling all of the cards). [0081] Returning to Figure 4A, the general-purpose network device 404 includes hardware 440 comprising a set of one or more processor(s) 442 (which are often COTS processors) and physical NIs 446, as well as non-transitory machine-readable storage media 448 having stored therein software 450. During operation, the processor(s) 442 execute the software 450 to instantiate one or more sets of one or more applications 464A-R. While one embodiment does not implement virtualization, alternative embodiments may use different forms of virtualization. For example, in one such alternative embodiment the virtualization layer 454 represents the kernel of an operating system (or a shim executing on a base operating system) that allows for the creation of multiple instances 462A-R called software containers that may each be used to execute one (or more) of the sets of applications 464A-R; where the multiple software containers (also called virtualization engines, virtual private servers, or jails) are user spaces (typically a virtual memory space) that are separate from each other and separate from the kernel space in which the operating system is run; and where the set of applications running in a given user space, unless explicitly allowed, cannot access the memory of the other processes. In another such alternative embodiment the virtualization layer 454 represents a hypervisor (sometimes referred to as a virtual machine monitor (VMM)) or a hypervisor executing on top of a host operating system, and each of the sets of applications 464A-R is run on top of a guest operating system within an instance 462A-R called a virtual machine (which may in some cases be considered a tightly isolated form of software container) that is run on top of the hypervisor - the guest operating system and application may not know they are running on a virtual machine as opposed to running on a “bare metal” host electronic device, or through para-virtualization the operating system and/or application may be aware of the presence of virtualization for optimization purposes. In yet other alternative embodiments, one, some or all of the applications are implemented as unikernel(s), which can be generated by compiling directly with an application only a limited set of libraries (e.g., from a library operating system (LibOS) including drivers/libraries of OS services) that provide the particular OS services needed by the application. As a unikernel can be implemented to run directly on hardware 440, directly on a hypervisor (in which case the unikernel is sometimes described as running within a LibOS virtual machine), or in a software container, embodiments can be implemented fully with unikernels running directly on a hypervisor represented by virtualization layer 454, unikernels running within software containers represented by instances 462A-R, or as a combination of unikernels and the above-described techniques (e.g., unikernels and virtual machines both run directly on a hypervisor, unikernels and sets of applications that are run in different software containers).

[0082] The instantiation of the one or more sets of one or more applications 464A-R, as well as virtualization if implemented, are collectively referred to as software instance(s) 452. Each set of applications 464A-R, corresponding virtualization construct (e.g., instance 462A-R) if implemented, and that part of the hardware 440 that executes them (be it hardware dedicated to that execution and/or time slices of hardware temporally shared), forms a separate virtual network element(s) 460A-R. [0083] The virtual network element(s) 460A-R perform similar functionality to the virtual network element(s) 430A-R - e.g., similar to the control communication and configuration module(s) 432A and forwarding table(s) 434A (this virtualization of the hardware 440 is sometimes referred to as network function virtualization (NFV)). Thus, NFV may be used to consolidate many network equipment types onto industry standard high volume server hardware, physical switches, and physical storage, which could be located in Data centers, NDs, and customer premise equipment (CPE). While embodiments of the invention are illustrated with each instance 462A-R corresponding to one VNE 460A-R, alternative embodiments may implement this correspondence at a finer level granularity (e.g., line card virtual machines virtualize line cards, control card virtual machine virtualize control cards, etc.); it should be understood that the techniques described herein with reference to a correspondence of instances 462A-R to VNEs also apply to embodiments where such a finer level of granularity and/or unikernels are used.

[0084] In certain embodiments, the virtualization layer 454 includes a virtual switch that provides similar forwarding services as a physical Ethernet switch. Specifically, this virtual switch forwards traffic between instances 462A-R and the physical NI(s) 446, as well as optionally between the instances 462A-R; in addition, this virtual switch may enforce network isolation between the VNEs 460A-R that by policy are not permitted to communicate with each other (e.g., by honoring virtual local area networks (VLANs)).

[0085] The third exemplary ND implementation in Figure 4A is a hybrid network device 406, which includes both custom ASICs/ special -purpose OS and COTS processors/standard OS in a single ND or a single card within an ND. In certain embodiments of such a hybrid network device, a platform VM (i.e., a VM that that implements the functionality of the special-purpose network device 402) could provide for para-virtualization to the networking hardware present in the hybrid network device 406.

[0086] Regardless of the above exemplary implementations of an ND, when a single one of multiple VNEs implemented by an ND is being considered (e.g., only one of the VNEs is part of a given virtual network) or where only a single VNE is currently being implemented by an ND, the shortened term network element (NE) is sometimes used to refer to that VNE. Also in all of the above exemplary implementations, each of the VNEs (e.g., VNE(s) 430A-R, VNEs 460A-R, and those in the hybrid network device 406) receives data on the physical NIs (e.g., 416, 446) and forwards that data out the appropriate ones of the physical NIs (e.g., 416, 446). For example, a VNE implementing IP router functionality forwards IP packets on the basis of some of the IP header information in the IP packet; where IP header information includes source IP address, destination IP address, source port, destination port (where “source port” and “destination port” refer herein to protocol ports, as opposed to physical ports of a ND), transport protocol (e.g., user datagram protocol (UDP), Transmission Control Protocol (TCP), and differentiated services code point (DSCP) values.

[0087] Figure 4C illustrates various exemplary ways in which VNEs may be coupled according to some embodiments of the invention. Figure 4C shows VNEs 470A.1-470A.P (and optionally VNEs 470A.Q-470A.R) implemented in ND 400A and VNE 470H.1 in ND 400H. In Figure 4C, VNEs 470A.1-P are separate from each other in the sense that they can receive packets from outside ND 400A and forward packets outside of ND 400A; VNE 470A.1 is coupled with VNE 470H.1, and thus they communicate packets between their respective NDs; VNE 470A.2-470A.3 may optionally forward packets between themselves without forwarding them outside of the ND 400A; and VNE 470A.P may optionally be the first in a chain of VNEs that includes VNE 470A.Q followed by VNE 470A.R (this is sometimes referred to as dynamic service chaining, where each of the VNEs in the series of VNEs provides a different service - e.g., one or more layer 4-7 network services). While Figure 4C illustrates various exemplary relationships between the VNEs, alternative embodiments may support other relationships (e.g., more/fewer VNEs, more/fewer dynamic service chains, multiple different dynamic service chains with some common VNEs and some different VNEs).

[0088] The NDs of Figure 4A, for example, may form part of the Internet or a private network; and other electronic devices (not shown; such as end user devices including workstations, laptops, netbooks, tablets, palm tops, mobile phones, smartphones, phablets, multimedia phones, Voice Over Internet Protocol (VOIP) phones, terminals, portable media players, GPS units, wearable devices, gaming systems, set-top boxes, Internet enabled household appliances) may be coupled to the network (directly or through other networks such as access networks) to communicate over the network (e.g., the Internet or virtual private networks (VPNs) overlaid on (e.g., tunneled through) the Internet) with each other (directly or through servers) and/or access content and/or services. Such content and/or services are typically provided by one or more servers (not shown) belonging to a service/content provider or one or more end user devices (not shown) participating in a peer-to-peer (P2P) service, and may include, for example, public webpages (e.g., free content, store fronts, search services), private webpages (e.g., usemame/password accessed webpages providing email services), and/or corporate networks over VPNs. For instance, end user devices may be coupled (e.g., through customer premise equipment coupled to an access network (wired or wirelessly)) to edge NDs, which are coupled (e.g., through one or more core NDs) to other edge NDs, which are coupled to electronic devices acting as servers. However, through compute and storage virtualization, one or more of the electronic devices operating as the NDs in Figure 4A may also host one or more such servers (e.g., in the case of the general purpose network device 404, one or more of the software instances 462A-R may operate as servers; the same would be true for the hybrid network device 406; in the case of the special-purpose network device 402, one or more such servers could also be run on a virtualization layer executed by the processor(s) 412); in which case the servers are said to be co-located with the VNEs of that ND.

[0089] A virtual network is a logical abstraction of a physical network (such as that in Figure 4A) that provides network services (e.g., L2 and/or L3 services). A virtual network can be implemented as an overlay network (sometimes referred to as a network virtualization overlay) that provides network services (e.g., layer 2 (L2, data link layer) and/or layer 3 (L3, network layer) services) over an underlay network (e.g., an L3 network, such as an Internet Protocol (IP) network that uses tunnels (e.g., generic routing encapsulation (GRE), layer 2 tunneling protocol (L2TP), IPSec) to create the overlay network).

[0090] A network virtualization edge (NVE) sits at the edge of the underlay network and participates in implementing the network virtualization; the network-facing side of the NVE uses the underlay network to tunnel frames to and from other NVEs; the outward-facing side of the NVE sends and receives data to and from systems outside the network. A virtual network instance (VNI) is a specific instance of a virtual network on a NVE (e.g., a NE/VNE on an ND, a part of a NE/VNE on a ND where that NE/VNE is divided into multiple VNEs through emulation); one or more VNIs can be instantiated on an NVE (e.g., as different VNEs on an ND). A virtual access point (VAP) is a logical connection point on the NVE for connecting external systems to a virtual network; a VAP can be physical or virtual ports identified through logical interface identifiers (e.g., a VLAN ID).

[0091] Examples of network services include: 1) an Ethernet LAN emulation service (an Ethernet-based multipoint service similar to an Internet Engineering Task Force (IETF) Multiprotocol Label Switching (MPLS) or Ethernet VPN (EVPN) service) in which external systems are interconnected across the network by a LAN environment over the underlay network (e.g., an NVE provides separate L2 VNIs (virtual switching instances) for different such virtual networks, and L3 (e.g., IP/MPLS) tunneling encapsulation across the underlay network); and 2) a virtualized IP forwarding service (similar to IETF IP VPN (e.g., Border Gateway Protocol (BGP)/MPLS IPVPN) from a service definition perspective) in which external systems are interconnected across the network by an L3 environment over the underlay network (e.g., an NVE provides separate L3 VNIs (forwarding and routing instances) for different such virtual networks, and L3 (e.g., IP/MPLS) tunneling encapsulation across the underlay network)). Network services may also include quality of service capabilities (e.g., traffic classification marking, traffic conditioning and scheduling), security capabilities (e.g., filters to protect customer premises from network - originated attacks, to avoid malformed route announcements), and management capabilities (e.g., full detection and processing).

[0092] Figure 4D illustrates a network with a single network element on each of the NDs of Figure 4A, and within this straight forward approach contrasts a traditional distributed approach (commonly used by traditional routers) with a centralized approach for maintaining reachability and forwarding information (also called network control), according to some embodiments of the invention. Specifically, Figure 4D illustrates network elements (NEs) 470A-H with the same connectivity as the NDs 400A-H of Figure 4A.

[0093] Figure 4D illustrates that the distributed approach 472 distributes responsibility for generating the reachability and forwarding information across the NEs 470A-H; in other words, the process of neighbor discovery and topology discovery is distributed.

[0094] For example, where the special-purpose network device 402 is used, the control communication and configuration module(s) 432A-R of the ND control plane 424 typically include a reachability and forwarding information module to implement one or more routing protocols (e.g., an exterior gateway protocol such as Border Gateway Protocol (BGP), Interior Gateway Protocol(s) (IGP) (e.g., Open Shortest Path First (OSPF), Intermediate System to Intermediate System (IS-IS), Routing Information Protocol (RIP), Label Distribution Protocol (LDP), Resource Reservation Protocol (RSVP) (including RSVP-Traffic Engineering (TE): Extensions to RSVP for LSP Tunnels and Generalized Multi-Protocol Label Switching (GMPLS) Signaling RSVP-TE)) that communicate with other NEs to exchange routes, and then selects those routes based on one or more routing metrics. Thus, the NEs 470A-H (e.g., the processor(s) 412 executing the control communication and configuration module(s) 432A-R) perform their responsibility for participating in controlling how data (e.g., packets) is to be routed (e.g., the next hop for the data and the outgoing physical NI for that data) by distributively determining the reachability within the network and calculating their respective forwarding information. Routes and adjacencies are stored in one or more routing structures (e.g., Routing Information Base (RIB), Label Information Base (LIB), one or more adjacency structures) on the ND control plane 424. The ND control plane 424 programs the ND forwarding plane 426 with information (e.g., adjacency and route information) based on the routing structure(s). For example, the ND control plane 424 programs the adjacency and route information into one or more forwarding table(s) 434A-R (e.g., Forwarding Information Base (FIB), Label Forwarding Information Base (LFIB), and one or more adjacency structures) on the ND forwarding plane 426. For layer 2 forwarding, the ND can store one or more bridging tables that are used to forward data based on the layer 2 information in that data. While the above example uses the special-purpose network device 402, the same distributed approach 472 can be implemented on the general-purpose network device 404 and the hybrid network device 406. [0095] Figure 4D illustrates that a centralized approach 474 (also known as software defined networking (SDN)) that decouples the system that makes decisions about where traffic is sent from the underlying systems that forwards traffic to the selected destination. The illustrated centralized approach 474 has the responsibility for the generation of reachability and forwarding information in a centralized control plane 476 (sometimes referred to as a SDN control module, controller, network controller, OpenFlow controller, SDN controller, control plane node, network virtualization authority, or management control entity), and thus the process of neighbor discovery and topology discovery is centralized. The centralized control plane 476 has a south bound interface 482 with a data plane 480 (sometime referred to the infrastructure layer, network forwarding plane, or forwarding plane (which should not be confused with a ND forwarding plane)) that includes the NEs 470A-H (sometimes referred to as switches, forwarding elements, data plane elements, or nodes). The centralized control plane 476 includes a network controller 478, which includes a centralized reachability and forwarding information module 479 that determines the reachability within the network and distributes the forwarding information to the NEs 470A-H of the data plane 480 over the south bound interface 482 (which may use the OpenFlow protocol). Thus, the network intelligence is centralized in the centralized control plane 476 executing on electronic devices that are typically separate from the NDs. [0096] For example, where the special-purpose network device 402 is used in the data plane 480, each of the control communication and configuration module(s) 432A-R of the ND control plane 424 typically include a control agent that provides the VNE side of the south bound interface 482. In this case, the ND control plane 424 (the processor(s) 412 executing the control communication and configuration module(s) 432A-R) performs its responsibility for participating in controlling how data (e.g., packets) is to be routed (e.g., the next hop for the data and the outgoing physical NI for that data) through the control agent communicating with the centralized control plane 476 to receive the forwarding information (and in some cases, the reachability information) from the centralized reachability and forwarding information module 479 (it should be understood that in some embodiments of the invention, the control communication and configuration module(s) 432A-R, in addition to communicating with the centralized control plane 476, may also play some role in determining reachability and/or calculating forwarding information - albeit less so than in the case of a distributed approach; such embodiments are generally considered to fall under the centralized approach 474, but may also be considered a hybrid approach). [0097] While the above example uses the special-purpose network device 402, the same centralized approach 474 can be implemented with the general purpose network device 404 (e.g., each of the VNE 460 A-R performs its responsibility for controlling how data (e.g., packets) is to be routed (e.g., the next hop for the data and the outgoing physical NI for that data) by communicating with the centralized control plane 476 to receive the forwarding information (and in some cases, the reachability information) from the centralized reachability and forwarding information module 479; it should be understood that in some embodiments of the invention, the VNEs 460A-R, in addition to communicating with the centralized control plane 476, may also play some role in determining reachability and/or calculating forwarding information - albeit less so than in the case of a distributed approach) and the hybrid network device 406. In fact, the use of SDN techniques can enhance the NFV techniques typically used in the general purpose network device 404 or hybrid network device 406 implementations as NFV is able to support SDN by providing an infrastructure upon which the SDN software can be run, and NFV and SDN both aim to make use of commodity server hardware and physical switches.

[0098] Figure 4D also shows that the centralized control plane 476 has a north bound interface 484 to an application layer 486, in which resides application(s) 488. The centralized control plane 476 has the ability to form virtual networks 492 (sometimes referred to as a logical forwarding plane, network services, or overlay networks (with the NEs 470A-H of the data plane 480 being the underlay network)) for the application(s) 488. Thus, the centralized control plane 476 maintains a global view of all NDs and configured NEs/VNEs, and it maps the virtual networks to the underlying NDs efficiently (including maintaining these mappings as the physical network changes either through hardware (ND, link, or ND component) failure, addition, or removal).

[0099] While Figure 4D shows the distributed approach 472 separate from the centralized approach 474, the effort of network control may be distributed differently or the two combined in certain embodiments of the invention. For example: 1) embodiments may generally use the centralized approach (SDN) 474, but have certain functions delegated to the NEs (e.g., the distributed approach may be used to implement one or more of fault monitoring, performance monitoring, protection switching, and primitives for neighbor and/or topology discovery); or 2) embodiments of the invention may perform neighbor discovery and topology discovery via both the centralized control plane and the distributed protocols, and the results compared to raise exceptions where they do not agree. Such embodiments are generally considered to fall under the centralized approach 474, but may also be considered a hybrid approach. [00100] While Figure 4D illustrates the simple case where each of the NDs 400A-H implements a single NE 470A-H, it should be understood that the network control approaches described with reference to Figure 4D also work for networks where one or more of the NDs 400A-H implement multiple VNEs (e.g., VNEs 430A-R, VNEs 460A-R, those in the hybrid network device 406). Alternatively or in addition, the network controller 478 may also emulate the implementation of multiple VNEs in a single ND. Specifically, instead of (or in addition to) implementing multiple VNEs in a single ND, the network controller 478 may present the implementation of a VNE/NE in a single ND as multiple VNEs in the virtual networks 492 (all in the same one of the virtual network(s) 492, each in different ones of the virtual network(s) 492, or some combination). For example, the network controller 478 may cause an ND to implement a single VNE (a NE) in the underlay network, and then logically divide up the resources of that NE within the centralized control plane 476 to present different VNEs in the virtual network(s) 492 (where these different VNEs in the overlay networks are sharing the resources of the single VNE/NE implementation on the ND in the underlay network).

[00101] On the other hand, Figures 4E and 4F respectively illustrate exemplary abstractions of NEs and VNEs that the network controller 478 may present as part of different ones of the virtual networks 492. Figure 4E illustrates the simple case of where each of the NDs 400A-H implements a single NE 470A-H (see Figure 4D), but the centralized control plane 476 has abstracted multiple of the NEs in different NDs (the NEs 470A-C and G-H) into (to represent) a single NE 4701 in one of the virtual network(s) 492 of Figure 4D, according to some embodiments of the invention. Figure 4E shows that in this virtual network, the NE 4701 is coupled to NE 470D and 470F, which are both still coupled to NE 470E.

[00102] Figure 4F illustrates a case where multiple VNEs (VNE 470A.1 and VNE 470H.1) are implemented on different NDs (ND 400A and ND 400H) and are coupled to each other, and where the centralized control plane 476 has abstracted these multiple VNEs such that they appear as a single VNE 470T within one of the virtual networks 492 of Figure 4D, according to some embodiments of the invention. Thus, the abstraction of a NE or VNE can span multiple NDs.

[00103] While some embodiments of the invention implement the centralized control plane 476 as a single entity (e.g., a single instance of software running on a single electronic device), alternative embodiments may spread the functionality across multiple entities for redundancy and/or scalability purposes (e.g., multiple instances of software running on different electronic devices).

[00104] Similar to the network device implementations, the electronic device(s) running the centralized control plane 476, and thus the network controller 478 including the centralized reachability and forwarding information module 479, may be implemented a variety of ways (e.g., a special purpose device, a general-purpose (e.g., COTS) device, or hybrid device). These electronic device(s) would similarly include processor(s), a set or one or more physical NIs, and a non-transitory machine-readable storage medium having stored thereon the centralized control plane software. For instance, Figure 5 illustrates, a general purpose control plane device 504 including hardware 540 comprising a set of one or more processor(s) 542 (which are often COTS processors) and physical NIs 546, as well as non-transitory machine readable storage media 548 having stored therein centralized control plane (CCP) software 550.

[00105] In embodiments that use compute virtualization, the processor(s) 542 typically execute software to instantiate a virtualization layer 554 (e.g., in one embodiment the virtualization layer 554 represents the kernel of an operating system (or a shim executing on a base operating system) that allows for the creation of multiple instances 562A-R called software containers (representing separate user spaces and also called virtualization engines, virtual private servers, or jails) that may each be used to execute a set of one or more applications; in another embodiment the virtualization layer 554 represents a hypervisor (sometimes referred to as a virtual machine monitor (VMM)) or a hypervisor executing on top of a host operating system, and an application is run on top of a guest operating system within an instance 562A-R called a virtual machine (which in some cases may be considered a tightly isolated form of software container) that is run by the hypervisor ; in another embodiment, an application is implemented as a unikemel, which can be generated by compiling directly with an application only a limited set of libraries (e.g., from a library operating system (LibOS) including drivers/libraries of OS services) that provide the particular OS services needed by the application, and the unikemel can ran directly on hardware 540, directly on a hypervisor represented by virtualization layer 554 (in which case the unikemel is sometimes described as running within a LibOS virtual machine), or in a software container represented by one of instances 562A-R). Again, in embodiments where compute virtualization is used, during operation an instance of the CCP software 550 (illustrated as CCP instance 576A) is executed (e.g., within the instance 562A) on the virtualization layer 554. In embodiments where compute virtualization is not used, the CCP instance 576A is executed, as a unikemel or on top of a host operating system, on the “bare metal” general purpose control plane device 504. The instantiation of the CCP instance 576A, as well as the virtualization layer 554 and instances 562A-R if implemented, are collectively referred to as software instance(s) 552.

[00106] In some embodiments, the CCP instance 576A includes a network controller instance 578. The network controller instance 578 includes a centralized reachability and forwarding information module instance 579 (which is a middleware layer providing the context of the network controller 478 to the operating system and communicating with the various NEs), and an CCP application layer 580 (sometimes referred to as an application layer) over the middleware layer (providing the intelligence required for various network operations such as protocols, network situational awareness, and user - interfaces). At a more abstract level, this CCP application layer 580 within the centralized control plane 476 works with virtual network view(s) (logical view(s) of the network) and the middleware layer provides the conversion from the virtual networks to the physical view.

[00107] The centralized control plane 476 transmits relevant messages to the data plane 480 based on CCP application layer 580 calculations and middleware layer mapping for each flow. A flow may be defined as a set of packets whose headers match a given pattern of bits; in this sense, traditional IP forwarding is also flow-based forwarding where the flows are defined by the destination IP address for example; however, in other implementations, the given pattern of bits used for a flow definition may include more fields (e.g., 10 or more) in the packet headers. Different NDs/NEs/VNEs of the data plane 480 may receive different messages, and thus different forwarding information. The data plane 480 processes these messages and programs the appropriate flow information and corresponding actions in the forwarding tables (sometime referred to as flow tables) of the appropriate NE/VNEs, and then the NEs/VNEs map incoming packets to flows represented in the forwarding tables and forward packets based on the matches in the forwarding tables.

[00108] Standards such as OpenFlow define the protocols used for the messages, as well as a model for processing the packets. The model for processing packets includes header parsing, packet classification, and making forwarding decisions. Header parsing describes how to interpret a packet based upon a well-known set of protocols. Some protocol fields are used to build a match structure (or key) that will be used in packet classification (e.g., a first key field could be a source media access control (MAC) address, and a second key field could be a destination MAC address).

[00109] Packet classification involves executing a lookup in memory to classify the packet by determining which entry (also referred to as a forwarding table entry or flow entry) in the forwarding tables best matches the packet based upon the match structure, or key, of the forwarding table entries. It is possible that many flows represented in the forwarding table entries can correspond/match to a packet; in this case the system is typically configured to determine one forwarding table entry from the many according to a defined scheme (e.g., selecting a first forwarding table entry that is matched). Forwarding table entries include both a specific set of match criteria (a set of values or wildcards, or an indication of what portions of a packet should be compared to a particular value/values/wildcards, as defined by the matching capabilities - for specific fields in the packet header, or for some other packet content), and a set of one or more actions for the data plane to take on receiving a matching packet. For example, an action may be to push a header onto the packet, for the packet using a particular port, flood the packet, or simply drop the packet. Thus, a forwarding table entry for IPv4/IPv6 packets with a particular transmission control protocol (TCP) destination port could contain an action specifying that these packets should be dropped.

[00110] Making forwarding decisions and performing actions occurs, based upon the forwarding table entry identified during packet classification, by executing the set of actions identified in the matched forwarding table entry on the packet.

[00111] However, when an unknown packet (for example, a “missed packet” or a “match- miss” as used in OpenFlow parlance) arrives at the data plane 480, the packet (or a subset of the packet header and content) is typically forwarded to the centralized control plane 476. The centralized control plane 476 will then program forwarding table entries into the data plane 480 to accommodate packets belonging to the flow of the unknown packet. Once a specific forwarding table entry has been programmed into the data plane 480 by the centralized control plane 476, the next packet with matching credentials will match that forwarding table entry and take the set of actions associated with that matched entry.

[00112] A network interface (NI) may be physical or virtual; and in the context of IP, an interface address is an IP address assigned to a NI, be it a physical NI or virtual NI. A virtual NI may be associated with a physical NI, with another virtual interface, or stand on its own (e.g., a loopback interface, a point-to-point protocol interface). A NI (physical or virtual) may be numbered (a NI with an IP address) or unnumbered (a NI without an IP address). A loopback interface (and its loopback address) is a specific type of virtual NI (and IP address) of a NE/VNE (physical or virtual) often used for management purposes; where such an IP address is referred to as the nodal loopback address. The IP address(es) assigned to the NI(s) of a ND are referred to as IP addresses of that ND; at a more granular level, the IP address(es) assigned to NI(s) assigned to a NE/VNE implemented on a ND can be referred to as IP addresses of that NE/VNE.

[00113] While the flow diagrams in the figures show a particular order of operations performed by certain embodiments of the invention, it should be understood that such order is exemplary (e.g., alternative embodiments may perform the operations in a different order, combine certain operations, overlap certain operations, etc.).

[00114] While the invention has been described in terms of several embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described, can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting.

Claims

CLAIMS What is claimed is:

1. A method in an electronic device (102) for enabling selective transfer of data to a memory subsystem (164) of a processing unit (160), the method comprising: receiving (202) information from one or more applications (178A-N), a network interface (110), the memory subsystem (164), and an operating system; determining (204), based on the information, one or more configuration parameters for data associated with a destination address in a main memory (166) of the electronic device (102), wherein the data is intended to be transferred by the network interface (110) to a location of the destination address in the main memory (166); and configuring (206) the electronic device (102) with the configuration parameters, wherein the configuring causes a portion of the data associated with the destination address to be transferred to a cache (162) for the processing unit (160) instead of the main memory (166).

2. The method of claim 1, wherein the configuring (206) the electronic device (102) with the configuration parameters includes: updating, based on the configuration parameters, an Input/Output (I/O) address table 182 of an I/O memory manager 180 to include an entry for transferring the portion of the data to the cache (162).

3. The method of claim 1, wherein the configuring (206) the electronic device (102) with the configuration parameters includes: determining one or more encodings for bits of the destination address, wherein the bits are to be used for determining that the portion of the data is to be transferred to the cache (162) instead of the main memory (166).

4. The method of claim 1, wherein the information includes one or more of an identifier of the data, a priority level for the data, a physical address of a buffer in the main memory (166).

5. The method of claim 1, wherein the portion of the data is strictly less than an all the data.

6. A machine-readable medium comprising computer program code which when executed by the electronic device (102) carries out the method steps of any of claims 1-5.

7. An electronic device (102) comprising: a non-transitory machine -readable storage medium that provides instructions that, if executed by a processor, will cause the electronic device (102) to perform operations comprising, receiving (202) information from one or more applications (178A-N), a network interface (110), a memory subsystem (164), and an operating system, determining (204), based on the information, one or more configuration parameters for data associated with a destination address in a main memory (166) of the electronic device (102), wherein the data is intended to be transferred by the network interface (110) to a location of the destination address in the main memory (166), and configuring (206) the electronic device (102) with the configuration parameters, wherein the configuring causes a portion of the data associated with the destination address to be transferred to a cache (162) for a processing unit (160) instead of the main memory (166).

8. The electronic device of claim 7, wherein the configuring (206) the electronic device (102) with the configuration parameters includes: updating, based on the configuration parameters, an Input/Output (I/O) address table (182) of an I/O memory manager (180) to include an entry for transferring the portion of the data to the cache.

9. The electronic device of claim 7, wherein the configuring (206) the electronic device (102) with the configuration parameters includes: determining one or more encodings for bits of the destination address, wherein the bits are to be used for determining that the portion of the data is to be transferred to the cache (162) instead of the main memory (166).

10. The electronic device of claim 7, wherein the information includes one or more of an identifier of the data, a priority level for the data, a physical address of a buffer in the main memory (166).

11. The electronic device of claim 7, wherein the portion of the data is strictly less than an all the data.

12. A method comprising: receiving (302) a first request to transfer first data between a network interface (110) and a memory subsystem (164) of a processing unit (160) that are coupled through a communication bus, wherein the memory subsystem (164) includes a cache (162) for the processing unit (160); determining (304), based on a first destination address of the first data, that a first portion of the first data is to be transferred to the cache (162); and transferring (306) the first portion of the first data to the cache (162).

13. The method of claim 12, further comprising: determining (304) that another portion of the first data is to be transferred to a main memory (166) of the memory subsystem (164); and transferring (308) the other portion of the first data to the main memory (166).

14. The method of any of claims 12-13 further comprising: receiving (302) a second request to transfer second data between the network interface (110) and the memory subsystem (164); determining (304), based on a second destination address in the second request, that a second portion of the second data is to be dropped; and dropping (312) the second portion of the second data without transferring the second portion to the memory subsystem (164).

15. The method of any of claims 12-14, wherein the determining (304), based on the first destination address of the first data, that the first portion of the first data is to be transferred to the cache (162) includes: determining one or more cache segments to be used for the first portion when the processing unit (160) has Non-Uniform Caching Architecture (NUCA).

16. The method of any of claims 12-15, wherein the determining (304), based on the first destination address of the first data, that the first portion of the first data is to be transferred to the cache (162) includes: determining (322) an entry of an input/output (I/O) address table based on the first destination address of the first data and a first port identifier that identifies a first port of the communication bus through which the first data is received; determining (324) based on a first field of the entry of the I/O address table that a portion of the first data is to be transferred to the cache (162); and identifying (326) based on one or more fields of the entry which portion of the first data is to be transferred to the cache (162).

17. The method of any of claims 12-14, wherein the first destination address is a physical address indicating a location in the main memory (166) where the first data is intended to be transferred.

18. The method of claim 17, wherein the determining (304), based on the first destination address of the first data, that the first portion of the first data is to be transferred to the cache includes: determining (332) based on one or more bits in the first destination address that a portion of the first data is to be transferred to the cache (162); and identifying (334) based on the one or more bits of the first destination address which portion of the first data is to be transferred to the cache (162).

19. A machine-readable medium comprising computer program code which when executed by a computer carries out the method steps of any of claims 12-18.

20. An electronic device (102) comprising: a non-transitory machine -readable storage medium that provides instructions that, if executed by a processor, will cause the electronic device (102) to perform operations comprising, receiving (302) a first request to transfer first data between a network interface (110) and a memory subsystem (164) of a processing unit (160) that are coupled through a communication bus, wherein the memory subsystem (164) includes a cache (162) for the processing unit (160); determining (304), based on a first destination address of the first data, that a first portion of the first data is to be transferred to the cache (162); and transferring (306) the first portion of the first data to the cache (162).

21. The electronic device (102) of claim 20, wherein the operations further comprise: determining (304) that another portion of the first data is to be transferred to a main memory (166) of the memory subsystem (164); and transferring (308) the other portion of the first data to the main memory (166).

22. The electronic device (102) of any of claims 20-21, wherein the operations further comprise: receiving (302) a second request to transfer second data between the network interface (110) and the memory subsystem (164); determining (304), based on a second destination address in the second request, that a second portion of the second data is to be dropped; and dropping (312) the second portion of the second data without transferring the second portion to the memory subsystem (164).

23. The electronic device (102) of any of claims 20-22, wherein the determining (304), based on the first destination address of the first data, that the first portion of the first data is to be transferred to the cache (162) includes: determining one or more cache segments to be used for the first portion when the processing unit (160) has Non-Uniform Caching Architecture (NUCA).

24. The electronic device (102) of any of claims 20-23, wherein the determining (304), based on the first destination address of the first data, that the first portion of the first data is to be transferred to the cache (162) includes: determining (322) an entry of an input/output (I/O) address table based on the first destination address of the first data and a first port identifier that identifies a first port of the communication bus through which the first data is received; determining (324) based on a first field of the entry of the I/O address table that a portion of the first data is to be transferred to the cache (162); and identifying (326) based on one or more fields of the entry which portion of the first data is to be transferred to the cache (162).

25. The electronic device (102) of any of claims 20-22, wherein the first destination address is a physical address indicating a location in the main memory (166) where the first data is intended to be transferred.

26. The electronic device (102) of claim 25, wherein the determining (304), based on the first destination address of the first data, that the first portion of the first data is to be transferred to the cache includes: determining (332) based on one or more bits in the first destination address that a portion of the first data is to be transferred to the cache (162); and identifying (334) based on the one or more bits of the first destination address which portion of the first data is to be transferred to the cache (162).