WO2022263277A1 - Single function to perform multiple operations with distinct operation parameter validation - Google Patents

Single function to perform multiple operations with distinct operation parameter validation Download PDF

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Publication number
WO2022263277A1
WO2022263277A1 PCT/EP2022/065660 EP2022065660W WO2022263277A1 WO 2022263277 A1 WO2022263277 A1 WO 2022263277A1 EP 2022065660 W EP2022065660 W EP 2022065660W WO 2022263277 A1 WO2022263277 A1 WO 2022263277A1
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WIPO (PCT)
Prior art keywords
function
value
dimension
tensor
values
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Ceased
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PCT/EP2022/065660
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English (en)
French (fr)
Inventor
Cedric Lichtenau
Jonathan Bradbury
Laith ALBARAKAT
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IBM Deutschland GmbH
International Business Machines Corp
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IBM Deutschland GmbH
International Business Machines Corp
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Application filed by IBM Deutschland GmbH, International Business Machines Corp filed Critical IBM Deutschland GmbH
Priority to KR1020237039307A priority Critical patent/KR102808233B1/ko
Priority to AU2022293937A priority patent/AU2022293937B2/en
Priority to CN202280038619.4A priority patent/CN117396846A/zh
Priority to JP2023564573A priority patent/JP7812601B2/ja
Priority to EP22735336.4A priority patent/EP4356241A1/en
Priority to CA3215152A priority patent/CA3215152A1/en
Publication of WO2022263277A1 publication Critical patent/WO2022263277A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30185—Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/18—Complex mathematical operations for evaluating statistical data, e.g. average values, frequency distributions, probability functions, regression analysis
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Definitions

  • One or more aspects relate, in general, to facilitating processing within a computing environment, and in particular, to improving such processing.
  • accelerators In order to enhance processing in computing environments that are data and/or computational-intensive, co-processors are utilized, such as artificial intelligence accelerators (also referred to as neural network processors or neural network accelerators). Such accelerators provide a great deal of compute power used in performing, for instance, involved computations, such as computations on matrices or tensors.
  • Tensor computations are used in complex processing, including deep learning, which is a subset of machine learning.
  • Deep learning or machine learning an aspect of artificial intelligence, is used in various technologies, including but not limited to, engineering, manufacturing, medical technologies, automotive technologies, computer processing, etc.
  • Deep learning uses various operations that operate on tensor data. Each of the operations is independently implemented, increasing development and verification efforts.
  • the computer program product includes one or more computer readable storage media and program instructions collectively stored on the one or more computer readable storage media to perform a method.
  • the method includes obtaining an indication of a function to be executed, in which the function is one function of an instruction and configured to perform multiple operations.
  • a determination is made of an operation of the multiple operations to be performed, and a set of function-specific parameters is validated using a set of values and a corresponding set of relationships.
  • the set of values and corresponding set of relationships are based on the operation to be performed. As examples, one set of values and corresponding set of relationships are to be used for the operation to be performed, and another set of values and corresponding set of relationships are to be used for another operation of the multiple operations.
  • the determining the operation to be performed includes checking one or more function-specific parameters against at least one specific value. Based on the one or more function-specific parameters having a first select relationship with respect to the at least one specific value, the operation is one operation, and based on the one or more function-specific parameters having a second select relationship with respect to the at least one specific value, the operation is another operation.
  • the function includes an average pool function
  • the one or more function-specific parameters include one or more stride values, in which a stride value is an amount that a sliding window moves over an input tensor when computing one or more adjacent output tensor elements, the at least one specific value includes zero, the first select relationship includes equal and the operation is a mean-reduce operation based on the one or more stride values being equal to zero.
  • the second select relationship includes greater than and the operation is a pooling operation based on the one or more stride values being greater than zero.
  • the set of function-specific parameters includes one or more select-dimension window size values.
  • a select-dimension window size value specifies a number of elements in the select dimension that a sliding window contains, and the sliding window is configured to move over an input tensor of the function to produce an output tensor.
  • the function includes an average pool function
  • the operation includes a mean-reduce operation
  • the set of values and corresponding set of relationships to be used to validate the set of function-specific parameters includes: one value of one dimension of a select input tensor and corresponding relationship of equal, another value of another dimension of the select input tensor and corresponding relationship of equal, and a select value and corresponding relationship of less than or equal.
  • the validating includes, for instance, checking a value of a dimension-2 -window size is equal to a value of a dimension-2 of a first input tensor, a value of a dimension-3- window size is equal to a value of a dimension-3 of the first input tensor, the value of the dimension-2 -window size is less than or equal to the select value, and the value of the dimension-3 -window size is less than or equal to the select value.
  • the function includes an average pool function
  • the operation includes a pooling operation
  • the set of values and corresponding set of relationships to be used to validate the set of function-specific parameters includes: one value of one dimension of a select input tensor and corresponding relationship of less than or equal, and another value of another dimension of the select input tensor and corresponding relationship of less than or equal.
  • the validating includes, for instance, checking that a value of a dimension-2 - window size is less than or equal to a value of a dimension-2 of a first input tensor and a value of a dimension-3 -window size is less than or equal to a value of a dimension-3 of the first input tensor.
  • the determining the operation is based on at least one sliding window stride value of an input tensor, and the set of function-specific parameters includes at least one sliding window dimension of an input tensor.
  • FIG. 1 A depicts one example of a computing environment to incorporate and use one or more aspects of the present invention
  • FIG. IB depicts further details of a processor of FIG. 1 A, in accordance with one or more aspects of the present invention
  • FIG. 2 depicts one example of processing associated with executing a single function of an instruction that is configured to perform multiple operations but able to check distinct parameter conditions for the multiple operations, in accordance with one or more aspects of the present invention
  • FIG. 3 A depicts one example of a format of a Neural Network Processing Assist instruction, in accordance with one or more aspects of the present invention
  • FIG. 3B depicts one example of a general register used by the Neural Network Processing Assist instruction, in accordance with one or more aspects of the present invention
  • FIG. 3C depicts examples of function codes supported by the Neural Network Processing Assist instruction, in accordance with one or more aspects of the present invention
  • FIG. 3D depicts one example of another general register used by the Neural Network Processing Assist instruction, in accordance with one or more aspects of the present invention
  • FIG. 3E depicts one example of a parameter block used by a query function of the Neural Network Processing Assist instruction, in accordance with one or more aspects of the present invention
  • FIG. 3F depicts one example of a parameter block used by one or more non query functions of the Neural Network Processing Assist instruction, in accordance with one or more aspects of the present invention
  • FIG. 3G depicts one example of a tensor descriptor used by the Neural Network Processing Assist instruction, in accordance with one or more aspects of the present invention
  • FIG. 4 depicts one example of a format of a Neural Network Processing (NNP)-data-type-l data type, in accordance with one or more aspects of the present invention
  • FIGS. 5A-5C depict examples of an input data layout used by the Neural Network Processing Assist instruction, in accordance with one or more aspects of the present invention
  • FIGS. 6A-6C depict example output corresponding to the input data layout of FIGS. 5A-5C, in accordance with one or more aspects of the present invention
  • FIGS. 7A-7C depict one example of facilitating processing within a computing environment, in accordance with one or more aspects of the present invention.
  • FIG. 8A depicts another example of a computing environment to incorporate and use one or more aspects of the present invention.
  • FIG. 8B depicts one example of further details of a memory of FIG. 8 A, in accordance with one or more aspects of the present invention
  • FIG. 8C depicts another example of further details of a memory of FIG. 8 A, in accordance with one or more aspects of the present invention
  • FIG. 9A depicts yet another example of a computing environment to incorporate and use one or more aspects of the present invention.
  • FIG. 9B depicts further details of the memory of FIG. 9A, in accordance with one or more aspects of the present invention.
  • FIG. 10 depicts one embodiment of a cloud computing environment, in accordance with one or more aspects of the present invention.
  • FIG. 11 depicts one example of abstraction model layers, in accordance with one or more aspects of the present invention.
  • a capability is provided to facilitate processing within a computing environment.
  • an instruction is provided that is configured to implement multiple functions, and at least one function is configured to perform multiple operations with distinct parameter validation per operation.
  • a function configured to implement multiple operations is an average pooling function and the multiple operations include a mean-reduce operation and a pooling operation used, for instance, in deep learning.
  • the average pooling function performs different operations but is algorithmically reduced to a common algorithmic function using the same input tensors and function-specific-parameters but with different relative constraints.
  • the function configured to perform the multiple operations is initiated by an instruction.
  • the instruction is a Neural Network Processing Assist instruction, which is a single instruction (e.g., a single architected hardware machine instruction at the hardware/software interface) configured to perform multiple functions.
  • Each of the functions is configured as part of the single instruction (e.g., the single architected instruction), reducing use of system resources and complexity, and improving system performance.
  • At least one of the functions is configured to implement multiple operations (e.g., mean-reduce and pooling) based on input data, such as values of function-specific- parameters (e.g., function-specific-parameters 2 and 3, described below) provided by the instruction.
  • multiple operations e.g., mean-reduce and pooling
  • input data such as values of function-specific- parameters (e.g., function-specific-parameters 2 and 3, described below) provided by the instruction.
  • the instruction may be part of a general-purpose processor instruction set architecture (ISA), which is dispatched by a program on a processor, such as a general- purpose processor. It may be executed by the general-purpose processor and/or one or more functions of the instruction may be executed by a special-purpose processor, such as a co processor configured for certain functions, that is coupled to or part of the general-purpose processor. Other variations are also possible.
  • ISA general-purpose processor instruction set architecture
  • FIG. 1 A One embodiment of a computing environment to incorporate and use one or more aspects of the present invention is described with reference to FIG. 1 A.
  • the computing environment is based on the z/ Architecture ® instruction set architecture, offered by International Business Machines Corporation, Armonk, New York.
  • One embodiment of the z/ Architecture instruction set architecture is described in a publication entitled, “z/ Architecture Principles of Operation,” IBM Publication No. SA22- 7832-12, Thirteenth Edition, September 2019, which is hereby incorporated herein by reference in its entirety.
  • z/ Architecture instruction set architecture is only one example architecture; other architectures and/or other types of computing environments of International Business Machines Corporation and/or of other entities may include and/or use one or more aspects of the present invention
  • z/ Architecture and IBM are trademarks or registered trademarks of International Business Machines Corporation in at least one jurisdiction.
  • a computing environment 100 includes, for instance, a computer system 102 shown, e.g., in the form of a general-purpose computing device.
  • Computer system 102 may include, but is not limited to, one or more general-purpose processors or processing units 104 (e.g., central processing units (CPUs)), at least one special-purpose processor, such as a neural network processor 105, a memory 106 (a.k.a., system memory, main memory, main storage, central storage or storage, as examples), and one or more input/output (I/O) interfaces 108, coupled to one another via one or more buses and/or other connections.
  • processors 104, 105 and memory 106 are coupled to I/O interfaces 108 via one or more buses 110
  • processors 104, 105 are coupled to one another via one or more buses 111.
  • Bus 111 is, for instance, a memory or cache coherence bus
  • bus 110 represents, e.g., one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures.
  • bus architectures include the Industry Standard Architecture (ISA), the Micro Channel Architecture (MCA), the Enhanced ISA (EISA), the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnect (PCI).
  • one or more special-purpose processors may be separate from but coupled to one or more general-purpose processors and/or may be embedded within one or more general-purpose processors. Many variations are possible.
  • Memory 106 may include, for instance, a cache 112, such as a shared cache, which may be coupled to local caches 114 of processors 104 and/or to neural network processor 105, via, e.g., one or more buses 111. Further, memory 106 may include one or more programs or applications 116 and at least one operating system 118.
  • An example operating system includes a z/OS ® operating system, offered by International Business Machines Corporation, Armonk, New York. z/OS is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction. Other operating systems offered by International Business Machines Corporation and/or other entities may also be used.
  • Memory 106 may also include one or more computer readable program instructions 120, which may be configured to carry out functions of embodiments of aspects of the invention.
  • memory 106 includes processor firmware 122.
  • Processor firmware includes, e.g., the microcode or millicode of a processor. It includes, for instance, the hardware-level instructions and/or data structures used in implementation of higher level machine code. In one embodiment, it includes, for instance, proprietary code that is typically delivered as microcode or millicode that includes trusted software, microcode or millicode specific to the underlying hardware and controls operating system access to the system hardware.
  • Computer system 102 may communicate via, e.g., I/O interfaces 108 with one or more external devices 130, such as a user terminal, a tape drive, a pointing device, a display, and one or more data storage devices 134, etc.
  • a data storage device 134 may store one or more programs 136, one or more computer readable program instructions 138, and/or data, etc.
  • the computer readable program instructions may be configured to carry out functions of embodiments of aspects of the invention.
  • Computer system 102 may also communicate via, e.g., I/O interfaces 108 with network interface 132, which enables computer system 102 to communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), and/or a public network (e.g., the Internet), providing communication with other computing devices or systems.
  • networks such as a local area network (LAN), a general wide area network (WAN), and/or a public network (e.g., the Internet), providing communication with other computing devices or systems.
  • LAN local area network
  • WAN wide area network
  • public network e.g., the Internet
  • Computer system 102 may include and/or be coupled to removable/non removable, volatile/non-volatile computer system storage media.
  • it may include and/or be coupled to a non-removable, non-volatile magnetic media (typically called a "hard drive"), a magnetic disk drive for reading from and writing to a removable, non volatile magnetic disk (e.g., a "floppy disk"), and/or an optical disk drive for reading from or writing to a removable, non-volatile optical disk, such as a CD-ROM, DVD-ROM or other optical media.
  • a non-removable, non-volatile magnetic media typically called a "hard drive”
  • a magnetic disk drive for reading from and writing to a removable, non volatile magnetic disk (e.g., a "floppy disk”
  • an optical disk drive for reading from or writing to a removable, non-volatile optical disk, such as a CD-ROM, DVD-ROM or other optical media.
  • other hardware and/or software components could be used in
  • Computer system 102 may be operational with numerous other general-purpose or special-purpose computing system environments or configurations. Examples of well- known computing systems, environments, and/or configurations that may be suitable for use with computer system 102 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices, and the like.
  • a processor e.g., processor 104 and/or processor 105) includes a plurality of functional components (or a subset thereof) used to execute instructions. As depicted in FIG.
  • these functional components include, for instance, an instruction fetch component 150 to fetch instructions to be executed; an instruction decode unit 152 to decode the fetched instructions and to obtain operands of the decoded instructions; one or more instruction execute components 154 to execute the decoded instructions; a memory access component 156 to access memory for instruction execution, if necessary; and a write back component 158 to provide the results of the executed instructions.
  • One or more of the components may access and/or use one or more registers 160 in instruction processing.
  • one or more of the components may, in accordance with one or more aspects of the present invention, include at least a portion of or have access to one or more other components used in performing multiple operations with distinct parameter checking based on executing a single function, and/or in performing neural network processing assist processing of, e.g., a Neural Network Processing Assist instruction (or other processing that may use one or more aspects of the present invention), as described herein.
  • the one or more other components may include, for instance, a single function, multiple operations - distinct parameter validation component 170 and/or a neural network processing assist component 172 (and/or one or more other components).
  • an instruction is executed which is able to perform multiple functions, and at least one function implements multiple operations with distinct parameter validation.
  • An example of this processing is further described with reference to FIG. 2.
  • an instruction such as a Neural Network Processing Assist (NNPA) instruction (or another instruction) is initiated 200 on a processor, such as general-purpose processor 104.
  • a determination is made as to the function to be performed. This is determined, for instance, by checking the function code of the instruction. If the function to be performed is not a select function code, such as, for instance, a function code specifying an average pool function (e.g., NNPA AVGPOOL2D), then other processing is performed 204.
  • NNPA Neural Network Processing Assist
  • the function code specifies the select function code, e.g., the function code specifying the average pool function
  • processing continues, as described herein.
  • the processing is performed by the general- purpose processor initiating the instruction.
  • the processing may be performed by a special-purpose processor, such as a neural network accelerator (e.g., neural network accelerator 105) or by another general-purpose processor, special- purpose processor or other processor.
  • a neural network accelerator e.g., neural network accelerator 105
  • another general-purpose processor, special- purpose processor or other processor Other variations are also possible.
  • an input tensor e.g., input tensor 1
  • a window is, for instance, a select portion of an input tensor having a defined size.
  • the windows of the input are selected by moving a 2D sliding window over, e.g., dimensions 2 and 3 of the input tensor.
  • a summary of the window is an element in the output tensor.
  • the sliding window dimensions are described by, for instance, function- specific-parameters provided by the instruction, e.g., function-specific-parameter 4 and function-specific-parameter 5, examples of which are described herein.
  • the determination of the operation to be performed is made by checking select function-specific-parameters that are provided as an input to the instruction (e.g., in a parameter block used with the instruction).
  • the select function-specific- parameters are function-specific-parameter 2 (a.k.a., fn.sp2) and function-specific-parameter 3 (a.k.a., fn.sp3), each of which specifies, for instance, a sliding window stride.
  • the sliding window stride or stride is an amount that the sliding window moves over input tensor 1 when computing adjacent output tensor elements.
  • a padding type is equal to a select padding type, such a Valid. For instance, a check is made of a value of a particular function-specific-parameter, e.g., function-specific-parameter 1 (a.k.a., fn.spl), provided as input to the function.
  • a particular function-specific-parameter e.g., function-specific-parameter 1 (a.k.a., fn.spl)
  • dimension-2 window size a.k.a., a sliding window value
  • dimension-3 e.g., e3
  • a dimension-3 window size a.k.a., a sliding window value in fn.sp5 is checked against a value of inl.e3.
  • a select value e.g. 1024
  • a dimension-2 window size is compared to a select value, e.g., 1024.
  • test handling is performed 214. However, if the tests are satisfactory 212, then the function/selected operation (e.g., mean- reduce operation of an AVGPOOL2D function) is executed 216.
  • function/selected operation e.g., mean- reduce operation of an AVGPOOL2D function
  • a general-purpose processor (e.g., general-purpose processor 104) initiates the Neural Network Processing Assist instruction and for certain functions, such as non-query functions, like the AVGPOOL2D function, the general-purpose processor provides information, such as an indication of the function/operation to be performed and memory address information for input data (e.g., one or more input tensors) to the special-purpose processor (e.g., neural network processor 105), such that the special-purpose processor can execute the function/operation, as described herein.
  • the special-purpose processor e.g., neural network processor 105
  • processing returns to the general-purpose processor to complete the instruction.
  • the general-purpose processor or the special-purpose processor initiates the instruction, performs the function/operation and completes the instruction.
  • a pooling operation is to be performed, and thus, pooling specific tests are executed 230. Examples of these tests include, for instance, checking whether:
  • Values of fn.sp2 and fn.sp3 are less than or equal to a particular value, such as
  • dimension-2 and dimension-3 stride values are compared to a particular value, e.g., 30.
  • a padding type specified by function-specific-parameter 1 is equal to a select padding type, such as Valid. If the value in fn.spl is, e.g., Valid, then a check is made as to whether the sliding window value specified in fn.sp4 (also referred to as a dimension-2 window size) is less than or equal to a value of dimension-2 of a first input tensor (inl.e2) and whether the sliding window value specified in fn.sp5 (also referred to as a dimension-3 window size) is less than or equal to a value of dimension-3 of a first input tensor (inl.e3).
  • fn.spl e.g., Valid
  • the padding type specified in fn.spl is not equal to the select padding type, such as Valid. If, in one example, the padding type specified in fn.spl is not equal to the select padding type, such as Valid, then a check is made, for instance, as to whether a value of a dimension-2 (e2) of an output tensor (e.g., out.e2) is equal to a value of ceil (inl.e2/fn.sp4), and a check is made as to whether a value of a dimension- 3 (e3) of the output tensor (e.g., out.e3) is equal to a value of ceil (inl.e3/fn.sp5). That is,
  • test handling is performed 214. However, if these tests are satisfactory 212, then the function/selected operation (e.g., pooling operation of an AVGPOOL2D function) is executed 216, as described herein.
  • function/selected operation e.g., pooling operation of an AVGPOOL2D function
  • processing Upon completion of the function/operation, processing returns to the general- purpose processor and the instruction completes 240.
  • a Neural Network Processing Assist instruction 300 has an RRE format that denotes a register and register operation with an extended operation code (opcode).
  • Neural Network Processing Assist instruction 300 includes an operation code (opcode) field 302 (e.g., bits 0-15) indicating a neural network processing assist operation.
  • bits 16-31 of the instruction are reserved and are to contain zeros.
  • functions and/or operations of the instructions specific locations, specific fields and/or specific sizes of the fields are indicated (e.g., specific bytes and/or bits). However, other locations, fields and/or sizes may be provided.
  • the setting of a bit to a particular value e.g., one or zero, may be specified, this is only an example.
  • the bit, if set, may be set to a different value, such as the opposite value or to another value, in other examples. Many variations are possible.
  • the instruction uses a plurality of general registers implicitly specified by the instruction. For instance, Neural Network Processing Assist instruction 300 uses implied registers general register 0 and general register 1, examples of which are described with reference to FIGS. 3B and 3D, respectively.
  • general register 0 includes a function code field, and status fields which may be updated upon completion of the instruction.
  • general register 0 includes a response code field 310 (e.g., bits 0-15), an exception flags field 312 (e.g., bits 24-31) and a function code field 314 (e.g., bits 56-63).
  • bits 16-23 and 32-55 of general register 0 are reserved and are to contain zeros.
  • One or more fields are used by a particular function performed by the instruction.
  • Response Code (RC) 310 This field (e.g., bit positions 0-15) contains the response code.
  • a condition code e.g., one
  • a response code is stored.
  • a non-zero value is stored to the response code field, which indicates the cause of the invalid input condition recognized during execution and a selected condition code, e.g., 1, is set.
  • the codes stored to the response code field are defined, as follows, in one example:
  • a specified single tensor dimension is greater than the maximum dimension index size.
  • 0013 The size of a specified tensor is greater than the maximum tensor size.
  • F000-FFFF Function specific response codes are defined for certain functions.
  • Exception Flags (EF) 312 This field (e.g., bit positions 24-31) includes the exception flags. If an exception condition is detected during execution of the instruction, the corresponding exception flag control (e.g., bit) will be set to, e.g., one; otherwise, the control remains unchanged.
  • the exception flags field is to be initialized to zero prior to the first invocation of the instruction. Reserved flags are unchanged during execution of the instruction.
  • the flags stored to the exception flags field are defined as follows, in one example:
  • FC 314 This field (e.g., bit positions 56-63) includes the function code. Examples of assigned function codes for the Neural Network Processing Assist instruction are depicted in FIG. 3C. All other function codes are unassigned. If an unassigned or uninstalled function code is specified, a response code of, e.g., 0002 hex and a select condition code, e.g., 1, are set. This field is not modified during execution.
  • the Neural Network Processing Assist instruction also uses general register 1, an example of which is depicted in FIG. 3D.
  • bits 40-63 in the 24-bit addressing mode, bits 33-63 in the 31-bit addressing mode or bits 0-63 in the 64-bit addressing mode include an address of a parameter block 320.
  • the contents of general register 1 specify, for instance, a logical address of a leftmost byte of the parameter block in storage.
  • the parameter block is to be designated on a doubleword boundary; otherwise, a specification exception is recognized. For all functions, the contents of general register 1 are not modified.
  • access register 1 specifies an address space containing the parameter block, input tensors, output tensors and the function specific save area, as an example.
  • the parameter block may have different formats depending on the function specified by the instruction to be performed. For instance, a query function of the instruction has a parameter block of one format and other functions of the instruction have a parameter block of another format. In another example, all functions use the same parameter block format. Other variations are also possible.
  • a parameter block and/or the information in the parameter block is stored in memory, in hardware registers and/or in a combination of memory and/or registers. Other examples are also possible.
  • a parameter block used by a query function such as a NNPA- Query Available Functions (QAF) operation, is described with reference to FIG. 3E.
  • a NNPA-Query Available Functions parameter block 330 includes, for instance:
  • Installed Functions Vector 332 This field (e.g., bytes 0-31) of the parameter block includes the installed functions vector.
  • bits 0-255 of the installed functions vector correspond to function codes 0-255, respectively, of the Neural Network Processing Assist instruction. When a bit is, e.g., one, the corresponding function is installed; otherwise, the function is not installed.
  • Installed Parameter Block Formats Vector 334 This field (e.g., bytes 32-47) of the parameter block includes the installed parameter block formats vector.
  • bits 0-127 of the installed parameter block formats vector correspond to parameter block formats 0-127 for the non-query functions of the Neural Network Processing Assist instruction.
  • a bit is, e.g., one, the corresponding parameter block format is installed; otherwise, the parameter block format is not installed.
  • Installed Data Types 336 This field (e.g., bytes 48-49) of the parameter block includes the installed data types vector. In one example, bits 0-15 of the installed data types vector correspond to the data types being installed. When a bit is, e.g., one, the corresponding data type is installed; otherwise, the data type is not installed.
  • Example data types include (additional, fewer and/or other data types are possible):
  • Installed Data Layout Formats 338 This field (e.g., bytes 52-55) of the parameter block includes the installed data layout formats vector.
  • bits 0-31 of the installed data layout formats vector correspond to data layout formats being installed. When a bit is, e.g., one, the corresponding data layout format is installed; otherwise, the data layout format is not installed.
  • Example data layout formats include (additional, fewer and/or other data types are possible):
  • Maximum Dimension Index Size 340 This field (e.g., bytes 60-63) of the parameter block includes, e.g., a 32-bit unsigned binary integer that specifies a maximum number of elements in a specified dimension index size for any specified tensor.
  • the maximum dimension index size specifies a maximum number of bytes in a specified dimension index size for any specified tensor. Other examples are also possible.
  • Maximum Tensor Size 342 This field (e.g., bytes 64-71) of the parameter block includes, e.g., a 32-bit unsigned binary integer that specifies a maximum number of bytes in any specified tensor including any pad bytes required by the tensor format. In another example, the maximum tensor size specifies a maximum number of total elements in any specified tensor including any padding required by the tensor format. Other examples are also possible.
  • Installed-NNP-Data-Type-1 -Conversions Vector 344 This field (e.g., bytes 72- 73) of the parameter block includes the installed-NNP-Data-Type-1 -conversions vector.
  • bits 0-15 of the installed-NNP-Data-Type-1 -conversions vector correspond to installed data type conversion from/to NNP-data-type-1 format. When a bit is one, the corresponding conversion is installed; otherwise, the conversion is not installed. Additional, fewer and/or other conversions may be specified.
  • a parameter block for a query function is described with reference to FIG. 3E
  • other formats of a parameter block for a query function including the NNPA-Query Available Functions operation, may be used.
  • the format may depend, in one example, on the type of query function to be performed.
  • the parameter block and/or each field of the parameter block may include additional, fewer and/or other information.
  • a parameter block format for non-query functions such as non-query functions of the Neural- Network Processing Assist instruction.
  • a parameter block used by a non query function such as the AVGPOOL2D function of the Neural Network Processing Assist instruction, is described with reference to FIG. 3F.
  • a parameter block 350 employed by, e.g., the non query functions of the Neural Network Processing Assist instruction includes, for instance: [00109] Parameter Block Version Number 352: This field (e.g., bytes 0-1) of the parameter block specifies the version and size of the parameter block. In one example, bits 0-8 of the parameter block version number are reserved and are to contain zeros, and bits 9- 15 of the parameter block version number contain an unsigned binary integer specifying the format of the parameter block.
  • the query function provides a mechanism of indicating the parameter block formats available.
  • a response code of, e.g., 0001 hex is stored in general register 0 and the instruction completes by setting a condition code, e.g., condition code 1.
  • the parameter block version number is specified by the program and is not modified during the execution of the instruction.
  • Model Version Number 354 This field (e.g., byte 2) of the parameter block is an unsigned binary integer identifying the model which executed the instruction (e.g., the particular non-query function).
  • a continuation flag (described below) is one, the model version number may be an input to the operation for the purpose of interpreting the contents of a continuation state buffer field (described below) of the parameter block to resume the operation.
  • Continuation Flag 356 This field (e.g., bit 63) of the parameter block, when, e.g., one, indicates the operation is partially complete and the contents of the continuation state buffer may be used to resume the operation.
  • the program is to initialize the continuation flag to zero and not modify the continuation flag in the event the instruction is to be re-executed for the purpose of resuming the operation; otherwise, results are unpredictable.
  • Function-specific-save-area-address 358 This field (e.g., bytes 56-63) of the parameter block includes the logical address of the function specific save area.
  • the function-specific-save-area-address is to be aligned on a 4 K-byte boundary; otherwise, a response code of, e.g., 0015 hex is set in general register 0 and the instruction completes with a condition code of, e.g., 1.
  • the address is subject to the current addressing mode.
  • the size of the function specific save area depends on the function code.
  • a PER storage alteration event is recognized, when applicable, for the portion of the function specific save area that is stored.
  • a PER storage alteration event is recognized, when applicable, for the entire parameter block.
  • a PER storage alteration event is recognized, when applicable, for the portion of the parameter block that is stored.
  • a PER zero-address detection event is recognized, when applicable, for the parameter block. Zero address detection does not apply to the tensor addresses or the function-specific-save-area-address, in one example.
  • Output Tensor Descriptors e.g., 1-2
  • 360/Input Tensor Descriptors e.g., 1-3
  • 365 One example of a tensor descriptor is described with reference to FIG. 3G.
  • a tensor descriptor 360, 365 includes:
  • Data Layout Format 382 This field (e.g., byte 0) of the tensor descriptor specifies the data layout format.
  • Valid data layout formats include, for instance (additional, fewer and/or other data layout formats are possible):
  • the response code of, e.g., 0010 hex is stored in general register 0 and the instruction completes by setting condition code, e.g., 1.
  • Data Type 384 This field (e.g., byte 1) specifies the data type of the tensor. Examples of supported data types are described below (additional, fewer and/or other data types are possible):
  • a response code of, e.g.,
  • Dimension 1-4 Index Size 386 Collectively, dimension index sizes one through four specify the shape of a 4D tensor. Each dimension index size is to be greater than zero and less than or equal to the maximum dimension index size (340, FIG. 3E); otherwise, a response code of, e.g., 0012 hex is stored in general register 0 and the instruction completes by setting condition code, e.g., 1. The total tensor size is to be less than or equal to the maximum tensor size (342, FIG. 3E); otherwise, a response code, e.g., 0013 hex is stored in general register 0 and the instruction completes by setting condition code, e.g., 1.
  • Tensor Address 388 This field (e.g., bytes 24-31) of the tensor descriptor includes a logical address of the leftmost byte of the tensor. The address is subject to the current addressing mode. [00136] If the address is not aligned on the boundary of the associated data layout format, a response code of, e.g., 0014 hex, is stored in general register 0 and the instruction completes by setting condition code, e.g., 1.
  • access register 1 specifies the address space containing all active input and output tensors in storage.
  • parameter block 350 further includes, in one example, function-specific-parameters 1-5 (370), which may be used by specific functions, as described herein.
  • parameter block 350 includes, in one example, a continuation state buffer field 375, which includes data (or a location of data) to be used if operation of this instruction is to be resumed.
  • reserved fields of the parameter block should contain zeros.
  • reserved fields may be stored as zeros or remain unchanged.
  • a parameter block for a non-query function is described with reference to FIG. 3F
  • other formats of a parameter block for a non-query function including a non-query function of the Neural Network Processing Assist instruction, may be used.
  • the format may depend, in one example, on the type of function to be performed.
  • a tensor descriptor is described with reference to FIG. 3G
  • other formats may be used.
  • different formats for input and output tensors may be used. Other variations are possible.
  • Function Code 0 NNPA-QAF (Query Available Functions)
  • the Neural Network Processing Assist (NNPA) query function provides a mechanism to indicate selected information, such as, for instance, the availability of installed functions, installed parameter block formats, installed data types, installed data layout formats, maximum dimension index size and maximum tensor size.
  • the information is obtained and placed in a selected location, such as a parameter block (e.g., parameter block 330).
  • a parameter block e.g., parameter block 330.
  • reserved fields of the parameter block may be stored as zeros or may remain unchanged.
  • a processor such as general-purpose processor 104, obtains information relating to a specific processor, such as a specific model of a neural network processor, such as neural network processor 105.
  • a specific model of a processor or machine has certain capabilities.
  • Another model of the processor or machine may have additional, fewer and/or different capabilities and/or be of a different generation (e.g., a current or future generation) having additional, fewer and/or different capabilities.
  • the obtained information is placed in a parameter block (e.g., parameter block 330) or other structure that is accessible to and/or for use with one or more applications that may use this information in further processing.
  • the parameter block and/or information of the parameter block is maintained in memory.
  • the parameter block and/or information may be maintained in one or more hardware registers.
  • the query function may be a privileged operation executed by the operating system, which makes available an application programming interface to make this information available to the application or non- privileged program.
  • the query function is performed by a special- purpose processor, such as neural network processor 105. Other variations are possible.
  • the information is obtained, e.g., by the firmware of the processor executing the query function.
  • the firmware has knowledge of the attributes of the specific model of the specific processor (e.g., neural network processor). This information may be stored in, e.g., a control block, register and/or memory and/or otherwise be accessible to the processor executing the query function.
  • the obtained information includes, for instance, model-dependent detailed information regarding at least one or more data attributes of the specific processor, including, for instance, one or more installed or supported data types, one or more installed or supported data layout formats and/or one or more installed or supported data sizes of the selected model of the specific processor.
  • This information is model-dependent in that other models (e.g., previous models and/or future models) may not support the same data attributes, such as the same data types, data sizes and/or data layout formats.
  • condition code 0, as an example, is set.
  • Condition codes 1, 2 and 3 are not applicable to the query function, in one example. Further information relating to the obtained information is described below.
  • the obtained information includes model- dependent information about one or more data attributes of, e.g., a particular model of a neural network processor.
  • a data attribute is installed data types of the neural network processor.
  • a particular model of a neural network processor (or other processor) may support one or more data types, such as a NNP-data-type-1 data type (also referred to as a neural network processing-data-type-1 data type) and/or other data types, as examples.
  • the NNP-data-type-1 data type is a 16-bit floating-point format that provides a number of advantages for deep learning training and inference computations, including, for instance: preserves the accuracy of deep learning networks; eliminates the subnormal format which simplifies rounding modes and handling of corner cases; automatic rounding to the nearest value for arithmetic operations; and special entities of infinity and not-a-number (NaN) are combined into one value (NINF), which is accepted and handled by arithmetic operations.
  • NINF provides better defaults for exponent overflow and invalid operations (such as division by zero). This allows many programs to continue running without hiding such errors and without using specialized exception handlers.
  • Other model- dependent data types are also possible.
  • NNP-data-type-1 data may be represented in a format 400, which includes, for instance, a sign 402 (e.g., bit 0), an exponent + 31 404 (e.g., bits 1-6) and a fraction 406 (e.g., bits 7-15).
  • a sign 402 e.g., bit 0
  • an exponent + 31 404 e.g., bits 1-6
  • a fraction 406 e.g., bits 7-15.
  • Nmax is largest (in magnitude) representable finite number
  • Nmin is smallest (in magnitude) representable number
  • Biased Exponent The bias that is used to allow exponents to be expressed as unsigned numbers is shown above. Biased exponents are similar to characteristics of the binary floating-point format, except that no special meanings are attached to biased exponents of all zeros and all ones, as described below with reference to the classes of the NNP-data-type-1 data type.
  • Significand The binary point of a NNP-data-type-1 number is considered to be to the left of the leftmost fraction bit. To the left of the binary point there is an implied unit bit, which is considered to be one for normal numbers and zero for zeros. The fraction with the implied unit bit appended on the left is the significand of the number.
  • e is biased exponent shown in decimal
  • f is fraction in binary.
  • Each data item includes a sign, an exponent and a significand.
  • the exponent is biased such that all biased exponents are non-negative unsigned numbers and the minimum biased exponent is zero.
  • the significand includes an explicit fraction and an implicit unit bit to the left of the binary point. The sign bit is zero for plus and one for minus.
  • Zeros have a biased exponent of zero and a zero fraction. The implied unit bit is zero.
  • Normal numbers may have a biased exponent of any value. When the biased exponent is 0, the fraction is to be non-zero. When the biased exponent is all ones, the fraction is not to be all ones. Other biased exponent values may have any fraction value. The implied unit bit is one for all normal numbers.
  • NINF A NINF is represented by a biased exponent of all ones and a fraction of all ones.
  • a NINF represents a value not in the range of representable values in NNP-data- type-1 (i.e., 16-bit floating point designed for deep learning that has 6 exponent bits and 9 fraction bits). Normally, NINFs are just propagated during computations so that they will remain visible at the end.
  • NNP-data-type-1 data type is supported in one example
  • other specialized or non-standard data types may be supported, as well as one or more standard data types including, but not limited to: IEEE 754 short precision, binary floating-point 16- bit, IEEE half precision floating point, 8-bit floating point, 4-bit integer format and/or 8-bit integer format, to name a few.
  • These data formats have different qualities for neural network processing. As an example, smaller data types (e.g., less bits) can be processed faster and use less cache/memory, and larger data types provide greater result accuracy in the neural network.
  • a data type to be supported may have one or more assigned bits in the query parameter block (e.g., in installed data types field 336 of parameter block 330). For instance, specialized or non-standard data types supported by a particular processor are indicated in the installed data types field but standard data types are not indicated. In other embodiments, one or more standard data types are also indicated. Other variations are possible.
  • bit 0 of installed data types field 336 is reserved for the NNP-data-type-1 data type, and when it is set to, e.g., 1, it indicates that the processor supports NNP-data-type-1.
  • the bit vector of installed data types is configured to represent up to 16 data types, in which a bit is assigned to each data type.
  • a bit vector in other embodiments may support more or fewer data types.
  • a vector may be configured in which one or more bits are assigned to a data type. Many examples are possible and/or additional, fewer and/or other data types may be supported and/or indicated in the vector.
  • the query function obtains an indication of the data types installed on the model-dependent processor and places the indication in the parameter block by, e.g., setting one or more bits in installed data types field 336 of parameter block 330. Further, in one example, the query function obtains an indication of installed data layout formats (another data attribute) and places the information in the parameter block by, e.g., setting one or more bits in installed data layout formats field 338.
  • Example data layout formats include, for instance, a 4D-feature tensor layout and a 4D-kernel tensor layout.
  • the 4D-feature tensor layout is used, in one example, by the functions indicated herein, and in one example, the convolution function uses the 4D-kernel tensor layout.
  • These data layout formats arrange data in storage for a tensor in a way that increases processing efficiency in execution of the functions of the Neural Network Processing Assist instruction. For instance, to operate efficiently, the Neural Network Processing Assist instruction uses input tensors provided in particular data layout formats.
  • example layouts are provided, additional, fewer and/or other layouts may be provided for the functions described herein and/or other functions.
  • the use or availability of layouts for a particular processor model is provided by the vector of installed data layout formats (e.g., field 338 of parameter block 330).
  • the vector is, for instance, a bit vector of installed data layout formats that allows the CPU to convey to applications which layouts are supported. For instance, bit 0 is reserved for the 4D-feature tensor layout, and when it is set to, e.g., 1, it indicates that the processor supports a 4D-feature tensor layout; and bit 1 is reserved for the 4D-kernel tensor layout, and when it is set to, e.g., 1, it indicates that the processor supports a 4D-kernel tensor layout.
  • the bit vector of installed data layout formats is configured to represent up to 16 data layouts, in which a bit is assigned to each data layout.
  • a bit vector in other embodiments may support more or fewer data layouts.
  • a vector may be configured in which one or more bits are assigned to data layouts. Many examples are possible.
  • the Neural Network Processing Assist instruction operates with 4D-tensors, i.e., tensors with 4 dimensions.
  • 4D-tensors are obtained from generic input tensors described herein in, e.g., row-major, i.e., when enumerating the tensor elements in increasing memory address order, the inner dimension called El will be stepped up first through the El -index-size values starting with 0 through the El -index-size -1, before the index of the E2 dimension will be increased and the stepping through the El dimension is repeated.
  • the index of the outer dimension called the E4 dimension is increased last.
  • Tensors that have a lower number of dimensions will be represented as 4D-tensors with one or more dimensions of the 4D-tensor exceeding the original tensor dimensions set to 1.
  • the transformation of a row-major generic 4D-tensor with dimensions E4, E3, E2, El into a 4D-feature tensor layout (also referred to herein as NNPA data layout format 0 4D-feature tensor) is described herein:
  • a resulting tensor can be represented, for instance, as a 4D-tensor of, e.g., 64- element vectors or a 5D-tensor with dimensions:
  • the resulting tensor may be larger than the generic tensor. Elements of the resulting tensor with no corresponding elements in the generic tensor are called pad elements.
  • ⁇ E4 N - Size of mini -batch
  • ⁇ E3 H - Height of the 3D-tensor/image
  • ⁇ E2 W - Width of the 3D-tensor/image
  • ⁇ E3 Reserved, generally set to 1
  • the NNPA data layout format 0 provides, e.g., two dimensional data locality with 4k-Bytes blocks of data (pages) as well as 4k-Byte block data alignment for the outer dimensions of the generated tensor.
  • Pad element bytes are ignored for the input tensors and unpredictable for output tensors. PER storage-alteration on pad bytes is unpredictable.
  • FIGS. 5A-5C One example of an input data layout for a 4D-feature tensor layout, which has dimensions El, E2, E3 and E4, is shown in FIGS. 5A-5C, and an example output for the 4D-feature tensor layout is depicted in FIGS. 6A-6C.
  • a 3D-tensor 500 is shown, which has dimensions El, E2 and E3.
  • each 3D-tensor includes a plurality of 2D-tensors 502. The numbers in each 2D-tensor 502 describe memory offsets of where each of its elements would be in memory.
  • the inputs are used to lay-out the data of the original tensor (e.g., original 4D-tensor of FIGS. 5A-5C) in memory, as shown in FIGS. 6A-6C, which correspond to FIGS. 5A-5C.
  • the original tensor e.g., original 4D-tensor of FIGS. 5A-5C
  • FIGS. 6A-6C which correspond to FIGS. 5A-5C.
  • a unit of memory 600 (e.g., a memory page) includes a pre-selected number (e.g., 32) of rows 602, each of which is identified by, e.g., e2_page_idx; and each row has a pre-selected number (e.g., 64) of elements 604, each identified by, e.g., el _page_idx. If a row does not include the pre-selected number of elements, it is padded 606, referred to as row or El padding; and if the memory unit does not have a pre-selected number of rows, it is padded 608, referred to as page or E2 padding.
  • the row padding is e.g., zeros or other values
  • the page padding is, e.g., existing values, zeros, or other values.
  • output elements of a row are provided in memory (e.g., in a page) based on element positions in the El direction of its corresponding input. For instance, referring to FIG. 5 A, element positions 0, 1 and 2 of the three matrices shown (e.g., element positions at a same location in each matrix) are shown in row 0 of page 0 of FIG. 6A, etc.
  • the 4D-tensor is small and all of the elements of each 2D- tensor representing the 4D-tensor fits in one page. However, this is only one example.
  • a 2D-tensor may include one or more pages.
  • a 2D-tensor is created based on a reformatting of a 4D-tensor, then the number of pages of the 2D-tensor is based on the size of the 4D- tensor.
  • one or more ceil functions are used to determine the number of rows in a 2D-tensor and the number of elements in each row, which will indicate how many pages are to be used. Other variations are possible.
  • a neural network processor may support a 4D-kernel tensor, which re-arranges the elements of a 4D-tensor to reduce the number of memory accesses and data gathering steps when executing certain artificial intelligence (e.g., neural network processing assist) operations, such as a convolution.
  • a row-major generic 4D-tensor with dimensions E4, E3, E2, El is transformed into a NNPA data layout format 1 4D-kernel tensor (4D-kernel tensor), as described herein:
  • a resulting tensor can be represented as a 4D-tensor of, e.g., 64-element vectors or a 5D-tensor with dimensions:
  • the resulting tensor may be larger than the generic tensor. Elements of the resulting tensor with no corresponding elements in the generic tensor are called pad elements.
  • ⁇ E4 H - Height of the 3D-tensor/image
  • ⁇ E2 C - Number of Channels of the 3D-tensor
  • the NNPA data layout format 1 provides, e.g., two dimensional kernel parallelism within 4k-Byte blocks of data (pages) as well as 4k-Byte block data alignment for the outer dimensions of the generate tensor for efficient processing.
  • example data layout formats include a 4D-feature tensor layout and a 4D-kernel tensor layout
  • other data layout formats may be supported by the processor (e.g., neural network processor 105).
  • An indication of supported data layouts is obtained and placed in the query parameter block by setting one or more bits in, e.g., field 338.
  • the query parameter block also includes, in accordance with one or more aspects of the present invention, other data attribute information, which includes, e.g., supported size information for the data.
  • a processor such as a neural network processor, typically has limitations based on internal buffer sizes, processing units, data bus structures, firmware limitations, etc. that can limit the maximum size of tensor dimensions and/or the overall size of a tensor. Therefore, the query function provides fields to convey these limits to applications.
  • the processor based on executing the query function, obtains various data sizes, such as a maximum dimension index size (e.g., 65,536 elements) and a maximum tensor size (e.g., 8 GB), and includes this information in fields 340 and 342, respectively, of the parameter block (e.g., parameter block 330). Additional, fewer and/or other size information may also be supported by the processor (e.g., neural network processor 105), and thus, obtained and placed in the parameter block, e.g., fields 340, 342 and/or other fields. In other embodiments, the limitations could be smaller or larger, and/or the sizes may be in other units, such as bytes instead of elements, elements instead of bytes, etc. Further, other embodiments allow for different maximum sizes of each dimension, rather than the same maximum for all dimensions. Many variations are possible.
  • a maximum dimension index size e.g., 65,536 elements
  • a maximum tensor size e.g., 8 GB
  • a query function conveys detailed information relating to a specific model of a selected processor (e.g., neural network processor 105).
  • the detailed information includes, for instance, model-dependent information relating to a specific processor.
  • a processor may also support standard data attributes, such as standard data types, standard data layouts, etc., which are implied and not necessarily presented by the query function; although, in other embodiments, the query function may indicate all or various selected subsets of data attributes, etc.
  • standard data attributes such as standard data types, standard data layouts, etc., which are implied and not necessarily presented by the query function; although, in other embodiments, the query function may indicate all or various selected subsets of data attributes, etc.
  • example information is provided, other information may be provided in other embodiments.
  • the obtained information which may be different for different models of a processor and/or of different processors, is used to perform artificial intelligence and/or other processing.
  • the artificial intelligence and/or other processing may employ one or more non-query functions of, e.g., the Neural Network Processing Assist instruction.
  • a specific non-query function employed in the processing is performed by executing the Neural Network Processing Assist instruction one or more times and specifying the non-query specific function.
  • Examples of non-query functions supported by the Neural Network Processing Assist instruction include an AVGPOOL2D function and a MAXPOOL2D function, each of which is described below (additional, fewer and/or other functions are supported in one or more embodiments).
  • Function Code 80 NNPA-MAXPOOL2D
  • Function Code 81 NNPA-AVGPOOL2D
  • input tensor 1 described by the input tensor 1 descriptor (e.g., see FIG. 3G)
  • input tensor 1 descriptor e.g., see FIG. 3G
  • the windows of the input are selected by moving a 2D sliding window over dimensions 2 and 3.
  • a summary of the window is an element in the output tensor.
  • the sliding window dimensions are described by, e.g., function-specific-parameter 4 and function-specific-parameter 5. The amount that the sliding window moves over the input tensor 1 when computing adjacent output tensor elements is called the stride.
  • the sliding window stride is specified by, e.g., function-specific-parameter 2 and function-specific-parameter 3.
  • the Max operation defined below is performed on the window.
  • the NNPA-AVGPOOL2D operation is specified, the AVG operation defined below is performed on the window. If the specified padding type is Valid, all elements in the window are added to the collection used to compute the resulting output element. If the specified padding type is Same, depending on the location of the window, only a subset of elements from the window may be added to the collection used to compute the resulting output element (e.g., those elements outside the bounds of the tensor may be ignored).
  • a CollectElements operation adds an element to the collection of elements and increments the number of elements in the collection. Each time the window start position moves, the collection is emptied. It is unpredictable whether elements not required to perform the operations are accessed.
  • Max Operation In one example, the maximum value of the collection of elements in the window is computed by comparing all elements in the collection to each other and returning the largest value.
  • AVG (Average) Operation In one example, the average value of the collection of elements in the window is computed as the summation of, e.g., all elements in the collection divided by the number of elements in the collection.
  • fields are allocated as follows:
  • a pooling function-specific-parameter 1 controls the padding type.
  • bits 29-31 of function-specific-parameter 1 include a PAD field that specifies the padding type.
  • Example types include, for instance:
  • a response code of, e.g.,
  • condition code e.g. 1
  • bit positions 0-28 of function-specific-parameter 1 are reserved and are to contain zeros.
  • Function-specific-parameter 2 contains, e.g., a 32-bit unsigned binary integer that specifies the dimension-2-stride (D2S) which specifies the number of elements the sliding window moves in dimension 2 (also referred to as e2).
  • D2S dimension-2-stride
  • Function-specific-parameter 3 contains, e.g., a 32-bit unsigned binary integer that specifies the dimension-3 -stride (D3S) which specifies the number of elements the sliding window moves in dimension 3 (also referred to as e3).
  • Function-specific-parameter 4 contains, e.g., a 32-bit unsigned binary integer that specifies the dimension-2 -window-size (D2WS) which specifies the number of elements in dimension 2 the sliding window contains.
  • Function-specific-parameter 5 contains, e.g., a 32-bit unsigned binary integer that specifies the dimension-3 -window-size (D3WS) which specifies the number of elements in dimension 3 the sliding window contains.
  • D3WS dimension-3 -window-size
  • the specified values in function-specific-parameters 2-5 are to be less than or equal to the maximum dimension index size, and the specified values in function-specific-parameters 4-5 are to be greater than, e.g., zero; otherwise, response code, e.g., 0012 hex is reported and the operation completes with condition code, e.g., 1.
  • the dimension-2-stride and the dimension-3 -stride are both zero and either the dimension-2 -window size or the dimension-3 -window size is greater than, e.g., 1024, response code, e.g., F001 hex is stored. If the dimension-2-stride and the dimension-3- stride are both greater than, e.g., zero and either the dimension-2 -window-size or the dimension-3 -window-size is greater than, e.g., 64, response code, e.g., F002 hex is stored.
  • the dimension-2-stride and the dimension-3 -stride are both greater than, e.g., zero, and either the dimension-2 stride or the dimension-3 stride is greater than, e.g., 30, response code, e.g., F003 hex is stored. If the dimension-2-stride and the dimension-3 -stride are both greater than, e.g., zero and either the input tensor dimension-2 -index-size or the input tensor dimension-3 -index-size is greater than, e.g., 1024, response code, e.g., F004 hex is stored. For all of the above conditions, the instruction completes with condition code, e.g., 1.
  • response code e.g., 0010 hex or 0011 hex, respectively, is set in general register 0 and the instruction completes with condition code, e.g., 1.
  • the dimension-2-stride and the dimension-3 -stride are both zero (specifying, e.g., a mean-reduce operation of the AVGPOOL2D function), the following additional conditions are to be true, in one example:
  • the input tensor dimension-2 -index-size is to be equal to the dimension-2 -window size.
  • the input tensor dimension-3 -index-size is to be equal to the dimension-3 -window-size.
  • the dimension-2 -index-size and the dimension-3 -index-size of the output tensor are to be one.
  • both strides are to be non-zero, in one example.
  • the dimension-2-stride and the dimension-3 -stride are both greater than zero (specifying, e.g., a pooling operation of the AVGPOOL2D function), the following additional conditions are to be true, in one example:
  • the dimension-2 -window-size is to be less than or equal to the dimension-2 -index-size of the input tensor.
  • the dimension-3 -window-size is to be less than or equal to the dimension-3 -index-size of the input tensor.
  • D2WS is dimension-2 -window size and D3WS is dimension-
  • a general operand data exception is recognized when execution of the Neural Network Processing Assist instruction is attempted and there are, for instance, tensor descriptor inconsistencies.
  • Resulting Condition Codes for the Neural Network Processing Assist instruction include, for instance: 0 - Normal completion; 1 - Response code is set; 2 — ; 3 - CPU- determined amount of data processed.
  • the priority of execution for the Neural Network Processing Assist instruction includes, for instance:
  • Condition code 1 due to specified format of the parameter block not supported by the model.
  • a single instruction e.g., the Neural Network Processing Assist instruction
  • the AVGPOOL2D function is configured to implement a plurality of operations (e.g., mean- reduce and pooling).
  • a single instruction e.g., the Neural Network Processing Assist instruction
  • the AVGPOOL2D function is configured to implement a plurality of operations (e.g., mean- reduce and pooling).
  • mean-reduce and pooling operations execute differently, they can be algorithmically reduced to a common algorithmic operation with the same input tensors and function-specific-parameters but having different relative constraints.
  • the one difference is checking of the conditions (e.g., stride, window size) that differ between the two operations.
  • a single function of an instruction is provided that executes multiple operations and implements different bound checking for both operations on some of the parameters. This reduces, at the very least, code complexity, code duplication and verification efforts.
  • One or more aspects of the present invention are inextricably tied to computer technology and facilitate processing within a computer, improving performance thereof.
  • the use of a single architected machine instruction configured to perform various functions improves performance within the computing environment by reducing complexity, reducing use of resources and increasing processing speed.
  • the use of a single function to implement multiple operations reduces complexity, use of resources, coding and/or verification efforts, and improves system performance.
  • the instruction, function, and/or operations may be used in many technical fields, such as in computer processing, medical processing, engineering, automotive technologies, manufacturing, etc. By providing optimizations, these technical fields are improved by, e.g., reducing errors and/or execution time.
  • FIGS. 7A-7C Further details of one embodiment of facilitating processing within a computing environment, as it relates to one or more aspects of the present invention, are described with reference to FIGS. 7A-7C.
  • an indication of a function to be executed is obtained, in which the function is one function of an instruction and configured to perform multiple operations 700.
  • a determination is made of an operation of the multiple operations to be performed 702, and a set of function-specific parameters is validated using a set of values and a corresponding set of relationships 704.
  • the set of values and corresponding set of relationships are based on the operation to be performed 706. As examples, one set of values and corresponding set of relationships are to be used for the operation to be performed 708, and another set of values and corresponding set of relationships are to be used for another operation of the multiple operations 710.
  • a single function e.g., a single function of an architected instruction, to perform multiple operations but with per operation parameter validation, code complexity, code duplication and/or verification efforts are reduced, improving system performance.
  • the determining the operation to be performed includes checking one or more function-specific parameters against at least one specific value 720. Based on the one or more function-specific parameters having a first select relationship with respect to the at least one specific value, the operation is one operation 722, and based on the one or more function-specific parameters having a second select relationship with respect to the at least one specific value, the operation is another operation 724.
  • the function includes an average pool function
  • the one or more function-specific parameters include one or more stride values, in which a stride value is an amount that a sliding window moves over an input tensor when computing one or more adjacent output tensor elements, the at least one specific value includes zero, the first select relationship includes equal and the operation is a mean-reduce operation based on the one or more stride values being equal to zero 726.
  • the second select relationship includes greater than and the operation is a pooling operation based on the one or more stride values being greater than zero 728.
  • the set of function-specific parameters includes one or more select-dimension window size values 730.
  • a select-dimension window size value specifies a number of elements in the select dimension that a sliding window contains 732, and the sliding window is configured to move over an input tensor of the function to produce an output tensor 734.
  • the function includes an average pool function
  • the operation includes a mean-reduce operation
  • the set of values and corresponding set of relationships to be used to validate the set of function-specific parameters includes: one value of one dimension of a select input tensor and corresponding relationship of equal, another value of another dimension of the select input tensor and corresponding relationship of equal, and a select value and corresponding relationship of less than or equal 740.
  • the validating includes, for instance, checking a value of a dimension-2 -window size is equal to a value of a dimension-2 of a first input tensor, a value of a dimension-3- window size is equal to a value of a dimension-3 of the first input tensor, the value of the dimension-2 -window size is less than or equal to the select value, and the value of the dimension-3 -window size is less than or equal to the select value 746.
  • the function includes an average pool function
  • the operation includes a pooling operation
  • the set of values and corresponding set of relationships to be used to validate the set of function-specific parameters includes: one value of one dimension of a select input tensor and corresponding relationship of less than or equal, and another value of another dimension of the select input tensor and corresponding relationship of less than or equal 750.
  • the validating includes, for instance, checking that a value of a dimension-2 - window size is less than or equal to a value of a dimension-2 of a first input tensor and that a value of a dimension-3 -window size is less than or equal to a value of a dimension-3 of the first input tensor 756.
  • the determining the operation is based on at least one sliding window stride value of an input tensor 770, and the set of function-specific parameters includes at least one sliding window dimension of an input tensor 772.
  • FIG. 8A Another example of a computing environment to incorporate and use one or more aspects of the present invention is described with reference to FIG. 8A.
  • the computing environment of FIG. 8 A is based on the z/ Architecture ® instruction set architecture offered by International Business Machines Corporation, Armonk, New York.
  • the z/ Architecture instruction set architecture is only one example architecture.
  • the computing environment may be based on other architectures, including, but not limited to, the Intel ® x86 architectures, other architectures of International Business Machines Corporation, and/or architectures of other companies.
  • Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.
  • a computing environment 10 includes a central electronics complex (CEC) 11.
  • Central electronics complex 11 includes a plurality of components, such as, for instance, a memory 12 (a.k.a., system memory, main memory, main storage, central storage, storage) coupled to one or more processors, such as one or more general- purpose processors (a.k.a., central processing units (CPUs) 13) and one or more special- purpose processors (e.g., neural network processor 31), and to an input/output (I/O) subsystem 14.
  • processors such as one or more general- purpose processors (a.k.a., central processing units (CPUs) 13) and one or more special- purpose processors (e.g., neural network processor 31), and to an input/output (I/O) subsystem 14.
  • I/O input/output subsystem
  • the one or more special-purpose processors may be separate from the one or more general-purpose processors and/or at least one special-purpose processor may be embedded within at least one general-purpose processor. Other variations are also possible.
  • I/O subsystem 14 can be a part of the central electronics complex or separate therefrom. It directs the flow of information between main storage 12 and input/output control units 15 and input/output (I/O) devices 16 coupled to the central electronics complex.
  • Data storage device 17 can store one or more programs 18, one or more computer readable program instructions 19, and/or data, etc.
  • the computer readable program instructions can be configured to carry out functions of embodiments of aspects of the invention.
  • Central electronics complex 11 can include and/or be coupled to removable/non removable, volatile/non-volatile computer system storage media.
  • it can include and/or be coupled to a non-removable, non-volatile magnetic media (typically called a "hard drive"), a magnetic disk drive for reading from and writing to a removable, non volatile magnetic disk (e.g., a "floppy disk”), and/or an optical disk drive for reading from or writing to a removable, non-volatile optical disk, such as a CD-ROM, DVD-ROM or other optical media.
  • a non-removable, non-volatile magnetic media typically called a "hard drive”
  • a magnetic disk drive for reading from and writing to a removable, non volatile magnetic disk (e.g., a "floppy disk”
  • an optical disk drive for reading from or writing to a removable, non-volatile optical disk, such as a CD-ROM, DVD-ROM or other optical media.
  • other hardware and/or software components could be used in
  • central electronics complex 11 can be operational with numerous other general-purpose or special-purpose computing system environments or configurations.
  • Examples of well-known computing systems, environments, and/or configurations that may be suitable for use with central electronics complex 11 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices, and the like.
  • Central electronics complex 11 provides in one or more embodiments logical partitioning and/or virtualization support.
  • memory 12 includes, for example, one or more logical partitions 20, a hypervisor 21 that manages the logical partitions, and processor firmware 22.
  • hypervisor 21 is the Processor Resource/System Manager (PR/SMTM), offered by International Business Machines Corporation, Armonk, New York.
  • PR/SM is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction.
  • Each logical partition 20 is capable of functioning as a separate system. That is, each logical partition can be independently reset, run a guest operating system 23 such as the z/OS ® operating system, offered by International Business Machines Corporation, Armonk, New York, or other control code 24, such as coupling facility control code (CFCC), and operate with different programs 25.
  • a guest operating system 23 such as the z/OS ® operating system, offered by International Business Machines Corporation, Armonk, New York, or other control code 24, such as coupling facility control code (CFCC), and operate with different programs 25.
  • CFCC coupling facility control code
  • An operating system or application program running in a logical partition appears to have access to a full and complete system, but in reality, only a portion of it is available.
  • the z/OS operating system is offered as an example, other operating systems offered by International Business Machines Corporation and/or other companies may be used in accordance with one or more aspects of the present invention.
  • Memory 12 is coupled to, e.g., CPUs 13 (FIG. 8A), which are physical processor resources that can be allocated to the logical partitions.
  • a logical partition 20 may include one or more logical processors, each of which represents all or a share of a physical processor resource 13 that can be dynamically allocated to the logical partition.
  • the central electronics complex provides virtual machine support (either with or without logical partitioning support).
  • memory 12 of central electronics complex 11 includes, for example, one or more virtual machines 26, a virtual machine manager, such as a hypervisor 27, that manages the virtual machines, and processor firmware 28.
  • hypervisor 27 is the z/VM ® hypervisor, offered by International Business Machines Corporation, Armonk, New York. The hypervisor is sometimes referred to as a host.
  • z/VM is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction.
  • the virtual machine support of the central electronics complex provides the ability to operate large numbers of virtual machines 26, each capable of operating with different programs 29 and running a guest operating system 30, such as the Linux ® operating system.
  • Each virtual machine 26 is capable of functioning as a separate system. That is, each virtual machine can be independently reset, run a guest operating system, and operate with different programs.
  • An operating system or application program running in a virtual machine appears to have access to a full and complete system, but in reality, only a portion of it is available.
  • z/VM and Linux are offered as examples, other virtual machine managers and/or operating systems may be used in accordance with one or more aspects of the present invention.
  • the registered trademark Linux ® is used pursuant to a sublicense from the Linux Foundation, the exclusive licensee of Linus Torvalds, owner of the mark on a worldwide basis.
  • a computing environment 36 includes, for instance, a native central processing unit (CPU) 37, a memory 38, and one or more input/output devices and/or interfaces 39 coupled to one another via, for example, one or more buses 40 and/or other connections.
  • CPU central processing unit
  • computing environment 36 may include a PowerPC ® processor offered by International Business Machines Corporation, Armonk, New York; an HP Superdome with Intel ® Itanium ® II processors offered by Hewlett Packard Co., Palo Alto, California; and/or other machines based on architectures offered by International Business Machines Corporation, Hewlett Packard, Intel Corporation, Oracle, and/or others.
  • PowerPC is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction. Itanium is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.
  • Native central processing unit 37 includes one or more native registers 41, such as one or more general purpose registers and/or one or more special purpose registers used during processing within the environment. These registers include information that represents the state of the environment at any particular point in time. [00330] Moreover, native central processing unit 37 executes instructions and code that are stored in memory 38. In one particular example, the central processing unit executes emulator code 42 stored in memory 38. This code enables the computing environment configured in one architecture to emulate another architecture. For instance, emulator code 42 allows machines based on architectures other than the z/ Architecture instruction set architecture, such as PowerPC processors, HP Superdome servers or others, to emulate the z/ Architecture instruction set architecture and to execute software and instructions developed based on the z/ Architecture instruction set architecture.
  • native registers 41 such as one or more general purpose registers and/or one or more special purpose registers used during processing within the environment. These registers include information that represents the state of the environment at any particular point in time.
  • native central processing unit 37 executes instructions and code that are stored in memory
  • Guest instructions 43 stored in memory 38 comprise software instructions (e.g., correlating to machine instructions) that were developed to be executed in an architecture other than that of native CPU 37.
  • guest instructions 43 may have been designed to execute on a processor based on the z/ Architecture instruction set architecture, but instead, are being emulated on native CPU 37, which may be, for example, an Intel Itanium II processor.
  • emulator code 42 includes an instruction fetching routine 44 to obtain one or more guest instructions 43 from memory 38, and to optionally provide local buffering for the instructions obtained. It also includes an instruction translation routine 45 to determine the type of guest instruction that has been obtained and to translate the guest instruction into one or more corresponding native instructions 46. This translation includes, for instance, identifying the function to be performed by the guest instruction and choosing the native instruction(s) to perform that function.
  • emulator code 42 includes an emulation control routine 47 to cause the native instructions to be executed.
  • Emulation control routine 47 may cause native CPU 37 to execute a routine of native instructions that emulate one or more previously obtained guest instructions and, at the conclusion of such execution, return control to the instruction fetch routine to emulate the obtaining of the next guest instruction or a group of guest instructions.
  • Execution of the native instructions 46 may include loading data into a register from memory 38; storing data back to memory from a register; or performing some type of arithmetic or logic operation, as determined by the translation routine.
  • Each routine is, for instance, implemented in software, which is stored in memory and executed by native central processing unit 37.
  • one or more of the routines or operations are implemented in firmware, hardware, software or some combination thereof.
  • the registers of the emulated processor may be emulated using registers 41 of the native CPU or by using locations in memory 38.
  • guest instructions 43, native instructions 46 and emulator code 42 may reside in the same memory or may be disbursed among different memory devices.
  • An instruction that may be emulated includes the Neural Network Assist Processing instruction described herein, in accordance with one or more aspects of the present invention. Further, other instructions, functions, operations and/or one or more aspects of neural network processing may be emulated, in accordance with one or more aspects of the present invention.
  • computing environments described above are only examples of computing environments that can be used. Other environments, including but not limited to, non- partitioned environments, partitioned environments, cloud environments and/or emulated environments, may be used; embodiments are not limited to any one environment. Although various examples of computing environments are described herein, one or more aspects of the present invention may be used with many types of environments. The computing environments provided herein are only examples.
  • Each computing environment is capable of being configured to include one or more aspects of the present invention.
  • One or more aspects may relate to cloud computing.
  • Cloud computing is a model of service delivery for enabling convenient, on- demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal management effort or interaction with a provider of the service.
  • This cloud model may include at least five characteristics, at least three service models, and at least four deployment models.
  • On-demand self-service a cloud consumer can unilaterally provision computing capabilities, such as server time and network storage, as needed automatically without requiring human interaction with the service’s provider.
  • Broad network access capabilities are available over a network and accessed through standard mechanisms that promote use by heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs).
  • heterogeneous thin or thick client platforms e.g., mobile phones, laptops, and PDAs.
  • Resource pooling the provider’s computing resources are pooled to serve multiple consumers using a multi-tenant model, with different physical and virtual resources dynamically assigned and reassigned according to demand. There is a sense of location independence in that the consumer generally has no control or knowledge over the exact location of the provided resources but may be able to specify location at a higher level of abstraction (e.g., country, state, or datacenter).
  • Rapid elasticity capabilities can be rapidly and elastically provisioned, in some cases automatically, to quickly scale out and rapidly released to quickly scale in. To the consumer, the capabilities available for provisioning often appear to be unlimited and can be purchased in any quantity at any time.
  • Measured service cloud systems automatically control and optimize resource use by leveraging a metering capability at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency for both the provider and consumer of the utilized service.
  • level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts).
  • SaaS Software as a Service: the capability provided to the consumer is to use the provider’s applications running on a cloud infrastructure.
  • the applications are accessible from various client devices through a thin client interface such as a web browser (e.g., web-based e-mail).
  • a web browser e.g., web-based e-mail
  • the consumer does not manage or control the underlying cloud infrastructure including network, servers, operating systems, storage, or even individual application capabilities, with the possible exception of limited user-specific application configuration settings.
  • PaaS Platform as a Service
  • the consumer does not manage or control the underlying cloud infrastructure including networks, servers, operating systems, or storage, but has control over the deployed applications and possibly application hosting environment configurations.
  • IaaS Infrastructure as a Service
  • the consumer does not manage or control the underlying cloud infrastructure but has control over operating systems, storage, deployed applications, and possibly limited control of select networking components (e.g., host firewalls).
  • Private cloud the cloud infrastructure is operated solely for an organization. It may be managed by the organization or a third party and may exist on-premises or off- premises.
  • Public cloud the cloud infrastructure is made available to the general public or a large industry group and is owned by an organization selling cloud services.
  • Hybrid cloud the cloud infrastructure is a composition of two or more clouds (private, community, or public) that remain unique entities but are bound together by standardized or proprietary technology that enables data and application portability (e.g., cloud bursting for load-balancing between clouds).
  • a cloud computing environment is service oriented with a focus on statelessness, low coupling, modularity, and semantic interoperability.
  • An infrastructure that includes a network of interconnected nodes.
  • cloud computing environment 50 includes one or more cloud computing nodes 52 with which local computing devices used by cloud consumers, such as, for example, personal digital assistant (PDA) or cellular telephone 54A, desktop computer 54B, laptop computer 54C, and/or automobile computer system 54N may communicate.
  • Nodes 52 may communicate with one another. They may be grouped (not shown) physically or virtually, in one or more networks, such as Private, Community, Public, or Hybrid clouds as described hereinabove, or a combination thereof.
  • This allows cloud computing environment 50 to offer infrastructure, platforms and/or software as services for which a cloud consumer does not need to maintain resources on a local computing device.
  • computing devices 54A-N shown in FIG. 10 are intended to be illustrative only and that computing nodes 52 and cloud computing environment 50 can communicate with any type of computerized device over any type of network and/or network addressable connection (e.g., using a web browser).
  • FIG. 11 a set of functional abstraction layers provided by cloud computing environment 50 (FIG. 10) is shown. It should be understood in advance that the components, layers, and functions shown in FIG. 11 are intended to be illustrative only and embodiments of the invention are not limited thereto. As depicted, the following layers and corresponding functions are provided:
  • Hardware and software layer 60 includes hardware and software components.
  • hardware components include: mainframes 61; RISC (Reduced Instruction Set Computer) architecture based servers 62; servers 63; blade servers 64; storage devices 65; and networks and networking components 66.
  • software components include network application server software 67 and database software 68.
  • Virtualization layer 70 provides an abstraction layer from which the following examples of virtual entities may be provided: virtual servers 71; virtual storage 72; virtual networks 73, including virtual private networks; virtual applications and operating systems 74; and virtual clients 75.
  • management layer 80 may provide the functions described below.
  • Resource provisioning 81 provides dynamic procurement of computing resources and other resources that are utilized to perform tasks within the cloud computing environment.
  • Metering and Pricing 82 provide cost tracking as resources are utilized within the cloud computing environment, and billing or invoicing for consumption of these resources. In one example, these resources may include application software licenses.
  • Security provides identity verification for cloud consumers and tasks, as well as protection for data and other resources.
  • User portal 83 provides access to the cloud computing environment for consumers and system administrators.
  • Service level management 84 provides cloud computing resource allocation and management such that required service levels are met.
  • Service Level Agreement (SLA) planning and fulfillment 85 provide pre arrangement for, and procurement of, cloud computing resources for which a future requirement is anticipated in accordance with an SLA.
  • SLA Service Level Agreement
  • Workloads layer 90 provides examples of functionality for which the cloud computing environment may be utilized. Examples of workloads and functions which may be provided from this layer include: mapping and navigation 91; software development and lifecycle management 92; virtual classroom education delivery 93; data analytics processing 94; transaction processing 95; and neural network processing assist processing 96.
  • aspects of the present invention may be a system, a method, and/or a computer program product at any possible technical detail level of integration
  • the computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention
  • the computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device.
  • the computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing.
  • a non- exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing.
  • RAM random access memory
  • ROM read-only memory
  • EPROM or Flash memory erasable programmable read-only memory
  • SRAM static random access memory
  • CD-ROM compact disc read-only memory
  • DVD digital versatile disk
  • memory stick a floppy disk
  • mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon
  • a computer readable storage medium is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.
  • Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network.
  • the network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers.
  • a network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.
  • Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuitry, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++, or the like, and procedural programming languages, such as the "C" programming language or similar programming languages.
  • the computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server.
  • the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).
  • electronic circuitry including, for example, programmable logic circuitry, field- programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.
  • These computer readable program instructions may be provided to a processor of a computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
  • These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.
  • the computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
  • each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s).
  • the functions noted in the blocks may occur out of the order noted in the Figures.
  • two blocks shown in succession may, in fact, be accomplished as one step, executed concurrently, substantially concurrently, in a partially or wholly temporally overlapping manner, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.
  • one or more aspects may be provided, offered, deployed, managed, serviced, etc. by a service provider who offers management of customer environments.
  • the service provider can create, maintain, support, etc. computer code and/or a computer infrastructure that performs one or more aspects for one or more customers.
  • the service provider may receive payment from the customer under a subscription and/or fee agreement, as examples. Additionally or alternatively, the service provider may receive payment from the sale of advertising content to one or more third parties.
  • an application may be deployed for performing one or more embodiments.
  • the deploying of an application comprises providing computer infrastructure operable to perform one or more embodiments.
  • a computing infrastructure may be deployed comprising integrating computer readable code into a computing system, in which the code in combination with the computing system is capable of performing one or more embodiments.
  • a process for integrating computing infrastructure comprising integrating computer readable code into a computer system
  • the computer system comprises a computer readable medium, in which the computer medium comprises one or more embodiments.
  • the code in combination with the computer system is capable of performing one or more embodiments.
  • computing environments of other architectures can be used to incorporate and/or use one or more aspects.
  • different instructions, functions and/or operations may be used.
  • different types of registers and/or different registers may be used.
  • other data formats, data layouts and/or data sizes may be supported.
  • one or more general-purpose processors, one or more special-purpose processors or a combination of general-purpose and special-purpose processors may be used. Many variations are possible.
  • a data processing system suitable for storing and/or executing program code includes at least two processors coupled directly or indirectly to memory elements through a system bus.
  • the memory elements include, for instance, local memory employed during actual execution of the program code, bulk storage, and cache memory which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution.
  • I/O devices can be coupled to the system either directly or through intervening I/O controllers.
  • Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modems, and Ethernet cards are just a few of the available types of network adapters.

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11656851B2 (en) * 2021-10-22 2023-05-23 Microsoft Technology Licensing, Llc. Long-range modeling of source code files by syntax hierarchy
KR102899545B1 (ko) * 2023-12-26 2025-12-12 서울대학교산학협력단 텐서 데이터 이동 방법 및 장치

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180165577A1 (en) * 2016-12-13 2018-06-14 Google Inc. Performing average pooling in hardware

Family Cites Families (72)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5761105A (en) 1995-09-26 1998-06-02 Advanced Micro Devices, Inc. Reservation station including addressable constant store for a floating point processing unit
US8291003B2 (en) 2008-09-09 2012-10-16 International Business Machines Corporation Supporting multiple formats in a floating point processor
US9223687B2 (en) 2012-06-15 2015-12-29 International Business Machines Corporation Determining the logical address of a transaction abort
US9286130B2 (en) 2012-08-27 2016-03-15 International Business Machines Corporation Optimizing virtual machine deployment time by temporarily allocating more processing resources during the initial deployment time of the virtual machine
US10623386B1 (en) 2012-09-26 2020-04-14 Pure Storage, Inc. Secret sharing data protection in a storage system
US9201629B2 (en) 2013-03-14 2015-12-01 International Business Machines Corporation Instruction for performing a pseudorandom number seed operation
US9582295B2 (en) * 2014-03-18 2017-02-28 International Business Machines Corporation Architectural mode configuration
US9916185B2 (en) * 2014-03-18 2018-03-13 International Business Machines Corporation Managing processing associated with selected architectural facilities
US10061824B2 (en) 2015-01-30 2018-08-28 Splunk Inc. Cell-based table manipulation of event data
US9747546B2 (en) 2015-05-21 2017-08-29 Google Inc. Neural network processor
US10460230B2 (en) 2015-06-04 2019-10-29 Samsung Electronics Co., Ltd. Reducing computations in a neural network
US9710401B2 (en) 2015-06-26 2017-07-18 Intel Corporation Processors, methods, systems, and instructions to support live migration of protected containers
US10728169B1 (en) 2015-06-26 2020-07-28 Amazon Technologies, Inc. Instance upgrade migration
US9940101B2 (en) 2015-08-25 2018-04-10 Samsung Electronics Co., Ltd. Tininess prediction and handler engine for smooth handling of numeric underflow
US10726328B2 (en) 2015-10-09 2020-07-28 Altera Corporation Method and apparatus for designing and implementing a convolution neural net accelerator
US10552370B2 (en) 2015-10-08 2020-02-04 Via Alliance Semiconductor Co., Ltd. Neural network unit with output buffer feedback for performing recurrent neural network computations
US9569277B1 (en) 2016-01-29 2017-02-14 International Business Machines Corporation Rebalancing virtual resources for virtual machines based on multiple resource capacities
US10778707B1 (en) 2016-05-12 2020-09-15 Amazon Technologies, Inc. Outlier detection for streaming data using locality sensitive hashing
US10891538B2 (en) 2016-08-11 2021-01-12 Nvidia Corporation Sparse convolutional neural network accelerator
US10810484B2 (en) 2016-08-12 2020-10-20 Xilinx, Inc. Hardware accelerator for compressed GRU on FPGA
US10802992B2 (en) 2016-08-12 2020-10-13 Xilinx Technology Beijing Limited Combining CPU and special accelerator for implementing an artificial neural network
US10175980B2 (en) 2016-10-27 2019-01-08 Google Llc Neural network compute tile
US9959498B1 (en) 2016-10-27 2018-05-01 Google Llc Neural network instruction set architecture
US9785435B1 (en) * 2016-10-27 2017-10-10 International Business Machines Corporation Floating point instruction with selectable comparison attributes
US10120680B2 (en) 2016-12-30 2018-11-06 Intel Corporation Systems, apparatuses, and methods for arithmetic recurrence
CN118134744A (zh) 2017-04-07 2024-06-04 英特尔公司 用于多处理器平台上的深度学习网络执行流水线的方法和装置
WO2018193352A1 (en) 2017-04-17 2018-10-25 Cerebras Systems Inc. Dataflow triggered tasks for accelerated deep learning
CN107704922B (zh) 2017-04-19 2020-12-08 赛灵思公司 人工神经网络处理装置
US12154028B2 (en) 2017-05-05 2024-11-26 Intel Corporation Fine-grain compute communication execution for deep learning frameworks via hardware accelerated point-to-point primitives
US10338925B2 (en) 2017-05-24 2019-07-02 Microsoft Technology Licensing, Llc Tensor register files
US11216437B2 (en) 2017-08-14 2022-01-04 Sisense Ltd. System and method for representing query elements in an artificial neural network
US10642835B2 (en) 2017-08-14 2020-05-05 Sisense Ltd. System and method for increasing accuracy of approximating query results using neural networks
US10558599B2 (en) 2017-09-12 2020-02-11 Nxp Usa, Inc. Method and apparatus for loading a matrix into an accelerator
CN109543826A (zh) 2017-09-21 2019-03-29 杭州海康威视数字技术股份有限公司 一种基于深度神经网络的激活量量化方法及装置
KR102610820B1 (ko) 2017-09-27 2023-12-06 삼성전자주식회사 뉴럴 네트워크 시스템 및 뉴럴 네트워크 시스템의 동작방법
GB2568087B (en) 2017-11-03 2022-07-20 Imagination Tech Ltd Activation functions for deep neural networks
US11373088B2 (en) 2017-12-30 2022-06-28 Intel Corporation Machine learning accelerator mechanism
MX2020007385A (es) 2018-01-10 2020-11-24 Lynjohnston Llc Sistemas y metodos de inyector compacto.
US10832137B2 (en) 2018-01-30 2020-11-10 D5Ai Llc Merging multiple nodal networks
WO2019157599A1 (en) 2018-02-16 2019-08-22 The Governing Council Of The University Of Toronto Neural network accelerator
US10552199B2 (en) 2018-02-26 2020-02-04 Nutanix, Inc. System and method for binary throttling for live migration of virtual machines
US20200074293A1 (en) 2018-08-29 2020-03-05 DinoplusAI Holdings Limited Computing Device for Multiple Activation Functions in Neural Networks
US20190340499A1 (en) 2018-05-04 2019-11-07 Microsoft Technology Licensing, Llc Quantization for dnn accelerators
US10656913B2 (en) 2018-06-05 2020-05-19 International Business Machines Corporation Enhanced low precision binary floating-point formatting
US10620951B2 (en) 2018-06-22 2020-04-14 Intel Corporation Matrix multiplication acceleration of sparse matrices using column folding and squeezing
US10832139B2 (en) 2018-06-22 2020-11-10 Moffett Technologies Co. Limited Neural network acceleration and embedding compression systems and methods with activation sparsification
US10908906B2 (en) 2018-06-29 2021-02-02 Intel Corporation Apparatus and method for a tensor permutation engine
CN109146072B (zh) 2018-08-01 2021-03-23 上海天数智芯半导体有限公司 基于卷积神经网络加速器的数据重用方法
US10885277B2 (en) 2018-08-02 2021-01-05 Google Llc On-device neural networks for natural language understanding
US11455370B2 (en) 2018-11-19 2022-09-27 Groq, Inc. Flattened input stream generation for convolution with expanded kernel
US10817042B2 (en) 2018-09-27 2020-10-27 Intel Corporation Power savings for neural network architecture with zero activations during inference
US11861484B2 (en) 2018-09-28 2024-01-02 Qualcomm Incorporated Neural processing unit (NPU) direct memory access (NDMA) hardware pre-processing and post-processing
US11676003B2 (en) 2018-12-18 2023-06-13 Microsoft Technology Licensing, Llc Training neural network accelerators using mixed precision data formats
US10699465B1 (en) 2018-12-28 2020-06-30 Intel Corporation Cluster of scalar engines to accelerate intersection in leaf node
US20200218985A1 (en) 2019-01-03 2020-07-09 Alibaba Group Holding Limited System and method for synthetic-model-based benchmarking of ai hardware
US11645358B2 (en) 2019-01-29 2023-05-09 Hewlett Packard Enterprise Development Lp Generation of executable files corresponding to neural network models
US12165038B2 (en) 2019-02-14 2024-12-10 Microsoft Technology Licensing, Llc Adjusting activation compression for neural network training
US11157240B2 (en) 2019-02-15 2021-10-26 International Business Machines Corporation Perform cryptographic computation scalar multiply instruction
US11442700B2 (en) 2019-03-29 2022-09-13 Stmicroelectronics S.R.L. Hardware accelerator method, system and device
US10789402B1 (en) 2019-05-01 2020-09-29 Xilinx, Inc. Compiler and hardware abstraction layer architecture for a neural network accelerator
US11366771B2 (en) 2019-05-02 2022-06-21 EMC IP Holding Company LLC Host device with multi-path layer configured for detection and resolution of initiator-related conditions
US11790250B2 (en) 2019-05-09 2023-10-17 Intel Corporation Using computational cost and instantaneous load analysis for intelligent deployment of neural networks on multiple hardware executors
CN110197260B (zh) 2019-06-06 2020-10-02 百度在线网络技术（北京）有限公司 一种数据处理方法及装置
US11714572B2 (en) 2019-06-19 2023-08-01 Pure Storage, Inc. Optimized data resiliency in a modular storage system
TWI701612B (zh) 2019-06-19 2020-08-11 創鑫智慧股份有限公司 用於神經網路中激勵函數的電路系統及其處理方法
US11907827B2 (en) 2019-06-28 2024-02-20 Intel Corporation Schedule-aware tensor distribution module
US20190392296A1 (en) 2019-06-28 2019-12-26 John Brady Hardware agnostic deep neural network compiler
US11568238B2 (en) 2019-06-28 2023-01-31 Amazon Technologies, Inc. Dynamic processing element array expansion
US11630770B2 (en) 2019-07-11 2023-04-18 Meta Platforms Technologies, Llc Systems and methods for reading and writing sparse data in a neural network accelerator
US11567555B2 (en) 2019-08-30 2023-01-31 Intel Corporation Software assisted power management
US11727267B2 (en) 2019-08-30 2023-08-15 Intel Corporation Artificial neural network with trainable activation functions and fractional derivative values
US11797188B2 (en) 2019-12-12 2023-10-24 Sk Hynix Nand Product Solutions Corp. Solid state drive with multiplexed internal channel access during program data transfers

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180165577A1 (en) * 2016-12-13 2018-06-14 Google Inc. Performing average pooling in hardware

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
"z/Architecture Principles of Operation", September 2019, IBM PUBLICATION
ABDELFATTAH MOHAMED S ET AL: "DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration", 2018 28TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL), IEEE, 27 August 2018 (2018-08-27), pages 411 - 4117, XP033462516, DOI: 10.1109/FPL.2018.00077 *
AMD: ""RDNA 2" Instruction Set Architecture", 30 November 2020 (2020-11-30), pages 1 - 291, XP055964979, Retrieved from the Internet <URL:https://developer.amd.com/wp-content/resources/RDNA2_Shader_ISA_November2020.pdf> [retrieved on 20220926] *

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