WO2022257871A1 - 一种错误检测方法及相关装置 - Google Patents

一种错误检测方法及相关装置 Download PDF

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Publication number
WO2022257871A1
WO2022257871A1 PCT/CN2022/097095 CN2022097095W WO2022257871A1 WO 2022257871 A1 WO2022257871 A1 WO 2022257871A1 CN 2022097095 W CN2022097095 W CN 2022097095W WO 2022257871 A1 WO2022257871 A1 WO 2022257871A1
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Prior art keywords
test mode
target
fdti
executed
task
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PCT/CN2022/097095
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English (en)
French (fr)
Inventor
曹建龙
方锐
陈招娣
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华为技术有限公司
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Priority to EP22819469.2A priority Critical patent/EP4350524A1/en
Publication of WO2022257871A1 publication Critical patent/WO2022257871A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3668—Software testing
    • G06F11/3672—Test management
    • G06F11/3684—Test management for test design, e.g. generating new test cases
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3668—Software testing
    • G06F11/3672—Test management
    • G06F11/3688—Test management for test execution, e.g. scheduling of test suites

Definitions

  • the present application relates to the field of computer technology, in particular to an error detection method and a related device.
  • data processing devices may experience random hardware failures, such as permanent failures caused by short circuits or open circuits in integrated circuits, or temporary failures such as bit flips caused by exposure to natural radiation or particle impact .
  • an error detection mechanism can be provided for the processor to detect hardware errors and ensure that in the event of hardware errors Perform security operations.
  • a processor periodically executes a test pattern (test pattern) in a software test library (Software Test Library, STL) to detect errors in logic circuits.
  • test pattern test pattern
  • STL Software Test Library
  • the periodic execution of the test patterns in the STL by the processor will cause a large load on the processor, that is, the processor needs to spend more time to detect errors, thereby affecting the processing. device working efficiency.
  • the first aspect of the present application provides an error detection method, which is applied to terminals in fields with security requirements, such as vehicle-mounted terminals or control terminals in aerospace.
  • the method includes: obtaining a first schedule of a first task, the first schedule includes a first test mode, and the first test mode is used to detect an error of a target logic circuit, the target logic circuit is used for executing logic circuitry for said first task, said first task being configured to be executed within a target fault detection time interval FDTI;
  • the first task may be a task that needs to be executed in the target FDTI in the terminal, for example, may be a process or a thread that needs to be executed in the target FDTI in the terminal.
  • the way for the terminal to determine the first task may be to obtain it from the task queue.
  • the tasks in the task queue are tasks that are ready to be executed but have not been executed (or called tasks in the ready state).
  • the terminal can acquire the first task identifier (identifier , ID) to determine the first task, or to determine the first task based on the data structure corresponding to the first task; in the dispatch table corresponding to the first task, at least one test pattern (for example, including the and the first test mode and the second test mode), the at least one test mode corresponds to the machine instruction code of the first task, and the at least one test mode is used to detect errors in the target logic circuit.
  • the correspondence between the at least one test pattern and the machine instruction code of the first task means that based on the at least one test pattern, the error detection of the target logic circuit on which the machine instruction code of the first task depends can be realized;
  • test pattern sets There may be overlap between the test pattern sets corresponding to different tasks in the same FDTI (that is, the union of the two sets is not empty).
  • the executed test patterns within the FDTI are analyzed to generate a reasonable scheduling set.
  • the test model Before executing the test mode included in the first schedule, it is necessary to detect whether the test mode included in the first schedule has been executed in the current FDTI cycle, and if it has been executed, the test model can be directly skipped execution, if it has not been executed, the test mode can be executed;
  • the first test mode when the first test mode needs to be executed for the first time in the target FDTI, it will be executed, and when the first test mode has been executed in the target FDTI, it will not be executed again Execute the first test mode in the target FDTI, so that the same test mode is only executed once in the FDTI, and will not be executed repeatedly, reducing the load of the test mode in the STL on the processor, and reducing the detection error of the processor time spent, thereby improving the processor's work efficiency.
  • the method further includes: acquiring a second schedule of the second task, the second schedule of the schedule includes In the first test mode, the target logic circuit is a logic circuit for performing the second task, and the second task is to be performed within a target fault detection time interval FDTI; based on the first test mode Executed in the target FDTI, the execution of the first test mode is skipped in the target FDTI.
  • the first test mode When the first test mode needs to be executed for the first time in the target FDTI, the first test mode can be executed, and the second task (the second task is different from the first task) needs to be executed in the FDTI, then it can be obtained
  • the second schedule of the second task, the second schedule of the schedule also includes the first test pattern, then when the task is scheduled, it may be based on the fact that the first test pattern has been executed in the target FDTI, The execution of the first test mode is skipped in the target FDTI, so that the first test mode is only executed once in the FDTI and will not be executed repeatedly.
  • the detecting whether the first test mode has been executed in the target FDTI includes: acquiring a first identifier corresponding to the first test mode, and the first identifier It is used to indicate whether the first test mode has been executed in the target FDTI.
  • the first identifier can be represented by a bit mask (for example, the bit mask can be STLMask), for example, when the bit STLMask corresponding to the first test pattern in the mask is 1, it means that the first test pattern is in the current FDTI It has already been executed in the cycle, for example, when the bit STLMask corresponding to the first test mode in the mask is 0, it means that the first test mode has not been executed in the current FDTI cycle.
  • the first identifier STLMask is set to 0, and the timer is enabled. The timer period is FDTI. Every time the timer is triggered, the first identifier is reset to 0, and the timing is reset. device. For example, before executing the first task, it may be determined that the first test mode has not been executed in the target FDTI based on detecting that the first identifier STLMask corresponding to the first test mode is 0.
  • the detecting that the first test mode has not been executed in the target FDTI includes: detecting that the first identifier corresponding to the first test mode indicates that the first The test mode has not been executed in the target FDTI; after the first test mode is executed in the target FDTI, the method further includes: modifying the first identifier so that the first An identifier indicating that the first test mode was executed within the target FDTI.
  • the method further includes: acquiring a second identifier corresponding to the first test mode, The second identifier is used to indicate whether the first test mode needs to be executed; before the execution of the first test mode in the target FDTI, the method further includes: detecting the second identifier to indicate that the first test mode needs to be executed.
  • the second identifier may be used to indicate whether the first test mode needs to be executed, and when the second identifier indicates that the first test mode needs to be executed, the first test mode is executed in the target FDTI, the first The second identifier is associated with the first identifier. Only when the first identifier indicates that the first test pattern has not been executed in the target FDTI, the second identifier indicates that the first test pattern needs to be executed. When the first identifier The identifier indicates that the first test mode has already been executed within the target FDTI, and the second identifier indicates that the first test mode does not need to be executed.
  • the method further includes: modifying the second identifier, so that the second identifier indicates the The first test mode need not be executed.
  • the target task includes a process or a thread.
  • the second aspect of the present application provides a terminal, the terminal includes: a processing unit and an acquisition unit; the acquisition unit is configured to acquire a first schedule of a first task, the first schedule includes a first test mode, and the first schedule a test mode for detecting errors of a target logic circuit, said target logic circuit being a logic circuit for performing said first task to be performed within a target fault detection time interval FDTI; the process a unit for detecting whether the first test mode has been executed within the target FDTI;
  • the processing unit is further configured to skip execution of the first test mode in the target FDTI if it is detected that the first test mode has been executed in the target FDTI .
  • the obtaining unit is further configured to obtain a second schedule of the second task after the first test mode is executed in the target FDTI, and the second schedule of the schedule includes the In a first test mode, the target logic circuit is a logic circuit for performing the second task, and the second task is for being performed within a target fault detection time interval FDTI;
  • the processing unit is further configured to skip execution of the first test mode in the target FDTI based on the first test mode being executed in the target FDTI.
  • the acquiring unit is further configured to acquire a first identifier corresponding to the first test pattern, where the first identifier is used to indicate whether the first test pattern is within the target FDTI been executed.
  • the processing unit is further configured to detect that the first identifier corresponding to the first test mode indicates that the first test mode has not been executed in the target FDTI;
  • the first identifier After execution of the first test mode within the target FDTI, the first identifier is modified such that the first identifier indicates that the first test mode was executed within the target FDTI.
  • the processing unit is further configured to acquire a second identifier corresponding to the first test mode after detecting that the first test mode has not been executed in the target FDTI, the The second identifier is used to indicate whether the first test mode needs to be executed;
  • detecting the second identifier indicates that the first test mode needs to be performed.
  • the processing unit is further configured to modify the second identifier after executing the first test mode in the target FDTI, so that the second identifier indicates the first Test mode does not need to be executed.
  • the target task includes a process or a thread.
  • a third aspect of the present application provides a terminal, where the terminal includes: a processor; the processor is configured to:
  • the first schedule includes a first test pattern, the first test pattern is used to detect errors in a target logic circuit, and the target logic circuit is used to execute the first logic circuitry for tasks, said first task being to be executed within a target fault detection time interval FDTI;
  • the processor is further configured to:
  • the execution of the first test mode in the target FDTI is skipped.
  • the processor is further configured to:
  • a second schedule for a second task is obtained, the second schedule includes the first test pattern, and the target logic circuit is used for executing logic circuitry for said second task, said second task being configured to be executed within a target fault detection time interval FDTI;
  • Execution of the first test mode is skipped in the target FDTI based on the first test mode being executed in the target FDTI.
  • the processor is specifically configured to:
  • the processor is specifically configured to:
  • the first identifier After execution of the first test mode within the target FDTI, the first identifier is modified such that the first identifier indicates that the first test mode was executed within the target FDTI.
  • the processor is further configured to:
  • detecting the second identifier indicates that the first test mode needs to be performed.
  • the processor is further configured to:
  • the second identifier After execution of the first test mode within the target FDTI, the second identifier is modified such that the second identifier indicates that the first test mode need not be executed.
  • the target task includes a process or a thread.
  • the fourth aspect of the present application provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is run on a computer, the computer executes the method according to any one of the implementation manners of the first aspect.
  • the fifth aspect of the present application provides a computer program product, which, when running on a computer, causes the computer to execute the method according to any one of the implementation manners of the first aspect.
  • a sixth aspect of the present application provides a chip, including one or more processors. Part or all of the processor is used to read and execute the computer program stored in the memory, so as to execute the method in any possible implementation manner of any aspect above.
  • the chip includes a memory, and the memory and the processor are connected to the memory through a circuit or wires.
  • the chip further includes a communication interface, and the processor is connected to the communication interface.
  • the communication interface is used to receive data and/or information to be processed, and the processor obtains the data and/or information from the communication interface, processes the data and/or information, and outputs the processing result through the communication interface.
  • the communication interface may be an input-output interface.
  • An embodiment of the present application provides an error detection method, including: acquiring a first schedule of a first task, the first schedule includes a first test mode, and the first test mode is used to detect an error of a target logic circuit , the target logic circuit is a logic circuit for performing the first task, the first task is used to be performed within a target fault detection time interval FDTI; detecting that the first test pattern is within the target FDTI Whether it has been executed; if it is detected that the first test mode has not been executed in the target FDTI, then according to the first schedule, execute the first test mode in the target FDTI to detect error in the target logic circuit.
  • Figure 1a is a schematic diagram of a FDTI and FHTI provided in the embodiment of the present application.
  • FIG. 1b is a schematic structural diagram of a terminal provided in an embodiment of the present application.
  • FIG. 1c is a schematic diagram of an application architecture provided by an embodiment of the present application.
  • FIG. 2 is a schematic flow chart of an error detection method provided in an embodiment of the present application.
  • FIG. 3 is a schematic flow chart of an error detection method provided in an embodiment of the present application.
  • FIG. 4 is a schematic flow chart of an error detection method provided in an embodiment of the present application.
  • FIG. 5 is a schematic flowchart of an error detection method provided in an embodiment of the present application.
  • FIG. 6 is a schematic diagram of an error detection method provided in an embodiment of the present application.
  • FIG. 7 is a schematic flowchart of an error detection method provided in an embodiment of the present application.
  • FIG. 8 is a schematic diagram of an error detection method provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a state transition provided by an embodiment of the present application.
  • FIG. 10 and FIG. 11 are schematic structural diagrams of a terminal provided by an embodiment of the present application.
  • data processing devices may experience random hardware failures, such as permanent failures caused by short circuits or open circuits in integrated circuits, or temporary failures such as bit flips caused by exposure to natural radiation or particle impact .
  • Functional safety means that there are no unacceptable risks due to electronic system failures, and its ultimate goal is to prevent personal casualties or huge property losses due to electronic system failures.
  • the safety mechanism must detect the error in the system and deal with the error in time to ensure that the system can reach a safe state before danger occurs.
  • the time interval from when an error occurs to when an error is detected is called the Fault Detection Time Interval (FDTI); the interval from when an error is detected to when the system reaches a safe state is called the Fault Handle Time Interval (FHTI).
  • FDTI Fault Detection Time Interval
  • FHTI Fault Handle Time Interval
  • FIG. 1 a is a schematic diagram of an FDTI and an FHTI provided in an embodiment of the present application.
  • DCLS Dual-core Lockstep
  • the implementation method of DCLS is: two processors run the same program, and input the output results of the two processors into a comparison logic to compare whether the output results of the two processors are the same. If the output results of the two processors are the same, it can be determined that no error has occurred; if the output results of the two processors are not identical, it can be determined that a processor error has occurred.
  • this error detection method can effectively detect errors, it requires two processors to run the same program, which has the disadvantages of high cost and poor flexibility.
  • the error detection method is to detect the error of the logic circuit by periodically executing the test mode in the STL by the processor. Compared with the DCLS, the error detection method has lower cost and higher flexibility. However, since there are often more logic circuits in the system, in order to realize error detection of all logic circuits, STL usually includes more test modes. Therefore, periodically executing the test mode in the STL by the processor will cause a heavy load on the processor, that is, the processor needs to spend more time to detect errors, thereby affecting the working efficiency of the processor.
  • the terminal can execute the test mode included in the schedule by determining the schedule corresponding to the currently running task. Since the dispatch table only includes the test pattern corresponding to the machine instruction code of the task, the terminal detects errors based on the dispatch table, and can avoid executing all test patterns in the software test library, thereby reducing the load on the processor. Effectively improve the working efficiency of the processor.
  • the scheduling of SBIST can be divided into two parts: Low level (LL) scheduling and High level (HL) scheduling.
  • LL scheduling mainly completes the work of saving and restoring the context of test mode switching in STL and calling specific test modes.
  • HL scheduling uses SBIST as a task scheduling, because the full amount of STL takes a long time, which has a great impact on the real-time system.
  • HL Schedule By introducing HL Schedule into the kernel, the flexibility of scheduling can be increased, which is more friendly to real-time systems and is more recommended. The way.
  • the HL scheduler obtains the running time and cycle of STL at a relatively coarse-grained level. It has less information awareness of the test mode in STL and cannot achieve fine-grained control.
  • FDTI In an FDTI, it is possible There will be multiple tasks that need to be executed, and in FDTI, the test mode corresponding to each of the above multiple tasks that need to be executed needs to be executed. However, the corresponding test modes between different tasks may be repeated. If the FDTI will If the test pattern corresponding to each task that needs to be executed is fully executed, multiple repeated test patterns may be executed.
  • the same test pattern only needs to be executed once to ensure the safety of the system, so the above The SBIST scheduling method will cause the SBIST task to block for a long time, which will lead to a large load on the processor, that is, the processor needs to spend more time to detect errors, thereby affecting the working efficiency of the processor.
  • the terminal involved in this embodiment of the present application may be a device used for data processing in a field with security requirements.
  • examples of some terminals are: vehicle-mounted terminals in transportation, control terminals in aerospace, wireless terminals in industrial control, wireless terminals in self driving, remote medical Wireless terminals in surgery, wireless terminals in smart grid, wireless terminals in transportation safety, wireless terminals in smart city, wireless terminals in smart home Wait.
  • FIG. 1b is a schematic structural diagram of a terminal 101 provided in an embodiment of the present application.
  • the terminal 101 includes a processor 103 , and the processor 103 is coupled to a system bus 105 .
  • the processor 103 may be one or more processors, each of which may include one or more processor cores.
  • a display adapter (video adapter) 107 which can drive a display 109, and the display 109 is coupled to the system bus 105.
  • the system bus 105 is coupled to an input-output (I/O) bus through a bus bridge 111 .
  • the I/O interface 115 is coupled to the I/O bus.
  • I/O interface 115 communicates with various I/O devices, such as input device 117 (such as: touch screen, etc.), multimedia disk (media tray) 121, (for example, CD-ROM (compact disc read-only memory, CD- ROM), multimedia interface, etc.).
  • Transceiver 123 which can send and/or receive radio communication signals
  • camera 155 which can capture still and moving digital video images
  • external USB port 125 external USB port 125 .
  • the interface connected to the I/O interface 115 may be a USB interface.
  • the processor 103 may be any conventional processor, including a reduced instruction set computing (reduced instruction set computing, RISC) processor, a complex instruction set computing (complex instruction set computing, CISC) processor or a combination of the above.
  • the processor may be a special purpose device such as an ASIC.
  • the terminal 101 can communicate with the software deployment server 149 through the network interface 129 .
  • the network interface 129 is a hardware network interface, such as a network card.
  • the network 127 may be an external network, such as the Internet, or an internal network, such as Ethernet or a virtual private network (virtual private network, VPN).
  • the network 127 may also be a wireless network, such as a WiFi network, a cellular network, and the like.
  • Hard disk drive interface 131 is coupled to system bus 105 .
  • the hardware driver interface is connected to the hard disk drive 133 .
  • System memory 135 is coupled to system bus 105 .
  • Data running in the system memory 135 may include an operating system (OS) 137 of the terminal 101 , application programs 143 and a scheduler.
  • OS operating system
  • the operating system includes a Shell 139 and a kernel (kernel) 141.
  • Shell 139 is an interface between the user and the kernel of the operating system.
  • the shell is the outermost layer of the operating system. The shell manages the interaction between the user and the operating system: waiting for user input, interpreting user input to the operating system, and processing various operating system output.
  • Kernel 141 consists of those parts of the operating system that manage memory, files, peripherals, and system resources.
  • the kernel 141 directly interacts with the hardware.
  • the operating system kernel usually runs processes, and provides inter-process communication, CPU time slice management, interrupt, memory management, IO management, and the like.
  • the application program 143 includes programs related to controlling car driving, for example, a program that manages the interaction between the self-driving car and obstacles on the road, and a program that controls the route or speed of the self-driving car, The program that controls the interaction between the self-driving car and other self-driving cars on the road.
  • the terminal 101 can download the application program 143 from the software deployment server 149 .
  • the terminal 101 may also download the schedule corresponding to the application program 143 from the software deployment server 149 .
  • the sensor 153 is associated with the terminal 101 .
  • the sensor 153 is used to detect the environment around the terminal 101 .
  • the sensor 153 can detect animals, cars, obstacles and crosswalks, etc.
  • the sensor 153 can also detect the environment around the above-mentioned animals, cars, obstacles and crosswalks, such as: the environment around the animal, for example, around the animal Other animals present, weather conditions, brightness of surroundings, etc.
  • the sensor may be a radar system or the like.
  • FIG. 2 is a schematic flowchart of an error detection method 200 provided in an embodiment of the present application. As shown in FIG. 2 , the error detection method 200 includes the following steps.
  • Step 201 Acquire a first schedule of a first task, the first schedule includes a first test mode, and the first test mode is used to detect errors in a target logic circuit, the target logic circuit is used to execute the The logic circuit of the first task is configured to be executed within the target fault detection time interval FDTI.
  • the terminal may execute the error detection method 200 periodically, for example, execute the error detection method 200 every 30 milliseconds or 50 milliseconds, so as to ensure that the error detection method 200 that has occurred can be detected in time. mistake.
  • the first task may be a task that needs to be executed in the target FDTI in the terminal, for example, may be a process or a thread that needs to be executed in the target FDTI in the terminal.
  • the way for the terminal to determine the first task may be to obtain it from the task queue.
  • the tasks in the task queue are tasks that are ready to be executed but have not been executed (or called tasks in the ready state).
  • the terminal can acquire the first task identifier (identifier , ID) to determine the first task, or determine the first task based on the data structure corresponding to the first task, for example, determine which thread the first task is based on the thread ID.
  • the first task when the first task is a process, the first task may be, for example, a vehicle video inspection process, a vehicle speed calculation process, a radar detection process, a vehicle anti-lock brake process, or a tire pressure detection process.
  • the scheduler in a non-deterministic scheduling scenario, will not predict the tasks that need to be executed in the next FDTI, and only after entering the FDTI, will it perceive in real time which task will be executed next , so the priority preemption mode is set for the SBIST task.
  • the STL subset including at least one test mode
  • the scheduler can perceive the tasks that need to be executed in the current FDTI in real time, and then perceive the first task.
  • the scheduler can predict the tasks that need to be executed in the next FDTI.
  • most tasks need to statically determine the worst case execution time (worst case execution time) time, WCET) time to determine the priority order, so for this scenario, the SBIST task is not suitable for the default high priority, but should adapt to the scheduling algorithm and perform deterministic scheduling arrangement; in this scenario, the scheduler can be in the current
  • the FDTI previously perceives the tasks that need to be performed in the FDTI, and then perceives the first task.
  • any task that can be run in the terminal may have a corresponding scheduling table.
  • These schedules may be preset in the terminal, for example, or may be generated by the terminal based on task-based machine instruction codes. Therefore, the terminal may determine the first scheduling table corresponding to the first task in multiple scheduling tables, for example, in the case that the first task is a process, the terminal may determine the corresponding first scheduling table based on the process ID.
  • At least one test mode (for example, including the first test mode and the second test mode mentioned in the embodiment of the present application) may be included, and the at least one test mode is related to the machine of the first task Corresponding to the instruction code, the at least one test mode is used to detect errors of the target logic circuit.
  • the correspondence between the at least one test pattern and the machine instruction code of the first task means that based on the at least one test pattern, the error detection of the target logic circuit on which the machine instruction code of the first task depends can be realized.
  • the terminal executes the machine instruction code, it needs to rely on the logic circuit in the terminal, that is, execute the machine instruction code based on the logic circuit. Therefore, when at least one test pattern corresponding to the machine instruction code of the first task is determined, the logic circuit used when the terminal executes the machine instruction code of the first task can be determined based on the at least one test pattern.
  • the terminal when the terminal is running the first task, if an error occurs in the logic circuit that needs to be used during the running of the first task, then the terminal may generate a security error due to the error of the logic circuit when running the first task. risk. Therefore, executing the test mode based on the schedule table corresponding to the first task can realize the error detection of the logic circuit that needs to be used, and avoid the occurrence of safety risks. For other logic circuits, since the current terminal does not perform corresponding tasks, that is, no other logic circuits are needed, so even if an error occurs in this part of the logic circuit, there will be no safety risk.
  • At least one test mode in the first scheduling table is determined based on a first mapping relationship and at least one instruction type
  • the first mapping relationship includes a mapping relationship between an instruction type and a test mode
  • at least one The instruction type is determined based on the second mapping relationship and the machine instruction code set of the target task
  • the second mapping relationship includes the mapping relationship between the machine instruction code and the instruction type
  • the machine instruction code set includes a plurality of machine instruction codes.
  • the first test mode may be determined based on the foregoing first mapping relationship and at least one instruction type.
  • the task in the running process of the system can be scanned for instructions, and each task generates a corresponding dispatch table (each dispatch table includes at least one test pattern), in the process of STL dispatch analysis,
  • the analyzer of the HL scheduler analyzes the SBIST test sequence in the current cycle based on the task queue information, FDTI time and the schedule of each task generated in the preprocessing stage.
  • the analysis results are generated
  • the device generates a set of STL test patterns to be scheduled, and in the process of LL scheduling, the STL test set delivered by HL is scheduled to run at the highest privilege level through LL scheduling.
  • Step 202 detecting whether the first test mode has been executed in the target FDTI.
  • the first test mode after acquiring the first schedule of the first task, it may be detected whether the first test mode has been executed in the target FDTI.
  • test pattern sets there may be overlap between test pattern sets corresponding to different tasks in the same FDTI (that is, the union of the two sets is not empty).
  • the executed test patterns within the FDTI are analyzed to generate a reasonable scheduling set.
  • test model before performing the execution of the test mode included in the first schedule, it is necessary to detect whether the test mode included in the first schedule has been executed in the current FDTI cycle, and if it has been executed, Then the execution of the test model can be directly skipped, and if it has not been executed, the test model can be executed.
  • the first identifier may be used to indicate whether the first test mode has been executed within the target FDTI.
  • the first identifier may indicate that the first test mode has not been executed in the target FDTI, and when the first test mode is executed for the first time in the FDTI, the first test mode may be modified. identifiers, such that the first identifier may indicate that the first test mode has been executed within the target FDTI.
  • the first test mode is in The target FDTI has not been executed.
  • the first identifier can be represented by a bit mask (for example, the bit mask can be STLMask), for example, when the bit STLMask corresponding to the first test pattern in the mask is 1, it means that the first test pattern is in It has already been executed in the current FDTI cycle. For example, when the bit STLMask corresponding to the first test mode in the mask is 0, it means that the first test mode has not been executed in the current FDTI cycle.
  • the first identifier STLMask is set to 0, and the timer is enabled. The timer period is FDTI. Every time the timer is triggered, the first identifier is reset to 0, and the timing is reset. device. For example, before executing the first task, it may be determined that the first test mode has not been executed in the target FDTI based on detecting that the first identifier STLMask corresponding to the first test mode is 0.
  • the second identifier may also be used to indicate whether the first test mode needs to be executed, and when the second identifier indicates that the first test mode needs to be executed, the first test mode is executed in the target FDTI, The second identifier is associated with the first identifier, and only when the first identifier indicates that the first test pattern has not been executed within the target FDTI, the second identifier indicates that the first test pattern needs to be executed, when the first The identifier indicates that the first test mode has already been executed within the target FDTI and the second identifier indicates that the first test mode does not need to be executed.
  • the first test mode needs to be performed based on detecting that the second identifier indicates that the first test mode needs to be performed.
  • the second identifier can be represented by a bit mask (for example, the bit mask can be STLNeedExcuteMask).
  • the bit STLNeedExcuteMask corresponding to the first test pattern in the mask is 1, it means that the first test The pattern still needs to be executed in the current FDTI cycle.
  • the bit STLNeedExcuteMask corresponding to the first test pattern in the mask is 0, it means that the first test pattern does not need to be executed in the current FDTI cycle.
  • the second identifier STLNeedExcuteMask When performing initialization for FDTI, the second identifier STLNeedExcuteMask is set to 0, and the timer is enabled, and the timer period is FDTI. Every time the timer is triggered, the second identifier STLNeedExcuteMask is reset to 0, and reset timer. For example, before executing the first task, it may be determined that the first test mode needs to be executed based on detecting that the second identifier STLNeedExcuteMask corresponding to the first test mode is 1.
  • Step 203 if it is detected that the first test mode has not been executed in the target FDTI, execute the first test mode in the target FDTI according to the first schedule to detect the Error in the target logic circuit.
  • the first test mode may be executed in the target FDTI according to the first schedule, If it is detected that the first test mode has been executed in the target FDTI, the execution of the first test mode in the target FDTI is skipped. That is, only when the first test mode needs to be executed for the first time in the target FDTI, it will be executed, and when the first test mode has been executed in the target FDTI, it will not be executed again. Execution of the first test mode is performed once within the target FDTI.
  • the first test mode when the first test mode needs to be executed for the first time in the target FDTI, the first test mode can be executed, and the second task (the second task and the first task) also needs to be executed in the FDTI. different tasks), then the second schedule of the second task can be obtained, and the second schedule of the schedule also includes the first test pattern, then during task scheduling, it can be based on the first test pattern in all has been executed in the target FDTI, the execution of the first test mode is skipped in the target FDTI, so that the first test mode is only executed once in the FDTI and will not be executed repeatedly.
  • the first identifier after executing the first test mode in the target FDTI, the first identifier may be modified, so that the first identifier indicates that the first test mode is in the Executed within the target FDTI.
  • the second identifier may be modified such that the second identifier indicates that the first test mode need not be executed. For example, the execution of the first test mode may be skipped in the target FDTI based on the second identifier indicating that the first test mode does not need to be executed, so that the first test mode is only executed once in the FDTI, will not be repeated.
  • the scheduler will not predict the tasks that need to be executed in the next FDTI, and only after entering the FDTI, will it perceive in real time which task to execute next , so the priority preemption mode is set for the SBIST task.
  • the STL subset including at least one test mode
  • the scheduler can perceive the tasks that need to be executed in the current FDTI in real time, and then perceive the tasks.
  • the scheduler dispatches a task in the ready state from the task queue, obtains the taskID of the task, and finds the corresponding STL subset according to the taskID of the task, that is, the test mode set. For each test mode in the STL subset, judge according to the STLMask Whether this test mode has been executed in the current FDTI cycle. If it has been executed, make the next round of judgment.
  • the abscissa represents time
  • the ordinate represents the priority of the task
  • each colored square represents the time slice of a task occupying the CPU at the current time.
  • FDTI cycle From the origin to the dotted line is an FDTI cycle.
  • the SBSIT task corresponding to the task will be run first.
  • What runs in the SBIST task is a collection of STL test patterns related to the task.
  • the SBIST task has a higher priority and cannot be interrupted during the execution of the test sequence.
  • the test pattern subsets of each task are guaranteed not to overlap with each other. For example, before executing task 3, the test pattern subset corresponding to task 3 can be executed (except the test patterns in the test pattern subset corresponding to task 2).
  • the scheduler can predict the tasks that need to be executed in the next FDTI.
  • most tasks need to statically determine the worst case execution time. time, WCET) time to determine the priority order, so for this scenario, the SBIST task is not suitable for the default high priority, but should adapt to the scheduling algorithm and perform deterministic scheduling arrangement; in this scenario, the scheduler can be in the current
  • the FDTI previously perceives the tasks that need to be performed within the FDTI, and then perceives the tasks.
  • the scheduler can schedule a task in the ready state from the task queue, and if the task is a normal task, the normal task will be executed.
  • the test mode in the SBIST task can be divided into three states, (not executed, not required to execute), (not executed, required to execute), (executed, not required to execute), The initial state is (not executed, does not need to be executed). After passing the analyzer, keep the test mode state as it is or be (not executed, need to execute). After the test mode is executed, the state of (not executed, required to be executed) is converted to (executed, not required to be executed).
  • the running time of the SBIST test sequence in the present invention is shortened by about 75% compared with the prior art.
  • An embodiment of the present application provides an error detection method, including: acquiring a first schedule of a first task, the first schedule includes a first test mode, and the first test mode is used to detect an error of a target logic circuit , the target logic circuit is a logic circuit for performing the first task, the first task is used to be performed within a target fault detection time interval FDTI; detecting that the first test pattern is within the target FDTI Whether it has been executed; if it is detected that the first test mode has not been executed in the target FDTI, then according to the first schedule, execute the first test mode in the target FDTI to detect errors in the target logic circuit.
  • FIG. 10 is a schematic structural diagram of a terminal 1000 provided in an embodiment of the present application.
  • the terminal 1000 includes: a processing unit 1001 and an acquiring unit 1002 .
  • the acquiring unit 1002 is used to acquire a first schedule of a first task, the first schedule includes a first test mode, and the first test mode is used to detect an error of a target logic circuit, and the target logic circuit is used A logic circuit for executing the first task, the first task is used to be executed within the target fault detection time interval FDTI; the processing unit 1001 is used to detect whether the first test mode is executed within the target FDTI executed;
  • the processing unit 1001 is further configured to skip the execution of the first test mode in the target FDTI if it is detected that the first test mode has been executed in the target FDTI. implement.
  • the obtaining unit 1002 is further configured to obtain a second schedule of the second task after the first test mode is executed in the target FDTI, and the second schedule of the schedule includes the In the first test mode, the target logic circuit is a logic circuit for performing the second task, and the second task is used to be performed within the target fault detection time interval FDTI;
  • the processing unit 1001 is further configured to skip execution of the first test mode in the target FDTI based on the first test mode being executed in the target FDTI.
  • the acquiring unit 1002 is further configured to acquire a first identifier corresponding to the first test pattern, where the first identifier is used to indicate that the first test pattern is within the target FDTI whether it has been executed.
  • the processing unit 1001 is further configured to detect that the first identifier corresponding to the first test mode indicates that the first test mode has not been executed in the target FDTI;
  • the first identifier After execution of the first test mode within the target FDTI, the first identifier is modified such that the first identifier indicates that the first test mode was executed within the target FDTI.
  • the processing unit 1001 is further configured to acquire a second identifier corresponding to the first test mode after detecting that the first test mode has not been executed in the target FDTI, so The second identifier is used to indicate whether the first test mode needs to be executed;
  • detecting the second identifier indicates that the first test mode needs to be performed.
  • the processing unit 1001 is further configured to modify the second identifier after executing the first test mode in the target FDTI, so that the second identifier indicates the first A test pattern need not be executed.
  • the target task includes a process or a thread.
  • the terminal device may be the information recommendation device in FIG. 11. Please refer to FIG. 11.
  • FIG. 1100 may specifically be embodied as a virtual reality VR device, a mobile phone, a tablet, a notebook computer, a smart wearable device, etc., which are not limited here.
  • the terminal device 1100 includes: a receiver 1101, a transmitter 1102, a processor 1103, and a memory 1104 (the number of processors 1103 in the terminal device 1100 may be one or more, and one processor is taken as an example in FIG. 11 ) , where the processor 1103 may include an application processor 11031 and a communication processor 11032 .
  • the receiver 1101, the transmitter 1102, the processor 1103, and the memory 1104 may be connected through a bus or in other ways.
  • the memory 1104 may include read-only memory and random-access memory, and provides instructions and data to the processor 1103 .
  • a part of the memory 1104 may also include a non-volatile random access memory (non-volatile random access memory, NVRAM).
  • NVRAM non-volatile random access memory
  • the memory 1104 stores processors and operating instructions, executable modules or data structures, or their subsets, or their extended sets, wherein the operating instructions may include various operating instructions for implementing various operations.
  • the processor 1103 controls the operation of the terminal device.
  • various components of the terminal device are coupled together through a bus system, where the bus system may include a power bus, a control bus, and a status signal bus in addition to a data bus.
  • the various buses are referred to as bus systems in the figures.
  • the methods disclosed in the foregoing embodiments of the present application may be applied to the processor 1103 or implemented by the processor 1103 .
  • the processor 1103 may be an integrated circuit chip, which has a signal processing capability. In the implementation process, each step of the above method may be implemented by an integrated logic circuit of hardware in the processor 1103 or instructions in the form of software.
  • the above-mentioned processor 1103 can be a general-purpose processor, a digital signal processor (digital signal processing, DSP), a microprocessor or a microcontroller, and can further include an application-specific integrated circuit (application specific integrated circuit, ASIC), field programmable Field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.
  • DSP digital signal processing
  • ASIC application specific integrated circuit
  • FPGA field programmable Field-programmable gate array
  • the processor 1103 may implement or execute various methods, steps, and logic block diagrams disclosed in the embodiments of the present application.
  • a general-purpose processor may be a microprocessor, or the processor may be any conventional processor, and the like.
  • the steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in a mature storage medium in the field such as random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, register.
  • the storage medium is located in the memory 1104, and the processor 1103 reads the information in the memory 1104, and completes the steps of the above method in combination with its hardware.
  • the processor 1103 can read the information in the memory 1104, and combine its hardware to complete the steps related to data processing in step 201 to step 203 in the above embodiment.
  • the receiver 1101 can be used to receive input digital or character information, and generate signal input related to related settings and function control of the terminal device.
  • the transmitter 1102 can be used to output digital or character information through the first interface; the transmitter 1102 can also be used to send instructions to the disk group through the first interface to modify the data in the disk group.
  • An embodiment of the present application further provides a computer program product, which, when running on a computer, causes the computer to execute the steps of the error detection method described in the embodiment corresponding to FIG. 2 in the above embodiments.
  • An embodiment of the present application also provides a computer-readable storage medium, the computer-readable storage medium stores a program for signal processing, and when it is run on a computer, the computer executes the method described in the foregoing embodiments The steps of the image processing method.
  • the image display device provided in the embodiment of the present application may specifically be a chip, and the chip includes: a processing unit and a communication unit, the processing unit may be, for example, a processor, and the communication unit may be, for example, an input/output interface, a pin or a circuit, etc. .
  • the processing unit can execute the computer-executed instructions stored in the storage unit, so that the chips in the execution device execute the data processing methods described in the above embodiments, or make the chips in the training device execute the data processing methods described in the above embodiments.
  • the storage unit is a storage unit in the chip, such as a register, a cache, etc.
  • the storage unit may also be a storage unit located outside the chip in the wireless access device, such as only Read-only memory (ROM) or other types of static storage devices that can store static information and instructions, random access memory (random access memory, RAM), etc.
  • ROM Read-only memory
  • RAM random access memory
  • the disclosed system, device and method can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.
  • the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or part of the contribution to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium includes: various media capable of storing program codes such as U disk, mobile hard disk, read-only memory, random access memory, magnetic disk or optical disk.

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Abstract

一种错误检测方法，涉及计算机技术领域，其中错误检测方法包括：获取第一任务的第一调度表，所述第一调度表包括第一测试模式，所述第一测试模式用于检测目标逻辑电路的错误，所述目标逻辑电路为用于执行所述第一任务的逻辑电路，所述第一任务用于在目标故障检测时间间隔FDTI内被执行；检测所述第一测试模式在所述目标FDTI内是否被执行过；若检测到所述第一测试模式在所述目标FDTI内未被执行过，则根据所述第一调度表，在所述目标FDTI 内执行所述第一测试模式。本申请保证了同一个测试模式在FDTI内只执行一次，而不会重复被执行，降低了STL中的测试模式对处理器的负载，降低了处理器检测错误所花费的时间，从而提高了处理器的工作效率。

Description

一种错误检测方法及相关装置
本申请要求于2021年6月11日提交中国专利局、申请号为202110657038.6、发明名称为“一种错误检测方法及相关装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机技术领域，尤其涉及一种错误检测方法及相关装置。
背景技术
在计算机领域，数据处理装置可能会发生随机性的硬件故障，例如由集成电路中的短路或断路引起的永久性故障，或由暴露于自然辐射或粒子撞击引起的诸如位翻转之类的临时故障。
在某些安全性要求较高的应用领域中，例如安全性至关重要的汽车领域，为了确保功能安全，可以为处理器提供错误检测机制，以检测硬件错误并确保在发生硬件错误的情况下执行安全操作。
目前，相关技术中通过由处理器周期性的执行软件测试库(Software Test Library，STL)中的测试模式(test pattern)来检测逻辑电路的错误。然而，由于STL中包括有较多的测试模式，处理器周期性地执行STL中的测试模式会导致处理器的负载较大，即处理器需要花费较多的时间来检测错误，从而影响了处理器的工作效率。
发明内容
本申请第一方面提供一种错误检测方法，应用于具有安全性要求领域中的终端，例如车载终端或航空航天中的控制终端。
该方法包括：获取第一任务的第一调度表，所述第一调度表包括第一测试模式，所述第一测试模式用于检测目标逻辑电路的错误，所述目标逻辑电路为用于执行所述第一任务的逻辑电路，所述第一任务用于在目标故障检测时间间隔FDTI内被执行；
其中，该第一任务可以为终端中在目标FDTI内需要运行的任务，例如可以为终端中在目标FDTI内需要运行的进程或线程。终端确定第一任务的方式可以是任务队列中获取，任务队列中的任务为准备执行且未执行的任务(或者称之为处于ready状态的任务)，终端可以通过获取第一任务的标识(identifier，ID)来确定第一任务，或者基于第一任务对应的数据结构来确定第一任务；在第一任务所对应的调度表中，可以包括有至少一个测试模式(例如包括本申请实施例提及的第一测试模式以及第二测试模式)，该至少一个测试模式与第一任务的机器指令码对应，该至少一个测试模式用于检测目标逻辑电路的错误。其中，该至少一个测试模式与第一任务的机器指令码对应是指基于该至少一个测试模式，可以实现执行第一任务的机器指令码时所依赖的目标逻辑电路的错误检测；
检测所述第一测试模式在所述目标FDTI内是否被执行过；若检测到所述第一测试模式在所述目标FDTI内未被执行过，则根据所述第一调度表，在所述目标FDTI内执行所述 第一测试模式，以检测所述目标逻辑电路的错误；
在同一个FDTI内的不同任务对应的测试模式集合之间可能会存在重合的情况(即两个集合的并集不为空)。为了避免一个FDTI周期内测试模式的的重复执行，会对FDTI内的已执行的测试模式进行分析，生成合理的调度集合。在进行第一调度表包括的测试模式的执行之前，需要检测第一调度表包括的测试模式在当前的FDTI周期内是否已经被执行过，如果已经被执行过，则可以直接跳过该测试模型的执行，如果没有被执行过，则可以执行该测试模式；
本申请中，当第一测试模式在所述目标FDTI内是第一次需要被执行时，才会执行，而当第一测试模式在所述目标FDTI内已经被执行过时，则不会再一次在目标FDTI内进行第一测试模式的执行，使得同一个测试模式在FDTI内只执行一次，而不会重复被执行，降低了STL中的测试模式对处理器的负载，降低了处理器检测错误所花费的时间，从而提高了处理器的工作效率。
在一些可能的实现方式中，所述在所述目标FDTI内执行所述第一测试模式之后，所述方法还包括：获取第二任务的第二调度表，所述调度表第二调度表包括所述第一测试模式，所述目标逻辑电路为用于执行所述第二任务的逻辑电路，所述第二任务用于在目标故障检测时间间隔FDTI内被执行；基于所述第一测试模式在所述目标FDTI内被执行过，在所述目标FDTI内跳过所述第一测试模式的执行。
当第一测试模式在所述目标FDTI内是第一次需要被执行时，可以执行第一测试模式，而FDTI内还需要执行第二任务(第二任务和第一任务不同)，则可以获取第二任务的第二调度表，所述调度表第二调度表也包括所述第一测试模式，则在任务调度时，可以基于所述第一测试模式在所述目标FDTI内被执行过，在所述目标FDTI内跳过所述第一测试模式的执行，进而使得第一测试模式在FDTI内只执行一次，而不会重复被执行。
在一些可能的实现方式中，所述检测所述第一测试模式在所述目标FDTI内是否被执行过，包括：获取所述第一测试模式对应的第一标识符，所述第一标识符用于指示所述第一测试模式在所述目标FDTI内是否被执行过。
其中，第一标识符可以通过位掩码来表示(例如位掩码可以为STLMask)，例如当掩码中与第一测试模式对应的位STLMask为1时，表示该第一测试模式在当前FDTI周期中已经执行过，如当掩码中与第一测试模式对应的位STLMask为0时，表示第一测试模式在当前FDTI周期中还未执行。在进行针对于FDTI的初始化时，第一标识符STLMask置为0，并使能定时器，定时器周期为FDTI，定时器每触发一次，重置一次第一标识符为0，并重置定时器。例如，在执行第一任务之前，可以基于检测到所述第一测试模式对应的第一标识符STLMask为0，来确定第一测试模式在所述目标FDTI内未被执行过。
在一些可能的实现方式中，所述检测到所述第一测试模式在所述目标FDTI内未被执行过，包括：检测到所述第一测试模式对应的第一标识符指示所述第一测试模式在所述目 标FDTI内未被执行过；所述在所述目标FDTI内执行所述第一测试模式之后，所述方法还包括：修改所述第一标识符，以使得所述第一标识符指示所述第一测试模式在所述目标FDTI内被执行过。
在一些可能的实现方式中，所述检测到所述第一测试模式在所述目标FDTI内未被执行过之后，所述方法还包括：获取所述第一测试模式对应的第二标识符，所述第二标识符用于指示所述第一测试模式是否需要被执行；所述在所述目标FDTI内执行所述第一测试模式之前，所述方法还包括：检测到所述第二标识符指示所述第一测试模式需要被执行。
其中，可以通过第二标识符来指示所述第一测试模式是否需要被执行，当第二标识符指示所述第一测试模式需要被执行时，才在目标FDTI内执行第一测试模式，第二标识符和第一标识符相关联，只有当第一标识符指示第一测试模式在目标FDTI内未被执行过时，第二标识符才会指示第一测试模式需要被执行，当第一标识符指示第一测试模式在目标FDTI内已经被执行过时，第二标识符指示第一测试模式不需要被执行。
在一些可能的实现方式中，所述在所述目标FDTI内执行所述第一测试模式之后，所述方法还包括：修改所述第二标识符，以使得所述第二标识符指示所述第一测试模式不需要被执行。
在一些可能的实现方式中，所述目标任务包括进程或线程。
本申请第二方面提供一种终端，该终端包括：处理单元和获取单元；该获取单元用于获取第一任务的第一调度表，所述第一调度表包括第一测试模式，所述第一测试模式用于检测目标逻辑电路的错误，所述目标逻辑电路为用于执行所述第一任务的逻辑电路，所述第一任务用于在目标故障检测时间间隔FDTI内被执行；该处理单元用于检测所述第一测试模式在所述目标FDTI内是否被执行过；
若检测到所述第一测试模式在所述目标FDTI内未被执行过，则在所述目标FDTI内执行所述第一测试模式，以检测所述目标逻辑电路的错误。
在一些可能的实现方式中，该处理单元还用于若检测到所述第一测试模式在所述目标FDTI内被执行过，则在所述目标FDTI内跳过所述第一测试模式的执行。
在一些可能的实现方式中，该获取单元还用于在所述目标FDTI内执行所述第一测试模式之后，获取第二任务的第二调度表，所述调度表第二调度表包括所述第一测试模式，所述目标逻辑电路为用于执行所述第二任务的逻辑电路，所述第二任务用于在目标故障检测时间间隔FDTI内被执行；
该处理单元还用于基于所述第一测试模式在所述目标FDTI内被执行过，在所述目标FDTI内跳过所述第一测试模式的执行。
在一些可能的实现方式中，该获取单元还用于获取所述第一测试模式对应的第一标识符，所述第一标识符用于指示所述第一测试模式在所述目标FDTI内是否被执行过。
在一些可能的实现方式中，该处理单元还用于检测到所述第一测试模式对应的第一标识符指示所述第一测试模式在所述目标FDTI内未被执行过；
在所述目标FDTI内执行所述第一测试模式之后，修改所述第一标识符，以使得所述第一标识符指示所述第一测试模式在所述目标FDTI内被执行过。
在一些可能的实现方式中，该处理单元还用于检测到所述第一测试模式在所述目标FDTI内未被执行过之后，获取所述第一测试模式对应的第二标识符，所述第二标识符用于指示所述第一测试模式是否需要被执行；
在所述目标FDTI内执行所述第一测试模式之前，检测到所述第二标识符指示所述第一测试模式需要被执行。
在一些可能的实现方式中，该处理单元还用于在所述目标FDTI内执行所述第一测试模式之后，修改所述第二标识符，以使得所述第二标识符指示所述第一测试模式不需要被执行。
在一些可能的实现方式中，所述目标任务包括进程或线程。
本申请实施例只有当第一测试模式在所述目标FDTI内是第一次需要被执行时，才会执行，而当第一测试模式在所述目标FDTI内已经被执行过时，则不会再一次在目标FDTI内进行第一测试模式的执行，使得同一个测试模式在FDTI内只执行一次，而不会重复被执行，降低了STL中的测试模式对处理器的负载，降低了处理器检测错误所花费的时间，从而提高了处理器的工作效率。
本申请第三方面提供一种终端，该终端包括：处理器；所述处理器用于：
获取第一任务的第一调度表，所述第一调度表包括第一测试模式，所述第一测试模式用于检测目标逻辑电路的错误，所述目标逻辑电路为用于执行所述第一任务的逻辑电路，所述第一任务用于在目标故障检测时间间隔FDTI内被执行；
检测所述第一测试模式在所述目标FDTI内是否被执行过；
若检测到所述第一测试模式在所述目标FDTI内未被执行过，则在所述目标FDTI内执行所述第一测试模式，以检测所述目标逻辑电路的错误。
在一些可能的实现方式中，所述处理器还用于：
若检测到所述第一测试模式在所述目标FDTI内被执行过，则在所述目标FDTI内跳过所述第一测试模式的执行。
在一些可能的实现方式中，所述处理器还用于：
在所述目标FDTI内执行所述第一测试模式之后，获取第二任务的第二调度表，所述调度表第二调度表包括所述第一测试模式，所述目标逻辑电路为用于执行所述第二任务的逻辑电路，所述第二任务用于在目标故障检测时间间隔FDTI内被执行；
基于所述第一测试模式在所述目标FDTI内被执行过，在所述目标FDTI内跳过所述第一测试模式的执行。
在一些可能的实现方式中，所述处理器具体用于：
获取所述第一测试模式对应的第一标识符，所述第一标识符用于指示所述第一测试模式在所述目标FDTI内是否被执行过。
在一些可能的实现方式中，所述处理器具体用于：
检测到所述第一测试模式对应的第一标识符指示所述第一测试模式在所述目标FDTI 内未被执行过；
在所述目标FDTI内执行所述第一测试模式之后，修改所述第一标识符，以使得所述第一标识符指示所述第一测试模式在所述目标FDTI内被执行过。
在一些可能的实现方式中，所述处理器还用于：
检测到所述第一测试模式在所述目标FDTI内未被执行过之后，获取所述第一测试模式对应的第二标识符，所述第二标识符用于指示所述第一测试模式是否需要被执行；
在所述目标FDTI内执行所述第一测试模式之前，检测到所述第二标识符指示所述第一测试模式需要被执行。
在一些可能的实现方式中，所述处理器还用于：
在所述目标FDTI内执行所述第一测试模式之后，修改所述第二标识符，以使得所述第二标识符指示所述第一测试模式不需要被执行。
在一些可能的实现方式中，所述目标任务包括进程或线程。
本申请第四方面提供一种计算机可读存储介质，计算机可读存储介质中存储有计算机程序，当其在计算机上运行时，使得计算机执行如第一方面任意一种实现方式的方法。
本申请第五方面提供一种计算机程序产品，当其在计算机上运行时，使得计算机执行如第一方面任意一种实现方式的方法。
本申请第六方面提供一种芯片，包括一个或多个处理器。处理器中的部分或全部用于读取并执行存储器中存储的计算机程序，以执行上述任一方面任意可能的实现方式中的方法。可选地，该芯片该包括存储器，该存储器与该处理器通过电路或电线与存储器连接。进一步可选地，该芯片还包括通信接口，处理器与该通信接口连接。通信接口用于接收需要处理的数据和/或信息，处理器从该通信接口获取该数据和/或信息，并对该数据和/或信息进行处理，并通过该通信接口输出处理结果。该通信接口可以是输入输出接口。本申请提供的方法可以由一个芯片实现，也可以由多个芯片协同实现。
本申请实施例提供了一种错误检测方法，包括：获取第一任务的第一调度表，所述第一调度表包括第一测试模式，所述第一测试模式用于检测目标逻辑电路的错误，所述目标逻辑电路为用于执行所述第一任务的逻辑电路，所述第一任务用于在目标故障检测时间间隔FDTI内被执行；检测所述第一测试模式在所述目标FDTI内是否被执行过；若检测到所述第一测试模式在所述目标FDTI内未被执行过，则根据所述第一调度表，在所述目标FDTI内执行所述第一测试模式，以检测所述目标逻辑电路的错误。只有当第一测试模式在所述目标FDTI内是第一次需要被执行时，才会执行，而当第一测试模式在所述目标FDTI内已经被执行过时，则不会再一次在目标FDTI内进行第一测试模式的执行，使得同一个测试模式在FDTI内只执行一次，而不会重复被执行，降低了STL中的测试模式对处理器的负载，降低了处理器检测错误所花费的时间，从而提高了处理器的工作效率。
附图说明
图1a为本申请实施例提供的一种FDTI和FHTI的示意图；
图1b为本申请实施例提供的一种终端的结构示意图；
图1c为本申请实施例提供的一种应用架构示意图；
图2为本申请实施例提供的一种错误检测方法的流程示意图；
图3为本申请实施例提供的一种错误检测方法的流程示意图；
图4为本申请实施例提供的一种错误检测方法的流程示意图；
图5为本申请实施例提供的一种错误检测方法的流程示意图；
图6为本申请实施例提供的一种错误检测方法的示意图；
图7为本申请实施例提供的一种错误检测方法的流程示意图；
图8为本申请实施例提供的一种错误检测方法的示意图；
图9为本申请实施例提供的一种状态转换示意图；
图10和图11为本申请实施例提供的一种终端的结构示意图。
具体实施方式
下面结合附图，对本申请的实施例进行描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。本领域普通技术人员可知，随着技术的发展和新场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或模块的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或模块，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或模块。在本申请中出现的对步骤进行的命名或者编号，并不意味着必须按照命名或者编号所指示的时间/逻辑先后顺序执行方法流程中的步骤，已经命名或者编号的流程步骤可以根据要实现的技术目的变更执行次序，只要能达到相同或者相类似的技术效果即可。
在计算机领域，数据处理装置可能会发生随机性的硬件故障，例如由集成电路中的短路或断路引起的永久性故障，或由暴露于自然辐射或粒子撞击引起的诸如位翻转之类的临时故障。
随着数据处理装置在大量的领域中广泛应用，为避免由于数据处理装置所发生的硬件故障而带来的损失，人们提出了“功能安全”的概念。功能安全是指不存在由于电子系统故障引起的不可接受的风险，其最终目标是防止由于电子系统故障而造成人员伤亡或带来巨大的财产损失。
在安全性要求较高的领域中，例如航空航天、交通运输以及医疗等领域，为满足功能安全的要求，均具有相应的安全机制。这些安全机制都必须保证系统在检测到错误后达到安全状态，以防止造成危害。例如，在汽车领域中，典型的安全风险通常是由防抱死系统或动力转向系统的电子控制单元发生错误而引起的。在防抱死系统或动力转向系统的电子控制单元发生错误的情况下，可能会导致汽车发生致命的碰撞。为保证系统能够达到安全状态以防止安全风险事件的发生，需要及时检测到已发生的错误并处理这些错误。
简单来说，当系统发生错误时，安全机制必须检测到系统所发生的错误并及时处理该错误，确保系统能够在产生危险之前达到安全状态。通常，从错误发生到检测到错误的时间间隔称为错误检测时间(Fault Detection Time Interval，FDTI)；从检测到错误到系统达到安全状态的间隔则称为错误处理时间(Fault Handle Time Interval，FHTI)。示例性地，可以参阅图1a，图1a为本申请实施例提供的一种FDTI和FHTI的示意图。为避免产生危险，在系统发生错误之后，系统必须在一定的期限内达到安全状态，即FDTI和FHTI之和必须小于或等于某一时间阈值。因此，为了保证能够有足够长的FHTI来处理错误，以确保能够顺利地处理错误，尽可能地缩短FDTI则显得至关重要。
目前，相关技术中实现错误检测的一种方法为双核锁步(Dual-core Lockstep,DCLS)。DCLS的实现方法是：两个处理器运行同样的程序，并将两个处理器的输出结果输入至一个比较逻辑中，以比较两个处理器的输出结果是否相同。如果两个处理器的输出结果相同，则可以确定没有发生错误；如果两个处理器的输出结果不相同，则可以确定处理器发生了错误。这种错误检测的方式虽然能够有效地检测到错误，但是需要用到两个处理器来运行相同的程序，具有成本高和灵活性差的缺点。
因此，相关技术中提供了另一种基于软件的错误检测方法：软件内置自测(software-based built-in self-test，SBIST)。该错误检测方法为通过由处理器周期性执行STL中的测试模式来检测逻辑电路的错误，相比于DCLS，该错误检测方法的成本较低且灵活性较高。然而，由于系统中往往具有较多的逻辑电路，为实现所有逻辑电路的错误检测，STL中通常包括有较多的测试模式。因此，处理器周期性地执行STL中的测试模式会导致处理器的负载较大，即处理器需要花费较多的时间来检测错误，从而影响了处理器的工作效率。
有鉴于此，终端在执行错误检测的过程中，可以通过确定当前运行的任务所对应的调度表，来执行该调度表中所包括的测试模式。由于该调度表中仅包括与该任务的机器指令码所对应的测试模式，因此终端基于该调度表来检测错误，能够避免执行软件测试库中的所有测试模式，从而降低了处理器的负载，有效地提高了处理器的工作效率。
参照图1c，SBIST的调度可以分成两个部分：Low level(LL)调度和High level(HL)调度。其中，LL调度主要完成一些STL中测试模式切换的上下文保存、恢复以及调用具体的测试模式的工作。HL调度将SBIST作为一个任务调度，因为全量的STL耗时较长，这样对系统的实时影响较大，通过在内核引入HL Schedule，可以增加调度的弹性，对于实时系统更为友好，也是更推荐的方式。
然而，在现有的实现中，HL调度器相对粗粒度的获取STL的运行时间和周期，对于STL中的测试模式的信息感知较少，无法做到细粒度的控制，在一个FDTI内，可能会存在多个需要执行的任务，且在FDTI内，需要执行上述多个需要执行的任务中每个任务对应的测试模式，然而不同的任务之间对应的测试模式可能重复，如果再FDTI内将每个需要执行的任务对应的测试模式都完整执行，则可能会出现多个重复的测试模型被执行，由于在一个FDTI内，同一个测试模式只需要执行一次就可以保证系统的安全，因此上述SBIST的调度方式会使SBIST任务阻塞时间长，进而导致处理器的负载较大，即处理器需 要花费较多的时间来检测错误，从而影响了处理器的工作效率。
本申请实施例所涉及的终端可以为具有安全性要求的领域中用于数据处理的设备。目前，一些终端的举例为：交通运输中的车载终端、航空航天中的控制终端、工业控制(industrial control)中的无线终端、无人驾驶(self driving)中的无线终端、远程手术(remote medical surgery)中的无线终端、智能电网(smart grid)中的无线终端、运输安全(transportation safety)中的无线终端、智慧城市(smart city)中的无线终端、智慧家庭(smart home)中的无线终端等。
可以参阅图1b，图1b为本申请实施例提供的一种终端101的结构示意图。
如图1b所示，终端101包括处理器103，处理器103和系统总线105耦合。处理器103可以是一个或者多个处理器，其中每个处理器都可以包括一个或多个处理器核。显示适配器(video adapter)107，显示适配器可以驱动显示器109，显示器109和系统总线105耦合。系统总线105通过总线桥111和输入输出(I/O)总线耦合。I/O接口115和I/O总线耦合。I/O接口115和多种I/O设备进行通信，比如输入设备117(如：触摸屏等)，多媒体盘(media tray)121,(例如，只读光盘(compact disc read-only memory，CD-ROM)，多媒体接口等)。收发器123(可以发送和/或接收无线电通信信号)，摄像头155(可以捕捉静态和动态数字视频图像)和外部USB端口125。其中，可选地，和I/O接口115相连接的接口可以是USB接口。
其中，处理器103可以是任何传统处理器，包括精简指令集计算(reduced instruction set Computing，RISC)处理器、复杂指令集计算(complex instruction set computing，CISC)处理器或上述的组合。可选地，处理器可以是诸如ASIC的专用装置。
终端101可以通过网络接口129和软件部署服务器149通信。示例性的，网络接口129是硬件网络接口，比如，网卡。网络127可以是外部网络，比如因特网，也可以是内部网络，比如以太网或者虚拟私人网络(virtual private network，VPN)。可选地，网络127还可以是无线网络，比如WiFi网络，蜂窝网络等。
硬盘驱动器接口131和系统总线105耦合。硬件驱动接口和硬盘驱动器133相连接。系统内存135和系统总线105耦合。运行在系统内存135的数据可以包括终端101的操作系统(OS)137、应用程序143和调度表。
操作系统包括Shell 139和内核(kernel)141。Shell 139是介于使用者和操作系统的内核间的一个接口。shell是操作系统最外面的一层。shell管理使用者与操作系统之间的交互：等待使用者的输入，向操作系统解释使用者的输入，并且处理各种各样的操作系统的输出结果。
内核141由操作系统中用于管理存储器、文件、外设和系统资源的那些部分组成。内核141直接与硬件交互，操作系统内核通常运行进程，并提供进程间的通信，提供CPU时间片管理、中断、内存管理和IO管理等等。
示例性地，在终端101为车载终端的情况下，应用程序143包括控制汽车驾驶相关的程序，比如，管理自动驾驶的汽车和路上障碍物交互的程序，控制自动驾驶汽车路线或者速度的程序，控制自动驾驶汽车和路上其他自动驾驶汽车交互的程序。在一个实施例中， 在需要执行应用程序143时，终端101可以从软件部署服务器149下载应用程序143。在一个实施例中，在终端101从软件部署服务器149下载应用程序143时，终端101也可以从软件部署服务器149下载与该应用程序143对应的调度表。
传感器153和终端101关联。传感器153用于探测终端101周围的环境。举例来说，传感器153可以探测动物，汽车，障碍物和人行横道等，进一步传感器153还可以探测上述动物，汽车，障碍物和人行横道等物体周围的环境，比如：动物周围的环境，例如，动物周围出现的其他动物，天气条件，周围环境的光亮度等。可选地，如果终端101位于自动驾驶的汽车上，传感器可以是雷达系统等。
以上介绍了本申请实施例所提供的错误检测方法的应用场景，以下将详细介绍该错误检测方法的执行过程。
可以参阅图2，图2为本申请实施例提供的一种错误检测方法200的流程示意图。如图2所示，该错误检测方法200包括以下的步骤。
步骤201，获取第一任务的第一调度表，所述第一调度表包括第一测试模式，所述第一测试模式用于检测目标逻辑电路的错误，所述目标逻辑电路为用于执行所述第一任务的逻辑电路，所述第一任务用于在目标故障检测时间间隔FDTI内被执行。
本实施例中，在终端正常运行的过程中，终端可以周期性地执行该错误检测方法200，例如每隔30毫秒或50毫秒执行一次该错误检测方法200，以确保能够及时检测到已发生的错误。
在一个可能的实施例中，该第一任务可以为终端中在目标FDTI内需要运行的任务，例如可以为终端中在目标FDTI内需要运行的进程或线程。终端确定第一任务的方式可以是任务队列中获取，任务队列中的任务为准备执行且未执行的任务(或者称之为处于ready状态的任务)，终端可以通过获取第一任务的标识(identifier，ID)来确定第一任务，或者基于第一任务对应的数据结构来确定第一任务，例如基于线程ID确定第一任务具体是哪一个线程。示例性地，在第一任务为进程的情况下，该第一任务例如可以为车辆视频检查进程、车速计算进程、雷达检测进程、车辆防抱死进程或胎压检测进程等进程。
在一个可能的实施例中，在非确定性调度场景中，调度器不会预知接下来的一个FDTI内需要执行的任务，只有当进入该FDTI后，才会实时感知接下来要执行哪一个任务，因此对SBIST任务设置了优先级抢占方式，在FDTI内，每个普通任务(非SBIST任务)的执行之前会不可中断的执行该任务所对应的STL子集(包括至少一个测试模式)；在该场景中，调度器可以实时感知当前FDTI内需要执行的任务，进而感知到第一任务。
在一个可能的实施例中，在确定性调度场景中，调度器可以预知接下来的一个FDTI内需要执行的任务，为保证确定调度，大部分任务都需要静态确定最坏运行时间(worst Case execution time，WCET)时间，以此确定优先级排序，因此对于该场景下，SBIST任务不适合默认高优先级，而应该适应调度算法，进行确定性调度排列；在该场景中，调度器可以在当前FDTI之前感知到FDTI内需要执行的任务，进而感知到第一任务。
本实施例中，对于终端中可运行的任意一个任务，均可以具有对应的调度表。这些调 度表例如可以是预置于终端中的，也可以是由终端基于任务的机器指令码所生成的。因此，终端可以在多个调度表中确定第一任务所对应的第一调度表，例如在第一任务为进程的情况下，终端可以基于进程ID确定与其对应的第一调度表。
在第一任务所对应的调度表中，可以包括有至少一个测试模式(例如包括本申请实施例提及的第一测试模式以及第二测试模式)，该至少一个测试模式与第一任务的机器指令码对应，该至少一个测试模式用于检测目标逻辑电路的错误。其中，该至少一个测试模式与第一任务的机器指令码对应是指基于该至少一个测试模式，可以实现执行第一任务的机器指令码时所依赖的目标逻辑电路的错误检测。
简单来说，终端在执行机器指令码时，需要依赖于终端中的逻辑电路，即基于逻辑电路来执行机器指令码。因此，在确定了第一任务的机器指令码对应的至少一个测试模式的情况下，对于终端执行该第一任务的机器指令码时所使用到的逻辑电路，均可以基于该至少一个测试模式来实现错误的检测；
可以理解的是，在终端运行第一任务的过程中，如果第一任务运行过程中需要使用到的逻辑电路发生了错误，那么终端运行该第一任务时可能会由于逻辑电路的错误而产生安全风险。因此，基于该第一任务对应的调度表来执行测试模式，可以实现需要使用到的逻辑电路的错误检测，避免安全风险的产生。对于其他的逻辑电路，由于当前终端并没有执行相应的任务，即不需要使用到其他的逻辑电路，因此即便这部分逻辑电路发生了错误，也不会产生安全风险。
在一个可能的实施例中，第一调度表中的至少一个测试模式是基于第一映射关系和至少一个指令类型确定的，第一映射关系包括指令类型与测试模式之间的映射关系，至少一个指令类型是基于第二映射关系和目标任务的机器指令码集合确定的，第二映射关系包括机器指令码与指令类型之间的映射关系，机器指令码集合包括多个机器指令码。例如，可以基于上述第一映射关系和至少一个指令类型确定第一测试模式。
参照图3，在预处理过程：可以对系统运行过程中的任务进行指令扫描，每个任务都生成对应的调度表(每个调度表包括至少一个测试模式)，在STL调度分析的过程中，HL调度器的分析器基于任务队列信息与FDTI时间和在预处理阶段生成的每个任务的调度表，对当前周期内的SBIST测试序列进行分析，在STL调度生成的过程中，分析结果经过生成器，生成待调度的STL测试模式集合，并在LL调度过程中，由HL传递的STL测试集合通过LL调度在最高特权层进行调度运行。
步骤202，检测所述第一测试模式在所述目标FDTI内是否被执行过。
在一个可能的实施例中，在获取第一任务的第一调度表之后，可以检测第一测试模式在所述目标FDTI内是否被执行过。
本申请实施例中，在同一个FDTI内的不同任务对应的测试模式集合之间可能会存在重合的情况(即两个集合的并集不为空)。为了避免一个FDTI周期内测试模式的的重复执行，会对FDTI内的已执行的测试模式进行分析，生成合理的调度集合。
在一个可能的实施例中，在进行第一调度表包括的测试模式的执行之前，需要检测第 一调度表包括的测试模式在当前的FDTI周期内是否已经被执行过，如果已经被执行过，则可以直接跳过该测试模型的执行，如果没有被执行过，则可以执行该测试模式。
接下来描述如何检测第一测试模式在所述目标FDTI内是否被执行过；
在一个可能的实施例中，可以使用第一标识符来指示第一测试模式在所述目标FDTI内是否被执行过。在进行针对于FDTI的初始化时，可以第一标识符可以指示第一测试模式在所述目标FDTI内未被执行过，而当第一测试模式在FDTI第一次被执行后，可以修改第一标识符，使得第一标识符可以指示第一测试模式在所述目标FDTI内被执行过。
例如，在执行第一任务之前，可以基于检测到所述第一测试模式对应的第一标识符指示所述第一测试模式在所述目标FDTI内未被执行过，来确定第一测试模式在所述目标FDTI内未被执行过。
示例性的，第一标识符可以通过位掩码来表示(例如位掩码可以为STLMask)，例如当掩码中与第一测试模式对应的位STLMask为1时，表示该第一测试模式在当前FDTI周期中已经执行过，如当掩码中与第一测试模式对应的位STLMask为0时，表示第一测试模式在当前FDTI周期中还未执行。在进行针对于FDTI的初始化时，第一标识符STLMask置为0，并使能定时器，定时器周期为FDTI，定时器每触发一次，重置一次第一标识符为0，并重置定时器。例如，在执行第一任务之前，可以基于检测到所述第一测试模式对应的第一标识符STLMask为0，来确定第一测试模式在所述目标FDTI内未被执行过。
此外，还可以通过第二标识符来指示所述第一测试模式是否需要被执行，当第二标识符指示所述第一测试模式需要被执行时，才在目标FDTI内执行第一测试模式，第二标识符和第一标识符相关联，只有当第一标识符指示第一测试模式在目标FDTI内未被执行过时，第二标识符才会指示第一测试模式需要被执行，当第一标识符指示第一测试模式在目标FDTI内已经被执行过时，第二标识符指示第一测试模式不需要被执行。
例如，在执行第一任务之前，可以基于检测到所述第二标识符指示所述第一测试模式需要被执行，来确定第一测试模式需要被执行。
示例性的，参照图4，第二标识符可以通过位掩码来表示(例如位掩码可以为STLNeedExcuteMask)当掩码中与第一测试模式相对应的位STLNeedExcuteMask为1时，表示第一测试模式在当前FDTI周期中仍需执行，当掩码中与第一测试模式相对应的位STLNeedExcuteMask为0时，表示第一测试模式在当前FDTI周期中不需要执行。
在进行针对于FDTI的初始化时，第二标识符STLNeedExcuteMask置为0，并使能定时器，定时器周期为FDTI，定时器每触发一次，重置一次第二标识符STLNeedExcuteMask为0，并重置定时器。例如，在执行第一任务之前，可以基于检测到所述第一测试模式对应的第二标识符STLNeedExcuteMask为1，来确定第一测试模式需要被执行。
步骤203，若检测到所述第一测试模式在所述目标FDTI内未被执行过，则根据所述第一调度表，在所述目标FDTI内执行所述第一测试模式，以检测所述目标逻辑电路的错误。
本申请实施例中，若检测到所述第一测试模式在所述目标FDTI内未被执行过，则可以根据所述第一调度表，在所述目标FDTI内执行所述第一测试模式，若检测到所述第一 测试模式在所述目标FDTI内被执行过，则在所述目标FDTI内跳过所述第一测试模式的执行。也就是说，只有当第一测试模式在所述目标FDTI内是第一次需要被执行时，才会执行，而当第一测试模式在所述目标FDTI内已经被执行过时，则不会再一次在目标FDTI内进行第一测试模式的执行。
在一个可能的实施例中，当第一测试模式在所述目标FDTI内是第一次需要被执行时，可以执行第一测试模式，而FDTI内还需要执行第二任务(第二任务和第一任务不同)，则可以获取第二任务的第二调度表，所述调度表第二调度表也包括所述第一测试模式，则在任务调度时，可以基于所述第一测试模式在所述目标FDTI内被执行过，在所述目标FDTI内跳过所述第一测试模式的执行，进而使得第一测试模式在FDTI内只执行一次，而不会重复被执行。
在一个可能的实施例中，在所述目标FDTI内执行所述第一测试模式之后，可以修改所述第一标识符，以使得所述第一标识符指示所述第一测试模式在所述目标FDTI内被执行过。类似的，在所述目标FDTI内执行所述第一测试模式之后，可以修改所述第二标识符，以使得所述第二标识符指示所述第一测试模式不需要被执行。例如，可以基于第二标识符指示所述第一测试模式不需要被执行，在所述目标FDTI内跳过所述第一测试模式的执行，进而使得第一测试模式在FDTI内只执行一次，而不会重复被执行。
示例性的，参照图5，在非确定性调度场景下，调度器不会预知接下来的一个FDTI内需要执行的任务，只有当进入该FDTI后，才会实时感知接下来要执行哪一个任务，因此对SBIST任务设置了优先级抢占方式，在FDTI内，每个普通任务(非SBIST任务)的执行之前会不可中断的执行该任务所对应的STL子集(包括至少一个测试模式)；在该场景中，调度器可以实时感知当前FDTI内需要执行的任务，进而感知到任务。调度器从任务队列中调度一个处于ready状态的任务，获取该任务的taskID，并根据任务的taskID找到对应的STL子集，即测试模式集合，对每一个STL子集中的测试模式，根据STLMask判断该测试模式是否在当前FDTI周期内已执行。如果已执行，则做下一轮判断，如果未执行，则将STLNeedExcuteMask中对应的位置1，并执行该测试模式，并将执行过的测试模式对应的STLMask和STLNeedExcuteMask中的位为已执行和不需要执行，直到遍历所有的测试模式，在待执行完当前被调度任务的SBIST任务之后，可以继续执行被调度任务。依次执行任务队列中的其他任务。
参照图6，横坐标代表时间，纵坐标代表任务的优先级，每种颜色的方块代表一个任务在当前时间里占用CPU的时间片运行。从原点开始到虚线为止为一个FDTI周期，在这个周期内，任务1、2、3被调度器调度的时候，会首先运行与该任务对应的SBSIT任务。SBIST任务中运行的是与任务相关的STL测试模式集合。SBIST任务优先级较高，测试序列执行时不可中断。在FDTI调度时间里，各任务的测试模式子集保证相互不重复，例如在执行任务3之前，可以执行任务3对应的测试模式子集(除了任务2对应的测试模式子集中的测试模式)。
示例性的，参照图7，在确定性调度场景中，调度器可以预知接下来的一个FDTI内需要执行的任务，为保证确定调度，大部分任务都需要静态确定最坏运行时间(worst Case  execution time，WCET)时间，以此确定优先级排序，因此对于该场景下，SBIST任务不适合默认高优先级，而应该适应调度算法，进行确定性调度排列；在该场景中，调度器可以在当前FDTI之前感知到FDTI内需要执行的任务，进而感知到任务。调度器可以从任务队列中调度一个处于ready状态的任务，若该任务为普通任务，则执行普通任务。具体可以获取该任务的taskID，根据任务的taskID找到对应的STL set，即测试模式的集合，判断当前FDTI是否超时，如果没有超时的话，对每一个STL子集中的测试模式，根据STLMask判断该测试模式是否在当前FDTI周期内已执行。如果已执行，则做下一轮判断，直到遍历所有的测试模式。如果未执行，将STLNeedExcuteMask中对应的位置1，如果超时，则重新设置STLmask所有位为0；如果被调度到的任务是SBIST任务，则根据STLNeedExcuteMask执行SBIST测试序列，并在执行完后将STLNeedExcutemask对应的位置0，STLmask对应的位置1。
本申请实施例中，参照图9，可以将SBIST任务中的测试模式分为三种状态，(未执行、不需要执行)、(未执行、需要执行)、(已执行、不需要执行)，初始状态为(未执行、不需要执行)。经过分析器之后将测试模式状态保持原状态或者是(未执行、需要执行)。测试模式经过执行后将(未执行、需要执行)的状态转换为(已执行、不需要执行)。
如下表所示，本申请实施例的方法和现有技术的SBIST调度相比，本发明中SBIST测试序列运行时间比现有技术缩短了约75％左右。
  现有技术 本申请实施例
一次STL执行时间 4.205ms 1.005ms
本申请实施例提供了一种错误检测方法，包括：获取第一任务的第一调度表，所述第一调度表包括第一测试模式，所述第一测试模式用于检测目标逻辑电路的错误，所述目标逻辑电路为用于执行所述第一任务的逻辑电路，所述第一任务用于在目标故障检测时间间隔FDTI内被执行；检测所述第一测试模式在所述目标FDTI内是否被执行过；若检测到所述第一测试模式在所述目标FDTI内未被执行过，则根据所述第一调度表，在所述目标FDTI内执行所述第一测试模式，以检测所述目标逻辑电路的错误。只有当第一测试模式在所述目标FDTI内是第一次需要被执行时，才会执行，而当第一测试模式在所述目标FDTI内已经被执行过时，则不会再一次在目标FDTI内进行第一测试模式的执行，使得同一个测试模式在FDTI内只执行一次，而不会重复被执行，降低了STL中的测试模式对处理器的负载，降低了处理器检测错误所花费的时间，从而提高了处理器的工作效率。
在图1a至图9所对应的实施例的基础上，为了更好的实施本申请实施例的上述方案，下面还提供用于实施上述方案的相关设备。具体可以参阅图10，图10为本申请实施例提供的一种终端1000的结构示意图，该终端1000包括：处理单元1001和获取单元1002。该获取单元1002用于获取第一任务的第一调度表，所述第一调度表包括第一测试模式，所述第一测试模式用于检测目标逻辑电路的错误，所述目标逻辑电路为用于执行所述第一任务的逻辑电路，所述第一任务用于在目标故障检测时间间隔FDTI内被执行；该处理单元1001用于检测所述第一测试模式在所述目标FDTI内是否被执行过；
若检测到所述第一测试模式在所述目标FDTI内未被执行过，则在所述目标FDTI内执行所述第一测试模式，以检测所述目标逻辑电路的错误。
在一些可能的实现方式中，该处理单元1001还用于若检测到所述第一测试模式在所述目标FDTI内被执行过，则在所述目标FDTI内跳过所述第一测试模式的执行。
在一些可能的实现方式中，该获取单元1002还用于在所述目标FDTI内执行所述第一测试模式之后，获取第二任务的第二调度表，所述调度表第二调度表包括所述第一测试模式，所述目标逻辑电路为用于执行所述第二任务的逻辑电路，所述第二任务用于在目标故障检测时间间隔FDTI内被执行；
该处理单元1001还用于基于所述第一测试模式在所述目标FDTI内被执行过，在所述目标FDTI内跳过所述第一测试模式的执行。
在一些可能的实现方式中，该获取单元1002还用于获取所述第一测试模式对应的第一标识符，所述第一标识符用于指示所述第一测试模式在所述目标FDTI内是否被执行过。
在一些可能的实现方式中，该处理单元1001还用于检测到所述第一测试模式对应的第一标识符指示所述第一测试模式在所述目标FDTI内未被执行过；
在所述目标FDTI内执行所述第一测试模式之后，修改所述第一标识符，以使得所述第一标识符指示所述第一测试模式在所述目标FDTI内被执行过。
在一些可能的实现方式中，该处理单元1001还用于检测到所述第一测试模式在所述目标FDTI内未被执行过之后，获取所述第一测试模式对应的第二标识符，所述第二标识符用于指示所述第一测试模式是否需要被执行；
在所述目标FDTI内执行所述第一测试模式之前，检测到所述第二标识符指示所述第一测试模式需要被执行。
在一些可能的实现方式中，该处理单元1001还用于在所述目标FDTI内执行所述第一测试模式之后，修改所述第二标识符，以使得所述第二标识符指示所述第一测试模式不需要被执行。
在一些可能的实现方式中，所述目标任务包括进程或线程。
本申请实施例只有当第一测试模式在所述目标FDTI内是第一次需要被执行时，才会执行，而当第一测试模式在所述目标FDTI内已经被执行过时，则不会再一次在目标FDTI内进行第一测试模式的执行，使得同一个测试模式在FDTI内只执行一次，而不会重复被执行，降低了STL中的测试模式对处理器的负载，降低了处理器检测错误所花费的时间，从而提高了处理器的工作效率。
接下来介绍本申请实施例提供的一种终端设备，终端设备可以为图11中的信息推荐装置，请参阅图11，图11为本申请实施例提供的终端设备的一种结构示意图，终端设备1100具体可以表现为虚拟现实VR设备、手机、平板、笔记本电脑、智能穿戴设备等，此处不做限定。具体的，终端设备1100包括：接收器1101、发射器1102、处理器1103和存储器1104(其中终端设备1100中的处理器1103的数量可以一个或多个，图11中以一个处理器为例)，其中，处理器1103可以包括应用处理器11031和通信处理器11032。在本申请的一 些实施例中，接收器1101、发射器1102、处理器1103和存储器1104可通过总线或其它方式连接。
存储器1104可以包括只读存储器和随机存取存储器，并向处理器1103提供指令和数据。存储器1104的一部分还可以包括非易失性随机存取存储器(non-volatile random access memory，NVRAM)。存储器1104存储有处理器和操作指令、可执行模块或者数据结构，或者它们的子集，或者它们的扩展集，其中，操作指令可包括各种操作指令，用于实现各种操作。
处理器1103控制终端设备的操作。具体的应用中，终端设备的各个组件通过总线系统耦合在一起，其中总线系统除包括数据总线之外，还可以包括电源总线、控制总线和状态信号总线等。但是为了清楚说明起见，在图中将各种总线都称为总线系统。
上述本申请实施例揭示的方法可以应用于处理器1103中，或者由处理器1103实现。处理器1103可以是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法的各步骤可以通过处理器1103中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器1103可以是通用处理器、数字信号处理器(digital signal processing，DSP)、微处理器或微控制器，还可进一步包括专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field-programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。该处理器1103可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器1104，处理器1103读取存储器1104中的信息，结合其硬件完成上述方法的步骤。具体的，处理器1103可以读取存储器1104中的信息，结合其硬件完成上述实施例中步骤201至这步骤203中与数据处理相关的步骤。
接收器1101可用于接收输入的数字或字符信息，以及产生与终端设备的相关设置以及功能控制有关的信号输入。发射器1102可用于通过第一接口输出数字或字符信息；发射器1102还可用于通过第一接口向磁盘组发送指令，以修改磁盘组中的数据.
本申请实施例中还提供一种包括计算机程序产品，当其在计算机上运行时，使得计算机执行上述实施例中图2对应的实施例中描述的错误检测方法的步骤。
本申请实施例中还提供一种计算机可读存储介质，该计算机可读存储介质中存储有用于进行信号处理的程序，当其在计算机上运行时，使得计算机执行如前述实施例描述的方法中的图像处理方法的步骤。
本申请实施例提供的图像显示装置具体可以为芯片，芯片包括：处理单元和通信单元，所述处理单元例如可以是处理器，所述通信单元例如可以是输入/输出接口、管脚或电路等。该处理单元可执行存储单元存储的计算机执行指令，以使执行设备内的芯片执行上述实施例描述的数据处理方法，或者，以使训练设备内的芯片执行上述实施例描述的数据处理方法。可选地，所述存储单元为所述芯片内的存储单元，如寄存器、缓存等，所述存储单元 还可以是所述无线接入设备端内的位于所述芯片外部的存储单元，如只读存储器(read-only memory，ROM)或可存储静态信息和指令的其他类型的静态存储设备，随机存取存储器(random access memory，RAM)等。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器、随机存取存储器、磁碟或者光盘等各种可以存储程序代码的介质。

Claims (18)

  1. 一种错误检测方法，其特征在于，包括：
    获取第一任务的第一调度表，所述第一调度表包括第一测试模式，所述第一测试模式用于检测目标逻辑电路的错误，所述目标逻辑电路为用于执行所述第一任务的逻辑电路，所述第一任务用于在目标故障检测时间间隔FDTI内被执行；
    检测所述第一测试模式在所述目标FDTI内是否被执行过；
    若检测到所述第一测试模式在所述目标FDTI内未被执行过，则根据所述第一调度表，在所述目标FDTI内执行所述第一测试模式。
  2. 根据权利要求1所述的错误检测方法，其特征在于，所述方法还包括：
    若检测到所述第一测试模式在所述目标FDTI内被执行过，则在所述目标FDTI内跳过所述第一测试模式的执行。
  3. 根据权利要求1或2所述的错误检测方法，其特征在于，所述在所述目标FDTI内执行所述第一测试模式之后，所述方法还包括：
    获取第二任务的第二调度表，所述调度表第二调度表包括所述第一测试模式，所述目标逻辑电路为用于执行所述第二任务的逻辑电路，所述第二任务用于在目标故障检测时间间隔FDTI内被执行；
    基于所述第一测试模式在所述目标FDTI内被执行过，在所述目标FDTI内跳过所述第一测试模式的执行。
  4. 根据权利要求1至3任一所述的错误检测方法，其特征在于，所述检测所述第一测试模式在所述目标FDTI内是否被执行过，包括：
    获取所述第一测试模式对应的第一标识符，所述第一标识符用于指示所述第一测试模式在所述目标FDTI内是否被执行过。
  5. 根据权利要求4所述的错误检测方法，其特征在于，所述检测到所述第一测试模式在所述目标FDTI内未被执行过，包括：
    检测到所述第一测试模式对应的第一标识符指示所述第一测试模式在所述目标FDTI内未被执行过；
    所述在所述目标FDTI内执行所述第一测试模式之后，所述方法还包括：
    修改所述第一标识符，以使得所述第一标识符指示所述第一测试模式在所述目标FDTI内被执行过。
  6. 根据权利要求1至5任一所述的错误检测方法，其特征在于，所述检测到所述第一测试模式在所述目标FDTI内未被执行过之后，所述方法还包括：
    获取所述第一测试模式对应的第二标识符，所述第二标识符用于指示所述第一测试模 式是否需要被执行；
    所述在所述目标FDTI内执行所述第一测试模式之前，所述方法还包括：
    检测到所述第二标识符指示所述第一测试模式需要被执行。
  7. 根据权利要求6所述的错误检测方法，其特征在于，所述在所述目标FDTI内执行所述第一测试模式之后，所述方法还包括：
    修改所述第二标识符，以使得所述第二标识符指示所述第一测试模式不需要被执行。
  8. 根据权利要求1至7任一所述的错误检测方法，其特征在于，所述目标任务包括进程或线程。
  9. 一种终端，其特征在于，包括处理器；所述处理器用于：
    获取第一任务的第一调度表，所述第一调度表包括第一测试模式，所述第一测试模式用于检测目标逻辑电路的错误，所述目标逻辑电路为用于执行所述第一任务的逻辑电路，所述第一任务用于在目标故障检测时间间隔FDTI内被执行；
    检测所述第一测试模式在所述目标FDTI内是否被执行过；
    若检测到所述第一测试模式在所述目标FDTI内未被执行过，则在所述目标FDTI内执行所述第一测试模式。
  10. 根据权利要求9所述的终端，其特征在于，所述处理器还用于：
    若检测到所述第一测试模式在所述目标FDTI内被执行过，则在所述目标FDTI内跳过所述第一测试模式的执行。
  11. 根据权利要求9或10所述的终端，其特征在于，所述处理器还用于：
    在所述目标FDTI内执行所述第一测试模式之后，获取第二任务的第二调度表，所述调度表第二调度表包括所述第一测试模式，所述目标逻辑电路为用于执行所述第二任务的逻辑电路，所述第二任务用于在目标故障检测时间间隔FDTI内被执行；
    基于所述第一测试模式在所述目标FDTI内被执行过，在所述目标FDTI内跳过所述第一测试模式的执行。
  12. 根据权利要求9至11任一所述的终端，其特征在于，所述处理器具体用于：
    获取所述第一测试模式对应的第一标识符，所述第一标识符用于指示所述第一测试模式在所述目标FDTI内是否被执行过。
  13. 根据权利要求12所述的终端，其特征在于，所述处理器具体用于：
    检测到所述第一测试模式对应的第一标识符指示所述第一测试模式在所述目标FDTI内未被执行过；
    在所述目标FDTI内执行所述第一测试模式之后，修改所述第一标识符，以使得所述第一标识符指示所述第一测试模式在所述目标FDTI内被执行过。
  14. 根据权利要求9至13任意一项所述的终端，其特征在于，所述处理器还用于：
    检测到所述第一测试模式在所述目标FDTI内未被执行过之后，获取所述第一测试模式对应的第二标识符，所述第二标识符用于指示所述第一测试模式是否需要被执行；
    在所述目标FDTI内执行所述第一测试模式之前，检测到所述第二标识符指示所述第一测试模式需要被执行。
  15. 根据权利要求14所述的终端，其特征在于，所述处理器还用于：
    在所述目标FDTI内执行所述第一测试模式之后，修改所述第二标识符，以使得所述第二标识符指示所述第一测试模式不需要被执行。
  16. 根据权利要求9至15任意一项所述的终端，其特征在于，所述目标任务包括进程或线程。
  17. 一种计算机可读存储介质，其特征在于，包括计算机可读指令，当所述计算机可读指令在计算机上运行时，使得所述计算机执行如权利要求1至8中任一项所述的方法。
  18. 一种计算机程序产品，其特征在于，包括计算机可读指令，当所述包括计算机可读指令，在计算机上运行时，使得所述计算机执行如权利要求1至8任一项所述的方法。
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CN108491288A (zh) * 2017-02-21 2018-09-04 英特尔公司 优先化错误检测与调度
CN110192186A (zh) * 2017-01-24 2019-08-30 Arm有限公司 使用矢量处理电路的错误检测
CN111078550A (zh) * 2019-12-09 2020-04-28 深圳市网心科技有限公司 软件测试方法及装置、计算机装置及存储介质

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US20150161323A1 (en) * 2013-12-06 2015-06-11 Robert Bosch Gmbh Method for checking a hardware-configurable logic circuit for faults
CN110192186A (zh) * 2017-01-24 2019-08-30 Arm有限公司 使用矢量处理电路的错误检测
CN108491288A (zh) * 2017-02-21 2018-09-04 英特尔公司 优先化错误检测与调度
CN111078550A (zh) * 2019-12-09 2020-04-28 深圳市网心科技有限公司 软件测试方法及装置、计算机装置及存储介质

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