WO2022252082A1 - 一种数据处理方法、设备及系统 - Google Patents

一种数据处理方法、设备及系统 Download PDF

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Publication number
WO2022252082A1
WO2022252082A1 PCT/CN2021/097486 CN2021097486W WO2022252082A1 WO 2022252082 A1 WO2022252082 A1 WO 2022252082A1 CN 2021097486 W CN2021097486 W CN 2021097486W WO 2022252082 A1 WO2022252082 A1 WO 2022252082A1
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address
command
logical partition
storage device
computing device
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PCT/CN2021/097486
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English (en)
French (fr)
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吴黎明
张颇
朱强
何江
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华为技术有限公司
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Priority to CN202180098836.8A priority Critical patent/CN117413247A/zh
Priority to PCT/CN2021/097486 priority patent/WO2022252082A1/zh
Publication of WO2022252082A1 publication Critical patent/WO2022252082A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers

Definitions

  • the present application relates to the field of computer technology, in particular to a data processing method, device and system.
  • SSDs solid state drives
  • NAND Flash flash memory
  • the way the host interacts with traditional SSDs is that the host specifies the address in the write IO command, and then the SSD writes data to the address specified by the host according to the write command, but does not support concurrent data writing.
  • ZNS zoned namespace
  • LBA logical block address
  • SMR shingled magnetic recording
  • the cooperation process between the host (host) and the hard disk is as follows: when the host sends a write IO command to a certain zone in the SSD, the content carried by the write IO command includes The initial LBA of the zone, the number of LBAs occupied by the data, and the data itself. After ZNS SSD receives the IO, ZNS SSD independently decides where the data carried by the IO is actually written into the zone, and completes the write operation on ZNS SSD. Finally, send the address of the zone where the data is actually written to the host. The host needs to wait for the data to be written to be written, and then record the address of the actually written data.
  • This cooperation method can allow the host to target a single The zone sends multiple write IOs concurrently, but the cooperation between the host and the ZNS SSD requires changing the software architecture of the storage system including the traditional SSD and the host.
  • the flash translation layer flash Translation layer (FTL) is migrated from the inside of the SSD to the upper host side, and the traditional SSD driver needs to be changed, which introduces unnecessary complexity and additional workload.
  • the present application provides a data processing method, device, and system, so as to implement concurrent writing of data from a computing device to a storage device without changing the software architecture of a traditional storage system, and improve the efficiency of writing data.
  • the present application provides a computing device, where the computing device includes a processor and a communication interface, and the processor is coupled to a storage device through the communication interface.
  • the processor is configured to: obtain a first address of a first logical partition in the storage device, where the first address is the current start write address of the first logical partition, and the first logical partition is among the plurality of logical partitions included in the storage device Any one of the above, sending at least one first input and output IO command to the storage device, wherein the access address corresponding to each first IO command is located in the first address range, and the first address range is in the first logical partition according to the first address and
  • the logical address range determined by the preset first length receives first information sent by the storage device in response to at least one first IO command, and the first information is used by the computing device to issue an IO command corresponding to the second address.
  • the computing device specifies the address where data is actually written in the IO command, and the storage device writes data to the specified address of the first logical partition according to the IO command, which is consistent with the writing behavior of traditional SSDs, so there is no need to By changing the software architecture of the system, data can be concurrently written to the storage device, thereby reducing unnecessary complexity and workload.
  • the computing device can issue IO commands of any address within the first address range, and according to the storage device The first information fed back sends the IO command corresponding to the second address as soon as possible, so that the storage device continues to operate in the manner of sequentially writing data, thereby reducing the consumption of cache resources and effectively improving the efficiency of writing data.
  • the first length is determined according to the size of the first cache space
  • the first cache space is a cache space in a cache in the storage device for caching IO commands that access the first logical partition.
  • the computing device can write out-of-order data concurrently and cache them in the first cache space.
  • the speed of writing data is mainly affected by the size of the first cache space, and the number of IO commands affects the speed of writing data. smaller.
  • the processor is further configured to: configure the size of the first cache space.
  • the processor is further configured to: configure the size of the first cache space.
  • the first information includes the result of successfully writing the first data to the first address and the second address, and the second address is different from the first address
  • the processor is further configured to: A result of writing the first data and the second address at an address, and at least one second IO command is sent to the storage device, and the at least one second IO command includes a second IO command corresponding to the second address.
  • the current initial write address of the first logical partition is the second address
  • the access address corresponding to each second IO command in at least one second IO command is located in the second address range
  • the second The address range is a logical address range determined according to the second address and the first length in the first logical partition.
  • the current starting address of the first logical partition is the third address
  • the access address corresponding to each second IO command is located in the second address range
  • the second address range is the third address of the first logical partition.
  • the logical address range determined according to the third address and the first length.
  • the first information further includes at least one of the following second information items: the status code of the first cache space corresponding to the first logical partition, the status code indicating that the first cache space is full; the remaining capacity of the storage device .
  • the processor is further configured to: according to at least one item of second information included in the first information, determine whether to continue sending the second IO command located in the second address range to the storage device.
  • the first information further includes at least one of the following third pieces of information: the amount of data that has been cached in the first cache space corresponding to the first logical partition and has not been written into the first logical partition; The remaining capacity of the first cache space corresponding to the partition; the remaining capacity of the storage device; the remaining capacity of the first logical partition; the processor is also used to: if it is determined to continue to deliver the second IO located in the second address range When ordering, the quantity of the second IO commands within the second address range issued to the storage device is determined according to at least one item of second information included in the first information.
  • the computing device can obtain relevant information about the first cache space corresponding to the first logical partition, so as to control the speed at which the first logical partition issues IO commands.
  • the first information further includes a timed-out IO command in the first cache space corresponding to the first logical partition
  • the processor is further configured to: resend the timed-out IO command to the storage device.
  • the first information also includes the delay time corresponding to the IO command that is not successfully cached in the first cache space and to be resent, and the processor is specifically used to: after the waiting time reaches the delay time , to resend the IO command to be resent to the storage device.
  • the first information includes a failure result of writing the first data to the first address and a second address
  • the second address is the same as the first address
  • the processor is further used to:
  • a first IO command corresponding to the first address is sent to the storage device.
  • the present application provides a storage controller.
  • the storage controller includes a processor and a communication interface, and the processor is coupled to a computing device through the communication interface.
  • the processor is configured to: receive at least one first input and output IO command sent by the computing device, wherein the access address corresponding to each first IO command is located in the first address range, and the first address range is in the first logical partition according to the first A logical address range determined by an address and a preset first length, the first logical partition is any one of a plurality of logical partitions included in the storage device; at least one first IO command is stored in the first cache space; and the first logical partition is determined
  • the current initial write address of a logical partition is the first address, and the corresponding command is selected and executed from at least one first IO command according to the first address, and the first information is sent to the computing device, and the first information It is used for the computing device to deliver the IO command corresponding to the second address.
  • the computing device specifies the address where data is actually written in the IO command, and the storage controller writes data to the specified address of the first logical partition according to the IO command, which is consistent with the write behavior of traditional SSDs, so Concurrent writing of data to the storage controller can be realized without changing the software architecture of the system, thereby reducing unnecessary complexity and workload.
  • the scope of IO commands issued by the computing device is limited, and the first information is fed back to the computing device , the IO command corresponding to the address where the storage controller needs to write data can be issued as soon as possible, thereby reducing the consumption of cache resources and effectively improving the efficiency of writing data.
  • the first length is determined according to the size of the first cache space
  • the first cache space is a cache space in a cache in the storage device for caching IO commands that access the first logical partition.
  • the storage device can receive data sent by the computing device concurrently, and cache the data in the first cache space.
  • the speed of writing data is mainly affected by the size of the first cache space.
  • the number of IO commands has a great impact on the write data The impact of speed is small.
  • the size of the first cache space corresponding to the first logical partition is configured by the computing device.
  • the size of the first cache space on the computing device the number of IO commands issued by the computing device can be limited, thereby improving the efficiency of writing data.
  • the first IO command corresponding to the first address is found from the first cache space, and the first IO command corresponding to the first address includes the first data, the writing the first data at an address, and sending to the computing device first information including a result of successfully writing the first data to the first address and a second address, and the second address is the same as the The first address is different, and the first information is used by the computing device to issue an IO command corresponding to the second address.
  • the processor is further configured to: set a first duration for each first IO command in at least one first IO command, and when the storage duration of any first IO command in the first cache space exceeds After the first period of time, the timed-out first IO command is deleted from the first cache space, thereby preventing the timed-out IO command from consuming cache resources.
  • the processor is further configured to: receive at least one second IO command sent by the computing device, the at least one second IO command includes a second IO command corresponding to the second address, and each second IO command The corresponding access address is located in the second address range; if the current initial write address of the first logical partition is the second address, the second address range is the logical address determined according to the second address and the first length in the first logical partition range; or, if the current initial write address of the first logical partition is the third address, the second address range is the logical address range determined according to the third address and the first length in the first logical partition.
  • the storage device can timely receive the IO command corresponding to the current initial write address of the first logical partition, and the undelivered IO command corresponding to the access address after the current initial write address of the first logical partition. IO commands.
  • the first information further includes at least one item of the following second information: a status code of the first cache space corresponding to the first logical partition, and the status code indicates that the first The cache space is full; the remaining capacity of the storage device; at least one item of second information included in the first information is used for the computing device to determine whether to continue to issue the address located in the second address range to the storage device the second IO command.
  • the computing device can know in time when the first cache space is full or the remaining capacity is zero, and no longer send data to the first logical partition.
  • the first logical partition delivers write data.
  • the first information further includes at least one of the following third pieces of information: the first cache space corresponding to the first logical partition has been cached and has not been written into the first logical partition. data volume; the capacity of the remaining space of the first cache space corresponding to the first logical partition; the remaining capacity of the storage device; the remaining capacity of the first logical partition; at least one item included in the first information
  • the first information further includes timed-out IO commands in the first cache space corresponding to the first logical partition;
  • the timed-out IO command is used to resend the timed-out IO command to the storage device.
  • the first information further includes a delay time corresponding to an IO command that is not successfully cached in the first cache space and is to be resent, and the delay time is used for the calculation After the waiting time reaches the delay time, the device resends the IO command to be resent to the storage device.
  • the processor is specifically configured to: if the first IO command corresponding to the first address is not found in the first cache space, suspending the processing of the first IO command corresponding to the first logical partition write data, and send to the computing device first information including a result of failure to write data to the first address and the second address, and the second address is the same as the first address, and the second address The information is used for the computing device to issue the first IO command corresponding to the first address.
  • the present application provides a storage device, which includes a storage medium, a cache, and a storage controller as described in any possible design of the second aspect above, where the storage medium includes a plurality of logical partitions, the The multiple logical partitions include a first logical partition, the cache includes multiple cache spaces, the multiple cache spaces include a first cache space, and the first cache space is used for cache access to the first logical partition in the cache in the storage device
  • the cache space of the IO command; the storage controller is used to find the IO command corresponding to the current initial write address of the first logical partition from the first cache space, and carry the IO command corresponding to the found initial write address Data is written to the first logical partition.
  • the computing device specifies the address where the data is actually written in the IO command, and the storage device writes data to the specified address of the first logical partition according to the IO command, which is consistent with the writing behavior of traditional SSDs, so there is no need to
  • data can be written concurrently to the storage device, which can reduce unnecessary complexity and workload.
  • the computing device by limiting the range of IO commands issued by the computing device, the data that needs to be written to the storage device can be issued as soon as possible.
  • the IO command corresponding to the address can reduce the consumption of cache resources and effectively improve the efficiency of writing data.
  • the data in the first logical partition is written in a sequential writing manner.
  • the storage device is a ZNS SSD with a partition namespace.
  • a data processing method is applied to a computing device, and the method includes: obtaining a first address of a first logical partition in the storage device, where the first address is the current start writing address of the first logical partition
  • the first logical partition is any one of a plurality of logical partitions included in the storage device; sending at least one first input and output IO command to the storage device, wherein the access address corresponding to each first IO command is located in the first address range,
  • the first address range is a logical address range determined according to the first address and the preset first length in the first logical partition; the first information sent by the storage device in response to at least one first IO command is received, and the first information is used for
  • the computing device issues an IO command corresponding to the second address.
  • the first length is determined according to the size of the first cache space, and the first cache space is a cache space in a cache in the storage device for caching IO commands that access the first logical partition.
  • the method before acquiring the first address of the first logical partition in the storage device, the method further includes: configuring the size of the first cache space.
  • the first information includes the result of successfully writing the first data to the first address and the second address, and the second address is different from the first address
  • the receiving storage device responds to at least one first IO command
  • the first information sent it also includes: according to the result of successfully writing the first data to the first address and the second address, sending at least one second IO command to the storage device, at least one second IO command includes the second address Corresponding to the second IO command.
  • the current initial write address of the first logical partition is the second address
  • the access address corresponding to each second IO command in at least one second IO command is located in the second address range
  • the second The address range is a logical address range determined according to the second address and the first length in the first logical partition.
  • the current starting address of the first logical partition is the third address
  • the access address corresponding to each second IO command is located in the second address range
  • the second address range is the third address of the first logical partition.
  • the logical address range determined according to the third address and the first length.
  • the first information further includes at least one of the following second information items: the status code of the first cache space corresponding to the first logical partition, the status code indicating that the first cache space is full; the remaining capacity of the storage device .
  • the method further includes: according to at least one item of second information included in the first information, determining whether to continue delivering the second IO command located in the second address range to the storage device.
  • the first information further includes at least one of the following third pieces of information: the amount of data that has been cached in the first cache space corresponding to the first logical partition and has not been written into the first logical partition; The remaining capacity of the first cache space corresponding to the partition; the remaining capacity of the storage device; the remaining capacity of the first logical partition; the method also includes: if it is determined to continue sending the second IO command located in the second address range to the storage device , according to at least one item of second information included in the first information, determine the number of second IO commands within the second address range delivered to the storage device.
  • the first information further includes timed-out IO commands in the first cache space corresponding to the first logical partition.
  • the method also includes: resending the timed-out IO command to the storage device.
  • the first information further includes a delay time corresponding to an IO command that is not successfully cached in the first cache space and is to be resent.
  • the method also includes: resending the IO command to be resent to the storage device after the waiting time reaches the delay time.
  • sending at least one first input/output IO command to the storage device includes: concurrently sending at least one first IO command to the storage device.
  • the first information includes a result of failure to write the first data to the first address and a second address, and the second address is the same as the first address;
  • the receiving storage device responds to at least one first IO command After the first information is sent, it further includes: sending a first IO command corresponding to the first address to the storage device according to a result of failure to write the first data to the first address and the first address.
  • the present application provides a data processing method, the method is applied to a storage device or a storage controller in the storage device, and the method includes: receiving at least one first input and output IO command sent by the computing device, wherein each first The access address corresponding to an IO command is located in the first address range, and the first address range is the logical address range determined according to the first address and the preset first length in the first logical partition; at least one first IO command is stored in In the first cache space; determine that the current initial write address in the first logical partition is the first address, and select and execute a corresponding command from at least one first IO command according to the first address; send the first IO command to the computing device information, the first information is used by the computing device to issue the IO command corresponding to the second address.
  • the first length is determined according to the size of the first cache space, and the first cache space is a cache space in a cache in the storage device for caching IO commands that access the first logical partition.
  • the method before receiving at least one first input/output IO command sent by the computing device, the method further includes: configuring a size of the first buffer space.
  • the timed-out first IO command is deleted from the first cache space.
  • the at least one first IO command in the first cache space after storing the at least one first IO command in the first cache space, it further includes: receiving at least one second IO command sent by the computing device, the at least one second IO command includes the second address corresponding to The second IO command, the access address corresponding to each second IO command is located in the second address range; if the current start write address of the first logical partition is the second address, the second address range is the first logical partition The logical address range determined according to the second address and the first length; or, if the current initial write address of the first logical partition is the third address, the second address range is determined according to the third address and the first address in the first logical partition. A logical address range of determined length.
  • the first information further includes at least one of the following second information items: the status code of the first cache space corresponding to the first logical partition, the status code indicating that the first cache space is full; the remaining capacity of the storage device ; At least one item of second information included in the first information is used for the computing device to determine whether to continue issuing the second IO command located in the second address range to the storage device.
  • the first information further includes at least one of the following third pieces of information: the amount of data that has been cached in the first cache space corresponding to the first logical partition and has not been written into the first logical partition; The capacity of the remaining space of the first cache space corresponding to the partition; the remaining capacity of the storage device; the remaining capacity of the first logical partition; at least one item of second information included in the first information, which is used by the computing device to determine the The number of second IO commands located in the second address range.
  • the first information further includes timed-out IO commands in the first cache space corresponding to the first logical partition; the timed-out IO commands in the first cache space corresponding to the first logical partition are used to send data to the storage device Resend timed-out IO commands.
  • the first information also includes the delay time corresponding to the IO command that is not successfully cached in the first cache space and to be resent, and the delay time is used by the computing device when the waiting time reaches the delay time After that, resend the IO command to be resent to the storage device.
  • the corresponding first IO command suspends writing data to the first logical partition, and sends the first information including the result of failure to write data to the first address and the second address to the computing device, and the second address is the same as the first address , the first information is used for the computing device to issue the first IO command corresponding to the first address.
  • an embodiment of the present application provides a data processing system, including the computing device described in each design in the above first aspect and the storage device described in the above first aspect.
  • the embodiment of the present application provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program is run on a computer, the computer executes the above-mentioned fourth aspect.
  • the embodiment of the present application provides a computer program product, which, when the computer program product is run on a computer, causes the computer to execute the method described in each design in the above fourth aspect, or to execute the above fifth The methods described in each design of the aspect.
  • Fig. 1 schematically shows a kind of NAND Flash particle schematic diagram
  • Fig. 2 exemplarily shows a schematic diagram comparing a SMR SSD with a traditional SSD
  • Figure 3 exemplarily shows a schematic diagram of ZNS SSD and the host cooperating to write data
  • FIG. 4 exemplarily shows a schematic diagram of a system architecture applicable to an embodiment of the present application
  • FIG. 5 exemplarily shows a schematic flowchart of a data processing method provided by an embodiment of the present application
  • FIG. 6 exemplarily shows a schematic diagram of writing a single IO command
  • FIG. 7 is a schematic structural diagram of a device provided by an embodiment of the present application.
  • a device with data storage function can be a storage device with only data storage function, such as a memory, or a storage device with An electronic device that stores data and also has other functions.
  • the electronic device may be a portable electronic device including functions such as a personal digital assistant and/or a music player, such as a mobile phone, a tablet computer, a wearable device (such as a smart watch) with a wireless communication function, or a vehicle-mounted device.
  • portable electronic devices include, but are not limited to Or portable electronic devices with other operating systems.
  • the aforementioned portable electronic device may also be, for example, a laptop computer (Laptop) with a touch-sensitive surface (such as a touch panel). It should also be understood that, in some other embodiments of the present application, the above-mentioned electronic device may also be a desktop computer with a touch-sensitive surface (such as a touch panel).
  • a system including a storage device and a computing device is taken as an example for description.
  • the memory may be a volatile memory, may also be a nonvolatile memory, or may include both volatile and nonvolatile memory. It may also be a hard disk composed of these volatile memories or nonvolatile memories, such as SSD. Wherein, the volatile memory may be a random access memory (random access memory, RAM), which is used as an external cache.
  • RAM random access memory
  • RAM random access memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • DRAM synchronous dynamic random access memory
  • SDRAM double data rate synchronous dynamic random access memory
  • double data rate SDRAM double data rate SDRAM
  • DDR SDRAM enhanced synchronous dynamic random access memory
  • ESDRAM enhanced synchronous dynamic random access memory
  • serial link DRAM SLDRAM
  • direct memory bus random access memory direct rambus RAM, DR RAM
  • Non-volatile memory can be read-only memory (read-only memory, ROM), programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically erasable Programmable Read Only Memory
  • SSD storage device
  • SSD storage device
  • the SSD can include a storage controller and a storage medium, wherein the storage medium is composed of multiple NAND Flash particles arranged in rows and columns, and the multiple NAND Flash particles are connected to the storage controller through a bus.
  • each NAND Flash particle is composed of multiple Dies, each Die has multiple blocks (blocks), and each Block has multiple pages (pages).
  • the capacity of a single Die is generally 8GB/16GB/32GB or larger. If a single NAND Flash particle includes 8 Dies, the capacity of a single NAND particle can be 64GB/128GB/256GB or larger.
  • SSDs using Shingled Magnetic Recording (SMR) technology and Zoning Name Space (ZNS) technology.
  • SMR Shingled Magnetic Recording
  • ZNS Zoning Name Space
  • the first type is SMR SSD.
  • SMR SSD partially overlaps the data tracks on the disk, just like the tiles on the roof.
  • This technology is called shingled magnetic recording technology.
  • SMR SSDs using this technology Compared with traditional hard disks, SMR SSDs using this technology Generally speaking, the changes in the manufacturing process are very small, but it can increase the storage density of the disk and reduce the cost per unit capacity.
  • the read behavior of the SMR SSD is the same as that of the traditional hard disk, but its write behavior has undergone a huge change, that is, it no longer supports random write and in-place update write, and can only perform sequential append write.
  • a track overwrites any tracks it overlaps, destroying the data on it.
  • the hard disk platter is divided into concentric tracks, and there is a certain interval between the tracks to play a protective role.
  • the magnetic head of the hard disk is located above the disk recording medium, including a write head for writing and a read head for reading. Both the write head and the read head are independent components.
  • the write head needs to apply a strong magnetic field to change the recording on the disk, which further requires the write head to be large enough to generate the required write magnetic field strength. Therefore, the number of tracks per inch that can fit on a disk is determined by the width of the write head if the tracks don't have any overlap.
  • Shingled writing takes advantage of the fact that the magnetic field strength required for disk reading is lower than that required for writing.
  • the track width required for disk reading can be smaller than the track width required for writing.
  • the data on SMR SSD The writes are written by partially overlapping the previous track while leaving enough room for the narrower read head to read the previous track's data.
  • the SMR disk divides the track into several bands, that is, a continuously writable area formed by continuous tracks, and each area constitutes a basic unit that needs to be written sequentially.
  • Band is a physical concept on the SMR disk, and its corresponding logical concept is "zone", which is the sequential writing area of the SMR disk that the upper-layer software can see.
  • the second type is ZNS SSD.
  • ZNS is a newly proposed method of cooperating between hosts and disks in NVMe.
  • ZNS disks have the following characteristics:
  • the entire LBA space of the ZNS SSD is divided into multiple zones.
  • the size of a single zone is, for example, 4MB to 4GB.
  • a single zone is somewhat similar to an area divided by an SMR SSD.
  • the host can only write data sequentially, but cannot write data randomly, and can read data randomly.
  • a zone can correspond to one or more physical blocks on NAND Flash.
  • the sequential writing method of ZNS SSD requires the host to write data serially, and its performance is relatively low. Therefore, the concurrent writing method of zone append is introduced. As shown in Table 1, the concurrent writing mode of zone append can support concurrent writing of multiple write commands in a single zone.
  • the content of the write command includes the initial LBA of the zone, the number of LBAs occupied by the data, and the data itself.
  • ZNS SSD After ZNS SSD receives the IO command, ZNS SSD independently determines the data carried by the IO command The location actually written to the zone, after the ZNS SSD completes the write operation, sends the start address of the location where the data is actually written to the zone to the host, and the host records the address of the actually written data.
  • Table 1 exemplarily shows the content carried by IO commands and responses in the concurrent writing process of zone append:
  • Cmd# refers to multiple write commands issued concurrently
  • ZSLBA refers to the starting address of the zone
  • starting LBA refers to the starting address of the zone carried by each command
  • #LBAs refers to the number of LBAs corresponding to the command
  • assigned LBA refers to the starting LBA actually assigned by the SSD to this command, and the LBA will be returned to the host;
  • write pointer refers to the write pointer corresponding to the zone (when writing the command);
  • write pointer (after Cmd) refers to the write pointer corresponding to the zone (when the command is completed).
  • the cooperation between the host and the ZNS SSD can allow the host to issue multiple IO commands concurrently for a single zone.
  • flash translation layer Flash Translation
  • Layer FTL
  • the host needs to record the address where the data carried by each IO command is actually written, and the host needs to maintain the mapping relationship between the data and the storage address, which introduces unnecessary complexity and additional workload.
  • the present application proposes a data processing method to achieve concurrent writing of data to the solid-state hard disk without increasing the workload of the host.
  • FIG. 4 exemplarily shows a schematic diagram of a system architecture applicable to this embodiment of the present application.
  • the system architecture includes a computing device 100 and a storage device 200 .
  • the computing device 100 is configured to issue an input/output (IO) command to the storage device, and receive a response corresponding to the IO command, where the IO command carries data to be written and specifies
  • the storage address of the IO command, the response corresponding to the IO command includes first information, and the first information is used by the computing device to issue the IO command corresponding to the next address.
  • the computing device 100 is a device with data processing capability or computing capability, such as a host, and the computing device 100 may include a processor and a communication interface, wherein the processor may include but not limited to a central processing unit (central processing unit, CPU), a general-purpose processor or other processors etc.
  • the storage device 200 may include a storage controller 210 , a cache 220 and a storage medium 230 .
  • Computing device 100 and storage controller 210 , and storage controller 210 and storage medium 230 may be connected through a bus as shown in FIG. 4 , or may be connected through interconnection or other methods to realize communication.
  • the cache 220 includes at least one cache space, and the cache space is used to cache an IO command, and the IO command is used to instruct the storage controller 210 to write data to the storage unit.
  • the storage medium 230 may be divided into at least one logical space (or partition), each logical space (or partition) is called a storage unit, and a storage unit corresponds to a cache space one by one.
  • the storage unit in the embodiment of the present application can be, for example, a zone in a ZNS SSD, a namespace (namespace) in an NVME SSD, etc. In the following embodiments, the storage unit is a zone as an example for illustration, and will not be described in detail hereinafter.
  • the storage controller 210 is configured to receive the IO command sent by the computing device 100, and store the IO command in the cache. For a storage unit, after determining the address of the location pointed to by the write pointer of the storage unit, from the corresponding Search the cache space for an IO command carrying the address pointed to by the write pointer, and then write the data carried by the found IO command into the storage unit.
  • each component shown in FIG. 4 can be implemented in hardware, software, or a combination of hardware and software including one or more signal processing and/or application-specific integrated circuits, and details will not be repeated here. .
  • FIG. 5 exemplarily shows a schematic flow chart of a data processing method provided by an embodiment of the present application.
  • the steps performed by the storage device may also be performed by a storage controller.
  • the method includes:
  • a computing device acquires a first address of a first logical partition in a storage device.
  • the first address is the current initial write address of the first logical partition, and can also be understood as the first address in the first logical partition where data is not written, and where data can be written in all subsequent positions.
  • the first address, the second address, and the third address involved in the embodiment of the present application are Logical Block Addresses (LBAs), which will not be described in detail below.
  • the storage device may include one or more logical partitions.
  • the first logical partition in S501 may be any one of the multiple logical partitions included in the storage device. partition. It should be understood that in the embodiment of the present application, the description is made by taking the computing device to write data to a logical partition (ie, the first logical partition) in the storage device as an example. If the storage device includes multiple logical partitions, the embodiment of the present application The solution can also be applied to the scenario of writing data to each logical partition in the storage device.
  • the storage device may further include a cache, the cache includes one or more cache spaces, the cache includes a first cache space, and the first cache space is a cache in the cache in the storage device for caching the IO command for accessing the first logical partition space.
  • the size of the cache space corresponding to the first logical partition is the size of the cache of the storage device, which may also be greater than the size of the cache of the storage device; when the storage device includes When there are multiple logical partitions, the sum of the cache spaces corresponding to all the logical partitions may be equal to the size of the cache, or larger than the size of the cache of the storage device.
  • the storage device If the storage device detects that the cache is full, it can return the corresponding error code (or status code) to the computing device to prompt the computing device to retry after a delay, that is, the delayed re-delivery cannot be stored because the cache is full. IO commands in the cache.
  • the computing device does not configure the corresponding cache space size for each logical partition included in the storage device, the default cache is shared by all logical partitions, that is, the cache space corresponding to a single logical partition has no size Constraints, there is only one storage device cache size constraint.
  • the computing device may further configure a corresponding cache space size for each logical partition included in the storage device.
  • the computing device as the host
  • the storage device as the ZNS SSD
  • the ZNS SSD includes four first logical partitions as an example.
  • One logical partition is a zone, that is, the ZNS SSD includes four zones.
  • the memory of ZNS SSD can be used as a cache for each zone.
  • the metadata overhead is 0.5GB
  • the remaining 1.5GB of memory can be used as a cache.
  • the data in the cache space does not need backup power protection .
  • the host can configure the size of the cache space corresponding to each zone for the four zones according to actual needs. Among them, the size of the cache space can be configured when the host creates the zone, or the set feature command can be issued to realize the separate configuration of the cache space for the specified zone.
  • the computing device configures the size of the corresponding cache space for each logical partition, for example, configures the size of the first cache space for the first logical partition, and configures the size of the second cache space for the second logical partition, thereby Realize on-demand configuration of the size of each cache space.
  • the size of the cache space determines how large the address range of the computing device can be written out of sequence, so as to avoid mutual preemption due to the shared cache of multiple logical partitions in the scenario of writing data concurrently.
  • the problem of the space in the cache makes the concurrent writing capability of each logical partition stronger.
  • the computing device sends at least one first IO command to the storage device.
  • the storage device receives at least one first IO command sent by the computing device.
  • the computing device may send an indication of a first IO command to a storage controller in the storage device.
  • the access address corresponding to each first IO command in the at least one first IO command is located in the first address range, and the first address range is determined according to the first address and the preset first length in the first logical partition Logical address range.
  • the first length is determined according to the size of the first cache space.
  • the first cache space is a cache space for caching IO commands that access the first logical partition in the cache in the storage device.
  • the first address range It is an address range with the first address as the starting address and the size of the first cache space corresponding to the first logical partition as the length.
  • the computing device can determine the first address range based on the address currently pointed to by the write pointer and the size of the first cache space corresponding to the first logical partition.
  • the first address range is the LBA range and falls within the
  • the IO commands within the first address range can be stored out of order in the first cache space.
  • the computing device does not issue IO commands beyond the first address range, because even if the IO commands beyond the first address range are issued To the storage device, it is first stored in the first cache space.
  • the IO command whose access address exceeds the first address range has not been written yet, and the IO command whose access address exceeds the first address range The command has timed out.
  • the IO command whose access address is within the first address range has not been written into the first logical partition, it is also allowed to be overwritten, that is, it can be overwritten by a newly issued IO command carrying the same address.
  • the computing device issues the IO command P, and the access address carried by the IO command P is also 70M, then IO command Q is overridden by IO command P.
  • the first address range will be described below with reference to examples.
  • the size of the first cache space configured by the host as zone1 is 50M
  • the address currently pointed to by the write pointer is P
  • the first address range is P ⁇ P+50MB
  • the first address range is within the range of 10-60M.
  • the computing device may send at least one first IO command with an access address in the range of 10-60M to the storage device.
  • the computing device may issue one first IO command to the storage device, or may issue multiple first IO commands, and the access address of each first IO command is within the range of 10-60M.
  • the computing device issues multiple first IO commands, the multiple first IO commands may be sent to the storage device concurrently, so as to implement concurrent writing of data to the storage device.
  • the storage device stores at least one first IO command in the first cache space corresponding to the first logical partition.
  • the storage controller in the storage device stores at least one first IO command in the first cache space.
  • the storage controller can follow the address in the first logical partition Search the first IO commands from the first cache space sequentially, and write the data carried in the found first IO commands to the first logical partition. For some reasons, some first IO commands may stay in the cache for a long time. In the first cache space, there has been no opportunity to refresh. Taking command P as an example to illustrate, the reason why command P has not been able to get the opportunity to refresh in the first cache space may be the processing of the storage controller.
  • the speed is slow, and it may also be that other first IO commands corresponding to the address before the access address corresponding to the command P have not been issued to the storage device, which causes the access address in the first cache space to be lower than the access address corresponding to the command P. Subsequent other first IO commands have no chance to be written into the first logical partition. For this reason, in a possible implementation manner, after the storage controller stores the at least one first IO command in the first cache space, the storage controller can also provide the at least one first IO command for each first IO command The first duration is set, and after the storage duration of any first IO command in the first cache space exceeds the first duration, the timed-out first IO command is deleted from the first cache space. Therefore, it is possible to prevent the first IO command that times out from consuming cache resources.
  • the storage controller may also return to the computing device a status code that sends the first IO command timed out, To prompt the computing device to delay and resend the timed-out first IO command. Further, the storage controller can also send the delay time corresponding to the IO command that needs to be delayed and resent to the computing device. an IO command.
  • the timeout status code of the first IO command and the delay time corresponding to the IO command that needs to be delayed and resent can be separately sent to the computing device by the storage controller, or can be sent with the first information when the first information needs to be sent. The first information is sent together to the computing device.
  • the storage device determines that the current start writing address of the first logical partition is the first address.
  • the storage controller determines that the current start write address of the first logical partition is the first address.
  • the storage device selects and executes a corresponding command from at least one first IO command according to the first address.
  • the storage controller selects a corresponding command from at least one first IO command according to the first address.
  • the storage device sends first information to the computing device in response to the at least one first IO command, where the first information is used for the computing device to issue an IO command corresponding to the second address.
  • the computing device receives the first information sent by the storage device in response to the at least one first IO command.
  • the The first address writes the first data, and sends to the computing device first information including a result of successfully writing the first data to the first address and a second address, and the second address is the same as the first address
  • the second address is different from the above-mentioned first address, and the second address is used by the computing device to issue the IO command corresponding to the second address, so that the storage device continues to operate by writing data in sequence.
  • the second address may be an address of a first unwritten data location following the first address and different from an access address corresponding to the IO command in the first cache space.
  • the fact that the second address is different from the access address corresponding to the IO command in the first cache space may also be understood as: there is no IO command corresponding to the first address in the first cache space corresponding to the first logical partition.
  • the second address is the current initial write address of the first logical partition address
  • the third address is the current initial write address of the first logical partition
  • the second address is different from the third address.
  • the second address is the current initial write address of the first logical partition. That is to say, after the first address writes the first data, the write pointer currently points to the second address. At this time, the second address is the first address where no data is written, and the second address does not exist in the first cache space. The corresponding IO command, so the computing device needs to issue the IO command corresponding to the second address.
  • the computing device may also write the first data to the first address successfully and the second The address determines at least one second IO command.
  • at least one second IO command includes a second IO command corresponding to the second address, and the access address corresponding to each second IO command is located in the second address range, and the second address range is the first logical partition according to the second address and the logical address range determined by the first length.
  • the second address range is an address range starting from the second address and taking the size of the first cache space corresponding to the first logical partition as the length. Address The address pointed to by the write pointer when writing data.
  • the specific implementation of the second address range can refer to the relevant content of the above-mentioned first address range, the difference between the two is: the start address of the first address range is the first address, and the start address of the second address range is the second address , therefore, relative to the first address range, the second address range is equivalent to sliding backward by the length of the first data written to the first address in the entire address range.
  • the third address is the current initial write address of the first logical partition, and the second address is different from the third address. That is to say, after the first address writes the first data, the write pointer currently points to the third address. At this time, the third address is the first address where no data is written. In this case, the first cache space has the first The IO command corresponding to the three addresses does not exist, and there is no IO command corresponding to the second address, so the computing device needs to issue the IO command corresponding to the second address.
  • the computing device may also write the first data to the first address successfully and the second The address determines at least one second IO command.
  • at least one second IO command includes the second IO command corresponding to the second address, and the access address corresponding to each second IO command is located in the second address range, and the second address range is based on the third address in the first logical partition. and the logical address range determined by the first length.
  • the second address range is an address range starting from the third address and taking the size of the first cache space corresponding to the first logical partition as the length. Address The address pointed to by the write pointer when writing data.
  • the specific implementation of the second address range can refer to the relevant content of the above-mentioned first address range, the difference between the two is: the start address of the first address range is the third address, and the start address of the second address range is the third address , therefore, relative to the first address range, the second address range is equivalent to sliding backward by the length of the first data written to the first address in the entire address range.
  • the first logical partition includes a plurality of LBAs, namely LBA0, LBA1, LBA2, LBA3...LBAn, the length of each LBA is 4k, and the first cache space corresponding to the first logical partition (size is 40k)
  • There are command 1, command 2 and command 3 stored in it where command 1 is used to indicate to write 8k data 1 into LBA0 and LBA1, command 2 is used to indicate to write 4k data 1 to LBA2, and command 3 is used to indicate to write 8k data Data 3 is written to LBA5.
  • the write pointer points to the first address (that is, LBA0), and the computing device determines according to the LBA0 pointed to by the write pointer and the size of the first cache space as 40k
  • the address range 1 is LBA0-LBA10, and the computing device issues an IO command with an access address within the range of LBA0-LBA10 to the storage device.
  • the storage controller can search for the IO command corresponding to LBA0 from the first cache space, that is, command 1 is found, the storage controller writes data 1 to LBA0 and LBA1, and returns a response 1 to the computing device, and the response 1 includes successfully sending data to LBA0 and LBA1.
  • LBA1 writes data 1 and the access address (that is, LBA3) corresponding to the IO command expected to be received.
  • the write pointer points to the third address, that is, the IO command corresponding to the next unwritten address (that is, LBA2), and the computing device determines the address range 2 according to the LBA2 pointed to by the write pointer and the size of the first cache space as 40k
  • the computing device issues a command with an access address within the range of LBA2-LBA12 to the storage device.
  • the storage controller can search the IO command carrying LBA2 from the first cache space, that is, find command 2, the storage controller writes data 2 to LBA2, and data 1 is actually stored in LBA2. Afterwards, the write pointer points to the address of the next unwritten data (i.e. LBA3), and the storage controller searches the IO command corresponding to LBA3 from the first cache space, but does not find the IO command corresponding to LBA3, and waits for the computing device to send the corresponding IO command to the storage device. Issue the IO command corresponding to the LBA3.
  • the first information may also include at least one of the following second information: the first logic The status code of the first cache space corresponding to the partition, the status code indicates that the first cache space is full; the remaining capacity of the storage device.
  • the method further includes: according to at least one item of second information included in the first information, determining whether to continue delivering the second IO command located in the second address range to the storage device.
  • the computing device can know in time when the first cache space is full or the remaining capacity is zero, and no longer sends data to the first logical partition.
  • the first logical partition issues write data.
  • the first information also includes at least one of the following third pieces of information: the amount of data that has been cached in the first cache space corresponding to the first logical partition and has not been written into the first logical partition; The remaining capacity of the cache space; the remaining capacity of the storage device; the remaining capacity of the first logical partition; the method also includes: if it is determined to continue sending the second IO command located in the second address range to the storage device, according to the first information At least one item of second information is included to determine the number of second IO commands within the second address range issued to the storage device. Therefore, the computing device can obtain relevant information about the first cache space corresponding to the first logical partition, so that the speed at which the first logical partition issues IO commands can be controlled.
  • the first information also includes timed-out IO commands in the first cache space corresponding to the first logical partition.
  • the method also includes: resending the timed-out IO command to the storage device. Therefore, the computing device can know which IO commands need to be resent, so as to avoid missing IO commands whose timeout expires.
  • the first information may also include a delay time corresponding to an IO command that is not successfully cached in the first cache space and is to be resent.
  • the method also includes: resending the IO command to be resent to the storage device after the waiting time reaches the delay time. In this way, the continuous delivery of data can be avoided.
  • the cache capacity of the first cache space in the storage device can be displayed in identify.
  • MB or KB can be used as the unit, and the size of the first cache space is represented by bit. Assuming that the unit is 1MB, 8 bits are used to represent the first cache space.
  • the size of the cache space can represent a maximum of 256MB; if the unit is 10MB, it can represent a maximum of 2560MB; if it exceeds the capacity of the representation, it can be directly represented by the value of full F.
  • the storage device if it does not find the first IO command corresponding to the first address from the first cache space, it suspends writing data to the first logical partition, and sends to the computing device including The result of failure to write data at one address and the first information of the second address, and the second address is the same as the first address, and the first information is used by the computing device to issue the first IO command corresponding to the first address.
  • the storage controller selects a command matching the current write pointer from the first cache space corresponding to the first logical partition to write data to the first logical partition, if the storage device has not received the address corresponding to the write pointer If the IO command corresponding to the address pointed to by the write pointer cannot be found in the first cache space, then the writing of data to the first logical partition is suspended, and the address corresponding to the address currently pointed to by the write pointer can be periodically searched from the first cache space.
  • the IO command corresponding to the address currently pointed to by the write pointer can also be searched in real time for the IO command corresponding to the address currently pointed to by the write pointer, until the storage device receives the IO command corresponding to the address currently pointed to by the write pointer, and writes data to the address currently pointed to by the write pointer. Then, the write pointer points to the next address in the order of addresses in the first logical partition.
  • the computing device specifies the address where the data is actually written in the IO command, and the storage device writes data to the specified address of the first logical partition according to the IO command, which is consistent with the writing behavior of the traditional SSD, so there is no need to change the system
  • the software architecture can implement concurrent writing of data to the storage device, which can reduce unnecessary complexity and workload.
  • the computing device can issue IO commands of any address within the first address range, and according to the feedback from the storage device The first information sends the IO command corresponding to the second address as soon as possible, so that the storage device continues to operate in the manner of sequentially writing data, thereby reducing the consumption of cache resources and effectively improving the efficiency of writing data.
  • FIG. 6 exemplarily shows a schematic diagram of writing a single IO command.
  • zone X includes the area where writing has been completed, the area (100M) where IO commands are being issued to the ZNS SSD, and the area where IO commands are not allowed to be issued temporarily.
  • the size of the first cache space corresponding to zone X is 100MB.
  • command A is a command that can be written directly from disk to N command AND F1 command Ash (the data that the write pointer expects to write)
  • B The four commands , C, D, and E are data written out of order within the allowable range, and are temporarily cached in the first cache space, and cannot be written into the zone yet.
  • the command G is that ZNS SSD expects to receive the command of the next address after completing the writing of command A; only after the command G is received, the sequential writing of the zone can be advanced, otherwise the following commands can only be temporarily cached in Inside the first cache space.
  • the host randomly sends write IOs to the disk within the range of P ⁇ P+100MB, assuming that 5 IOs of A, B, C, D, and E are currently issued command, wherein the access address corresponding to command A is the same as the address pointed to by the write pointer.
  • the storage controller of the ZNS SSD searches whether there is an IO command corresponding to the address pointed to by the write pointer P in the first cache space corresponding to the zone X;
  • the addresses pointed to by the write pointers are the same, that is, the IO command corresponding to the address pointed to by the write pointer P is command A, then the storage controller writes the data carried in command A into the write pointer in zone X as shown in (a) in Figure 6 the address pointed to.
  • the storage controller of the ZNS SSD After the storage controller of the ZNS SSD finishes writing the data carried by command A, it returns the information corresponding to command A to the host.
  • the information can include any one or more of the following: 1) The data corresponding to command A has been written successfully ; 2) the address carried by the next IO command expected to be received, such as the command G shown in (a) in Figure 6, this command G has not yet been sent to the ZNS SSD, so it cannot be found in the first cache space The command G; 3) How much data has been cached in the first cache space corresponding to the zone X and is still not written successfully; 4) How much data can be cached in the first cache space corresponding to the zone X; 4) The entire ZNS SSD is still available How much data to cache.
  • the host continues the follow-up processing according to the information corresponding to the successfully written command A, for example, according to the information corresponding to the command A, extracts the address corresponding to the next IO command expected to be received, and then slides backward to allow the IO command to be issued Address range; further, according to how much data can be cached in the first cache space, determine how many IO commands can be issued in the future; it can also be based on how much data has been cached in the first cache space corresponding to the zone X and is still written successfully , and how much data the entire ZNS SSD can cache, which can be used for subsequent expansion or statistics, so that it is convenient to grasp the relevant information of the first cache space corresponding to the zone X in real time.
  • the storage device selects an IO command that matches the current write pointer from the first cache space, and writes data to the first logical partition.
  • the storage device can arbitrarily select an IO command from the first cache space to write data into the first logical partition, for example, you can choose to write data in the first logical partition.
  • the data carried by the IO command with the longest duration is stored in the cache space, and the data is written into the first logical partition.
  • FIG. 7 is a schematic structural diagram of a device provided in an embodiment of the present application.
  • the device may be a computing device or a storage controller, and the computing device or storage controller may also be a chip or a circuit, such as a device that can be set in a computing device.
  • the apparatus 700 may include a processor 701 and a communication interface 702, and the processor 701 and the communication interface 702 may specifically be connected through a bus.
  • the processor 701 is coupled to a storage device through the communication interface 702 .
  • the processor 701 can implement the method executed by the computing device in FIG. 5 above.
  • the processor 701 is coupled to a computing device through the communication interface 702 .
  • the processor 701 may implement the method performed by the storage controller in FIG. 5 above.
  • an embodiment of the present application further provides a storage device, and the storage device may also be a chip or a circuit, for example, a chip or a circuit that may be provided in the storage device.
  • the storage device can refer to the above-mentioned FIG. 4.
  • the storage device 200 includes a storage controller 210, a cache 220, and a storage medium 230.
  • the storage controller 210 can refer to FIG. equipment.
  • the storage device may execute the above method performed by the storage device.
  • the processor 701 may be one chip.
  • the processor 701 may be a field programmable gate array (field programmable gate array, FPGA), may be an application specific integrated circuit (ASIC), may also be a system chip (system on chip, SoC), or It can be a central processing unit (central processor unit, CPU), or a network processor (network processor, NP), or a digital signal processing circuit (digital signal processor, DSP), or a microcontroller (micro controller) unit, MCU), it can also be a programmable controller (programmable logic device, PLD) or other integrated chips.
  • FPGA field programmable gate array
  • ASIC application specific integrated circuit
  • SoC system on chip
  • CPU central processing unit
  • NP network processor
  • DSP digital signal processing circuit
  • microcontroller micro controller
  • MCU microcontroller
  • PLD programmable logic device
  • each step of the above method may be completed by an integrated logic circuit of hardware in the processor 701 or instructions in the form of software.
  • the steps of the methods disclosed in connection with the embodiments of the present application may be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor 701 .
  • the software module can be located in random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers and other mature storage media in the field.
  • the storage medium is located in a flash memory array, and the processor 701 reads information in the flash memory array, and completes the steps of the above method in combination with its hardware.
  • the processor 701 in the embodiment of the present application may be an integrated circuit chip, which has a signal processing capability.
  • each step of the above-mentioned method embodiments may be completed by an integrated logic circuit of hardware in a processor or instructions in the form of software.
  • the above-mentioned processor may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components .
  • DSP digital signal processor
  • ASIC application-specific integrated circuit
  • FPGA field-programmable gate array
  • Various methods, steps, and logic block diagrams disclosed in the embodiments of the present application may be implemented or executed.
  • a general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like.
  • the steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in a mature storage medium in the field such as random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, register.
  • the storage medium is located in the memory, and the processor reads the information in the memory, and completes the steps of the above method in combination with its hardware.
  • the memory in the embodiments of the present application may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memories.
  • the non-volatile memory can be read-only memory (read-only memory, ROM), programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically programmable Erases programmable read-only memory (electrically EPROM, EEPROM) or flash memory.
  • Volatile memory can be random access memory (RAM), which acts as external cache memory.
  • RAM random access memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • DRAM synchronous dynamic random access memory
  • SDRAM double data rate synchronous dynamic random access memory
  • ESDRAM enhanced synchronous dynamic random access memory
  • SLDRAM direct memory bus random access memory
  • direct rambus RAM direct rambus RAM
  • the present application also provides a computer program product, the computer program product including: computer program code, when the computer program code is run on the computer, the computer is made to execute the embodiment shown in FIG. 5 method in .
  • the present application also provides a computer-readable storage medium, the computer-readable medium stores program code, and when the program code is run on the computer, the computer is made to execute the implementation shown in Figure 5.
  • the storage medium may be any available medium that can be accessed by a computer, such as SSD, PCM, and the like.
  • the present application further provides a data processing system, where the data processing system includes the computing device described in any one of the foregoing contents, a storage controller, and a flash memory array.
  • the embodiments of the present application may be provided as methods, systems, or computer program products. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions
  • the device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

一种数据处理方法、设备及系统，其中计算设备包括处理器和通信接口，处理器通过通信接口耦合至存储设备，处理器，用于：获取存储设备中的第一逻辑分区的第一地址，第一地址为第一逻辑分区当前的起始写入地址，第一逻辑分区为存储设备包括的多个逻辑分区中的任一个，向存储设备发送至少一个第一输入输出IO命令，每个第一IO命令对应的访问地址位于第一地址范围内，第一地址范围为第一逻辑分区中根据第一地址和预设的第一长度确定的逻辑地址范围，接收存储设备响应于至少一个第一IO命令而发送的第一信息，第一信息用于计算设备下发第二地址对应的IO命令，从而无需改变系统的软件架构就可实现向存储设备并发写数据，有效提高写数据的效率。

Description

一种数据处理方法、设备及系统 技术领域
本申请涉及计算机技术领域，尤其涉及一种数据处理方法、设备及系统。
背景技术
随着存储技术的不断发展，固态硬盘(solid state drive，SSD)因在性能、可靠性、能耗、轻便性上有着绝对优势而广泛应用于各个领域，SSD采用快闪记忆体(NAND Flash)作为存储介质，通常，SSD会包含多个NAND Flash颗粒。主机与传统的SSD交互的方式为主机在写IO命令中指定地址，然后SSD根据写命令向主机指定的地址中写入数据，但是不支持实现并发写数据。为进一步提高固态硬盘各方面的性能，业界提出了分区命名空间(zoned namespace，ZNS)SSD，其中，ZNS SSD的整个逻辑区块地址(logical block address，LBA)空间划分为多个分区(zone)，zone类似于叠瓦式磁记录(shingled magnetic recording，SMR)盘划分的一个区域，从而实现分区存储。由于zone内要求顺序写入，当多线程写入同一个zone时，多个线程之间会因为写指针的竞争导致写入速度受限或者写入位置不正确的问题，为此，ZNS提供了附加写(append)的写入模式，这种写入模式中主机(host)和硬盘的配合过程为：主机向SSD中的某个zone下发写IO命令时，该写IO命令携带的内容包括该zone的起始LBA、数据所占LBA的个数和数据本身，ZNS SSD接收到IO后，由ZNS SSD自主决定该IO携带的数据实际写入到zone中的位置，在ZNS SSD完成写操作后，将数据实际写入的该zone的位置的地址发送给host，host需要等待待写入的数据完成写入之后，再记录该实际写入数据的地址，这种配合方式能够允许host针对单个zone并发地下发多个写IO，但是主机与ZNS SSD的这种配合方式，需要改变包括传统的SSD和主机的存储系统中的软件架构才能实现，例如将传统的SSD中的闪存转换层(flash translation layer，FTL)从SSD内部迁移到上层的主机端，而且还需要改动传统的SSD的驱动器，从而引入了不必要的复杂度和额外的工作量。
发明内容
本申请提供一种数据处理方法、设备及系统，以实现在不改变传统存储系统的软件架构的情况下，实现计算设备向存储设备并发写数据，提高写数据的效率。
第一方面，本申请提供一种计算设备，该计算设备包括处理器和通信接口，处理器通过通信接口耦合至存储设备。处理器，用于：获取存储设备中的第一逻辑分区的第一地址，第一地址为第一逻辑分区当前的起始写入地址，第一逻辑分区为存储设备包括的多个逻辑分区中的任一个，向存储设备发送至少一个第一输入输出IO命令，其中每个第一IO命令对应的访问地址位于第一地址范围内，第一地址范围为第一逻辑分区中根据第一地址和预设的第一长度确定的逻辑地址范围，接收存储设备响应于至少一个第一IO命令而发送的第一信息，第一信息用于计算设备下发第二地址对应的IO命令。
本申请实施例中，计算设备通过在IO命令中指定数据实际写入的地址，存储设备根据IO命令向第一逻辑分区在的指定地址写入数据，与传统的SSD的写行为一致，所以无需改变系统的软件架构就可以实现向存储设备并发写数据，从而可以降低不必要的复杂度 和工作量，而且，计算设备可以下发第一地址范围内的任意地址的IO命令，并根据存储设备反馈的第一信息尽快下发第二地址对应的IO命令，以使存储设备按照顺序写数据的方式继续运行，从而可以减少缓存资源的消耗，有效提高写数据的效率。
在一种可能的设计中，第一长度根据第一缓存空间的大小确定，第一缓存空间为存储设备中的缓存中用于缓存访问第一逻辑分区的IO命令的缓存空间。该设计中，计算设备可以大并发地进行数据的乱序写，并缓存在第一缓存空间，写数据的快慢主要受第一缓存空间的大小的影响，IO命令的数量对写数据的快慢影响较小。
在一种可能的设计中，处理器，还用于：配置第一缓存空间的大小。通过配置第一缓存空间的大小，可以实现限制计算设备下发的IO命令的数量，从而提高写数据的效率。
在一种可能的设计中，第一信息包括成功向第一地址写入第一数据的结果和第二地址，且第二地址与第一地址不同，处理器，还用于：根据成功向第一地址写入第一数据的结果和第二地址，向存储设备发送至少一个第二IO命令，至少一个第二IO命令包括第二地址对应的第二IO命令。通过该设计，在向第一地址写成功数据的情况下，可以尽快下发下一个新的地址的IO命令。
在一种可能的设计中，第一逻辑分区当前的起始写入地址为第二地址，至少一个第二IO命令中每个第二IO命令对应的访问地址位于第二地址范围内，第二地址范围为第一逻辑分区中根据第二地址和第一长度确定的逻辑地址范围。通过该设计，在第一逻辑分区当前的起始写入地址对应的IO命令还未下发的情况下，计算设备可以尽快下发该第一逻辑分区当前的起始写入地址对应的IO命令。
在一种可能的设计中，第一逻辑分区当前的起始写入地址为第三地址，每个第二IO命令对应的访问地址位于第二地址范围内，第二地址范围为第一逻辑分区中根据第三地址和第一长度确定的逻辑地址范围。通过该设计，在第一逻辑分区当前的起始写入地址对应的IO命令已下发的情况下，计算设备可以尽快下发该第一逻辑分区当前的起始写入地址之后的访问地址对应的未下发的IO命令。
在一种可能的设计中，第一信息还包括以下至少一项第二信息：第一逻辑分区对应的第一缓存空间的状态码，状态码指示第一缓存空间已满；存储设备的剩余容量。处理器，还用于：根据第一信息包括的至少一项第二信息，确定是否继续向存储设备下发位于第二地址范围内的第二IO命令。通过该设计，可以在第一缓存空间已满或剩余容量为零时及时知晓，不再往第一逻辑分区下发数据，这样可形成反压机制，避免计算设备无限制的往该第一逻辑分区下发写数据。
在一种可能的设计中，第一信息还包括以下至少一项第三信息：第一逻辑分区对应的第一缓存空间已缓存的、且未写入第一逻辑分区的数据量；第一逻辑分区对应的第一缓存空间的剩余容量；存储设备的剩余容量；第一逻辑分区的剩余容量；处理器，还用于：若确定继续向存储设备下发位于第二地址范围内的第二IO命令时，根据第一信息包括的至少一项第二信息，确定向存储设备下发的位于第二地址范围内的第二IO命令的数量。通过该设计，计算设备可以获取到该第一逻辑分区对应的第一缓存空间的相关信息，从而可以实现控制该第一逻辑分区下发IO命令的速度。
在一种可能的设计中，第一信息还包括第一逻辑分区对应的第一缓存空间中超时的IO命令，处理器还用于：向存储设备重发超时的IO命令。通过该设计，可以使得计算设备知晓哪些IO命令需要重发，避免漏写超时结束的IO命令。
在一种可能的设计中，第一信息还包括未成功缓存在第一缓存空间的、且待重发的IO命令对应的延时时长，处理器具体用于：在等待时长达到延时时长后，向存储设备重发待重发的IO命令。通过该设计，可以避免不停的下发数据。
在一种可能的设计中，第一信息包括向第一地址写入第一数据失败的结果和第二地址，第二地址与第一地址相同，处理器，还用于：根据向第一地址写入第一数据失败的结果和第一地址，向存储设备发送第一地址对应的第一IO命令。通过该设计，在向第一地址写数据失败的情况下，可以尽快下发第一地址对应的IO命令。
第二方面，本申请提供一种存储控制器，该存储控制器包括处理器和通信接口，处理器通过通信接口耦合至计算设备。处理器，用于：接收计算设备发送的至少一个第一输入输出IO命令，其中每个第一IO命令对应的访问地址位于第一地址范围内，第一地址范围为第一逻辑分区中根据第一地址和预设的第一长度确定的逻辑地址范围，第一逻辑分区为存储设备包括的多个逻辑分区中的任一个；将至少一个第一IO命令存储于第一缓存空间中；确定第一逻辑分区当前的起始写入地址为第一地址，并根据第一地址从至少一个第一IO命令中选择并执行对应的命令，向所述计算设备发送第一信息，所述第一信息用于所述计算设备下发第二地址对应的IO命令。
本申请实施例中，通过计算设备在IO命令中指定数据实际写入的地址，存储控制器根据IO命令向第一逻辑分区在的指定地址写入数据，与传统的SSD的写行为一致，所以无需改变系统的软件架构就可以实现向存储控制器并发写数据，从而可以降低不必要的复杂度和工作量，而且，通过计算设备限定下发IO命令的范围，并向计算设备反馈第一信息，可以尽快下发存储控制器需要写入数据的地址对应的IO命令，从而可以减少缓存资源的消耗，有效提高写数据的效率。
在一种可能的设计中，第一长度根据第一缓存空间的大小确定，第一缓存空间为存储设备中的缓存中用于缓存访问第一逻辑分区的IO命令的缓存空间。该设计中，存储设备可以接收到计算设备大并发地下发数据，并将数据缓存在第一缓存空间，写数据的快慢主要受第一缓存空间的大小的影响，IO命令的数量对写数据的快慢影响较小。
在一种可能的设计中，第一逻辑分区对应的第一缓存空间的大小为计算设备配置。通过计算设备配置第一缓存空间的大小，可以实现限制计算设备下发的IO命令的数量，从而提高写数据的效率。
在一种可能的设计中，若从第一缓存空间中查找到所述第一地址对应的第一IO命令，所述第一地址对应的第一IO命令包括第一数据，则向所述第一地址写入所述第一数据，并向所述计算设备发送包括成功向所述第一地址写入第一数据的结果和第二地址的第一信息，且所述第二地址与所述第一地址不同，所述第一信息用于所述计算设备下发所述第二地址对应的IO命令。通过该设计，在成功向第一地址写入数据时，可以尽快获取到下一个需要写入数据的地址对应的IO命令，从而可以提高写数据的效率。
在一种可能的设计中，处理器，还用于：为至少一个第一IO命令中每个第一IO命令设置第一时长，在任一第一IO命令在第一缓存空间中的存储时长超出第一时长后，从第一缓存空间中删除超时的第一IO命令，从而可以避免超时的IO命令消耗缓存资源。
在一种可能的设计中，处理器，还用于：接收计算设备发送的至少一个第二IO命令，至少一个第二IO命令包括第二地址对应的第二IO命令，每个第二IO命令对应的访问地址位于第二地址范围内；若第一逻辑分区当前的起始写入地址为第二地址，第二地址范围 为第一逻辑分区中根据第二地址和第一长度确定的逻辑地址范围；或者，若第一逻辑分区当前的起始写入地址为第三地址，第二地址范围为第一逻辑分区中根据第三地址和第一长度确定的逻辑地址范围。通过该设计，存储设备可以及时接收到该第一逻辑分区当前的起始写入地址对应的IO命令，以及该第一逻辑分区当前的起始写入地址之后的访问地址对应的未下发的IO命令。
在一种可能的设计中，所述第一信息还包括以下至少一项第二信息：所述第一逻辑分区对应的所述第一缓存空间的状态码，所述状态码指示所述第一缓存空间已满；所述存储设备的剩余容量；所述第一信息包括的至少一项第二信息，用于计算设备确定是否继续向所述存储设备下发位于所述第二地址范围内的所述第二IO命令。通过该设计，可以使得计算设备在第一缓存空间已满或剩余容量为零时及时知晓，不再往第一逻辑分区下发数据，这样可形成反压机制，避免计算设备无限制的往该第一逻辑分区下发写数据。
在一种可能的设计中，所述第一信息还包括以下至少一项第三信息：所述第一逻辑分区对应的第一缓存空间已缓存的、且未写入所述第一逻辑分区的数据量；所述第一逻辑分区对应的第一缓存空间的剩余空间的容量；所述存储设备的剩余容量；所述第一逻辑分区的剩余容量；所述第一信息包括的至少一项第二信息，用于所述计算设备确定向所述存储设备下发的位于所述第二地址范围内的第二IO命令的数量。通过该设计，可以使得计算设备可以获取到该第一逻辑分区对应的第一缓存空间的相关信息，从而可以实现控制该第一逻辑分区下发IO命令的速度。
在一种可能的设计中，所述第一信息还包括所述第一逻辑分区对应的所述第一缓存空间中超时的IO命令；所述第一逻辑分区对应的所述第一缓存空间中超时的IO命令，用于向所述存储设备重发所述超时的IO命令。通过该设计，可以使得计算设备知晓哪些IO命令需要重发，避免漏写超时结束的IO命令。
在一种可能的设计中，所述第一信息还包括未成功缓存在所述第一缓存空间的、且待重发的IO命令对应的延时时长，所述延时时长用于所述计算设备在等待时长达到所述延时时长后，向所述存储设备重发所述待重发的IO命令。通过该设计，可以避免不停的下发数据。
在一种可能的设计中，所述处理器，具体用于：若从所述第一缓存空间中未查找到所述第一地址对应的第一IO命令，则暂停向所述第一逻辑分区写数据，并向所述计算设备发送包括向所述第一地址写数据失败的结果和所述第二地址的第一信息，且所述第二地址与所述第一地址相同，所述第一信息用于所述计算设备下发所述第一地址对应的第一IO命令。通过该设计，在未成功向第一地址写入数据时，可以尽快获取到当前需要写数据的第一地址对应的IO命令，从而可以提高写数据的效率。
第三方面，本申请提供一种存储设备，该存储设备包括存储介质、缓存以及如上述第二方面中任一可能的设计中所述的存储控制器，存储介质包括多个逻辑分区，所述多个逻辑分区包括第一逻辑分区，所述缓存包括多个缓存空间，所述多个缓存空间包括第一缓存空间，第一缓存空间为存储设备中的缓存中用于缓存访问第一逻辑分区的IO命令的缓存空间；存储控制器用于从第一缓存空间中查找第一逻辑分区当前的起始写入地址对应的IO命令，并将查找到的起始写入地址对应的IO命令携带的数据写入第一逻辑分区。
本申请实施例中，通过计算设备在IO命令中指定数据实际写入的地址，存储设备根据IO命令向第一逻辑分区在的指定地址写入数据，与传统的SSD的写行为一致，所以无 需改变系统的软件架构就可以实现向存储设备并发写数据，从而可以降低不必要的复杂度和工作量，而且，通过计算设备限定下发IO命令的范围，可以尽快下发存储设备需要写入数据的地址对应的IO命令，从而可以减少缓存资源的消耗，有效提高写数据的效率。
在一种可能的设计中，第一逻辑分区中的数据为通过顺序写入方式写入。
在一种可能的设计中，存储设备为分区命名空间固态硬盘ZNS SSD。
第四方面，一种数据处理方法，该方法应用于计算设备，该方法包括：获取存储设备中的第一逻辑分区的第一地址，第一地址为第一逻辑分区当前的起始写入地址；第一逻辑分区为存储设备包括的多个逻辑分区中的任一个；向存储设备发送至少一个第一输入输出IO命令，其中每个第一IO命令对应的访问地址位于第一地址范围内，第一地址范围为第一逻辑分区中根据第一地址和预设的第一长度确定的逻辑地址范围；接收存储设备响应于至少一个第一IO命令而发送的第一信息，第一信息用于计算设备下发第二地址对应的IO命令。
在一种可能的设计中，第一长度根据第一缓存空间的大小确定，第一缓存空间为存储设备中的缓存中用于缓存访问第一逻辑分区的IO命令的缓存空间。
在一种可能的设计中，获取存储设备中的第一逻辑分区的第一地址之前，该方法还包括：配置第一缓存空间的大小。
在一种可能的设计中，第一信息包括成功向第一地址写入第一数据的结果和第二地址，且第二地址与第一地址不同，接收存储设备响应于至少一个第一IO命令而发送的第一信息之后，还包括：根据成功向第一地址写入第一数据的结果和第二地址，向存储设备发送至少一个第二IO命令，至少一个第二IO命令包括第二地址对应的第二IO命令。
在一种可能的设计中，第一逻辑分区当前的起始写入地址为第二地址，至少一个第二IO命令中每个第二IO命令对应的访问地址位于第二地址范围内，第二地址范围为第一逻辑分区中根据第二地址和第一长度确定的逻辑地址范围。
在一种可能的设计中，第一逻辑分区当前的起始写入地址为第三地址，每个第二IO命令对应的访问地址位于第二地址范围内，第二地址范围为第一逻辑分区中根据第三地址和第一长度确定的逻辑地址范围。
在一种可能的设计中，第一信息还包括以下至少一项第二信息：第一逻辑分区对应的第一缓存空间的状态码，状态码指示第一缓存空间已满；存储设备的剩余容量。该方法还包括：根据第一信息包括的至少一项第二信息，确定是否继续向存储设备下发位于第二地址范围内的第二IO命令。
在一种可能的设计中，第一信息还包括以下至少一项第三信息：第一逻辑分区对应的第一缓存空间已缓存的、且未写入第一逻辑分区的数据量；第一逻辑分区对应的第一缓存空间的剩余容量；存储设备的剩余容量；第一逻辑分区的剩余容量；该方法还包括：若确定继续向存储设备下发位于第二地址范围内的第二IO命令时，根据第一信息包括的至少一项第二信息，确定向存储设备下发的位于第二地址范围内的第二IO命令的数量。
在一种可能的设计中，第一信息还包括第一逻辑分区对应的第一缓存空间中超时的IO命令。该方法还包括：向存储设备重发超时的IO命令。
在一种可能的设计中，第一信息还包括未成功缓存在第一缓存空间的、且待重发的IO命令对应的延时时长。该方法还包括：在等待时长达到延时时长后，向存储设备重发待重发的IO命令。
在一种可能的设计中，向存储设备发送至少一个第一输入输出IO命令，包括：向存储设备并发发送至少一个第一IO命令。
在一种可能的设计中，第一信息包括向第一地址写入第一数据失败的结果和第二地址，第二地址与第一地址相同；接收存储设备响应于至少一个第一IO命令而发送的第一信息之后，还包括：根据向第一地址写入第一数据失败的结果和第一地址，向存储设备发送第一地址对应的第一IO命令。
上述第四方面中的各项设计所对应的有益效果，具体请参照上述第一方面中的各项设计所对应的有益效果，此处不再一一重复赘述。
第五方面，本申请提供一种数据处理方法，该方法应用于存储设备或存储设备中的存储控制器，该方法包括：接收计算设备发送的至少一个第一输入输出IO命令，其中每个第一IO命令对应的访问地址位于第一地址范围内，第一地址范围为第一逻辑分区中根据第一地址和预设的第一长度确定的逻辑地址范围；将至少一个第一IO命令存储于第一缓存空间中；确定第一逻辑分区中当前的起始写入地址为第一地址，并根据第一地址从至少一个第一IO命令中选择并执行对应的命令；向计算设备发送第一信息，第一信息用于计算设备下发第二地址对应的IO命令。
在一种可能的设计中，第一长度根据第一缓存空间的大小确定，第一缓存空间为存储设备中的缓存中用于缓存访问第一逻辑分区的IO命令的缓存空间。
在一种可能的设计中，接收计算设备发送的至少一个第一输入输出IO命令之前，还包括：配置第一缓存空间的大小。
在一种可能的设计中，根据第一地址从至少一个第一IO命令中选择并执行对应的命令；向计算设备发送第一信息，包括：若从第一缓存空间中查找到第一地址对应的第一IO命令，第一地址对应的第一IO命令包括第一数据，则向第一地址写入第一数据，并向计算设备发送包括成功向第一地址写入第一数据的结果和第二地址的第一信息，且第二地址与第一地址不同，第一信息用于计算设备下发第二地址对应的IO命令。
在一种可能的设计中，将至少一个第一IO命令存储于第一缓存空间中之后，还包括：为至少一个第一IO命令中每个第一IO命令设置第一时长，在任一第一IO命令在第一缓存空间中的存储时长超出第一时长后，从第一缓存空间中删除超时的第一IO命令。
在一种可能的设计中，将至少一个第一IO命令存储于第一缓存空间中之后，还包括：接收计算设备发送的至少一个第二IO命令，至少一个第二IO命令包括第二地址对应的第二IO命令，每个第二IO命令对应的访问地址位于第二地址范围内；若第一逻辑分区当前的起始写入地址为第二地址，第二地址范围为第一逻辑分区中根据第二地址和第一长度确定的逻辑地址范围；或者，若第一逻辑分区当前的起始写入地址为第三地址，第二地址范围为第一逻辑分区中根据第三地址和第一长度确定的逻辑地址范围。
在一种可能的设计中，第一信息还包括以下至少一项第二信息：第一逻辑分区对应的第一缓存空间的状态码，状态码指示第一缓存空间已满；存储设备的剩余容量；第一信息包括的至少一项第二信息，用于计算设备确定是否继续向存储设备下发位于第二地址范围内的第二IO命令。
在一种可能的设计中，第一信息还包括以下至少一项第三信息：第一逻辑分区对应的第一缓存空间已缓存的、且未写入第一逻辑分区的数据量；第一逻辑分区对应的第一缓存空间的剩余空间的容量；存储设备的剩余容量；第一逻辑分区的剩余容量；第一信息包括 的至少一项第二信息，用于计算设备确定向存储设备下发的位于第二地址范围内的第二IO命令的数量。
在一种可能的设计中，第一信息还包括第一逻辑分区对应的第一缓存空间中超时的IO命令；第一逻辑分区对应的第一缓存空间中超时的IO命令，用于向存储设备重发超时的IO命令。
在一种可能的设计中，第一信息还包括未成功缓存在第一缓存空间的、且待重发的IO命令对应的延时时长，延时时长用于计算设备在等待时长达到延时时长后，向存储设备重发待重发的IO命令。
在一种可能的设计中，根据第一地址从至少一个第一IO命令中选择并执行对应的命令；向计算设备发送第一信息，包括：若从第一缓存空间中未查找到第一地址对应的第一IO命令，则暂停向第一逻辑分区写数据，并向计算设备发送包括向第一地址写数据失败的结果和第二地址的第一信息，且第二地址与第一地址相同，第一信息用于计算设备下发第一地址对应的第一IO命令。
上述第五方面中的各项设计所对应的有益效果，具体请参照上述第二方面中的各项设计所对应的有益效果，此处不再一一重复赘述。
第六方面，本申请实施例提供一种数据处理系统，包括上述第一方面中的各项设计所述的计算设备以及上述第一方面所述的存储设备。
第七方面，本申请实施例提供一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机程序，当所述计算机程序在计算机上运行时，使得计算机执行上述第四方面中的各项设计所述的方法，或者，执行上述第五方面中的各项设计所述的方法。
第八方面，本申请实施例提供一种计算机程序产品，当所述计算机程序产品在计算机上运行时，使得计算机执行上述第四方面中的各项设计所述的方法，或者，执行上述第五方面中的各项设计所述的方法。
上述第六方面至第八方面中的各项设计所对应的有益效果，具体请参照上述第四方面或第五方面中的各项设计所对应的有益效果，此处不再一一重复赘述。
附图说明
图1示例性示出一种NAND Flash颗粒示意图；
图2示例性示出一种SMR SSD与传统SSD对比示意图；
图3示例性示出ZNS SSD与主机配合写数据示意图；
图4示例性示出本申请实施例适用的一种系统架构示意图；
图5示例性示出本申请实施例提供的一种数据处理方法的流程示意图；
图6示例性示出单个IO命令写入示意图；
图7为本申请实施例提供的一种装置的结构示意图。
具体实施方式
本申请中的数据处理方案可以适用于包括具有数据存储功能的设备与计算设备的系统，其中，具有数据存储功能的设备例如可以为只具有数据存储功能的存储设备，如存储器，也可以为具有数据存储功能且还具有其它功能的电子设备。电子设备可以是包含诸如 个人数字助理和/或音乐播放器等功能的便携式电子设备，诸如手机、平板电脑、具备无线通讯功能的可穿戴设备(如智能手表)、或车载设备等。便携式电子设备的示例性实施例包括但不限于搭载
Figure PCTCN2021097486-appb-000001
或者其它操作系统的便携式电子设备。上述便携式电子设备也可以是诸如具有触敏表面(例如触控面板)的膝上型计算机(Laptop)等。还应当理解的是，在本申请其他一些实施例中，上述电子设备也可以是具有触敏表面(例如触控面板)的台式计算机。以下实施例中以系统包括存储设备和计算设备为例进行说明。
示例性地，存储器可以是易失性存储器，也可以是非易失性存储器，或可包括易失性和非易失性存储器两者。还可以是由这些易失性存储器或非易失性存储器所构成的硬盘，如SSD。其中，易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，如静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(dynamic RAM，DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM，DR RAM)。非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器
(electrically EPROM，EEPROM)或闪存。应注意，本申请描述的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
为便于理解，下文将以存储设备为SSD为例进行介绍。应理解，下文中所出现的“SSD”也可以替换为与SSD具有相似特性的任一其它存储设备，本申请对此不做限定。
SSD可包括存储控制器和存储介质，其中存储介质是由多个NAND Flash颗粒按照行列方式排列而成，多个NAND Flash颗粒通过总线连通至存储控制器。如图1所示，每个NAND Flash颗粒由多个Die组成，每个Die有多个区块(block)，每个Block有多个页(page)。单个Die的容量一般为8GB/16GB/32GB或更大，如果单个NAND Flash颗粒包括8个Die，则单个NAND颗粒的容量可以做到64GB/128GB/256GB或更大。
目前，为了提高传统的SSD各方面的性能，业界提出了采用叠瓦式磁记录(SMR)技术和分区命名空间(ZNS)技术的SSD，以下分别SMR SSD和ZNS SSD这两种SSD进行介绍。
第一种，SMR SSD。
如图2所示，SMR SSD将盘片上的数据磁道部分重叠，就像屋顶上的瓦片一样，这种技术被称为叠瓦式磁记录技术，采用该技术的SMR SSD相较于传统硬盘来说，在制造工艺方面的变动非常小，但却可以提高磁盘存储密度，降低单位容量的成本。SMR SSD的读行为和传统硬盘相同，但它的写行为有了巨大的变化，即不再支持随机写和原地更新写，只能进行顺序追加写，这是由于SMR SSD上新写入的磁道会覆盖与之重叠的所有磁道，从而摧毁其上的数据。
硬盘盘片被划分为同心圆状的磁道，磁道与磁道之间具有一定间隔，起到保护作用。硬盘的磁头位于盘片记录介质的上方，包含用于写入的写磁头和用于读取的读磁头，写磁头和读磁头都是独立的部件。在磁盘上想要写入数据，需要写磁头施加较强的磁场来改变 盘片上的记录，这就进一步要求写磁头足够大以产生所需的写入磁场强度。因此，如果磁道没有任何重叠，磁盘上每英寸能容纳的磁道数量由写磁头的宽度所决定。
叠瓦式写入则利用了磁盘读取所需要的磁场强度低于写入所需要的磁场强度的事实，磁盘读取所需的磁道宽度可以小于写入所需的轨道宽度，SMR SSD上数据的写入是通过部分重叠前一条磁道写入的，同时留出了足够的空间给较窄的读磁头读取前一条磁道的数据。
SMR磁盘将磁道划分为若干个带(band)，即由连续磁道所构成的可连续写入区域，每个区域构成一个需要顺序写入的基本单元。Band是SMR盘上的物理概念，其对应的逻辑概念是“区域”(zone)，是上层软件所能看到的SMR盘的顺序写区域。
第二种，ZNS SSD。
ZNS是NVMe里面新提出的一种主机和盘配合的方式。ZNS盘具有如下特性：
(1)如图3所示，ZNS SSD的整个LBA空间被划分为多个zone，单个zone的大小例如为4MB～4GB，单个zone有点类似于SMR SSD划分的一个区域。
(2)在单个zone里面，主机只能顺序写入数据，不能随机写入数据，可以随机读数据。
(3)某个zone被从头到尾写完一遍后，再次写入数据的时候，必须先将整个zone擦除掉，然后才能按顺序从头到尾进行数据的写入，一般来说，这里的一个zone，可以对应到NAND Flash上的一个或多个物理block。
(4)整个zone的数据是一起淘汰的，不需要进行有效数据的搬移，盘没有写放大。而常规的固态盘，是找包含无效数据最多的这种物理block，将其有效数据搬移走，然后将该block擦除，这就涉及到有效数据的搬移，从而有一定的写放大，ZNS的配合方式将写放大消除掉了。
本申请的下列实施例基于第二种ZNS SSD进行介绍。ZNS SSD顺序写入数据的方式，要求host串行地进行数据的写入，性能相对比较低，因此又引入了分区附加写(zone append)的这种并发写入的方式。如表1所示，zone append的并发写入方式能够支持单个zone内多个写命令的并发写，这种写入模式中host和硬盘的配合过程为：主机向ZNS SSD中的某个zone下发写命令时，该写命令携带内容包括该zone的起始LBA、数据所占的LBA的个数和数据本身，ZNS SSD接收到该IO命令后，由ZNS SSD自主决定该IO命令携带的数据实际写入到zone中的位置，在ZNS SSD完成写操作后，将数据实际写入到该zone的位置的起始地址发送给host，host记录该实际写入数据的地址。
表1示例性示出了zone append的并发写过程中的IO命令和响应携带的内容：
Figure PCTCN2021097486-appb-000002
Figure PCTCN2021097486-appb-000003
先对表1中的各个术语进行介绍：
Cmd#是指并发下发的多个写命令；
ZSLBA是指zone的起始地址；
starting LBA是指每个命令携带的zone的起始地址；
#LBAs是指命令对应的LBA个数；
assigned LBA是指SSD给这个命令实际分配的起始LBA，该LBA会返回给host；
write pointer是指该zone对应的写指针(写该命令的时候)；
write pointer(after Cmd)是指该zone对应的写指针(完成该命令的时候)。
主机与ZNS SSD的这种配合方式能够允许host针对单个zone并发地下发多个IO命令，但是为了实现上述主机与ZNS SSD的这种配合方式，需要将传统的SSD中的闪存转换层(Flash Translation Layer，FTL)从SSD内部迁移到上层的主机端，也就是说，需要重新设计存储系统的软件架构，而且需要传统驱动器不需要的额外软件，从而引入了不必要的复杂度和额外的工作量。
需要host记录每个IO命令携带的数据实际写入的地址，host需要维护数据与存储地址之间的映射关系，这样引入了不必要的复杂度和额外的工作量。
有鉴于此，本申请提出一种数据处理方法，用以实现不增加主机的工作量的情况下，实现向固态硬盘并发写数据。
下面将结合附图对本申请作进一步地详细描述。需要说明的是，在本申请的描述中“至少一个”是指一个或多个，其中，多个是指两个或两个以上。鉴于此，本发明实施例中也可以将“多个”理解为“至少两个”。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，字符“/”，如无特殊说明，一般表示前后关联对象是一种“或”的关系。以及，除非有特别说明，本申请实施例提及“第一”、“第二”等序数词是用于对多个对象进行区分，不用于限定多个对象的顺序、时序、优先级或者重要程度。
图4示例性示出本申请实施例适用的一种系统架构示意图，如图4所示，该系统架构中包括计算设备100和存储设备200。
计算设备100，用于向存储设备下发输入输出(input/output，IO)命令，以及接收该IO命令对应的响应，该IO命令中携带有待写入的数据、以及为待写入的数据指定的存储地址，该IO命令对应的响应包括第一信息，第一信息用于计算设备下发下一个地址对应的IO命令。计算设备100为具有数据处理能力或计算能力的设备，例如主机，计算设备100可包括处理器和通信接口，其中处理器可以包括但不限于中央处理器(central processing unit，CPU)、通用处理器或其他处理器等。
存储设备200可以包括存储控制器210、缓存220和存储介质230。计算设备100与存储控制器210之间、以及存储控制器210与存储介质230之间可以如图4所示的通过总线连接，也可以通过互连或其它方式连接，以实现通信。
其中，缓存220包括至少一个缓存空间，缓存空间用于缓存IO命令，IO命令用于指示存储控制器210向存储单元写入数据。存储介质230可以划分为至少一个逻辑空间(或分区)，每个逻辑空间(或分区)称为一个存储单元，存储单元与缓存空间一一对应。本申请实施例中的存储单元例如可以是ZNS SSD中的zone，NVME SSD中的命名空间(namespace)等，以下实施例中以存储单元为zone为例进行说明，后文不再赘述。
存储控制器210用于接收计算设备100发送的IO命令，并将IO命令存储于缓存中，针对一个存储单元，在确定该存储单元的写指针指向的位置的地址之后，从该存储单元对应的缓存空间中查找携带写指针指向的位置的地址的IO命令，然后，将查找到的IO命令携带的数据写入该存储单元中。
需要说明的是，图4中所示出的各部件可以在包括一个或多个信号处理和/或专用集成电路在内的硬件、软件、或硬件和软件的组合中实现，在此不予赘述。
下面结合图4所示的系统架构，通过具体的实施例来介绍本申请中的数据处理方法的具体实现过程。
图5示例性示出本申请实施例提供的一种数据处理方法的流程示意图，本申请实施例中，存储设备执行的步骤也可以由存储控制器执行，如图5所示，该方法包括：
S501，计算设备获取存储设备中的第一逻辑分区的第一地址。
该第一地址为第一逻辑分区当前的起始写入地址，也可以理解为第一逻辑分区中首个未写入数据的位置、且后续位置都可以写入数据的地址。本申请实施例中涉及到的第一地址、第二地址、以及第三地址等为逻辑区块地址(LBA)，后文不再赘述。
本申请实施例中，存储设备可以包括一个或多个逻辑分区，当存储设备包括多个逻辑分区时，S501中的第一逻辑分区可以为存储设备中包括的多个逻辑分区中的任一个逻辑分区。应理解，本申请实施例中，是以计算设备向存储设备中的一个逻辑分区(即第一逻辑分区)写数据为例进行说明的，如果存储设备包括多个逻辑分区，本申请实施例的方案也可以适用于向存储设备中的每个逻辑分区写数据的场景。
存储设备还可以包括缓存，缓存中包括一个或多个缓存空间，缓存中包括第一缓存空间，该第一缓存空间为存储设备中的缓存中用于缓存访问第一逻辑分区的IO命令的缓存空间。当存储设备包括一个逻辑分区(即第一逻辑分区)时，该第一逻辑分区对应的缓存空间的大小即为存储设备的缓存的大小，也可以大于存储设备的缓存的大小；当存储设备包括多个逻辑分区时，所有的逻辑分区对应的缓存空间的总和可以等于缓存的大小，也可以大于存储设备的缓存的大小。如果存储设备检测到缓存已写满，可以向计算设备返回相应的错误码(或者称为状态码)，以提示计算设备延时重试，即延时重新下发因缓存已写满而无法存储于缓存中的IO命令。
在一种可能的实现方式中，计算设备没有为存储设备包括的各个逻辑分区配置对应的缓存空间的大小，则默认缓存为所有逻辑分区共享，也就是说，单个逻辑分区对应的缓存空间没有大小约束，只有一个存储设备的缓存的大小的约束。
在另一可能的实现方式中，在计算设备获取存储设备中的第一逻辑分区的第一地址之前，计算设备还可以为存储设备包括的各个逻辑分区分别配置对应的缓存空间的大小。
在一个示例中，以计算设备为主机，存储设备为ZNS SSD，ZNS SSD包括四个第一逻辑分区为例，一个逻辑分区即为一个zone，即ZNS SSD包括四个zone。一般情况下，ZNS SSD的内存，可以作为缓存供各个zone使用，例如，2GB的内存，元数据开销为0.5GB，剩下的1.5GB内存都可作为缓存，缓存空间内的数据无需备电保护。host可以根据实际需要，为四个zone分别配置每个zone对应的缓存空间的大小。其中，缓存空间的大小可以在host创建zone时配置，也可以通过下发set feature命令，以实现针对指定的zone单独配置缓存空间的大小。
通过该实现方式，计算设备为每个逻辑分区配置对应的缓存空间的大小，例如为第一逻辑分区配置第一缓存空间的大小，又例如为第二逻辑分区配置第二缓存空间的大小，从而实现按需配置各个缓存空间的大小，缓存空间的大小决定了计算设备能够在多大地址范围内乱序写，从而可以避免多个逻辑分区在并发写数据的场景下，因共享缓存而出现相互抢占缓存内的空间的问题，从而使得每个逻辑分区的并发写能力更强。
S502，计算设备向存储设备发送至少一个第一IO命令。相应的，存储设备接收计算设备发送的至少一个第一IO命令。
具体的，计算设备可以向存储设备中的存储控制器发送指示一个第一IO命令。
其中，该至少一个第一IO命令中每个第一IO命令对应的访问地址位于第一地址范围内，第一地址范围为第一逻辑分区中根据第一地址和预设的第一长度确定的逻辑地址范围。第一IO命令中可以有一个字段来指示该第一IO命令访问存储设备的逻辑地址。
一种可能的实施方式中，第一长度根据第一缓存空间的大小确定，第一缓存空间为存储设备中的缓存中用于缓存访问第一逻辑分区的IO命令的缓存空间，第一地址范围为以第一地址为起始地址，且以第一逻辑分区对应的第一缓存空间的大小为长度的地址范围。
对于一个逻辑分区来说，计算设备可以基于写指针当前指向的地址和该第一逻辑分区对应的第一缓存空间的大小，确定第一地址范围，该第一地址范围是LBA范围，落在该第一地址范围内的IO命令可以乱序存储于第一缓存空间中，一般而言，计算设备不下发超出该第一地址范围的IO命令，因为超出该第一地址范围的IO命令即使下发至存储设备，先存储于第一缓存空间中，当向第一逻辑分区顺序写入数据时，还未写到访问地址超出第一地址范围的IO命令，该访问地址超出第一地址范围的IO命令已经超时。此外，访问地址在该第一地址范围内的IO命令，只要还未被写入到第一逻辑分区中，也允许被覆盖写，即可以被新下发的携带相同地址的IO命令覆盖。例如，以IO命令Q携带的访问地址为70M为例，该IO命令Q还未被写到第一逻辑分区中，计算设备下发IO命令P，IO命令P携带的访问地址也为70M，那么IO命令Q被IO命令P覆盖。
下面结合示例对第一地址范围进行说明。
以计算设备为host、第一逻辑分区为zone1为例，host为zone1配置的第一缓存空间的大小为50M，写指针当前指向的地址为P，那么第一地址范围为P～P+50MB，假设写指针当前指向的地址为10M，那么第一地址范围为10～60M的范围内。计算设备可以向存储设备发送至少一个访问地址在10～60M的范围内的第一IO命令。
计算设备可以向存储设备下发一个第一IO命令，也可以下发多个第一IO命令，每个第一IO命令的访问地址在10～60M范围内。当计算设备下发多个第一IO命令时，多个第一IO命令可以是并发发送至存储设备，从而实现向存储设备并发写数据。
S503，存储设备将至少一个第一IO命令存储于第一逻辑分区对应的第一缓存空间中。
具体的，存储设备中的存储控制器将至少一个第一IO命令存储于第一缓存空间中。
由于计算设备可以并发向存储设备下发多个第一IO命令，而且可以乱序下发，随着第一缓存空间存储的第一IO命令增多，存储控制器可以按照第一逻辑分区中的地址顺序从第一缓存空间查找第一IO命令，并将查找到的第一IO命令中携带的数据写入第一逻辑分区中，由于某些原因，可能会出现有些第一IO命令长时间滞留在第一缓存空间中，一直得不到下刷的机会，以命令P为例进行说明，影响命令P在第一缓存空间中一直得不到下刷的机会的原因，可能是存储控制器的处理速度慢，也可能是在该命令P对应的访问地址之前的地址所对应其它第一IO命令还没有下发到存储设备，从而引起在第一缓存空间中的访问地址在命令P对应的访问地址之后的其它第一IO命令没机会写入到第一逻辑分区中。为此，一种可能的实施方式中，在存储控制器将至少一个第一IO命令存储于第一缓存空间中之后，存储控制器还可以为至少一个第一IO命令中每个第一IO命令设置第一时长，在任一第一IO命令在第一缓存空间中的存储时长超出第一时长后，从第一缓存空间中删除超时的第一IO命令。从而可以避免超时的第一IO命令消耗缓存资源。
在一种可能的实施方式中，在任一第一IO命令在第一缓存空间中的存储时长超出第一时长后，存储控制器还可以向计算设备返回发送该第一IO命令超时的状态码，以提示计算设备延时重发该超时的第一IO命令。进一步，存储控制器还可以向计算设备发送需要延时重发的IO命令对应的延时时长，例如延时时长为5ms，那么计算设备可以在5ms后重新向存储控制器下发该超时的第一IO命令。可选的，该第一IO命令超时的状态码和需要延时重发的IO命令对应的延时时长可以分别由存储控制器单独发送给计算设备，也可以在需要发送第一信息时，与第一信息一起发送给计算设备。
S504，存储设备确定第一逻辑分区当前的起始写入地址为第一地址。
在具体实施中，存储控制器确定第一逻辑分区当前的起始写入地址为第一地址。
S505，存储设备根据第一地址从至少一个第一IO命令中选择并执行对应的命令。
在具体实施中，存储控制器根据第一地址从至少一个第一IO命令中选择对应的命令。
S506，存储设备响应于至少一个第一IO命令而向计算设备发送第一信息，所述第一信息用于所述计算设备下发第二地址对应的IO命令。相应的，计算设备接收存储设备响应于所述至少一个第一IO命令而发送的第一信息。
具体的，存储设备从第一缓存空间中是否查找到第一地址对应的第一IO命令。
在一种可能的实施方式中，若从第一缓存空间中查找到所述第一地址对应的第一IO命令，所述第一地址对应的第一IO命令包括第一数据，则向所述第一地址写入所述第一数据，并向所述计算设备发送包括成功向所述第一地址写入第一数据的结果和第二地址的第一信息，且所述第二地址与所述第一地址不同，第二地址为用于计算设备下发第二地址对应的IO命令，以使存储设备按照顺序写数据的方式继续运行。
在一种实施方式中，该第二地址可以为第一地址之后、且与第一缓存空间中的IO命令对应的访问地址不同的首个未写入数据的位置的地址。其中，第二地址与第一缓存空间中的IO命令对应的访问地址不同也可以理解为：第一逻辑分区对应的第一缓存空间中不存在第一地址对应的IO命令。存储设备向计算设备发送第一信息时，第一逻辑分区中还未在该第二地址写入任何数据，而且在第一逻辑分区对应的第一缓存空间中也并未查找到该第二地址对应的IO命令，所以该第二地址也是存储设备期望接收到IO命令中携带的下一个地址，通过在第一信息中携带第二地址，可以使得计算设备及时下发存储设备期望接 收到的第二地址对应的IO命令。
在存储设备中的存储控制器向第一逻辑分区中的第一地址写入第一数据之后，可能会有两种情况，情况一，第二地址为该第一逻辑分区当前的起始写入地址；情况二，第三地址为该第一逻辑分区当前的起始写入地址，且第二地址与第三地址不同。针对这两种情况，存储设备的后续处理不同，分别描述如下：
情况一，第二地址为该第一逻辑分区当前的起始写入地址。也就是说，在第一地址写入第一数据之后，写指针当前指向第二地址，此时，第二地址就是首个未写入数据的地址，第一缓存空间并不存在该第二地址对应的IO命令，所以需要计算设备下发该第二地址对应的IO命令。
一种可能的实施方式中，在计算设备接收存储设备响应于至少一个第一IO命令而发送的第一信息之后，计算设备还可以根据成功向第一地址写入第一数据的结果和第二地址，确定至少一个第二IO命令。其中，至少一个第二IO命令包括第二地址对应的第二IO命令，每个第二IO命令对应的访问地址位于第二地址范围内，第二地址范围为第一逻辑分区中根据第二地址和第一长度确定的逻辑地址范围。
在该情况二中，第二地址范围为以第二地址为起始地址，以第一逻辑分区对应的第一缓存空间的大小为长度的地址范围，第二地址为存储控制器成功在第一地址写入数据时写指针指向的地址。其中，第二地址范围的具体实现可以参考上述第一地址范围的相关内容，二者区别在于：第一地址范围的起始地址为第一地址，第二地址范围的起始地址为第二地址，因此，第二地址范围相对于第一地址范围来说，相当于整个地址范围向后滑动了写入到第一地址的第一数据的长度。
情况二，第三地址为该第一逻辑分区当前的起始写入地址，且第二地址与第三地址不同。也就是说，在第一地址写入第一数据之后，写指针当前指向第三地址，此时，第三地址就是首个未写入数据的地址，这种情况下，第一缓存空间存在第三地址对应的IO命令，而不存在该第二地址对应的IO命令，所以需要计算设备下发第二地址对应的IO命令。
一种可能的实施方式中，在计算设备接收存储设备响应于至少一个第一IO命令而发送的第一信息之后，计算设备还可以根据成功向第一地址写入第一数据的结果和第二地址，确定至少一个第二IO命令。其中，至少一个第二IO命令包括第二地址对应的第二IO命令，每个第二IO命令对应的访问地址位于第二地址范围内，第二地址范围为第一逻辑分区中根据第三地址和第一长度确定的逻辑地址范围。
在该情况二中，第二地址范围为以第三地址为起始地址，以第一逻辑分区对应的第一缓存空间的大小为长度的地址范围，第三地址为存储控制器成功在第一地址写入数据时写指针指向的地址。其中，第二地址范围的具体实现可以参考上述第一地址范围的相关内容，二者区别在于：第一地址范围的起始地址为第三地址，第二地址范围的起始地址为第三地址，因此，第二地址范围相对于第一地址范围来说，相当于整个地址范围向后滑动了写入到第一地址的第一数据的长度。
举个例子，第一逻辑分区包括多个LBA，分别为LBA0、LBA1、LBA2、LBA3……LBAn，每个LBA的长度为4k，该第一逻辑分区对应的第一缓存空间(大小为40k)中存储有命令1，命令2和命令3，其中命令1用于指示将8k的数据1写入LBA0和LBA1，命令2用于指示将4k的数据1写入LBA2，命令3用于指示将8k的数据3写入LBA5。
以第一地址为第一逻辑分区的起始地址LBA0为例，首先，写指针指向第一地址(即 LBA0)，计算设备根据写指针指向的LBA0、以及第一缓存空间的大小为40k，确定地址范围1为LBA0～LBA10，计算设备向存储设备下发访问地址在LBA0～LBA10范围内的IO命令。
存储控制器可以从第一缓存空间中查找LBA0对应的IO命令，即找到命令1，存储控制器向LBA0和LBA1写入数据1，并向计算设备返回响应1，响应1包括已成功向LBA0和LBA1写入数据1、以及期待接收到的IO命令对应的访问地址(即LBA3)。
之后，写指针指向第三地址，即下一个未写入数据的地址(即LBA2)对应的IO命令，计算设备根据写指针指向的LBA2、以及第一缓存空间的大小为40k，确定地址范围2为LBA2～LBA12，计算设备向存储设备下发访问地址在LBA2～LBA12范围内的命令。
存储控制器可以从第一缓存空间中查找携带LBA2的IO命令，即找到命令2，存储控制器向LBA2写入数据2，数据1实际存储在LBA2中。之后，写指针指向下一个未写入数据的地址(即LBA3)，存储控制器从第一缓存空间中查找LBA3对应的IO命令，但并未找到LBA3对应的IO命令，等待计算设备向存储设备下发该LBA3对应的IO命令。
在一种可能的实施方式中，第一信息除了包括成功向第一地址写入第一数据的结果和第二地址之外，第一信息还可以包括以下至少一项第二信息：第一逻辑分区对应的第一缓存空间的状态码，状态码指示第一缓存空间已满；存储设备的剩余容量。该方法还包括：根据第一信息包括的至少一项第二信息，确定是否继续向存储设备下发位于第二地址范围内的第二IO命令。该实施方式中，可以使得计算设备在第一缓存空间已满或剩余容量为零时及时知晓，不再往第一逻辑分区下发数据，这样可形成反压机制，避免计算设备无限制的往该第一逻辑分区下发写数据。
进一步地，第一信息还包括以下至少一项第三信息：第一逻辑分区对应的第一缓存空间已缓存的、且未写入第一逻辑分区的数据量；第一逻辑分区对应的第一缓存空间的剩余容量；存储设备的剩余容量；第一逻辑分区的剩余容量；该方法还包括：若确定继续向存储设备下发位于第二地址范围内的第二IO命令时，根据第一信息包括的至少一项第二信息，确定向存储设备下发的位于第二地址范围内的第二IO命令的数量。从而可以使得计算设备可以获取到该第一逻辑分区对应的第一缓存空间的相关信息，从而可以实现控制该第一逻辑分区下发IO命令的速度。
更进一步地，第一信息还包括第一逻辑分区对应的第一缓存空间中超时的IO命令。该方法还包括：向存储设备重发超时的IO命令。从而可以使得计算设备知晓哪些IO命令需要重发，避免漏写超时结束的IO命令。
更进一步地，第一信息还可以包括未成功缓存在第一缓存空间的、且待重发的IO命令对应的延时时长。该方法还包括：在等待时长达到延时时长后，向存储设备重发待重发的IO命令。从而可以避免不停的下发数据。
存储设备中第一缓存空间的缓存能力可以在identify里呈现，对于数据量，可以以MB或KB为单位，用bit表示第一缓存空间的大小，假设单位是1MB，用8个bit表示第一缓存空间的大小，最大可以表示256MB；如果单位是10MB，最大可以表示2560MB；如果超过表示的能力，则直接用全F的值表示。
在另一种可能的实施方式中，若存储设备从第一缓存空间中未查找到第一地址对应的第一IO命令，则暂停向第一逻辑分区写数据，并向计算设备发送包括向第一地址写数据失败的结果和第二地址的第一信息，且第二地址与第一地址相同，第一信息用于计算设备 下发第一地址对应的第一IO命令。
通过上述实施例，存储控制器从第一逻辑分区对应的第一缓存空间中选择与当前写指针匹配的命令向第一逻辑分区中写数据，如果存储设备还未收到写指针指向的地址对应的IO命令，即第一缓存空间中查找不到写指针指向的地址对应的IO命令，那么暂停向第一逻辑分区写数据，可以周期性从第一缓存空间中查找写指针当前指向的地址对应的IO命令，也可以实时查找写指针当前指向的地址对应的IO命令，直到存储设备收到该写指针当前指向的地址对应的IO命令，向该写指针当前指向的地址写入数据。然后，写指针按照第一逻辑分区中的地址顺序指向下一个地址。
通过上述方法，计算设备通过在IO命令中指定数据实际写入的地址，存储设备根据IO命令向第一逻辑分区在的指定地址写入数据，与传统的SSD的写行为一致，所以无需改变系统的软件架构就可以实现向存储设备并发写数据，从而可以降低不必要的复杂度和工作量，而且，计算设备可以下发第一地址范围内的任意地址的IO命令，并根据存储设备反馈的第一信息尽快下发第二地址对应的IO命令，以使存储设备按照顺序写数据的方式继续运行，从而可以减少缓存资源的消耗，有效提高写数据的效率。
下面以存储设备为ZNS SSD，第一逻辑分区为分区(zone)X为例，结合图6，对本申请的数据处理方法进行说明。
图6示例性示出单个IO命令写入示意图。如图6所示，zone X包括已完成写的区域、正在往ZNS SSD下发IO命令的区域(100M)、暂不允许下发IO命令的区域，zone X对应的第一缓存空间的大小为100MB。
如图6中(a)所示，从当前写指针P指向的位置，向后推100MB，该P～P+100MB的地址范围内的IO命令可以乱序下发给ZNS SSD，假设Zone X对应的缓存区域已经收到A、B、C、D、E这5个命令，这时命令A是可以直接由盘往N命令AND Fl命令Ash写的命令(写指针期望写入的数据)，B、C、D、E这4个命令是在允许范围内乱序写入的数据，暂时缓存在第一缓存空间里面，还无法写入zone中去。而命令G是ZNS SSD在完成命令A的写入后，期望接收到下一个地址的命令；只有G这个命令收到后，zone的顺序写入才能推进下去，否则后面的命令只能暂时缓存在第一缓存空间里面。
如图6中(b)所示，命令A写成功后，zone的可以往盘写入数据的区域往后滑动命令A对应IO大小的范围(命令A的CQE返回期望接收的下一个IO的offset，这个offset可以作为host侧允许下发IO的起始LBA地址：P)；命令A返回后，host可以下发P指针往后100MB范围内的任何还未下发的IO；这时下发的IO会缓存在第一缓存空间里面；只有G对应的这个IO下发给SSD后，顺序写才能继续推进。
下面给出针对图6的写数据流程，包括如下步骤：
S1，基于zone X的写指针P所指的位置，主机在P～P+100MB范围内，随机下发写IO给盘，假设当前下发了A、B、C、D、E这5个IO命令，其中，命令A对应的访问地址与写指针指向的地址相同。
S2，基于zone X的写指针P，ZNS SSD的存储控制器查找该zone X对应的第一缓存空间中是否有写指针P指向的地址对应的IO命令；由于查找到命令A对应的访问地址与写指针指向的地址相同，即写指针P指向的地址对应的IO命令为命令A，则存储控制器将命令A中携带的数据写入如图6中(a)所示的zone X中写指针指向的地址。
S3，ZNS SSD的存储控制器完成命令A携带的数据写入后，向主机返回命令A对应的信息，该信息可以包括以下任一项或多项内容：1)命令A对应的数据已写成功；2)期望接收到的下一个IO命令携带的地址，例如图6中(a)所示的命令G，该命令G还未下发到ZNS SSD中，所以在第一缓存空间中查找不到该命令G；3)该zone X对应的第一缓存空间已缓存了多少还为写成功的数据；4)该zone X对应的第一缓存空间还可以缓存多少数据；4)整个ZNS SSD还可以缓存多少数据。
S4，主机根据已经写成功的命令A对应的信息，继续后续处理，例如，根据命令A对应的信息，提取期望接收到的下一个IO命令对应的地址，然后向后滑动允许下发IO命令的地址范围；进一步，还可以根据第一缓存空间还可以缓存多少数据，确定后续还可以下发多少IO命令；还可以根据该zone X对应的第一缓存空间已缓存了多少还为写成功的数据，以及整个ZNS SSD还可以缓存多少数据，可以作为后续扩展或统计用，便于实时掌握该zone X对应的第一缓存空间的相关信息。
本申请实施例中，对于要求顺序递增写入数据的存储设备，存储设备从第一缓存空间中选择与当前写指针匹配的IO命令，向第一逻辑分区中写入数据，具体方法可以参见上述实施例。而对于乱序写入数据的存储设备，与上述实施例不同点在于，存储设备可以从第一缓存空间中任意选择IO命令，向第一逻辑分区中写入数据，例如，可以选择在第一缓存空间里面存储时长最长的IO命令携带的数据，向第一逻辑分区中写入数据。
根据前述方法，图7为本申请实施例提供的一种装置的结构示意图，该装置可以为计算设备或存储控制器，该计算设备或存储控制器也可以为芯片或电路，比如可设置于计算设备或存储控制器中的芯片或电路。如图7所示，该装置700可以包括处理器701和通信接口702，处理器701和通信接口702具体可通过总线连接。
当该装置700为计算设备时，处理器701通过所述通信接口702耦合至存储设备。处理器701可实现上述图5中的计算设备所执行的方法。
当该装置700为存储控制器时，处理器701通过所述通信接口702耦合计算设备。处理器701可实现上述图5中的存储控制器所执行的方法。
根据前述方法，本申请实施例还提供一种存储设备，该存储设备也可以为芯片或电路，比如可设置于存储设备中的芯片或电路。该存储设备可以参照上述图4，存储设备200包括存储控制器210、缓存220和存储介质230，存储控制器210可以参照图7，其中存储控制器210中的处理器701通过通信接口702耦合计算设备。存储设备可以执行上述存储设备所执行方法。
应理解，上述处理器701可以是一个芯片。例如，该处理器701可以是现场可编程门阵列(field programmable gate array，FPGA)，可以是专用集成芯片(application specific integrated circuit，ASIC)，还可以是系统芯片(system on chip，SoC)，还可以是中央处理器(central processor unit，CPU)，还可以是网络处理器(network processor，NP)，还可以是数字信号处理电路(digital signal processor，DSP)，还可以是微控制器(micro controller unit，MCU)，还可以是可编程控制器(programmable logic device，PLD)或其他集成芯片。
在实现过程中，上述方法的各步骤可以通过处理器701中的硬件的集成逻辑电路或者软件形式的指令完成。结合本申请实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器701中的硬件及软件模块组合执行完成。软件模块可以位于随机 存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于闪存阵列，处理器701读取闪存阵列中的信息，结合其硬件完成上述方法的步骤。
应注意，本申请实施例中的处理器701可以是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法实施例的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器可以是通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现场可编程门阵列(FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤。
可以理解，本申请实施例中的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(dynamic RAM，DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM，DR RAM)。应注意，本文描述的系统和方法的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
该存储控制器所涉及的与本申请实施例提供的技术方案相关的概念，解释和详细说明及其他步骤请参见前述方法或其他实施例中关于这些内容的描述，此处不做赘述。
根据本申请实施例提供的方法，本申请还提供一种计算机程序产品，该计算机程序产品包括：计算机程序代码，当该计算机程序代码在计算机上运行时，使得该计算机执行图5所示实施例中的方法。
根据本申请实施例提供的方法，本申请还提供一种计算机可读存储介质，该计算机可读介质存储有程序代码，当该程序代码在计算机上运行时，使得该计算机执行图5所示实施例中的方法。其中，存储介质可以是计算机能够存取的任何可用介质，例如SSD、PCM等。
根据本申请实施例提供的方法，本申请还提供一种数据处理系统，该数据处理系统包括上述内容任一所述的计算设备、存储控制器和闪存阵列。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机 可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的保护范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (30)

  1. 一种计算设备，其特征在于，包括：处理器和通信接口，所述处理器通过所述通信接口耦合至存储设备；
    所述处理器，用于：
    获取所述存储设备中的第一逻辑分区的第一地址，所述第一地址为所述第一逻辑分区当前的起始写入地址；所述第一逻辑分区为所述存储设备包括的多个逻辑分区中的任一个；
    向所述存储设备发送至少一个第一输入输出IO命令，其中每个第一IO命令对应的访问地址位于第一地址范围内，所述第一地址范围为所述第一逻辑分区中根据所述第一地址和预设的第一长度确定的逻辑地址范围；
    接收所述存储设备响应于所述至少一个第一IO命令而发送的第一信息；所述第一信息用于所述计算设备下发第二地址对应的IO命令。
  2. 如权利要求1所述的计算设备，其特征在于，所述第一长度根据第一缓存空间的大小确定，所述第一缓存空间为所述存储设备中的缓存中用于缓存访问所述第一逻辑分区的IO命令的缓存空间。
  3. 如权利要求2所述的计算设备，其特征在于，所述处理器，还用于：
    配置所述第一缓存空间的大小。
  4. 如权利要求1-3任一项所述的计算设备，其特征在于，所述第一信息包括成功向所述第一地址写入第一数据的结果和第二地址，且所述第二地址与所述第一地址不同，所述处理器，还用于：
    根据所述成功向所述第一地址写入第一数据的结果和第二地址，向所述存储设备发送至少一个第二IO命令，所述至少一个第二IO命令包括所述第二地址对应的第二IO命令。
  5. 如权利要求4所述的计算设备，其特征在于，所述第一逻辑分区当前的起始写入地址为所述第二地址，所述至少一个第二IO命令中每个所述第二IO命令对应的访问地址位于第二地址范围内，所述第二地址范围为所述第一逻辑分区中根据所述第二地址和所述第一长度确定的逻辑地址范围。
  6. 如权利要求4所述的计算设备，其特征在于，所述第一逻辑分区当前的起始写入地址为所述第三地址，每个所述第二IO命令对应的访问地址位于第二地址范围内，所述第二地址范围为所述第一逻辑分区中根据所述第三地址和所述第一长度确定的逻辑地址范围。
  7. 如权利要求5或6所述的计算设备，其特征在于，所述第一信息还包括以下至少一项第二信息：
    所述第一逻辑分区对应的所述第一缓存空间的状态码，所述状态码指示所述第一缓存空间已满；
    所述存储设备的剩余容量；
    所述处理器，还用于：
    根据所述第一信息包括的至少一项第二信息，确定是否继续向所述存储设备下发位于所述第二地址范围内的所述第二IO命令。
  8. 如权利要求7所述的计算设备，其特征在于，所述第一信息还包括以下至少一项第三信息：
    所述第一逻辑分区对应的第一缓存空间已缓存的、且未写入所述第一逻辑分区的数据量；
    所述第一逻辑分区对应的第一缓存空间的剩余容量；
    所述存储设备的剩余容量；
    所述第一逻辑分区的剩余容量；
    所述处理器，还用于：
    若确定继续向所述存储设备下发位于所述第二地址范围内的所述第二IO命令时，根据所述第一信息包括的至少一项第二信息，确定向所述存储设备下发的位于所述第二地址范围内的第二IO命令的数量。
  9. 如权利要求8所述的计算设备，其特征在于，所述第一信息还包括所述第一逻辑分区对应的所述第一缓存空间中超时的IO命令，所述处理器还用于：
    向所述存储设备重发所述超时的IO命令。
  10. 如权利要求7-9任一项所述的计算设备，其特征在于，
    所述第一信息还包括未成功缓存在所述第一缓存空间的、且待重发的IO命令对应的延时时长，所述处理器具体用于：
    在等待时长达到所述延时时长后，向所述存储设备重发所述待重发的IO命令。
  11. 如权利要求1-3任一项所述的计算设备，其特征在于，所述第一信息包括向所述第一地址写入第一数据失败的结果和所述第二地址，所述第二地址与所述第一地址相同，所述处理器，还用于：
    根据所述向所述第一地址写入第一数据失败的结果和所述第一地址，向所述存储设备发送所述第一地址对应的第一IO命令。
  12. 一种存储控制器，其特征在于，包括处理器和通信接口，所述处理器通过所述通信接口耦合至计算设备；
    所述处理器，用于：
    接收所述计算设备发送的至少一个第一输入输出IO命令，其中每个所述第一IO命令对应的访问地址位于第一地址范围内，所述第一地址范围为所述第一逻辑分区中根据所述第一地址和预设的第一长度确定的逻辑地址范围；第一逻辑分区为存储设备包括的多个逻辑分区中的任一个；
    将所述至少一个第一IO命令存储于所述第一缓存空间中；
    确定所述第一逻辑分区当前的起始写入地址为第一地址，并根据所述第一地址从所述至少一个第一IO命令中选择并执行对应的命令；
    向所述计算设备发送第一信息，所述第一信息用于所述计算设备下发第二地址对应的IO命令。
  13. 如权利要求12所述的存储控制器，其特征在于，所述第一长度根据第一缓存空间的大小确定，所述第一缓存空间为所述存储设备中的缓存中用于缓存访问所述第一逻辑分区的IO命令的缓存空间。
  14. 如权利要求13所述的存储控制器，其特征在于，所述第一逻辑分区对应的第一缓存空间的大小为所述计算设备配置。
  15. 如权利要求12-14任一项所述的存储控制器，其特征在于，所述处理器，具体用于：
    若从第一缓存空间中查找到所述第一地址对应的第一IO命令，所述第一地址对应的 第一IO命令包括第一数据，则向所述第一地址写入所述第一数据，并向所述计算设备发送包括成功向所述第一地址写入第一数据的结果和第二地址的第一信息，且所述第二地址与所述第一地址不同，所述第一信息用于所述计算设备下发所述第二地址对应的IO命令。
  16. 如权利要求12-15任一项所述的存储控制器，其特征在于，所述处理器，还用于：
    为所述至少一个第一IO命令中每个第一IO命令设置第一时长，在任一所述第一IO命令在第一缓存空间中的存储时长超出所述第一时长后，从所述第一缓存空间中删除超时的第一IO命令。
  17. 如权利要求12-16任一项所述的存储控制器，其特征在于，所述处理器，还用于：
    接收所述计算设备发送的至少一个第二IO命令，所述至少一个第二IO命令包括所述第二地址对应的第二IO命令，每个所述第二IO命令对应的访问地址位于第二地址范围内；
    若所述第一逻辑分区当前的起始写入地址为所述第二地址，所述第二地址范围为所述第一逻辑分区中根据所述第二地址和所述第一长度确定的逻辑地址范围；或者，若所述第一逻辑分区当前的起始写入地址为第三地址，所述第二地址范围为所述第一逻辑分区中根据所述第三地址和所述第一长度确定的逻辑地址范围。
  18. 如权利要求17所述的存储控制器，其特征在于，所述第一信息还包括以下至少一项第二信息：
    所述第一逻辑分区对应的所述第一缓存空间的状态码，所述状态码指示所述第一缓存空间已满；
    所述存储设备的剩余容量；
    所述第一信息包括的至少一项第二信息，用于计算设备确定是否继续向所述存储设备下发位于所述第二地址范围内的所述第二IO命令。
  19. 如权利要求18所述的存储控制器，其特征在于，所述第一信息还包括以下至少一项第三信息：
    所述第一逻辑分区对应的第一缓存空间已缓存的、且未写入所述第一逻辑分区的数据量；
    所述第一逻辑分区对应的第一缓存空间的剩余空间的容量；
    所述存储设备的剩余容量；
    所述第一逻辑分区的剩余容量；
    所述第一信息包括的至少一项第二信息，用于所述计算设备确定向所述存储设备下发的位于所述第二地址范围内的第二IO命令的数量。
  20. 如权利要求19所述的存储控制器，其特征在于，所述第一信息还包括所述第一逻辑分区对应的所述第一缓存空间中超时的IO命令；所述第一逻辑分区对应的所述第一缓存空间中超时的IO命令，用于向所述存储设备重发所述超时的IO命令。
  21. 如权利要求19所述的存储控制器，其特征在于，所述第一信息还包括未成功缓存在所述第一缓存空间的、且待重发的IO命令对应的延时时长，所述延时时长用于所述计算设备在等待时长达到所述延时时长后，向所述存储设备重发所述待重发的IO命令。
  22. 如权利要求12-14任一项所述的存储控制器，其特征在于，所述处理器，具体用于：
    若从所述第一缓存空间中未查找到所述第一地址对应的第一IO命令，则暂停向所述第一逻辑分区写数据，并向所述计算设备发送包括向所述第一地址写数据失败的结果和所述第二地址的第一信息，且所述第二地址与所述第一地址相同，所述第一信息用于所述计 算设备下发所述第一地址对应的第一IO命令。
  23. 一种存储设备，其特征在于，包括存储介质、缓存以及如上述权利要求12-22中任一项所述的存储控制器，所述存储介质包括多个逻辑分区，所述多个逻辑分区包括第一逻辑分区，所述缓存包括多个缓存空间，所述多个缓存空间包括第一缓存空间，所述第一缓存空间为所述存储设备中的缓存中用于缓存访问所述第一逻辑分区的IO命令的缓存空间；
    所述存储控制器用于从所述第一缓存空间中查找所述第一逻辑分区当前的起始写入地址对应的IO命令，并将查找到的所述起始写入地址对应的IO命令携带的数据写入所述第一逻辑分区。
  24. 如权利要求23所述的存储设备，其特征在于，所述第一逻辑分区中的数据为通过顺序写入方式写入。
  25. 如权利要求23或24所述的存储设备，其特征在于，所述存储设备为分区命名空间固态硬盘ZNS SSD。
  26. 一种数据处理方法，其特征在于，所述方法包括：
    获取存储设备中的第一逻辑分区的第一地址，所述第一地址为所述第一逻辑分区当前的起始写入地址；所述第一逻辑分区为所述存储设备包括的多个逻辑分区中的任一个；
    向所述存储设备发送至少一个第一输入输出IO命令，其中每个所述第一IO命令对应的访问地址位于第一地址范围内，所述第一地址范围为所述第一逻辑分区中根据所述第一地址和预设的第一长度确定的逻辑地址范围；
    接收所述存储设备响应于所述至少一个第一IO命令而发送的第一信息，所述第一信息用于所述计算设备下发第二地址对应的IO命令。
  27. 一种数据处理方法，其特征在于，所述方法包括：
    接收计算设备发送的至少一个第一输入输出IO命令，其中每个所述第一IO命令对应的访问地址位于第一地址范围内，所述第一地址范围为所述第一逻辑分区中根据所述第一地址和预设的第一长度确定的逻辑地址范围；
    将所述至少一个第一IO命令存储于所述第一缓存空间中；
    确定所述第一逻辑分区中当前的起始写入地址为第一地址，并根据所述第一地址从所述至少一个第一IO命令中选择并执行对应的命令；
    向所述计算设备发送第一信息，所述第一信息用于所述计算设备下发第二地址对应的IO命令。
  28. 一种数据处理系统，其特征在于，包括如权利要求1-11任一项所述的计算设备以及如权利要求23-25任一项所述的存储设备。
  29. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有计算机程序，当所述计算机程序在计算机上运行时，使得计算机执行权利要求26所述的方法，或者，执行权利要求27所述的方法。
  30. 一种计算机程序产品，其特征在于，当所述计算机程序产品在计算机上运行时，使得计算机执行权利要求26所述的方法，或者，执行权利要求27所述的方法。
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