WO2022251716A1 - Matrice et bande d'imagerie et système de suppression de bruit de pixel combinés - Google Patents

Matrice et bande d'imagerie et système de suppression de bruit de pixel combinés Download PDF

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Publication number
WO2022251716A1
WO2022251716A1 PCT/US2022/031465 US2022031465W WO2022251716A1 WO 2022251716 A1 WO2022251716 A1 WO 2022251716A1 US 2022031465 W US2022031465 W US 2022031465W WO 2022251716 A1 WO2022251716 A1 WO 2022251716A1
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WIPO (PCT)
Prior art keywords
value
pixel
imaging
data
readout circuit
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PCT/US2022/031465
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English (en)
Inventor
Paul Pryor
Pieter G. ROOS
Richard Weisfield
Ivan P. Mollov
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Varex Imaging Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority claimed from US17/334,681 external-priority patent/US11812187B2/en
Priority claimed from US17/334,353 external-priority patent/US11750944B2/en
Application filed by Varex Imaging Corporation filed Critical Varex Imaging Corporation
Priority to CN202280007277.XA priority Critical patent/CN116491126A/zh
Priority to EP22812317.0A priority patent/EP4349004A1/fr
Priority to JP2023526897A priority patent/JP2024521603A/ja
Publication of WO2022251716A1 publication Critical patent/WO2022251716A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/30—Transforming light or analogous information into electric information
    • H04N5/32—Transforming X-rays

Definitions

  • FIG.1 is a block diagram of an imaging system including an imaging array and an imaging strip according to some embodiments.
  • FIG. 2 is a flowchart of an operation of an imaging system according to some embodiments.
  • FIG.3 is a block diagram of an imaging system including a substrate according to some embodiments.
  • FIG.4 is a block diagram of an imaging system with separate row drivers according to some embodiments.
  • FIG.5 is a block diagram of an imaging system where an imaging strip is a subset of an imaging array according to some embodiments.
  • FIG. 6 is a block diagram of an imaging system with split data lines according to some embodiments.
  • FIGS.7A-7B are block diagrams of imaging systems with selectively couplable split data lines according to some embodiments. [0010] FIGS.
  • FIG. 8A-8B are block diagrams of imaging systems with multiple data lines according to some embodiments.
  • FIG.9A is a block diagram of a pixel and associated electronics in an imaging system according to some embodiments.
  • FIG. 9B is a block diagram of an imaging array and associated electronics in the imaging system according to some embodiments.
  • FIG.10 is a timing diagram of a double sampling operation.
  • FIG.11A is a timing diagram according to some embodiments.
  • FIG. 11B is a flowchart of an operation of an imaging system according to some embodiments.
  • FIG.12A is a timing diagram according to some embodiments. [0017] FIG.
  • FIG. 12B is a flowchart of an operation of an imaging system according to some embodiments.
  • FIG.13A is a timing diagram according to some embodiments.
  • FIG. 13B is a flowchart of an operation of an imaging system according to some embodiments.
  • FIG.13C is a timing diagram according to some other embodiments.
  • FIG.13D is a timing diagram according to some other embodiments.
  • FIG.14 is a flowchart of a technique of operating an imaging system according to some embodiments.
  • FIG. 15 is a block diagram of a 2D x-ray imaging system according to some embodiments. DETAILED DESCRIPTION [0024] Some embodiments relate to imaging systems including an imaging array and an imaging strip.
  • Imaging systems used in dental panels may perform a panoramic imaging operation where an imaging strip is irradiated as the detector rotates around the patient’s head.
  • This imaging strip can be integrated as part of a large-format flat panel detector.
  • the image is generated by rapidly scanning the unused rows of the detector, an operation referred to as “scrubbing,” and only turning on particular rows of the panel for image readout.
  • This approach suffers from two problems. First, the frame rate is limited by the time it takes to scrub the unused pixels. Second, the imaging may be dose rate limited in particular applications such as medical imaging and thus, background electronic noise has a greater impact on image quality due to the lower available signal.
  • an array can be about 16 x 16 centimeters (cm) in size with pixel sizes of approximately 100 micrometers ( ⁇ m).
  • the matrix of pixels is addressed by a set of gate drivers and read out by an orthogonal set of readout charge amplifiers. Full size images may be acquired by sequentially turning on each row of TFTs and simultaneously reading out the pixel charges on each of the array’s data lines.
  • the row drivers are controlled to rapidly scan through a first portion of the matrix until the first row of the imaging strip.
  • the row drivers are controlled to slow down to normal readout rate for the duration of the rows of the imaging strip, which may be about 60-100 rows, and then rapidly scan through the remainder of the gate lines to scrub the rest of the imager.
  • embodiments include different configurations of imaging arrays and imaging strips.
  • a separate imaging array and a separate imaging strip may be disposed in the same housing and share common electronics.
  • the imaging array and the imaging strip may be disposed on the same substrate.
  • FIG.1 is a block diagram of an imaging system including an imaging array and an imaging strip according to some embodiments.
  • the imaging system 100 includes an imaging array 102 and an imaging strip 104.
  • the imaging array 102 and imaging strip 104 are disposed in the same housing 110.
  • the imaging array 102 may be a two-dimensional (2D) array of pixels.
  • the imaging array 102 may include a 1600 x 1600 array of pixels. While an imaging array 102 with equal numbers of pixels in rows and columns has been used as an example, in other embodiments, the number of rows and columns may be different.
  • the imaging strip (or linear imaging array or linear array) 104 is an array of pixels with a relatively low aspect ratio, which may or may not be a 2D array.
  • the imaging strip 104 may include an array of 1 pixel x 1600 pixels.
  • the imaging strip 104 may include an array of about 80 pixels x 1600 pixels.
  • the aspect ratio of the shorter dimension to the longer dimension is less than about 0.05, 0.1, or 0.3.
  • the imaging array 102 and the imaging strip 104 may be based on the same, similar, or different technology.
  • the imaging array 102 may include an amorphous silicon (a-Si) based array while the imaging strip may be based on higher cost and/or higher resolution complementary metal oxide semiconductors (CMOS), indium gallium zinc oxide (IGZO), or a photon counting technology, such as cadmium telluride (CdTe), cadmium zinc telluride (CdZnTe or CZT), selenium photodetectors, or the like.
  • CMOS complementary metal oxide semiconductors
  • IGZO indium gallium zinc oxide
  • a photon counting technology such as cadmium telluride (CdTe), cadmium zinc telluride (CdZnTe or CZT), selenium photodetectors, or the like.
  • one or both of the imaging array 102 and the imaging strip 104 may be based on IGZO.
  • one or both of the imaging array 102 and the imaging strip 104 may be associated with one or more scintillators.
  • the scintillator(s) may include a variety of materials configured to convert x-ray photons into photons detectable by the corresponding imaging array 102 or imaging strip 104.
  • a scintillator may include cesium iodide (CsI), cadmium tungstate (CdWO4), polyvinyl toluene (PVT), or the like.
  • a scintillator examples include gadolinium oxysulfide (Gd2O2S; GOS; Gadox), gadolinium oxysulfide doped with terbium (Gd2O2S:Tb), or the like
  • the one or both of the imaging array 102 and the imaging strip may not include a scintillator but may include direct conversion materials including CdTe, CdZnTe or CZT, selenium, or the like.
  • Pixels of the imaging array 102 and the imaging strip 104 may be the same, similar, or different.
  • One or more of the size, layout, spacing, internal components, internal electrical connections, or the like of the pixels may be the same or different.
  • the imaging array 102 may include 50 micrometer ( ⁇ m) pixels for better single shot accuracy while the imaging strip 104 may have 100 ⁇ m pixels for better signal-to-noise ratio and/or faster speed.
  • one of the imaging array 102 and the imaging strip 104 may have 1T pixels while the other has 4T pixels. While particular examples of differences between the pixels have been used as examples, in other embodiments, the pixels may have other differences.
  • the imaging system 100 includes a readout circuit 106-1 coupled to the imaging array 102.
  • the readout circuit 106-1 may include one or more amplifiers (e.g., charge amplifiers) for columns of the imaging array 102.
  • the readout circuit 106-1 may include a charge amplifier for each of the columns of the imaging array 102. As will be described in further detail below, each pixel of a column may be coupled to a data line that is coupled to an input of one of the charge amplifiers of the readout circuit 106-1.
  • the imaging system 100 includes a readout circuit 106-2 coupled to the imaging strip 104.
  • the readout circuit 106-2 may include one or more charge amplifiers for columns of the imaging strip 104.
  • the readout circuit 106-2 may include a charge amplifier for each of the columns of the imaging array 102.
  • each pixel of a column may be coupled to a data line that is coupled to an input of one of the charge amplifiers of the readout circuit 106-2.
  • the readout circuit 106-1 may be different from the readout circuit 106-2.
  • data lines coupling the pixels of the imaging array 102 to the readout circuit 106-1 may be longer than data lines coupling the pixels of the imaging strip 104 to the readout circuit 106-2 (e.g., due to the larger number of pixel rows).
  • the readout circuit 106-2 may have a different configuration, may be operated differently, or the like due to the lower capacitance of the associated data lines.
  • the imaging system 100 includes common electronics 108 coupled to the first readout circuit 106-1 and the second readout circuit 106-2.
  • the common electronics 108 are configured to generate image data in response to at least one of the first readout circuit 106-1 and the second readout circuit 106-2. In some operations, the common electronics 108 generates the image data based on the data from the readout circuit 106-1. In other operations, the common electronics 108 are configured to generate the image data based on the data from the readout circuit 106-2.
  • the common electronics 108 is configured to generate the image data based on both the data from the readout circuit 106-1 and the data from the readout circuit 106-2.
  • the common electronics 108 may include a variety of different circuits shared between the imaging array 102 and the imaging strip 104, and the readout circuits 106-1 and 106-2.
  • the common electronics 108 may include a power supply configured to generate power for the imaging array 102 and the imaging strip 104, and the readout circuits 106-1 and 106-2.
  • the common electronics 108 may include a processor 109, configured to control various operations described herein.
  • Such a processor 109 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit, a microcontroller, a programmable logic device, discrete circuits, a combination of such devices, or the like.
  • the processor 109 may include internal portions, such as registers, cache memory, processing cores, or the like, and may also include external interfaces, such as address and data bus interfaces, interrupt interfaces, or the like. Although only one processor 109 is illustrated in the common electronics 108, multiple processors 109 may be present.
  • the system common electronics 108 may connect the processor 109 to internal and external components such as the imaging array 102 and the imaging strip 104, the readout circuits 106-1 and 106-2, and an external computer 115.
  • the external computer 115 is an example of a device that may be coupled (e.g., via wired, optical, or wireless connection) to the imaging system 100 to receive image data from the common electronics 108.
  • the common electronics 108 may be configured to receive and respond to commands from the external computer 115, exchange data with the external computer 115, or the like.
  • the external computer 115 may take a variety of forms such as a desktop computer, server, workstation, tablet computer, mobile device, user interface terminal, or the like.
  • the imaging array 102 and the imaging strip 104 are separate.
  • the imaging array 102 and the imaging strip 104 may be disposed on separate substrates that are each attached to the housing 110.
  • the imaging array 102 and the imaging strip 104 may be disposed such that incident radiation may enter a common window or opening 112 and be detected by either the imaging array 102 or the imaging strip 104.
  • the imaging strip 104 may have a configuration that results in lower noise, a higher framerate, higher resolution, or the like than the imaging array 102.
  • the imaging array 102 and imaging strip 104 may be used for different applications.
  • a user may use a single imaging system 100 for the different applications or a user may use a detector in a single housing 110 in various imaging systems.
  • the imaging array 102 and the imaging strip 104 may not be in operation at the same time.
  • the common electronics 108 may be used exclusively for the operation of one of the imaging array 102 and the imaging strip 104 at a time. The operation of the common electronics 108 may be different for each of the imaging array 102 and the imaging strip 104.
  • FIG. 2 is a flowchart of an operation of an imaging system according to some embodiments.
  • first data is read from the imaging array 102 using the readout circuit 106- 1 in 200.
  • row drivers associated with the imaging array 102 may be sequentially activated to read out data from the imaging array 102 row by row using the readout circuit 106-1.
  • the common electronics 108 may be configured to control of the row drivers and the readout circuit 106-1 to read out the desired data.
  • second data is read from the imaging strip 104 using the readout circuit 106- 2.
  • row drivers associated with the imaging strip 104 may be sequentially activated to read out data from the imaging strip 104 row by row using the readout circuit 106- 2.
  • the common electronics 108 may also be configured to control the row drivers and the readout circuit 106-2 to read out the desired data.
  • data from the imaging array 102 and the imaging strip 104 are respectively processed in the common electronics 108 to generate different sets of image data. The processing in the common electronics 108 in 204 and 206 may be the same, similar, or different.
  • the data from the imaging strip 104 may be processed in a manner to generate image data that results in reduced noise as compared with the processing of the data from the imaging array 102.
  • data from the imaging array 102 may be used to generate a video stream while data from the imaging strip 104 may be used to generate a panoramic image.
  • the processing in 204 and 206 may be performed at the same time, in parallel, sequentially, or the like.
  • 204 may be performed before 202.
  • 200 and 204 may be performed after 206.
  • FIG. 3 is a block diagram of an imaging system including a substrate according to some embodiments.
  • the imaging system 300 may be similar to the imaging system 100 of FIG. 1 and include the same or similar components. For clarity, some components are omitted, but may be present. As described above, in some embodiments, the imaging array 102 and the imaging strip 104 may be separate and formed on different substrates. In some embodiments, the imaging system 300 includes a substrate 114.
  • the substrate 114 may be a single substrate formed of such as glass, plastic or polymer, ceramic, an organic or inorganic semiconductor, or the like.
  • the imaging array 102 and the imaging strip 104 may be formed in or on the substrate 114. For example, the imaging array 102 and the imaging strip 104 may be separate integrated circuit dies that are attached to the substrate 114.
  • the imaging array 102 and the imaging strip 104 may be formed in different portions of the same integrated circuit die, such as in different portions of a semiconductor substrate. [0048] In some embodiments, the imaging array 102 and the imaging strip 104 may still be separate electronic devices, even if the imaging array 102 and the imaging strip 104 are immediately adjacent to one another on the same semiconductor substrate. That is. the imaging array 102 and the imaging strip 104 may have no electrical connections to each other except for parasitic connections through the substrate and/or connections through the readout circuits 106-1 and 106-2 and the common electronics 108. [0049] In some embodiments, the readout circuits 106-1 and 106-2 may be formed on substrates different from the substrate 114.
  • FIG.4 is a block diagram of an imaging system with separate row drivers according to some embodiments.
  • the imaging system 400 may be similar to the imaging system 100 and 300 described above. However, the imaging array 102 is coupled to row driver 416b while the imaging strip 104 is coupled to the row driver 416a.
  • the row drivers 416a and 416b are separate circuits while in others, the row drivers 416a and 416b are part of the same integrated circuit as the corresponding imaging strip 104 or imaging array 102 or both.
  • the row drivers 416a and 416b may be coupled to and controlled by the common electronics 108.
  • the row driver 416a is configured to be sequentially activated to read out the imaging strip 104 row by row.
  • the row driver 416b is configured to be sequentially activated to read out the imaging array 102 row by row.
  • the common electronics 108 may be configured to change the signals, timing, or the like when controlling the row driver 416a as compared to when controlling the row driver 416b.
  • FIG.5 is a block diagram of an imaging system where an imaging strip is a subset of an imaging array according to some embodiments.
  • the imaging system 500 may be similar to the imaging systems 100, 300, and 400 described above. However, the imaging strip 104 is a subset of the imaging array 102.
  • the imaging strip 104 may be disposed on an edge of the imaging array 102.
  • the imaging array 102 may have a size of 1600 pixels x 1600 pixels.
  • the imaging strip may include the top 80 rows of pixels of the array for a size of 1600 pixels x 80 pixels. While a particular size of the imaging strip 104 has been used as an example, the size may be different while maintaining the aspect ratio described above.
  • the imaging array 102 may be coupled to row drivers 516.
  • the row drivers 516 coupled to the imaging strip 104 portion of the imaging array 102 may be shared. When the imaging strip 104 is used to generate an image, the associated row select lines 516a may be used.
  • the pixels of the imaging strip 104 may be identical to and formed the same as the pixels of the remainder of the imaging array 102.
  • the pixels of the imaging strip 104 may have the same size, shape, pitch, or the like.
  • pitch refers to the pixel length or width along with the spacing between pixels.
  • FIG. 6 is a block diagram of an imaging system with split data lines according to some embodiments.
  • the imaging system 600 may be similar to the imaging system 500 as described above, or the like.
  • the imaging system 600 includes split data lines 618.
  • the data lines 618 are split into two groups, data lines 618a and data lines 618b.
  • Data lines 618a are coupled to the imaging strip 104 portion of the imaging array 102 and coupled to readout circuit 106-2.
  • Data lines 618b are coupled to the remainder of the imaging array 102 and coupled to readout circuit 106-1.
  • the location of the split between the data lines 618a and 618b may be in a variety of locations.
  • the split is about 30% of the column length where the date lines 618a are coupled to 30% of pixels in a column while data lines 618b are coupled to 70% of pixels in a column. While 30% is used as an example, in other embodiments, the location may be different, such as a split at 1%, 5%, 10%, 20%, or the like. In other embodiments, split may be at a particular number of pixels from an edge, such as about 80 pixels or less, but still less than 30% of the number of pixels in a column of the imaging array 102.
  • the split may be located such that only pixels of the imaging strip 104 are coupled to the data lines 618a while pixels outside of the imaging strip 104 are coupled to the data lines 618b. In other embodiments, some pixels outside of the imaging strip 104 are coupled to the data lines 618a but the total number of pixels of a column coupled to the data lines 618a may be less than about 30%. [0058] Having the split at less than about 30% provides benefits for the imaging strip 104. In some embodiments, the noise may be less as the data lines 618a are shorter than the data lines 618b.
  • that lower noise may cause artifacts to appear in an image generated using the imaging array 102; however, as will be described in further detail below, additional noise or an equivalent may be added to the data generated by the imaging strip 104 when the entire imaging array 102 is used to generate an image.
  • the downstream processing may be different. For example, a different dark level matching operation may be performed as compared with the remainder of the imaging array 102.
  • an amount of noise reduction and/or increase in signal to noise ratio may be about 10%, 20%, 40%, 50%, or more.
  • the shorter data lines 618a results in a lower data line capacitance and resistance, which may reduce electronic readout noise.
  • charge amplifiers may have a minimum noise of about 200 electrons (e-), that increases linearly with added data line capacitance.
  • the noise slope is controlled by the power applied to the charge amplifiers and the bandwidth setting of associated sample and hold circuits.
  • the resistance of the data lines produces thermal noise, or Johnson noise, that gets multiplied by the data line capacitance. This Johnson noise increases with length but may be negligible for shorter data lines such as data lines 618a coupled to the imaging strip 104. The resulting noise may be close to the minimum noise of the charge amplifier in combination with the kTC noise of the pixel.
  • This noise (estimated to be 400 e-) may be about 40% less than the noise from an array of the same size where the data lines are not split (approximately 700 e-).
  • the term kTC noise refers to noise generated by temperature (T) and capacitance (C) multiplied by the Boltzmann constant (k), such as thermal noise multiplied by the data line capacitance and the Boltzmann constant.
  • the Boltzmann constant (k) is a proportionality factor that relates the average relative kinetic energy of particles with the thermodynamic temperature of the particles.
  • the shorter length may also increase readout speed. For example, fewer rows may be read during a read operation of the pixels of the imaging strip 104.
  • the remainder of the imaging array 102 need not be scrubbed to read the pixels of the imaging strip 104.
  • the control logic 103 may continue passing tokens (i.e., signals that propagate along the row driver 616 to activate the rows) into the row driver 616 every 80 gate clocks to activate the row select signals 616a. These tokens may pass though the remaining row drivers 616 and scrub the rest of the imaging array 102 using row select signals 616b without interfering with the readout of the imaging strip 104. This may increase readout speed of the imaging strip 104.
  • the rate for scrubbing pixels is about 1 microsecond ( ⁇ s) per row
  • the time it takes to scrub a 1600 row imaging array 102 outside of an 80 row imaging strip 104 is about 1.52 milliseconds (ms).
  • ms milliseconds
  • an 80 row imaging strip 104 takes 1.28 ms to readout.
  • the total time is about 2.8 ms resulting in a maximum frame rate of 357 fps.
  • the readout time is just the 1.28 ms resulting in a frame rate of about 780 fps.
  • the readout circuits 106-1 and 106-2 may be the same and/or operated the same way while in other embodiments, the readout circuits 106-1 and 106-2 may be different and/or operated differently.
  • the readout circuits 106-1 and 106-2 may be identical.
  • the readout circuits 106-1 and 106-2 are identical but operated differently, such as having different gain, current, capacitance, or the like.
  • the readout circuits 106-1 and 106-2 may be different where the readout circuits 106-2 are optimized for the shorter data lines 618a.
  • the reading of the first data from the imaging array 102 includes reading the first data from the imaging array 102 through data lines 618b.
  • reading the second data from the imaging strip 104 includes reading the second data from the imaging strip 104 using data lines 618a that are different from the data lines 618b.
  • FIGS.7A-7B are block diagrams of imaging systems with selectively couplable split data lines according to some embodiments. Referring to FIG. 7A, the imaging system 700a may be similar to the imaging system 600 described above. However, the system 700a incudes data lines 718a coupled to the imaging strip 104, data lines 718b coupled to a remainder of the imaging array 102.
  • the data lines 718a and 718b are separate but selectively couplable by switches 722. Each of the switches 722 may selectively couple one of the data lines 718a to the corresponding data line 718b.
  • the switches 722 may include one or more transistors coupling the data lines 718a and 718b.
  • the switches 722 may be controlled by the control logic 103 such that when the imaging strip 104 is read, the switches 722 are open. As a result, lower capacitances from the data lines 718a alone are presented to the readout circuit 106-2. However, when the imaging array 102 is read, the data lines 718a and 718b may be coupled together to function as single data lines.
  • the data from the imaging array 102 may be read through the coupled data lines 718a and 718b through the readout circuit 106-1.
  • the imaging system 700b may be similar to the imaging system 700a.
  • the data lines associated with the imaging array 102 may include the data lines 718a, 718c, and 718d.
  • a split between the data lines 718c and 718d may be at 50% of the distance along the imaging array 102. For example, 50% of the pixel rows may be on one side of the split between the data lines 718c and 718d and 50% of the pixel rows may be on the other side of the split.
  • the data lines 718a and 718c may be selectively couplable by the switches 722 in response to the control logic 103.
  • the imaging strip 104 may be read by using the switches 722 to decouple the data lines 718a and the 718c and reading using the readout circuit 106-2 through the data lines 718a.
  • the data lines 718a and 718c may be coupled by the switches 722 and read using the readout circuit 106-2 through the combination of the data lines 718a and 718c.
  • the remainder of the imaging array 102 may be read through the data lines 718d using the readout circuit 106-1.
  • the coupling of the data lines 718a and 718c may occur at less than 50% of the of the pixel rows or data lines 718a may cover less than 30% of the entire imaging array 102.
  • a portion of the data lines of the entire imaging array 102 may be decoupled from the data lines 718a associated with the imaging strip 104. That portion may be a subset of the remainder outside of the imaging strip 104 or the entire remainder as in the imaging systems 700a and 700b.
  • reading the first data from the imaging array 102 includes electrically coupling the first data lines 718a or 718c to the second data lines 718b when reading the first data from the imaging array 102.
  • reading the second data from the imaging strip 104 includes electrically decoupling the first data lines 718a or 718c from the second data lines 718b when reading the second data from the imaging strip 104.
  • FIGS. 8A-8B are block diagrams of imaging systems with multiple data lines according to some embodiments.
  • the imaging system 800a may be similar to the imaging systems 500 and 600 described above. However, the imaging system 800a includes data lines 818a and 818e.
  • the data lines 818a are coupled to pixels of the imaging strip 104.
  • the data lines 818e are coupled to pixels of the entire imaging array 102 including the pixels of the imaging strip 104.
  • at least two data lines 818a and 818e are coupled to each pixel of the imaging strip 104.
  • the imaging system 800b may be similar to the imaging system 800a.
  • the data lines for the imaging array 102 may include split data lines 818d and 818f, which are split halfway along the imaging array 102.
  • the readout circuit 106-2 may include separate inputs for the data lines 818a and 818f.
  • the readout circuit 106-1 may be coupled to the data lines 818d. Accordingly, when the imaging strip 104 is read, data lines 818a are used while when the imaging array 102 is read, data lines 818d and 818f are used.
  • an amount of noise present in data read from the imaging strip 104 may be less than an amount of noise present in data read from the remainder of the imaging array 102.
  • the data lines used to read data from the imaging strip 104 may be shorter than data lines used to read data from the imaging array 102. Those data lines may have less capacitance and contribute less noise. In some applications, the reduced noise may be desirable.
  • the reduced noise present when reading the imaging strip 104 may allow a lower dose to be used for the same signal to noise ratio in the resulting image, a higher signal for the same dose, a different tradeoff among the various factors the two, or the like.
  • the readout circuit 106-2 may be operated in a manner that increases an amount of noise read from the imaging strip 104.
  • built- in test capacitors, external capacitors, or other capacitors may be selectively coupled to the inputs of the readout circuit 106-2, a power of one or more amplifiers may be reduced, and/or the bandwidth of components of the readout circuit 106-2, such as the amplifiers and/or sample and hold circuits may be increased.
  • These operations may add electronic noise and can be adjusted to match the overall noise between the imaging strip 104 and the rest of the imaging array 102.
  • a typical 20 ⁇ s line time may use 40 kilohertz (kHz) low pass filters for noise reduction.
  • the electronic noise is about 600-800 e-.
  • a low power normal noise mode of operation may be used, test capacitors having capacitances similar to that of the data lines that are built into the readout circuit 106- 2 are coupled to the data lines, and/or the bandwidth is increased to 105 kHz. This operation gives a similar overall noise in the imaging strip 104 strip of about 600-800 e-.
  • the imaging systems described above, 400, 600, 700a, 700b, 800a, 800b, or the like may be operated in a mode where power may be managed dynamically.
  • the control logic 103 may be configured to control amplifiers of a readout circuit 106-1 or 106-2 to operate in a higher power mode to reduce noise when reading the entire imaging array 102.
  • the amplifiers of the readout circuit 106-2 may be operated in a lower power mode.
  • While the lower power mode of operation may increase the relative amount of noise and/or decrease signal-to-noise ratio (SNR), the power consumption is lower.
  • the amplifiers of the readout circuit 106-1 may be turned off, put in a sleep mode with significantly lower power consumption, or the like.
  • the readout circuits 106-1 and 106- 2 may be placed in the higher power mode to reduce the impact of noise. Dynamically switching between these modes of operation may reduce the power consumption of the imaging system 500, 600, 700a, 700b, 800a, 800b, or the like, reduce the temperature, and/or improve the reliability.
  • an impact of pixel kTC noise in an image may be reduced.
  • FIG.9A is a block diagram of a pixel and associated electronics in an imaging system according to some embodiments.
  • FIG.9B is a block diagram of an imaging array and associated electronics in the imaging system according to some embodiments.
  • the imaging system 900 includes pixels 902 disposed in rows and columns.
  • a pixel 902 includes a photodetector 904 (e.g., photodiode) and a transistor 906 (i.e., switch).
  • the transistor 906 is configured to selectively couple the photodetector 904 to a data line 908 in response to a row select signal (RSS). Multiple pixels 902 may be coupled to a single data line 908 in a column.
  • the data line 908 is coupled to an amplifier 910.
  • the amplifier 910 is an integrating amplifier including a reset transistor (or reset switch) 910a and a charge storage device 910b, such as a capacitor.
  • the reset transistor 910a is configured to reset the amplifier 910 in response to a reset signal Reset.
  • the output of the amplifier 910 may be selectively coupled to an analog to digital converter (ADC) 912 through a select transistor 911 in response to a sample signal Sample.
  • ADC analog to digital converter
  • Control logic 903 may be coupled to the various components described above.
  • the control logic 903 may be coupled to row drivers 901.
  • the control logic may be configured to control the row drivers 901 to generate the row select signals RSS for the rows of the pixels 902.
  • the control logic 903 may be configured to configured and control the operations of the ADC 912, FPGA, 914, processor 918, or the like.
  • the control logic 903 may include a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit, a microcontroller, a programmable logic device, discrete circuits, a combination of such devices, or the like.
  • the control logic 903 may include internal portions, such as registers, cache memory, processing cores, or the like, and may also include external interfaces, such as address and data bus interfaces, interrupt interfaces, or the like.
  • other interface devices such as logic chipsets, hubs, memory controllers, communication interfaces, or the like may be part of the imaging system 900 to connect control logic 903 to internal and external components.
  • FIG.10 is a timing diagram of a double sampling operation.
  • the system 900 may be operated according to the timing diagram of FIG.10.
  • the transistor 910a may be enabled to reset the amplifier 910 in response to the pulse on the reset signal Reset.
  • the transistor (or switch) 906 is disabled as the row select signal RSS is disabled.
  • the sample signal Sample is activated while the row select signal RSS is disabled to sample the reset value at the output of the amplifier 910 as Ri. After acquiring the value Ri, the sample signal Sample is deactivated. After deactivating the sample signal Sample, the row select signal RSS is enabled, enabling the transistor 906. As a result, charge from the photodetector 904 accumulates in the amplifier 910. The sample signal Sample is enabled to sample the value Si at the output of the amplifier 910.
  • Equations 1 and 2 show the components of the sampled values Ri and Si. is the sampled reset voltage including noise contributed by the amplifier 910. is the desired signal from the pixel 902. V is the pixel kTC noise left over from the previous reading of the pixel 902. noise is the noise due to the data line 908.
  • Equation 3 is the difference between Ri and The result includes the desired signal, along with the pixel kTC noise, and the data line noise
  • equation 3 may be performed in a variety of ways, such as by analog correlated double sampling (ACDS), digital correlated double sampling (DCDS), or other processes that would subtract the signals Ri and Si.
  • ACDS analog correlated double sampling
  • DCDS digital correlated double sampling
  • Fixed pattern noise sources may be caused by pixel-to-pixel or amplifier-to- amplifier variation. Fixed pattern noise may not change from frame to frame. However, pixel kTC noise is generated by resistance in the pixel semiconductor switch and stored on the capacitance of the photodetector 904. The pixel kTC noise may vary from frame to frame. Fixed pattern noise can be reduced through manufacturing control. The reduction of pixel kTC noise can be made by reducing the capacitance of the photodetector 904 by reducing the size of the photodetector 904; however, reducing the size of the photodetector 904 may reduce other factors, such as sensitivity, efficiency, or the like. [0088] The result in equation 3 still has the pixel kTC noise.
  • the pixel kTC noise may be reduced by changes to the pixel design such as adding additional transistors.
  • pixels formed using some semiconductor technologies, such as in amorphous silicon (a-Si) the size of the transistors may be prohibitive.
  • a single transistor may take up a significant percentage of a pixel for a given pixel size. Adding more transistors would significantly reduce the pixel area available for the photodetector 904, reducing the efficiency of the system 900.
  • the system 900 may be operated differently, reducing the pixel kTC noise.
  • a measurement may be performed where the pixel kTC noise may be acquired and used to reduce or eliminate the pixel kTC noise from a signal measurement.
  • the pixel noise kTC noise is presented to the input of the amplifier 910 (and subsequently output) from the amplifier 910 after the signal sample is taken and the transistor 906 is disabled by disabling the row select signal RSS.
  • a sample may be acquired to capture the kTC noise. This sample may be stored and then used to reduce or eliminate the pixel kTC noise from the signal from the pixel 902 in the next frame. [0090] That measurement may then be used to remove or reduce the pixel kTC noise in the final value. Thus, a measurement from a previous frame is used to reduce or cancel pixel kTC noise in a current frame.
  • FIG. 11A is a timing diagram according to some embodiments.
  • FIG. 11B is a flowchart of an operation of an imaging system according to some embodiments. Referring to FIGS.9A, 9B, 11A, and 11B, in 1100 a first value for a pixel 902 coupled to a data line 908 is acquired through a switch using a readout circuit while the switch is in an off state.
  • CMOS complementary metal oxide semiconductor
  • the transistor 906 is an example of the switch and the readout circuit includes the amplifier 910 and at least some downstream components.
  • This first value a sample R/S is acquired in an N- 1-th frame, while the transistor 906 is disabled. Subsequent processing may occur before later operations are performed for frame N.
  • the readout circuit is reset. In this example, the amplifier 910 is reset. However, in other embodiments, additional components may be reset. Resetting the amplifier 910 may include discharging the charge storage device 910b by activating the rest signal Reset.
  • a second value for the pixel 902 is acquired after resetting the readout circuit. In this example, the value R1 is acquired after resetting the amplifier 910.
  • the switch is turned on.
  • the row select signal RSS is activated, turning on the transistor 906.
  • charge from the pixel 902 may be transferred to the amplifier 910.
  • a third value for the pixel 902 is acquires after turning on the switch.
  • the value S1 is acquired after turning on the transistor 906.
  • the first value, the second value, and the third value are combined into a combined value for the pixel 902.
  • the three values R1, S1, and R/S are combined into the combined value for the pixel 920.
  • the three values R1, S1, and R/S may be combined in various ways to reduce or eliminate pixel kTC noise.
  • a stored value based on the first value is stored.
  • a value based on the value R/S may be stored in the FPGA 914, the memory 916, the processor, 920, or another downstream system.
  • the stored value is based on the value from the previous frame N-1.
  • the stored value may be combined with the values R1 and S1 from the current frame N. Accordingly, the combination in 1110 may include the combination of the first value by way of the stored value based on the first value.
  • an entire frame’s worth of R/S values or the derived values may be stored for each of the pixels 902.
  • An entire frame’s worth of the values R1 and S1, whether separate or combined, may be combined with the stored R/S values.
  • the operations described herein involve the acquisition of an additional sample during the readout process. As this additional sample takes additional time, the readout time is increased. However, the noise may be reduced, potentially increasing the signal to noise ratio, allowing for a lower dose, or the like. Accordingly, in some embodiments, an increase in readout time may be traded for a decrease in noise, a lower dose, or the like. [0099] In some embodiments, the noise reduction benefit has a greater impact when the data line 908 capacitance is smaller.
  • FIG. 12A is a timing diagram according to some embodiments.
  • FIG. 12A is a timing diagram according to some embodiments.
  • FIG. 12B is a flowchart of an operation of an imaging system according to some embodiments.
  • the operation may be similar to that of FIG.11A and 11B including the operations 1100, 1101 (optionally) 1102, 1104, 1106, and 1108 being similar to those described above with respect to FIG. 11B.
  • the readout circuit is reset.
  • the amplifier 910 may be reset with a pulse on the reset signal Reset. This operation may be the same or a similar operation to the later performed reset in 1102.
  • a fourth value for the pixel 902 is acquired while the switch is in an on state.
  • Equation 7 is the sampled value R2.
  • Equation 8 is the sampled value at R3.
  • the value R3 is sampled after the switch 906 transitions to an off state.
  • Equation 9 is the difference between R2 and R3.
  • Equation 10 is Vpixel(N), the sum of Vp1(N) and Vp2(N-1). While different data line noises Vdataline noise 1 and Vdataline noise 2 were added, the resulting combination is effectively the square root of two times a generic data line noise level. [00107] (7) [00108] (8) [00109] (9) [00110] (10) [00111] The values R2 and R3 that were sampled on the previous frame N-1 have the pixel kTC noise from that previous frame.
  • the amplifier 910 is reset and a sample is made after the reset. This generates value R1.
  • the pixel 902 is turned on by turning on switch 906 and another sample is made for the signal, generating value S1.
  • the two samples R1 and S1 are then subtracted as was done before. [00112] After the sample of the signal to generate value S1 is performed the transistor 906 is not opened, but remains in the on state.
  • the amplifier 910 is reset by a pulse on the reset signal Reset and a sample is acquired, value R2. This sample includes the reset value of the amplifier 910.
  • the pixel kTC noise is transferred and is integrated by the amplifier 910.
  • some charge remains in the pixel 902 and an equal and opposite amount is integrated by the amplifier 910.
  • This integrated amount is the opposite of the pixel kTC noise that will be present the next time the pixel 902 is read.
  • the output of the amplifier 910 is sampled again, acquiring value R3, which includes the reset value, the pixel kTC noise and the data line 908 noise.
  • the pixel kTC noise is the pixel kTC noise that will appear the next time the pixel 902 is read in the next frame.
  • Equation 6 may be performed by using correlated double sampling techniques. For example, whether analog or digital, a correlated double sampling technique may be used to generate the difference between R2 and R3 as shown in Equation 9. Similarly, at a different time, the correlated double sampling technique may be used to generate the difference between R1 and S1 as shown in Equation 6. Thus, the different values may be combined into two different correlated values. Those correlated values may be combined as in Equation 10.
  • existing hardware may be used to generate the values Vp1(N) and Vp2(N-1) by controlling various signals such as the reset signal Reset and row select signal RSS.
  • two correlated double sampling operations may be performed to eventually produce one frame’s worth of image data.
  • 1204 of FIG. 12B may be replaced with 1208 and subsequent processing. After operations 1200 to 1108, in 1208, the first value and the fourth value may be combined into a first correlated value.
  • the values R2 and R3 may be combined through a correlated double sampling technique.
  • the second value and the third value may be combined into a second correlated value.
  • R1 and S1 may be combined through a correlated double sampling technique.
  • the first correlated value and the second correlated value are combined into the combined value for the pixel 902.
  • the combination may be performed by a variety of devices, such as the FPGA 914, the processor 918, the control logic 903, an external computer 913, or the like.
  • FIG. 13A is a timing diagram according to some embodiments.
  • FIG. 13B is a flowchart of an operation of an imaging system according to some embodiments.
  • the signals that generate values R1 and S1 may be similar to those described above. However, a third value S2 based on a previous frame is combined with those values. [00117]
  • the operations are the same or similar as 1102 to 1108 for FIG.11B to generate values R1 and S1. These operations are for a previous frame N-1.
  • the first value for the pixel 902 for use in a subsequent frame is acquired without resetting the corresponding readout circuit. For example, when acquiring the first value, the switch is in an off state. Thus, after 1306, the row select signal RSS is disabled, turning off transistor 906.
  • a value S2 is then acquired as the first value for use in the subsequent frame N.
  • operations 1302 to 1308 are repeated, generating the values R1 and S1 for the frame N.
  • Operation 1310 is performed similar to operation 1110 to combine the first value, the second value, and the third value.
  • Operation 1300 may be performed, generating value S2 for frame N for use in frame N+1.
  • Equations 11 and 12 give the components of R1(N-1) and S1(N-1).
  • (11) [00120] (12) [00121]
  • a value S2 is acquired after the value S1 is acquired for the previous frame N-1.
  • That value S2 is acquired after the transistor 906 is turned off and without resetting the amplifier 910.
  • the resulting value S2 includes both the previously integrated value S1 plus the pixel kTC noise as represented by Equation 13 and simplified in Equation 14. [00122] , (13) [00123] (14) [00124] Subtracting S1 from S2 results in the pixel kTC noise for the previous frame N-1 as shown in Equation 15. [00125] , (15) [00126]
  • the values R1 and S1 are acquired and combined as shown in Equations 16-18.
  • the pixel kTC noise from Equation 15 was previously generated. It may be added to Vp1(N) to remove the pixel kTC noise from the previous frame N-1.
  • FIG.13C is a timing diagram according to some embodiments.
  • a digital correlated double sampling technique may be used.
  • signals to be sampled may be shifted on to sampling capacitors or other sample storage devices.
  • the operation may be similar to that of FIG.13A.
  • the sampling capacitors may be a bank of sampling capacitors where the usage of the capacitors is rotated among the sampling operations. Sample signals Sample may be activated as described above to sample values R1, S1, and S2. However, the bank of sampling capacitors may include an even number of sampling capacitors.
  • a fourth sample signal 1350 or additional sample signals may be activated to ensure that the associated pixel 902 sees the same sampling capacitor. While one sample signal 1350 is used as an example, more may be present as needed. The sampled value may be irrelevant. Accordingly, the ASIN may not be activated. Thus, in some embodiments, the number of times that signals are shifted in to be sampled may be less than the number of times the sample signal Sample is activated.
  • FIG.13D is a timing diagram according to some embodiments. Referring to FIGS. 9A, 9B, 13B, and 13D, in some embodiments, the operations may be performed using analog correlated double sampling. In response to a clamp signal Clamp a reset value R1 may be stored on a sampling capacitor.
  • That sampling capacitor may be coupled to an analog subtraction device, such as a differential amplifier, that performs the analog subtractions associated with the analog correlated double sampling.
  • an analog subtraction device such as a differential amplifier
  • two measurements are digitized as intermediate values.
  • S1 and S2 both include the reset value R1.
  • R1 is subtracted through the analog correlated double sampling operation from both S1 and S2 before the samples are digitized.
  • subsequent operations that may be performed digitally may be represented by equations 20-22 where S’1 is the digitized value after R1 was subtracted from S1 in the differential amplifier and S’2 is similarly the digitized value after R1 was subtracted from S2.
  • FIG.14 is a flowchart of a technique of operating an imaging system according to some embodiments.
  • a mode of operation is selected.
  • operations similar those described in FIGS.11B, 12B, 12C, 13B, or the like as described above may be performed.
  • lower noise data may be acquired.
  • some applications may need a higher framerate.
  • a second mode of operation may be selected where, in 1402, a correlated double sampling operation is performed. In this mode, the acquisition of the first value is not performed. Accordingly, the operation of the system may be switched from a lower noise mode to a higher frame rate mode.
  • the second mode may be selected when the imaging system is used for fluoroscopy or another application where a higher framerate may be desirable.
  • the first mode may be selected to generate an image with a lower noise, a lower dose, or the like.
  • a frame of data may not be available and/or may be discarded.
  • a first frame of data for frame N-1 may be used to generate the first values and other values. That frame of data may not be used to generate an image or a frame of a video signal. Instead, that data may be used to initialize the processing described above so that each subsequent frame may have available the values from the previous frame to perform the lower noise processing described above.
  • the operations described above to reduce or eliminate pixel kTC noise may be applied to the imaging strip 104 described above.
  • the imaging strip 104 may have a relatively shorter data line coupling the imaging strip 104 to the readout circuit 106-2.
  • the common electronics 108 and the readout circuit 106-2 may be configured as described above to reduce kTC noise.
  • the modes of operation described with respect to FIG. 14 may be switched depending on whether the imaging strip 104 is read. For example, if the imaging strip 104 is part of the imaging array 102, and the entire imaging array 102 is being read, the operations described above to reduce pixel kTC noise may not be performed.
  • FIG. 15 is a block diagram of a 2D x-ray imaging system according to some embodiments.
  • the 2D x-ray imaging system 1500 includes an x-ray source 1502 and detector 1510.
  • the detector 1510 may include an imaging system 100, 200, 400, 500, 600, 700a, 700b, 800a, 800b, 900, or the like as described above.
  • the x-ray source 1502 is disposed relative to the detector 1510 such that x-rays 1520 may be generated to pass through a specimen 1522 and detected by the detector 1510.
  • the detector 1510 is part of a medical imaging system.
  • the 2D x-ray imaging system 1500 may include a portable vehicle scanning system as part of a cargo scanning system.
  • Some embodiments include a system, comprising: a housing 110; an imaging array 102 disposed within the housing 110; an imaging strip 104 disposed within the housing 110; a first readout circuit 106-1 coupled to the imaging array 102; a second readout circuit 106-2 coupled to the imaging strip 104; and common electronics 108 coupled to the first readout circuit 106-1 and the second readout circuit 106-2 and configured to generate image data in response to at least one of the first readout circuit 106-1 and the second readout circuit 106-2.
  • the imaging array 102 and the imaging strip 104 are separate. [00147] In some embodiments, the imaging array 102 and the imaging strip 104 are separate and formed on the same substrate 114. [00148] In some embodiments, at least one of a size, layout, resolution, and internal components of pixels of the imaging array 102 is different from a corresponding at least one of a size, layout, resolution, and internal components of pixels of the imaging strip 104. [00149] In some embodiments, the imaging strip 104 is a subset of the imaging array 102. [00150] In some embodiments, the imaging strip 104 is less than 30% of the imaging array 102.
  • the system further comprises data lines 618, 718, 818 coupled to the imaging array 102 and the imaging strip 104.
  • the system further comprises a plurality of switches 722 dividing the data lines 718 into a plurality of first data lines 718b coupled to the imaging strip 104 and a plurality of second data lines 718b coupled to a remainder of the imaging array 102 outside of the imaging strip 104.
  • the system further comprises a plurality of first data lines 618a coupled to the subset of the imaging array 102 including the imaging strip 104; a plurality of second data lines 618b separate from the first data lines 618a and coupled to the imaging array 102 outside of the imaging strip 104.
  • the system further comprises an x-ray source configured to generate an x-ray beam; a detector disposed to receive the x-ray beam and including the housing 110, the imaging array 102, the imaging strip 104, the first readout circuit 106-1, the second readout circuit 106-2, and the common electronics 108.
  • Some embodiments include a method, comprising: reading first data from an imaging array 102 disposed within a housing 110 using at least a first readout circuit 106-1; reading second data from an imaging strip 104 disposed within the housing 110 using at least a second readout circuit 106-2; processing the first data in common electronics 108 to generate first image data; and processing the second data in the common electronics 108 to generate second image data.
  • the imaging array 102 and the imaging strip 104 are separate.
  • the imaging array 102 and the imaging strip 104 are formed on the same substrate 114.
  • a pixel size of pixels of the imaging array 102 is different from a pixel size of pixels of the imaging strip 104.
  • the imaging strip 104 is a subset of the imaging array 102.
  • the imaging strip 104 is less than 30% of the imaging array 102.
  • reading the first data from the imaging array 102 disposed within a housing 110 using at least the first readout circuit 106-1 comprises reading the first data from the imaging array 102 through first data lines 618, 718, 818; and reading the second data from the imaging strip 104 disposed within the housing 110 using at least the second readout circuit 106-2 comprises reading the second data from the imaging strip 104 using second data lines 618, 718, 818 different from the first data lines 618, 718, 818.
  • reading the first data from the imaging array 102 disposed within a housing 110 using at least the first readout circuit 106-1 comprises reading the first data from the imaging array 102 through first data lines 618, 718, 818; and reading the second data from the imaging strip 104 disposed within the housing 110 using at least the second readout circuit 106-2 comprises reading the second data from the imaging strip 104 using second data lines 618, 718, 818; and further comprising electrically coupling the first data lines 618, 718, 818 to the second data lines 618, 718, 818 when reading the first data from the imaging array 102.
  • Some embodiments include a system, comprising: means for reading first data from an imaging array disposed within a housing; means for reading second data from an imaging strip disposed within the housing; means for processing the first data in common electronics 108 to generate first image data; and means for processing the second data in the common electronics 108 to generate second image data.
  • Examples of the means for reading first data from an imaging array disposed within a housing include the readout circuits 106-1 and associated data lines
  • Examples of the means for reading second data from an imaging strip disposed within the housing include the readout circuits 106-2 and associated data lines.
  • Examples of the means for processing the first data in common electronics to generate first image data include the common electronics 108.
  • Examples of the means for processing the second data in the common electronics to generate second image data include the common electronics 108.
  • the imaging strip 104 is a subset of the imaging array 102.
  • Some embodiments include a system, comprising: a plurality of pixels 902; a plurality of data lines 908 coupled to the pixels 902; a plurality of switches 906 coupling the pixels 902 to the data lines 908; a plurality of readout circuits 910-918 coupled to the data lines 908; control logic 903 coupled to the readout circuits 910-918, the control logic 903 configured to, for one of the pixels 902: acquire a first value for the pixel 902 while the corresponding switch 906 is in an off state; reset the corresponding readout circuit 910-918 corresponding for the pixel; acquire a second value for the pixel 902 after resetting the readout circuit; turn on the corresponding switch 906; acquire a third value for the pixel 902 after turning on the
  • control logic 903 is further configured to, for the one of the pixels 902: store a stored value for the pixel 902 based on the first value; and combine the second value, the third value, and the stored value into the combined value for the pixel 902. [00171] In some embodiments, the control logic 903 is further configured to, for the one of the pixels 902: before acquiring the first value for the pixel: reset the corresponding readout circuit; and acquire a fourth value for the pixel 902 while the corresponding switch 906 is in an on state; and combine the first value, the second value, the third value, and the fourth value into the combined value for the pixel 902.
  • control logic 903 is further configured to, for the one of the pixels 902: add the third value minus the second value and the first value minus the fourth value to combine the first value, the second value, the third value, and the fourth value into the combined value for the pixel 902. [00173] In some embodiments, the control logic 903 is further configured to, for the one of the pixels 902: combine the first value and the fourth value into a first correlated value; combine the second value and the third value into a second correlated value; and combine the first correlated value and the second correlated value into the combined value for the pixel 902.
  • control logic 903 is further configured to, for the one of the pixels 902: acquire the first value for the pixel 902 for a subsequent frame without resetting the corresponding readout circuit. [00175] In some embodiments, the control logic 903 is further configured to, for the one of the pixels 902: subtract the first value and the second value from the third value to combine the first value, the second value, and the third value into the combined value for the pixel 902.
  • control logic 903 is further configured to, for the one of the pixels 902: switch 906between: a first mode of operation where the first value, the second value, and the third value are combined into the combined value for the pixel; and a second mode of operation where the second value, and the third value are combined into the combined value for the pixel 902 and acquiring the first value for the pixel 902 while the corresponding switch 906 is in the off state is not performed.
  • the system further comprises an x-ray source configured to generate an x-ray beam; a detector including the pixels 902 and disposed to receive the x-ray beam.
  • Some embodiments include a method, comprising: acquiring a first value for a pixel 902 coupled to a data line through a switch 906 using a readout circuit 910-918 while the switch 906 is in an off state; resetting the readout circuit; acquiring a second value for the pixel 902 after resetting the readout circuit; turning on the switch 906; acquiring a third value for the pixel 902 after turning on the switch 906; and combining the first value, the second value, and the third value into a combined value for the pixel 902.
  • the method further comprises storing a stored value for the pixel 902 based on the first value; and wherein combining the first value, the second value, and the third value into the combined value for the pixel 902 comprises combining the second value, the third value, and the stored value into the combined value for the pixel 902.
  • the method further comprises before acquiring the first value for the pixel: resetting the readout circuit; and acquiring a fourth value for the pixel 902 while the switch 906 is in an on state; and wherein combining the first value, the second value, and the third value into the combined value for the pixel 902 comprises combining the first value, the second value, the third value, and the fourth value into the combined value for the pixel 902. [00181] In some embodiments, combining the first value, the second value, the third value, and the fourth value into the combined value for the pixel 902 comprises: adding the third value minus the second value and the first value minus the fourth value.
  • the method further comprises combining the first value and the fourth value into a first correlated value; combining the second value and the third value into a second correlated value; and combine the first correlated value and the second correlated value into the combined value for the pixel 902.
  • the method further comprises acquiring the first value for the pixel 902 for a subsequent frame without resetting the corresponding readout circuit.
  • combining the first value, the second value, and the third value into the combined value for the pixel 902 comprises: subtracting the first value and the second value from the third value.
  • the method further comprises switching between: a first mode of operation where the first value, the second value, and the third value are combined into the combined value for the pixel; and a second mode of operation where the second value, and the third value are combined into the combined value for the pixel 902 and acquiring the first value for the pixel 902 while the corresponding switch 906 is in the off state is not performed.
  • the method further comprises generating an x-ray beam using an x-ray source; and generating an image using a detector including the pixel 902 disposed to receive the x-ray beam.
  • Some embodiments include a system, comprising: means for acquiring a first value for a pixel coupled to a data line through a switch using a readout circuit while the switch is in an off state; means for resetting the readout circuit; means for acquiring a second value for the pixel after resetting the readout circuit; means for turning on the switch; means for acquiring a third value for the pixel after turning on the switch; and means for combining the first value, the second value, and the third value into a combined value for the pixel.
  • Examples of the means for acquiring a first value for a pixel coupled to a data line through a switch using a readout circuit while the switch is in an off state include the switches 906, row drivers 901, data lines 908, and readout circuits 910-918.
  • Examples of the means for resetting the readout circuit include the switch 910a and control logic 903.
  • Examples of the means for acquiring a second value for the pixel after resetting the readout circuit include the switches 906, row drivers 901, data lines 908, and readout circuits 910-918
  • Examples of the means for turning on the switch include the control logic 903.
  • Examples of the means for acquiring a third value for the pixel after turning on the switch include the switches 906, row drivers 901, data lines 908, and readout circuits 910-918.
  • Examples of the means for combining the first value, the second value, and the third value into a combined value for the pixel include the switches 906, row drivers 901, data lines 908, readout circuits 910-918, and the external computer 913.
  • the system further comprises means for acquiring the first value for the pixel for a subsequent frame without resetting the corresponding readout circuit.
  • Examples of the means for acquiring the first value for the pixel for a subsequent frame without resetting the corresponding readout circuit include the switches 906, row drivers 901, data lines 908, and readout circuits 910-918.
  • claim 4 can depend from either of claims 1 and 3, with these separate dependencies yielding two distinct embodiments; claim 5 can depend from any one of claims 1, 3, or 4, with these separate dependencies yielding three distinct embodiments; claim 6 can depend from any one of claims 1, 3, 4, or 5, with these separate dependencies yielding four distinct embodiments; and so on.

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  • Measurement Of Radiation (AREA)

Abstract

Certains modes de réalisation du système comprennent une pluralité : de pixels ; de lignes de données couplées aux pixels ; de commutateurs couplant les pixels aux lignes de données ; de circuits de lecture couplés aux lignes de données. Le système comprend également une logique de commande couplée aux circuits de lecture, la logique de commande étant configurée, pour l'un des pixels : pour acquérir une première valeur du pixel pendant que le commutateur correspondant est dans un état éteint ; pour réinitialiser le circuit de lecture correspondant qui correspond au pixel ; pour acquérir une deuxième valeur du pixel après réinitialisation du circuit de lecture ; pour mettre en marche le commutateur correspondant ; pour acquérir une troisième valeur du pixel après la mise en marche du commutateur correspondant ; et pour combiner les valeurs en une valeur de pixel combinée. Certains modes de réalisation du système comprennent : un boîtier ; une matrice d'imagerie dans le boîtier ; une bande d'imagerie dans le boîtier ; un premier circuit de lecture couplé à la matrice d'imagerie ; un second circuit de lecture couplé à la bande d'imagerie ; et une électronique commune couplée aux premier et second circuits de lecture et configurée pour générer des données d'image en réponse au premier et/ou au second circuit de lecture.
PCT/US2022/031465 2021-05-28 2022-05-27 Matrice et bande d'imagerie et système de suppression de bruit de pixel combinés WO2022251716A1 (fr)

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CN202280007277.XA CN116491126A (zh) 2021-05-28 2022-05-27 组合成像阵列和条及像素噪声消除系统
EP22812317.0A EP4349004A1 (fr) 2021-05-28 2022-05-27 Matrice et bande d'imagerie et système de suppression de bruit de pixel combinés
JP2023526897A JP2024521603A (ja) 2021-05-28 2022-05-27 組み合わせたイメージングアレイとストリップ及びピクセルノイズキャンセリングシステム

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US17/334,353 2021-05-28
US17/334,681 US11812187B2 (en) 2021-05-28 2021-05-28 Combined imaging array and strip
US17/334,353 US11750944B2 (en) 2021-05-28 2021-05-28 Pixel noise cancellation system
US17/334,681 2021-05-28

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WO2022251716A1 true WO2022251716A1 (fr) 2022-12-01

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100141804A1 (en) * 2004-05-05 2010-06-10 Centre National De La Recherche Scientifique-Cnrs Image data processing method by reducing image noise, and camera integrating means for implementing said method
US7796174B1 (en) * 2006-04-25 2010-09-14 Ball Aerospace & Technologies Corp. Hybrid imager
US8558929B2 (en) * 2006-12-20 2013-10-15 Carestream Health, Inc. Imaging array for multiple frame capture
US20140016879A1 (en) * 2009-03-02 2014-01-16 Flir Systems, Inc. Pixel-wise noise reduction in thermal images
US20170188987A1 (en) * 2016-01-05 2017-07-06 BAE Systems Imaging Solutions Inc. System and Method for Adjusting Dental X-ray Exposure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100141804A1 (en) * 2004-05-05 2010-06-10 Centre National De La Recherche Scientifique-Cnrs Image data processing method by reducing image noise, and camera integrating means for implementing said method
US7796174B1 (en) * 2006-04-25 2010-09-14 Ball Aerospace & Technologies Corp. Hybrid imager
US8558929B2 (en) * 2006-12-20 2013-10-15 Carestream Health, Inc. Imaging array for multiple frame capture
US20140016879A1 (en) * 2009-03-02 2014-01-16 Flir Systems, Inc. Pixel-wise noise reduction in thermal images
US20170188987A1 (en) * 2016-01-05 2017-07-06 BAE Systems Imaging Solutions Inc. System and Method for Adjusting Dental X-ray Exposure

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